1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2025 SpacemiT Technology Co. Ltd 4 */ 5 6 #ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ 7 #define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ 8 9 /* APBS (PLL) clocks */ 10 #define CLK_PLL1 0 11 #define CLK_PLL2 1 12 #define CLK_PLL3 2 13 #define CLK_PLL4 3 14 #define CLK_PLL5 4 15 #define CLK_PLL6 5 16 #define CLK_PLL7 6 17 #define CLK_PLL8 7 18 #define CLK_PLL1_D2 8 19 #define CLK_PLL1_D3 9 20 #define CLK_PLL1_D4 10 21 #define CLK_PLL1_D5 11 22 #define CLK_PLL1_D6 12 23 #define CLK_PLL1_D7 13 24 #define CLK_PLL1_D8 14 25 #define CLK_PLL1_DX 15 26 #define CLK_PLL1_D64 16 27 #define CLK_PLL1_D10_AUD 17 28 #define CLK_PLL1_D100_AUD 18 29 #define CLK_PLL2_D1 19 30 #define CLK_PLL2_D2 20 31 #define CLK_PLL2_D3 21 32 #define CLK_PLL2_D4 22 33 #define CLK_PLL2_D5 23 34 #define CLK_PLL2_D6 24 35 #define CLK_PLL2_D7 25 36 #define CLK_PLL2_D8 26 37 #define CLK_PLL2_66 27 38 #define CLK_PLL2_33 28 39 #define CLK_PLL2_50 29 40 #define CLK_PLL2_25 30 41 #define CLK_PLL2_20 31 42 #define CLK_PLL2_D24_125 32 43 #define CLK_PLL2_D120_25 33 44 #define CLK_PLL3_D1 34 45 #define CLK_PLL3_D2 35 46 #define CLK_PLL3_D3 36 47 #define CLK_PLL3_D4 37 48 #define CLK_PLL3_D5 38 49 #define CLK_PLL3_D6 39 50 #define CLK_PLL3_D7 40 51 #define CLK_PLL3_D8 41 52 #define CLK_PLL4_D1 42 53 #define CLK_PLL4_D2 43 54 #define CLK_PLL4_D3 44 55 #define CLK_PLL4_D4 45 56 #define CLK_PLL4_D5 46 57 #define CLK_PLL4_D6 47 58 #define CLK_PLL4_D7 48 59 #define CLK_PLL4_D8 49 60 #define CLK_PLL5_D1 50 61 #define CLK_PLL5_D2 51 62 #define CLK_PLL5_D3 52 63 #define CLK_PLL5_D4 53 64 #define CLK_PLL5_D5 54 65 #define CLK_PLL5_D6 55 66 #define CLK_PLL5_D7 56 67 #define CLK_PLL5_D8 57 68 #define CLK_PLL6_D1 58 69 #define CLK_PLL6_D2 59 70 #define CLK_PLL6_D3 60 71 #define CLK_PLL6_D4 61 72 #define CLK_PLL6_D5 62 73 #define CLK_PLL6_D6 63 74 #define CLK_PLL6_D7 64 75 #define CLK_PLL6_D8 65 76 #define CLK_PLL6_80 66 77 #define CLK_PLL6_40 67 78 #define CLK_PLL6_20 68 79 #define CLK_PLL7_D1 69 80 #define CLK_PLL7_D2 70 81 #define CLK_PLL7_D3 71 82 #define CLK_PLL7_D4 72 83 #define CLK_PLL7_D5 73 84 #define CLK_PLL7_D6 74 85 #define CLK_PLL7_D7 75 86 #define CLK_PLL7_D8 76 87 #define CLK_PLL8_D1 77 88 #define CLK_PLL8_D2 78 89 #define CLK_PLL8_D3 79 90 #define CLK_PLL8_D4 80 91 #define CLK_PLL8_D5 81 92 #define CLK_PLL8_D6 82 93 #define CLK_PLL8_D7 83 94 #define CLK_PLL8_D8 84 95 96 /* MPMU clocks */ 97 #define CLK_MPMU_PLL1_307P2 0 98 #define CLK_MPMU_PLL1_76P8 1 99 #define CLK_MPMU_PLL1_61P44 2 100 #define CLK_MPMU_PLL1_153P6 3 101 #define CLK_MPMU_PLL1_102P4 4 102 #define CLK_MPMU_PLL1_51P2 5 103 #define CLK_MPMU_PLL1_51P2_AP 6 104 #define CLK_MPMU_PLL1_57P6 7 105 #define CLK_MPMU_PLL1_25P6 8 106 #define CLK_MPMU_PLL1_12P8 9 107 #define CLK_MPMU_PLL1_12P8_WDT 10 108 #define CLK_MPMU_PLL1_6P4 11 109 #define CLK_MPMU_PLL1_3P2 12 110 #define CLK_MPMU_PLL1_1P6 13 111 #define CLK_MPMU_PLL1_0P8 14 112 #define CLK_MPMU_PLL1_409P6 15 113 #define CLK_MPMU_PLL1_204P8 16 114 #define CLK_MPMU_PLL1_491 17 115 #define CLK_MPMU_PLL1_245P76 18 116 #define CLK_MPMU_PLL1_614 19 117 #define CLK_MPMU_PLL1_47P26 20 118 #define CLK_MPMU_PLL1_31P5 21 119 #define CLK_MPMU_PLL1_819 22 120 #define CLK_MPMU_PLL1_1228 23 121 #define CLK_MPMU_APB 24 122 #define CLK_MPMU_SLOW_UART 25 123 #define CLK_MPMU_SLOW_UART1 26 124 #define CLK_MPMU_SLOW_UART2 27 125 #define CLK_MPMU_WDT 28 126 #define CLK_MPMU_WDT_BUS 29 127 #define CLK_MPMU_RIPC 30 128 #define CLK_MPMU_I2S_153P6 31 129 #define CLK_MPMU_I2S_153P6_BASE 32 130 #define CLK_MPMU_I2S_SYSCLK_SRC 33 131 #define CLK_MPMU_I2S1_SYSCLK 34 132 #define CLK_MPMU_I2S_BCLK 35 133 #define CLK_MPMU_I2S0_SYSCLK_SEL 36 134 #define CLK_MPMU_I2S2_SYSCLK_SEL 37 135 #define CLK_MPMU_I2S3_SYSCLK_SEL 38 136 #define CLK_MPMU_I2S4_SYSCLK_SEL 39 137 #define CLK_MPMU_I2S5_SYSCLK_SEL 40 138 #define CLK_MPMU_I2S0_SYSCLK_DIV 41 139 #define CLK_MPMU_I2S2_SYSCLK_DIV 42 140 #define CLK_MPMU_I2S3_SYSCLK_DIV 43 141 #define CLK_MPMU_I2S4_SYSCLK_DIV 44 142 #define CLK_MPMU_I2S5_SYSCLK_DIV 45 143 #define CLK_MPMU_I2S0_SYSCLK 46 144 #define CLK_MPMU_I2S2_SYSCLK 47 145 #define CLK_MPMU_I2S3_SYSCLK 48 146 #define CLK_MPMU_I2S4_SYSCLK 49 147 #define CLK_MPMU_I2S5_SYSCLK 50 148 149 /* APBC clocks */ 150 #define CLK_APBC_UART0 0 151 #define CLK_APBC_UART2 1 152 #define CLK_APBC_UART3 2 153 #define CLK_APBC_UART4 3 154 #define CLK_APBC_UART5 4 155 #define CLK_APBC_UART6 5 156 #define CLK_APBC_UART7 6 157 #define CLK_APBC_UART8 7 158 #define CLK_APBC_UART9 8 159 #define CLK_APBC_UART10 9 160 #define CLK_APBC_UART0_BUS 10 161 #define CLK_APBC_UART2_BUS 11 162 #define CLK_APBC_UART3_BUS 12 163 #define CLK_APBC_UART4_BUS 13 164 #define CLK_APBC_UART5_BUS 14 165 #define CLK_APBC_UART6_BUS 15 166 #define CLK_APBC_UART7_BUS 16 167 #define CLK_APBC_UART8_BUS 17 168 #define CLK_APBC_UART9_BUS 18 169 #define CLK_APBC_UART10_BUS 19 170 #define CLK_APBC_GPIO 20 171 #define CLK_APBC_GPIO_BUS 21 172 #define CLK_APBC_PWM0 22 173 #define CLK_APBC_PWM1 23 174 #define CLK_APBC_PWM2 24 175 #define CLK_APBC_PWM3 25 176 #define CLK_APBC_PWM4 26 177 #define CLK_APBC_PWM5 27 178 #define CLK_APBC_PWM6 28 179 #define CLK_APBC_PWM7 29 180 #define CLK_APBC_PWM8 30 181 #define CLK_APBC_PWM9 31 182 #define CLK_APBC_PWM10 32 183 #define CLK_APBC_PWM11 33 184 #define CLK_APBC_PWM12 34 185 #define CLK_APBC_PWM13 35 186 #define CLK_APBC_PWM14 36 187 #define CLK_APBC_PWM15 37 188 #define CLK_APBC_PWM16 38 189 #define CLK_APBC_PWM17 39 190 #define CLK_APBC_PWM18 40 191 #define CLK_APBC_PWM19 41 192 #define CLK_APBC_PWM0_BUS 42 193 #define CLK_APBC_PWM1_BUS 43 194 #define CLK_APBC_PWM2_BUS 44 195 #define CLK_APBC_PWM3_BUS 45 196 #define CLK_APBC_PWM4_BUS 46 197 #define CLK_APBC_PWM5_BUS 47 198 #define CLK_APBC_PWM6_BUS 48 199 #define CLK_APBC_PWM7_BUS 49 200 #define CLK_APBC_PWM8_BUS 50 201 #define CLK_APBC_PWM9_BUS 51 202 #define CLK_APBC_PWM10_BUS 52 203 #define CLK_APBC_PWM11_BUS 53 204 #define CLK_APBC_PWM12_BUS 54 205 #define CLK_APBC_PWM13_BUS 55 206 #define CLK_APBC_PWM14_BUS 56 207 #define CLK_APBC_PWM15_BUS 57 208 #define CLK_APBC_PWM16_BUS 58 209 #define CLK_APBC_PWM17_BUS 59 210 #define CLK_APBC_PWM18_BUS 60 211 #define CLK_APBC_PWM19_BUS 61 212 #define CLK_APBC_SPI0_I2S_BCLK 62 213 #define CLK_APBC_SPI1_I2S_BCLK 63 214 #define CLK_APBC_SPI3_I2S_BCLK 64 215 #define CLK_APBC_SPI0 65 216 #define CLK_APBC_SPI1 66 217 #define CLK_APBC_SPI3 67 218 #define CLK_APBC_SPI0_BUS 68 219 #define CLK_APBC_SPI1_BUS 69 220 #define CLK_APBC_SPI3_BUS 70 221 #define CLK_APBC_RTC 71 222 #define CLK_APBC_RTC_BUS 72 223 #define CLK_APBC_TWSI0 73 224 #define CLK_APBC_TWSI1 74 225 #define CLK_APBC_TWSI2 75 226 #define CLK_APBC_TWSI4 76 227 #define CLK_APBC_TWSI5 77 228 #define CLK_APBC_TWSI6 78 229 #define CLK_APBC_TWSI8 79 230 #define CLK_APBC_TWSI0_BUS 80 231 #define CLK_APBC_TWSI1_BUS 81 232 #define CLK_APBC_TWSI2_BUS 82 233 #define CLK_APBC_TWSI4_BUS 83 234 #define CLK_APBC_TWSI5_BUS 84 235 #define CLK_APBC_TWSI6_BUS 85 236 #define CLK_APBC_TWSI8_BUS 86 237 #define CLK_APBC_TIMERS0 87 238 #define CLK_APBC_TIMERS1 88 239 #define CLK_APBC_TIMERS2 89 240 #define CLK_APBC_TIMERS3 90 241 #define CLK_APBC_TIMERS4 91 242 #define CLK_APBC_TIMERS5 92 243 #define CLK_APBC_TIMERS6 93 244 #define CLK_APBC_TIMERS7 94 245 #define CLK_APBC_TIMERS0_BUS 95 246 #define CLK_APBC_TIMERS1_BUS 96 247 #define CLK_APBC_TIMERS2_BUS 97 248 #define CLK_APBC_TIMERS3_BUS 98 249 #define CLK_APBC_TIMERS4_BUS 99 250 #define CLK_APBC_TIMERS5_BUS 100 251 #define CLK_APBC_TIMERS6_BUS 101 252 #define CLK_APBC_TIMERS7_BUS 102 253 #define CLK_APBC_AIB 103 254 #define CLK_APBC_AIB_BUS 104 255 #define CLK_APBC_ONEWIRE 105 256 #define CLK_APBC_ONEWIRE_BUS 106 257 #define CLK_APBC_I2S0_BCLK 107 258 #define CLK_APBC_I2S1_BCLK 108 259 #define CLK_APBC_I2S2_BCLK 109 260 #define CLK_APBC_I2S3_BCLK 110 261 #define CLK_APBC_I2S4_BCLK 111 262 #define CLK_APBC_I2S5_BCLK 112 263 #define CLK_APBC_I2S0 113 264 #define CLK_APBC_I2S1 114 265 #define CLK_APBC_I2S2 115 266 #define CLK_APBC_I2S3 116 267 #define CLK_APBC_I2S4 117 268 #define CLK_APBC_I2S5 118 269 #define CLK_APBC_I2S0_BUS 119 270 #define CLK_APBC_I2S1_BUS 120 271 #define CLK_APBC_I2S2_BUS 121 272 #define CLK_APBC_I2S3_BUS 122 273 #define CLK_APBC_I2S4_BUS 123 274 #define CLK_APBC_I2S5_BUS 124 275 #define CLK_APBC_DRO 125 276 #define CLK_APBC_IR0 126 277 #define CLK_APBC_IR1 127 278 #define CLK_APBC_TSEN 128 279 #define CLK_APBC_TSEN_BUS 129 280 #define CLK_APBC_IPC_AP2RCPU 130 281 #define CLK_APBC_IPC_AP2RCPU_BUS 131 282 #define CLK_APBC_CAN0 132 283 #define CLK_APBC_CAN1 133 284 #define CLK_APBC_CAN2 134 285 #define CLK_APBC_CAN3 135 286 #define CLK_APBC_CAN4 136 287 #define CLK_APBC_CAN0_BUS 137 288 #define CLK_APBC_CAN1_BUS 138 289 #define CLK_APBC_CAN2_BUS 139 290 #define CLK_APBC_CAN3_BUS 140 291 #define CLK_APBC_CAN4_BUS 141 292 293 /* APMU clocks */ 294 #define CLK_APMU_AXICLK 0 295 #define CLK_APMU_CCI550 1 296 #define CLK_APMU_CPU_C0_CORE 2 297 #define CLK_APMU_CPU_C1_CORE 3 298 #define CLK_APMU_CPU_C2_CORE 4 299 #define CLK_APMU_CPU_C3_CORE 5 300 #define CLK_APMU_CCIC2PHY 6 301 #define CLK_APMU_CCIC3PHY 7 302 #define CLK_APMU_CSI 8 303 #define CLK_APMU_ISP_BUS 9 304 #define CLK_APMU_D1P_1228P8 10 305 #define CLK_APMU_D1P_819P2 11 306 #define CLK_APMU_D1P_614P4 12 307 #define CLK_APMU_D1P_491P52 13 308 #define CLK_APMU_D1P_409P6 14 309 #define CLK_APMU_D1P_307P2 15 310 #define CLK_APMU_D1P_245P76 16 311 #define CLK_APMU_V2D 17 312 #define CLK_APMU_DSI_ESC 18 313 #define CLK_APMU_LCD_HCLK 19 314 #define CLK_APMU_LCD_DSC 20 315 #define CLK_APMU_LCD_PXCLK 21 316 #define CLK_APMU_LCD_MCLK 22 317 #define CLK_APMU_CCIC_4X 23 318 #define CLK_APMU_CCIC1PHY 24 319 #define CLK_APMU_SC2_HCLK 25 320 #define CLK_APMU_SDH_AXI 26 321 #define CLK_APMU_SDH0 27 322 #define CLK_APMU_SDH1 28 323 #define CLK_APMU_SDH2 29 324 #define CLK_APMU_USB2_BUS 30 325 #define CLK_APMU_USB3_PORTA_BUS 31 326 #define CLK_APMU_USB3_PORTB_BUS 32 327 #define CLK_APMU_USB3_PORTC_BUS 33 328 #define CLK_APMU_USB3_PORTD_BUS 34 329 #define CLK_APMU_QSPI 35 330 #define CLK_APMU_QSPI_BUS 36 331 #define CLK_APMU_DMA 37 332 #define CLK_APMU_AES_WTM 38 333 #define CLK_APMU_VPU 39 334 #define CLK_APMU_DTC 40 335 #define CLK_APMU_GPU 41 336 #define CLK_APMU_MC_AHB 42 337 #define CLK_APMU_TOP_DCLK 43 338 #define CLK_APMU_UCIE 44 339 #define CLK_APMU_UCIE_SBCLK 45 340 #define CLK_APMU_RCPU 46 341 #define CLK_APMU_DSI4LN2_DSI_ESC 47 342 #define CLK_APMU_DSI4LN2_LCD_DSC 48 343 #define CLK_APMU_DSI4LN2_LCD_PXCLK 49 344 #define CLK_APMU_DSI4LN2_LCD_MCLK 50 345 #define CLK_APMU_DSI4LN2_DPU_ACLK 51 346 #define CLK_APMU_DPU_ACLK 52 347 #define CLK_APMU_UFS_ACLK 53 348 #define CLK_APMU_EDP0_PXCLK 54 349 #define CLK_APMU_EDP1_PXCLK 55 350 #define CLK_APMU_PCIE_PORTA_MSTE 56 351 #define CLK_APMU_PCIE_PORTA_SLV 57 352 #define CLK_APMU_PCIE_PORTB_MSTE 58 353 #define CLK_APMU_PCIE_PORTB_SLV 59 354 #define CLK_APMU_PCIE_PORTC_MSTE 60 355 #define CLK_APMU_PCIE_PORTC_SLV 61 356 #define CLK_APMU_PCIE_PORTD_MSTE 62 357 #define CLK_APMU_PCIE_PORTD_SLV 63 358 #define CLK_APMU_PCIE_PORTE_MSTE 64 359 #define CLK_APMU_PCIE_PORTE_SLV 65 360 #define CLK_APMU_EMAC0_BUS 66 361 #define CLK_APMU_EMAC0_REF 67 362 #define CLK_APMU_EMAC0_1588 68 363 #define CLK_APMU_EMAC0_RGMII_TX 69 364 #define CLK_APMU_EMAC1_BUS 70 365 #define CLK_APMU_EMAC1_REF 71 366 #define CLK_APMU_EMAC1_1588 72 367 #define CLK_APMU_EMAC1_RGMII_TX 73 368 #define CLK_APMU_EMAC2_BUS 74 369 #define CLK_APMU_EMAC2_REF 75 370 #define CLK_APMU_EMAC2_1588 76 371 #define CLK_APMU_EMAC2_RGMII_TX 77 372 #define CLK_APMU_ESPI_SCLK_SRC 78 373 #define CLK_APMU_ESPI_SCLK 79 374 #define CLK_APMU_ESPI_MCLK 80 375 #define CLK_APMU_CAM_SRC1 81 376 #define CLK_APMU_CAM_SRC2 82 377 #define CLK_APMU_CAM_SRC3 83 378 #define CLK_APMU_CAM_SRC4 84 379 #define CLK_APMU_ISIM_VCLK0 85 380 #define CLK_APMU_ISIM_VCLK1 86 381 #define CLK_APMU_ISIM_VCLK2 87 382 #define CLK_APMU_ISIM_VCLK3 88 383 384 /* DCIU clocks */ 385 #define CLK_DCIU_HDMA 0 386 #define CLK_DCIU_DMA350 1 387 #define CLK_DCIU_C2_TCM_PIPE 2 388 #define CLK_DCIU_C3_TCM_PIPE 3 389 390 #endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */ 391