1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (C) 2015 Samsung Electronics Co., Ltd. 4 * Author: Kaustabh Chakraborty <kauschluss@disroot.org> 5 * 6 * Device Tree binding constants for Exynos7870 clock controller. 7 */ 8 9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H 10 #define _DT_BINDINGS_CLOCK_EXYNOS7870_H 11 12 /* CMU_MIF */ 13 #define CLK_DOUT_MIF_APB 1 14 #define CLK_DOUT_MIF_BUSD 2 15 #define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3 16 #define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4 17 #define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5 18 #define CLK_DOUT_MIF_CMU_FSYS_BUS 6 19 #define CLK_DOUT_MIF_CMU_FSYS_MMC0 7 20 #define CLK_DOUT_MIF_CMU_FSYS_MMC1 8 21 #define CLK_DOUT_MIF_CMU_FSYS_MMC2 9 22 #define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10 23 #define CLK_DOUT_MIF_CMU_G3D_SWITCH 11 24 #define CLK_DOUT_MIF_CMU_ISP_CAM 12 25 #define CLK_DOUT_MIF_CMU_ISP_ISP 13 26 #define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14 27 #define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15 28 #define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16 29 #define CLK_DOUT_MIF_CMU_ISP_VRA 17 30 #define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18 31 #define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19 32 #define CLK_DOUT_MIF_CMU_PERI_BUS 20 33 #define CLK_DOUT_MIF_CMU_PERI_SPI0 21 34 #define CLK_DOUT_MIF_CMU_PERI_SPI1 22 35 #define CLK_DOUT_MIF_CMU_PERI_SPI2 23 36 #define CLK_DOUT_MIF_CMU_PERI_SPI3 24 37 #define CLK_DOUT_MIF_CMU_PERI_SPI4 25 38 #define CLK_DOUT_MIF_CMU_PERI_UART0 26 39 #define CLK_DOUT_MIF_CMU_PERI_UART1 27 40 #define CLK_DOUT_MIF_CMU_PERI_UART2 28 41 #define CLK_DOUT_MIF_HSI2C 29 42 #define CLK_FOUT_MIF_BUS_PLL 30 43 #define CLK_FOUT_MIF_MEDIA_PLL 31 44 #define CLK_FOUT_MIF_MEM_PLL 32 45 #define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33 46 #define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34 47 #define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35 48 #define CLK_GOUT_MIF_CMU_FSYS_BUS 36 49 #define CLK_GOUT_MIF_CMU_FSYS_MMC0 37 50 #define CLK_GOUT_MIF_CMU_FSYS_MMC1 38 51 #define CLK_GOUT_MIF_CMU_FSYS_MMC2 39 52 #define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40 53 #define CLK_GOUT_MIF_CMU_G3D_SWITCH 41 54 #define CLK_GOUT_MIF_CMU_ISP_CAM 42 55 #define CLK_GOUT_MIF_CMU_ISP_ISP 43 56 #define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44 57 #define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45 58 #define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46 59 #define CLK_GOUT_MIF_CMU_ISP_VRA 47 60 #define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48 61 #define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49 62 #define CLK_GOUT_MIF_CMU_PERI_BUS 50 63 #define CLK_GOUT_MIF_CMU_PERI_SPI0 51 64 #define CLK_GOUT_MIF_CMU_PERI_SPI1 52 65 #define CLK_GOUT_MIF_CMU_PERI_SPI2 53 66 #define CLK_GOUT_MIF_CMU_PERI_SPI3 54 67 #define CLK_GOUT_MIF_CMU_PERI_SPI4 55 68 #define CLK_GOUT_MIF_CMU_PERI_UART0 56 69 #define CLK_GOUT_MIF_CMU_PERI_UART1 57 70 #define CLK_GOUT_MIF_CMU_PERI_UART2 58 71 #define CLK_GOUT_MIF_CP_PCLK_HSI2C 59 72 #define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60 73 #define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61 74 #define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62 75 #define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63 76 #define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64 77 #define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65 78 #define CLK_GOUT_MIF_HSI2C_IPCLK 66 79 #define CLK_GOUT_MIF_HSI2C_ITCLK 67 80 #define CLK_GOUT_MIF_MUX_BUSD 68 81 #define CLK_GOUT_MIF_MUX_BUS_PLL 69 82 #define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70 83 #define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71 84 #define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72 85 #define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73 86 #define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74 87 #define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75 88 #define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76 89 #define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77 90 #define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78 91 #define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79 92 #define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80 93 #define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81 94 #define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82 95 #define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83 96 #define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84 97 #define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85 98 #define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86 99 #define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87 100 #define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88 101 #define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89 102 #define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90 103 #define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91 104 #define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92 105 #define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93 106 #define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94 107 #define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95 108 #define CLK_GOUT_MIF_MUX_MEDIA_PLL 96 109 #define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97 110 #define CLK_GOUT_MIF_MUX_MEM_PLL 98 111 #define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99 112 #define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100 113 #define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101 114 #define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102 115 #define CLK_MOUT_MIF_BUSD 103 116 #define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104 117 #define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105 118 #define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106 119 #define CLK_MOUT_MIF_CMU_FSYS_BUS 107 120 #define CLK_MOUT_MIF_CMU_FSYS_MMC0 108 121 #define CLK_MOUT_MIF_CMU_FSYS_MMC1 109 122 #define CLK_MOUT_MIF_CMU_FSYS_MMC2 110 123 #define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111 124 #define CLK_MOUT_MIF_CMU_ISP_CAM 112 125 #define CLK_MOUT_MIF_CMU_ISP_ISP 113 126 #define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114 127 #define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115 128 #define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116 129 #define CLK_MOUT_MIF_CMU_ISP_VRA 117 130 #define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118 131 #define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119 132 #define CLK_MOUT_MIF_CMU_PERI_BUS 120 133 #define CLK_MOUT_MIF_CMU_PERI_SPI0 121 134 #define CLK_MOUT_MIF_CMU_PERI_SPI1 122 135 #define CLK_MOUT_MIF_CMU_PERI_SPI2 123 136 #define CLK_MOUT_MIF_CMU_PERI_SPI3 124 137 #define CLK_MOUT_MIF_CMU_PERI_SPI4 125 138 #define CLK_MOUT_MIF_CMU_PERI_UART0 126 139 #define CLK_MOUT_MIF_CMU_PERI_UART1 127 140 #define CLK_MOUT_MIF_CMU_PERI_UART2 128 141 #define MIF_NR_CLK 129 142 143 /* CMU_DISPAUD */ 144 #define CLK_DOUT_DISPAUD_APB 1 145 #define CLK_DOUT_DISPAUD_DECON_ECLK 2 146 #define CLK_DOUT_DISPAUD_DECON_VCLK 3 147 #define CLK_DOUT_DISPAUD_MI2S 4 148 #define CLK_DOUT_DISPAUD_MIXER 5 149 #define CLK_FOUT_DISPAUD_AUD_PLL 6 150 #define CLK_FOUT_DISPAUD_PLL 7 151 #define CLK_GOUT_DISPAUD_APB_AUD 8 152 #define CLK_GOUT_DISPAUD_APB_AUD_AMP 9 153 #define CLK_GOUT_DISPAUD_APB_DISP 10 154 #define CLK_GOUT_DISPAUD_BUS 11 155 #define CLK_GOUT_DISPAUD_BUS_DISP 12 156 #define CLK_GOUT_DISPAUD_BUS_PPMU 13 157 #define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14 158 #define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15 159 #define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16 160 #define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17 161 #define CLK_GOUT_DISPAUD_DECON_ECLK 18 162 #define CLK_GOUT_DISPAUD_DECON_VCLK 19 163 #define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20 164 #define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21 165 #define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22 166 #define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23 167 #define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24 168 #define CLK_GOUT_DISPAUD_MUX_BUS_USER 25 169 #define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26 170 #define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27 171 #define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28 172 #define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29 173 #define CLK_GOUT_DISPAUD_MUX_MI2S 30 174 #define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31 175 #define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32 176 #define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33 177 #define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34 178 #define CLK_GOUT_DISPAUD_MUX_PLL 35 179 #define CLK_GOUT_DISPAUD_MUX_PLL_CON 36 180 #define CLK_MOUT_DISPAUD_BUS_USER 37 181 #define CLK_MOUT_DISPAUD_DECON_ECLK 38 182 #define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39 183 #define CLK_MOUT_DISPAUD_DECON_VCLK 40 184 #define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41 185 #define CLK_MOUT_DISPAUD_MI2S 42 186 #define DISPAUD_NR_CLK 43 187 188 /* CMU_FSYS */ 189 #define CLK_FOUT_FSYS_USB_PLL 1 190 #define CLK_GOUT_FSYS_BUSP3_HCLK 2 191 #define CLK_GOUT_FSYS_MMC0_ACLK 3 192 #define CLK_GOUT_FSYS_MMC1_ACLK 4 193 #define CLK_GOUT_FSYS_MMC2_ACLK 5 194 #define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6 195 #define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7 196 #define CLK_GOUT_FSYS_MUX_USB_PLL 8 197 #define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9 198 #define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10 199 #define CLK_GOUT_FSYS_PPMU_ACLK 11 200 #define CLK_GOUT_FSYS_PPMU_PCLK 12 201 #define CLK_GOUT_FSYS_SROMC_HCLK 13 202 #define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14 203 #define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15 204 #define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16 205 #define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17 206 #define FSYS_NR_CLK 18 207 208 /* CMU_G3D */ 209 #define CLK_DOUT_G3D_APB 1 210 #define CLK_DOUT_G3D_BUS 2 211 #define CLK_FOUT_G3D_PLL 3 212 #define CLK_GOUT_G3D_ASYNCS_D0_CLK 4 213 #define CLK_GOUT_G3D_ASYNC_PCLKM 5 214 #define CLK_GOUT_G3D_CLK 6 215 #define CLK_GOUT_G3D_MUX 7 216 #define CLK_GOUT_G3D_MUX_PLL 8 217 #define CLK_GOUT_G3D_MUX_PLL_CON 9 218 #define CLK_GOUT_G3D_MUX_SWITCH_USER 10 219 #define CLK_GOUT_G3D_PPMU_ACLK 11 220 #define CLK_GOUT_G3D_PPMU_PCLK 12 221 #define CLK_GOUT_G3D_QE_ACLK 13 222 #define CLK_GOUT_G3D_QE_PCLK 14 223 #define CLK_GOUT_G3D_SYSREG_PCLK 15 224 #define CLK_MOUT_G3D 16 225 #define CLK_MOUT_G3D_SWITCH_USER 17 226 #define G3D_NR_CLK 18 227 228 /* CMU_ISP */ 229 #define CLK_DOUT_ISP_APB 1 230 #define CLK_DOUT_ISP_CAM_HALF 2 231 #define CLK_FOUT_ISP_PLL 3 232 #define CLK_GOUT_ISP_CAM 4 233 #define CLK_GOUT_ISP_CAM_HALF 5 234 #define CLK_GOUT_ISP_ISPD 6 235 #define CLK_GOUT_ISP_ISPD_PPMU 7 236 #define CLK_GOUT_ISP_MUX_CAM 8 237 #define CLK_GOUT_ISP_MUX_CAM_USER 9 238 #define CLK_GOUT_ISP_MUX_ISP 10 239 #define CLK_GOUT_ISP_MUX_ISPD 11 240 #define CLK_GOUT_ISP_MUX_PLL 12 241 #define CLK_GOUT_ISP_MUX_PLL_CON 13 242 #define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14 243 #define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15 244 #define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16 245 #define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17 246 #define CLK_GOUT_ISP_MUX_USER 18 247 #define CLK_GOUT_ISP_MUX_VRA 19 248 #define CLK_GOUT_ISP_MUX_VRA_USER 20 249 #define CLK_GOUT_ISP_VRA 21 250 #define CLK_MOUT_ISP_CAM 22 251 #define CLK_MOUT_ISP_CAM_USER 23 252 #define CLK_MOUT_ISP_ISP 24 253 #define CLK_MOUT_ISP_ISPD 25 254 #define CLK_MOUT_ISP_USER 26 255 #define CLK_MOUT_ISP_VRA 27 256 #define CLK_MOUT_ISP_VRA_USER 28 257 #define ISP_NR_CLK 29 258 259 /* CMU_MFCMSCL */ 260 #define CLK_DOUT_MFCMSCL_APB 1 261 #define CLK_GOUT_MFCMSCL_MFC 2 262 #define CLK_GOUT_MFCMSCL_MSCL 3 263 #define CLK_GOUT_MFCMSCL_MSCL_BI 4 264 #define CLK_GOUT_MFCMSCL_MSCL_D 5 265 #define CLK_GOUT_MFCMSCL_MSCL_JPEG 6 266 #define CLK_GOUT_MFCMSCL_MSCL_POLY 7 267 #define CLK_GOUT_MFCMSCL_MSCL_PPMU 8 268 #define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9 269 #define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10 270 #define CLK_MOUT_MFCMSCL_MFC_USER 11 271 #define CLK_MOUT_MFCMSCL_MSCL_USER 12 272 #define MFCMSCL_NR_CLK 13 273 274 /* CMU_PERI */ 275 #define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1 276 #define CLK_GOUT_PERI_GPIO2_PCLK 2 277 #define CLK_GOUT_PERI_GPIO5_PCLK 3 278 #define CLK_GOUT_PERI_GPIO6_PCLK 4 279 #define CLK_GOUT_PERI_GPIO7_PCLK 5 280 #define CLK_GOUT_PERI_HSI2C1_IPCLK 6 281 #define CLK_GOUT_PERI_HSI2C2_IPCLK 7 282 #define CLK_GOUT_PERI_HSI2C3_IPCLK 8 283 #define CLK_GOUT_PERI_HSI2C4_IPCLK 9 284 #define CLK_GOUT_PERI_HSI2C5_IPCLK 10 285 #define CLK_GOUT_PERI_HSI2C6_IPCLK 11 286 #define CLK_GOUT_PERI_I2C0_PCLK 12 287 #define CLK_GOUT_PERI_I2C1_PCLK 13 288 #define CLK_GOUT_PERI_I2C2_PCLK 14 289 #define CLK_GOUT_PERI_I2C3_PCLK 15 290 #define CLK_GOUT_PERI_I2C4_PCLK 16 291 #define CLK_GOUT_PERI_I2C5_PCLK 17 292 #define CLK_GOUT_PERI_I2C6_PCLK 18 293 #define CLK_GOUT_PERI_I2C7_PCLK 19 294 #define CLK_GOUT_PERI_I2C8_PCLK 20 295 #define CLK_GOUT_PERI_MCT_PCLK 21 296 #define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22 297 #define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23 298 #define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24 299 #define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25 300 #define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26 301 #define CLK_GOUT_PERI_SPI0_PCLK 27 302 #define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28 303 #define CLK_GOUT_PERI_SPI1_PCLK 29 304 #define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30 305 #define CLK_GOUT_PERI_SPI2_PCLK 31 306 #define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32 307 #define CLK_GOUT_PERI_SPI3_PCLK 33 308 #define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34 309 #define CLK_GOUT_PERI_SPI4_PCLK 35 310 #define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36 311 #define CLK_GOUT_PERI_TMU_CLK 37 312 #define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38 313 #define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39 314 #define CLK_GOUT_PERI_UART0_EXT_UCLK 40 315 #define CLK_GOUT_PERI_UART0_PCLK 41 316 #define CLK_GOUT_PERI_UART1_EXT_UCLK 42 317 #define CLK_GOUT_PERI_UART1_PCLK 43 318 #define CLK_GOUT_PERI_UART2_EXT_UCLK 44 319 #define CLK_GOUT_PERI_UART2_PCLK 45 320 #define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46 321 #define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47 322 #define PERI_NR_CLK 48 323 324 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */ 325