1*c04269c0SLad Prabhakar /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*c04269c0SLad Prabhakar * 3*c04269c0SLad Prabhakar * Copyright (C) 2025 Renesas Electronics Corp. 4*c04269c0SLad Prabhakar */ 5*c04269c0SLad Prabhakar #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 6*c04269c0SLad Prabhakar #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 7*c04269c0SLad Prabhakar 8*c04269c0SLad Prabhakar #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*c04269c0SLad Prabhakar 10*c04269c0SLad Prabhakar /* Core Clock list */ 11*c04269c0SLad Prabhakar #define R9A09G056_SYS_0_PCLK 0 12*c04269c0SLad Prabhakar #define R9A09G056_CA55_0_CORE_CLK0 1 13*c04269c0SLad Prabhakar #define R9A09G056_CA55_0_CORE_CLK1 2 14*c04269c0SLad Prabhakar #define R9A09G056_CA55_0_CORE_CLK2 3 15*c04269c0SLad Prabhakar #define R9A09G056_CA55_0_CORE_CLK3 4 16*c04269c0SLad Prabhakar #define R9A09G056_CA55_0_PERIPHCLK 5 17*c04269c0SLad Prabhakar #define R9A09G056_CM33_CLK0 6 18*c04269c0SLad Prabhakar #define R9A09G056_CST_0_SWCLKTCK 7 19*c04269c0SLad Prabhakar #define R9A09G056_IOTOP_0_SHCLK 8 20*c04269c0SLad Prabhakar #define R9A09G056_USB2_0_CLK_CORE0 9 21*c04269c0SLad Prabhakar #define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 22*c04269c0SLad Prabhakar #define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 23*c04269c0SLad Prabhakar 24*c04269c0SLad Prabhakar #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ 25