1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 * 3 * Copyright (C) 2025 Renesas Electronics Corp. 4 */ 5 #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 6 #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 7 8 #include <dt-bindings/clock/renesas-cpg-mssr.h> 9 10 /* Core Clock list */ 11 #define R9A09G056_SYS_0_PCLK 0 12 #define R9A09G056_CA55_0_CORE_CLK0 1 13 #define R9A09G056_CA55_0_CORE_CLK1 2 14 #define R9A09G056_CA55_0_CORE_CLK2 3 15 #define R9A09G056_CA55_0_CORE_CLK3 4 16 #define R9A09G056_CA55_0_PERIPHCLK 5 17 #define R9A09G056_CM33_CLK0 6 18 #define R9A09G056_CST_0_SWCLKTCK 7 19 #define R9A09G056_IOTOP_0_SHCLK 8 20 #define R9A09G056_USB2_0_CLK_CORE0 9 21 #define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 22 #define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 23 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ 25