1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 * 3 * Copyright (C) 2026 Renesas Electronics Corp. 4 */ 5 #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ 6 #define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ 7 8 #include <dt-bindings/clock/renesas-cpg-mssr.h> 9 10 /* R9A08G046 CPG Core Clocks */ 11 #define R9A08G046_CLK_I 0 12 #define R9A08G046_CLK_IC0 1 13 #define R9A08G046_CLK_IC1 2 14 #define R9A08G046_CLK_IC2 3 15 #define R9A08G046_CLK_IC3 4 16 #define R9A08G046_CLK_P0 5 17 #define R9A08G046_CLK_P1 6 18 #define R9A08G046_CLK_P2 7 19 #define R9A08G046_CLK_P3 8 20 #define R9A08G046_CLK_P4 9 21 #define R9A08G046_CLK_P5 10 22 #define R9A08G046_CLK_P6 11 23 #define R9A08G046_CLK_P7 12 24 #define R9A08G046_CLK_P8 13 25 #define R9A08G046_CLK_P9 14 26 #define R9A08G046_CLK_P10 15 27 #define R9A08G046_CLK_P13 16 28 #define R9A08G046_CLK_P14 17 29 #define R9A08G046_CLK_P15 18 30 #define R9A08G046_CLK_P16 19 31 #define R9A08G046_CLK_P17 20 32 #define R9A08G046_CLK_P18 21 33 #define R9A08G046_CLK_P19 22 34 #define R9A08G046_CLK_P20 23 35 #define R9A08G046_CLK_M0 24 36 #define R9A08G046_CLK_M1 25 37 #define R9A08G046_CLK_M2 26 38 #define R9A08G046_CLK_M3 27 39 #define R9A08G046_CLK_M4 28 40 #define R9A08G046_CLK_M5 29 41 #define R9A08G046_CLK_M6 30 42 #define R9A08G046_CLK_AT 31 43 #define R9A08G046_CLK_B 32 44 #define R9A08G046_CLK_ETHTX01 33 45 #define R9A08G046_CLK_ETHTX02 34 46 #define R9A08G046_CLK_ETHRX01 35 47 #define R9A08G046_CLK_ETHRX02 36 48 #define R9A08G046_CLK_ETHRM0 37 49 #define R9A08G046_CLK_ETHTX11 38 50 #define R9A08G046_CLK_ETHTX12 39 51 #define R9A08G046_CLK_ETHRX11 40 52 #define R9A08G046_CLK_ETHRX12 41 53 #define R9A08G046_CLK_ETHRM1 42 54 #define R9A08G046_CLK_G 43 55 #define R9A08G046_CLK_HP 44 56 #define R9A08G046_CLK_SD0 45 57 #define R9A08G046_CLK_SD1 46 58 #define R9A08G046_CLK_SD2 47 59 #define R9A08G046_CLK_SPI0 48 60 #define R9A08G046_CLK_SPI1 49 61 #define R9A08G046_CLK_S0 50 62 #define R9A08G046_CLK_SWD 51 63 #define R9A08G046_OSCCLK 52 64 #define R9A08G046_OSCCLK2 53 65 #define R9A08G046_MIPI_DSI_PLLCLK 54 66 #define R9A08G046_USB_SCLK 55 67 68 /* R9A08G046 Module Clocks */ 69 #define R9A08G046_CA55_SCLK 0 70 #define R9A08G046_CA55_PCLK 1 71 #define R9A08G046_CA55_ATCLK 2 72 #define R9A08G046_CA55_GICCLK 3 73 #define R9A08G046_CA55_PERICLK 4 74 #define R9A08G046_CA55_ACLK 5 75 #define R9A08G046_CA55_TSCLK 6 76 #define R9A08G046_CA55_CORECLK0 7 77 #define R9A08G046_CA55_CORECLK1 8 78 #define R9A08G046_CA55_CORECLK2 9 79 #define R9A08G046_CA55_CORECLK3 10 80 #define R9A08G046_SRAM_ACPU_ACLK0 11 81 #define R9A08G046_SRAM_ACPU_ACLK1 12 82 #define R9A08G046_SRAM_ACPU_ACLK2 13 83 #define R9A08G046_GIC600_GICCLK 14 84 #define R9A08G046_IA55_CLK 15 85 #define R9A08G046_IA55_PCLK 16 86 #define R9A08G046_MHU_PCLK 17 87 #define R9A08G046_SYC_CNT_CLK 18 88 #define R9A08G046_DMAC_ACLK 19 89 #define R9A08G046_DMAC_PCLK 20 90 #define R9A08G046_OSTM0_PCLK 21 91 #define R9A08G046_OSTM1_PCLK 22 92 #define R9A08G046_OSTM2_PCLK 23 93 #define R9A08G046_MTU_X_MCK_MTU3 24 94 #define R9A08G046_POE3_CLKM_POE 25 95 #define R9A08G046_GPT_PCLK 26 96 #define R9A08G046_POEG_A_CLKP 27 97 #define R9A08G046_POEG_B_CLKP 28 98 #define R9A08G046_POEG_C_CLKP 29 99 #define R9A08G046_POEG_D_CLKP 30 100 #define R9A08G046_WDT0_PCLK 31 101 #define R9A08G046_WDT0_CLK 32 102 #define R9A08G046_WDT1_PCLK 33 103 #define R9A08G046_WDT1_CLK 34 104 #define R9A08G046_WDT2_PCLK 35 105 #define R9A08G046_WDT2_CLK 36 106 #define R9A08G046_XSPI_HCLK 37 107 #define R9A08G046_XSPI_ACLK 38 108 #define R9A08G046_XSPI_CLK 39 109 #define R9A08G046_XSPI_CLKX2 40 110 #define R9A08G046_SDHI0_IMCLK 41 111 #define R9A08G046_SDHI0_IMCLK2 42 112 #define R9A08G046_SDHI0_CLK_HS 43 113 #define R9A08G046_SDHI0_IACLKS 44 114 #define R9A08G046_SDHI0_IACLKM 45 115 #define R9A08G046_SDHI1_IMCLK 46 116 #define R9A08G046_SDHI1_IMCLK2 47 117 #define R9A08G046_SDHI1_CLK_HS 48 118 #define R9A08G046_SDHI1_IACLKS 49 119 #define R9A08G046_SDHI1_IACLKM 50 120 #define R9A08G046_SDHI2_IMCLK 51 121 #define R9A08G046_SDHI2_IMCLK2 52 122 #define R9A08G046_SDHI2_CLK_HS 53 123 #define R9A08G046_SDHI2_IACLKS 54 124 #define R9A08G046_SDHI2_IACLKM 55 125 #define R9A08G046_GE3D_CLK 56 126 #define R9A08G046_GE3D_AXI_CLK 57 127 #define R9A08G046_GE3D_ACE_CLK 58 128 #define R9A08G046_ISU_ACLK 59 129 #define R9A08G046_ISU_PCLK 60 130 #define R9A08G046_H264_CLK_A 61 131 #define R9A08G046_H264_CLK_P 62 132 #define R9A08G046_CRU_SYSCLK 63 133 #define R9A08G046_CRU_VCLK 64 134 #define R9A08G046_CRU_PCLK 65 135 #define R9A08G046_CRU_ACLK 66 136 #define R9A08G046_MIPI_DSI_SYSCLK 67 137 #define R9A08G046_MIPI_DSI_ACLK 68 138 #define R9A08G046_MIPI_DSI_PCLK 69 139 #define R9A08G046_MIPI_DSI_VCLK 70 140 #define R9A08G046_MIPI_DSI_LPCLK 71 141 #define R9A08G046_LVDS_PLLCLK 72 142 #define R9A08G046_LVDS_CLK_DOT0 73 143 #define R9A08G046_LCDC_CLK_A 74 144 #define R9A08G046_LCDC_CLK_D 75 145 #define R9A08G046_LCDC_CLK_P 76 146 #define R9A08G046_SSI0_PCLK2 77 147 #define R9A08G046_SSI0_PCLK_SFR 78 148 #define R9A08G046_SSI1_PCLK2 79 149 #define R9A08G046_SSI1_PCLK_SFR 80 150 #define R9A08G046_SSI2_PCLK2 81 151 #define R9A08G046_SSI2_PCLK_SFR 82 152 #define R9A08G046_SSI3_PCLK2 83 153 #define R9A08G046_SSI3_PCLK_SFR 84 154 #define R9A08G046_USB_U2H0_HCLK 85 155 #define R9A08G046_USB_U2H1_HCLK 86 156 #define R9A08G046_USB_U2P0_EXR_CPUCLK 87 157 #define R9A08G046_USB_U2P1_EXR_CPUCLK 88 158 #define R9A08G046_USB_PCLK 89 159 #define R9A08G046_ETH0_CLK_AXI 90 160 #define R9A08G046_ETH0_CLK_CHI 91 161 #define R9A08G046_ETH0_CLK_TX_I 92 162 #define R9A08G046_ETH0_CLK_RX_I 93 163 #define R9A08G046_ETH0_CLK_TX_180_I 94 164 #define R9A08G046_ETH0_CLK_RX_180_I 95 165 #define R9A08G046_ETH0_CLK_RMII_I 96 166 #define R9A08G046_ETH0_CLK_PTP_REF_I 97 167 #define R9A08G046_ETH0_CLK_TX_I_RMII 98 168 #define R9A08G046_ETH0_CLK_RX_I_RMII 99 169 #define R9A08G046_ETH1_CLK_AXI 100 170 #define R9A08G046_ETH1_CLK_CHI 101 171 #define R9A08G046_ETH1_CLK_TX_I 102 172 #define R9A08G046_ETH1_CLK_RX_I 103 173 #define R9A08G046_ETH1_CLK_TX_180_I 104 174 #define R9A08G046_ETH1_CLK_RX_180_I 105 175 #define R9A08G046_ETH1_CLK_RMII_I 106 176 #define R9A08G046_ETH1_CLK_PTP_REF_I 107 177 #define R9A08G046_ETH1_CLK_TX_I_RMII 108 178 #define R9A08G046_ETH1_CLK_RX_I_RMII 109 179 #define R9A08G046_I2C0_PCLK 110 180 #define R9A08G046_I2C1_PCLK 111 181 #define R9A08G046_I2C2_PCLK 112 182 #define R9A08G046_I2C3_PCLK 113 183 #define R9A08G046_SCIF0_CLK_PCK 114 184 #define R9A08G046_SCIF1_CLK_PCK 115 185 #define R9A08G046_SCIF2_CLK_PCK 116 186 #define R9A08G046_SCIF3_CLK_PCK 117 187 #define R9A08G046_SCIF4_CLK_PCK 118 188 #define R9A08G046_SCIF5_CLK_PCK 119 189 #define R9A08G046_RSCI0_PCLK 120 190 #define R9A08G046_RSCI0_TCLK 121 191 #define R9A08G046_RSCI1_PCLK 122 192 #define R9A08G046_RSCI1_TCLK 123 193 #define R9A08G046_RSCI2_PCLK 124 194 #define R9A08G046_RSCI2_TCLK 125 195 #define R9A08G046_RSCI3_PCLK 126 196 #define R9A08G046_RSCI3_TCLK 127 197 #define R9A08G046_RSPI0_PCLK 128 198 #define R9A08G046_RSPI0_TCLK 129 199 #define R9A08G046_RSPI1_PCLK 130 200 #define R9A08G046_RSPI1_TCLK 131 201 #define R9A08G046_RSPI2_PCLK 132 202 #define R9A08G046_RSPI2_TCLK 133 203 #define R9A08G046_CANFD_PCLK 134 204 #define R9A08G046_CANFD_CLK_RAM 135 205 #define R9A08G046_GPIO_HCLK 136 206 #define R9A08G046_ADC0_ADCLK 137 207 #define R9A08G046_ADC0_PCLK 138 208 #define R9A08G046_ADC1_ADCLK 139 209 #define R9A08G046_ADC1_PCLK 140 210 #define R9A08G046_TSU_PCLK 141 211 #define R9A08G046_PDM_PCLK 142 212 #define R9A08G046_PDM_CCLK 143 213 #define R9A08G046_PCI_ACLK 144 214 #define R9A08G046_PCI_CLKL1PM 145 215 #define R9A08G046_PCI_CLK_PMU 146 216 #define R9A08G046_SPDIF_PCLK 147 217 #define R9A08G046_I3C_TCLK 148 218 #define R9A08G046_I3C_PCLK 149 219 #define R9A08G046_VBAT_BCLK 150 220 #define R9A08G046_BSC_X_BCK_BSC 151 221 222 /* R9A08G046 Resets */ 223 #define R9A08G046_CA55_RST0_0 0 224 #define R9A08G046_CA55_RST0_1 1 225 #define R9A08G046_CA55_RST0_2 2 226 #define R9A08G046_CA55_RST0_3 3 227 #define R9A08G046_CA55_RST4_0 4 228 #define R9A08G046_CA55_RST4_1 5 229 #define R9A08G046_CA55_RST4_2 6 230 #define R9A08G046_CA55_RST4_3 7 231 #define R9A08G046_CA55_RST8 8 232 #define R9A08G046_CA55_RST9 9 233 #define R9A08G046_CA55_RST10 10 234 #define R9A08G046_CA55_RST11 11 235 #define R9A08G046_CA55_RST12 12 236 #define R9A08G046_CA55_RST13 13 237 #define R9A08G046_CA55_RST14 14 238 #define R9A08G046_CA55_RST15 15 239 #define R9A08G046_CA55_RST16 16 240 #define R9A08G046_SRAM_ACPU_ARESETN0 17 241 #define R9A08G046_SRAM_ACPU_ARESETN1 18 242 #define R9A08G046_SRAM_ACPU_ARESETN2 19 243 #define R9A08G046_GIC600_GICRESET_N 20 244 #define R9A08G046_GIC600_DBG_GICRESET_N 21 245 #define R9A08G046_IA55_RESETN 22 246 #define R9A08G046_MHU_RESETN 23 247 #define R9A08G046_SYC_RESETN 24 248 #define R9A08G046_DMAC_ARESETN 25 249 #define R9A08G046_DMAC_RST_ASYNC 26 250 #define R9A08G046_GTM0_PRESETZ 27 251 #define R9A08G046_GTM1_PRESETZ 28 252 #define R9A08G046_GTM2_PRESETZ 29 253 #define R9A08G046_MTU_X_PRESET_MTU3 30 254 #define R9A08G046_POE3_RST_M_REG 31 255 #define R9A08G046_GPT_RST_C 32 256 #define R9A08G046_POEG_A_RST 33 257 #define R9A08G046_POEG_B_RST 34 258 #define R9A08G046_POEG_C_RST 35 259 #define R9A08G046_POEG_D_RST 36 260 #define R9A08G046_WDT0_PRESETN 37 261 #define R9A08G046_WDT1_PRESETN 38 262 #define R9A08G046_WDT2_PRESETN 39 263 #define R9A08G046_XSPI_HRESETN 40 264 #define R9A08G046_XSPI_ARESETN 41 265 #define R9A08G046_SDHI0_IXRST 42 266 #define R9A08G046_SDHI1_IXRST 43 267 #define R9A08G046_SDHI2_IXRST 44 268 #define R9A08G046_SDHI0_IXRSTAXIM 45 269 #define R9A08G046_SDHI0_IXRSTAXIS 46 270 #define R9A08G046_SDHI1_IXRSTAXIM 47 271 #define R9A08G046_SDHI1_IXRSTAXIS 48 272 #define R9A08G046_SDHI2_IXRSTAXIM 49 273 #define R9A08G046_SDHI2_IXRSTAXIS 50 274 #define R9A08G046_GE3D_RESETN 51 275 #define R9A08G046_GE3D_AXI_RESETN 52 276 #define R9A08G046_GE3D_ACE_RESETN 53 277 #define R9A08G046_ISU_ARESETN 54 278 #define R9A08G046_ISU_PRESETN 55 279 #define R9A08G046_H264_X_RESET_VCP 56 280 #define R9A08G046_H264_CP_PRESET_P 57 281 #define R9A08G046_CRU_CMN_RSTB 58 282 #define R9A08G046_CRU_PRESETN 59 283 #define R9A08G046_CRU_ARESETN 60 284 #define R9A08G046_MIPI_DSI_CMN_RSTB 61 285 #define R9A08G046_MIPI_DSI_ARESET_N 62 286 #define R9A08G046_MIPI_DSI_PRESET_N 63 287 #define R9A08G046_LCDC_RESET_N 64 288 #define R9A08G046_SSI0_RST_M2_REG 65 289 #define R9A08G046_SSI1_RST_M2_REG 66 290 #define R9A08G046_SSI2_RST_M2_REG 67 291 #define R9A08G046_SSI3_RST_M2_REG 68 292 #define R9A08G046_USB_U2H0_HRESETN 69 293 #define R9A08G046_USB_U2H1_HRESETN 70 294 #define R9A08G046_USB_U2P0_EXL_SYSRST 71 295 #define R9A08G046_USB_PRESETN 72 296 #define R9A08G046_USB_U2P1_EXL_SYSRST 73 297 #define R9A08G046_ETH0_ARESET_N 74 298 #define R9A08G046_ETH1_ARESET_N 75 299 #define R9A08G046_I2C0_MRST 76 300 #define R9A08G046_I2C1_MRST 77 301 #define R9A08G046_I2C2_MRST 78 302 #define R9A08G046_I2C3_MRST 79 303 #define R9A08G046_SCIF0_RST_SYSTEM_N 80 304 #define R9A08G046_SCIF1_RST_SYSTEM_N 81 305 #define R9A08G046_SCIF2_RST_SYSTEM_N 82 306 #define R9A08G046_SCIF3_RST_SYSTEM_N 83 307 #define R9A08G046_SCIF4_RST_SYSTEM_N 84 308 #define R9A08G046_SCIF5_RST_SYSTEM_N 85 309 #define R9A08G046_RSPI0_PRESETN 86 310 #define R9A08G046_RSPI1_PRESETN 87 311 #define R9A08G046_RSPI2_PRESETN 88 312 #define R9A08G046_RSPI0_TRESETN 89 313 #define R9A08G046_RSPI1_TRESETN 90 314 #define R9A08G046_RSPI2_TRESETN 91 315 #define R9A08G046_CANFD_RSTP_N 92 316 #define R9A08G046_CANFD_RSTC_N 93 317 #define R9A08G046_GPIO_RSTN 94 318 #define R9A08G046_GPIO_PORT_RESETN 95 319 #define R9A08G046_GPIO_SPARE_RESETN 96 320 #define R9A08G046_ADC0_PRESETN 97 321 #define R9A08G046_ADC0_ADRST_N 98 322 #define R9A08G046_ADC1_PRESETN 99 323 #define R9A08G046_ADC1_ADRST_N 100 324 #define R9A08G046_TSU_PRESETN 101 325 #define R9A08G046_PDM_PRESETN 102 326 #define R9A08G046_PCI_ARESETN 103 327 #define R9A08G046_SPDIF_RST 104 328 #define R9A08G046_I3C_TRESETN 105 329 #define R9A08G046_I3C_PRESETN 106 330 #define R9A08G046_VBAT_BRESETN 107 331 #define R9A08G046_RSCI0_PRESETN 108 332 #define R9A08G046_RSCI1_PRESETN 109 333 #define R9A08G046_RSCI2_PRESETN 110 334 #define R9A08G046_RSCI3_PRESETN 111 335 #define R9A08G046_RSCI0_TRESETN 112 336 #define R9A08G046_RSCI1_TRESETN 113 337 #define R9A08G046_RSCI2_TRESETN 114 338 #define R9A08G046_RSCI3_TRESETN 115 339 #define R9A08G046_LVDS_RESET_N 116 340 #define R9A08G046_BSC_X_PRESET_BSC 117 341 342 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ */ 343