1*54ce17ddSBiju Das /* SPDX-License-Identifier: GPL-2.0 2*54ce17ddSBiju Das * 3*54ce17ddSBiju Das * Copyright (C) 2019 Renesas Electronics Corp. 4*54ce17ddSBiju Das */ 5*54ce17ddSBiju Das #ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ 6*54ce17ddSBiju Das #define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ 7*54ce17ddSBiju Das 8*54ce17ddSBiju Das #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*54ce17ddSBiju Das 10*54ce17ddSBiju Das /* r8a774b1 CPG Core Clocks */ 11*54ce17ddSBiju Das #define R8A774B1_CLK_Z 0 12*54ce17ddSBiju Das #define R8A774B1_CLK_ZG 1 13*54ce17ddSBiju Das #define R8A774B1_CLK_ZTR 2 14*54ce17ddSBiju Das #define R8A774B1_CLK_ZTRD2 3 15*54ce17ddSBiju Das #define R8A774B1_CLK_ZT 4 16*54ce17ddSBiju Das #define R8A774B1_CLK_ZX 5 17*54ce17ddSBiju Das #define R8A774B1_CLK_S0D1 6 18*54ce17ddSBiju Das #define R8A774B1_CLK_S0D2 7 19*54ce17ddSBiju Das #define R8A774B1_CLK_S0D3 8 20*54ce17ddSBiju Das #define R8A774B1_CLK_S0D4 9 21*54ce17ddSBiju Das #define R8A774B1_CLK_S0D6 10 22*54ce17ddSBiju Das #define R8A774B1_CLK_S0D8 11 23*54ce17ddSBiju Das #define R8A774B1_CLK_S0D12 12 24*54ce17ddSBiju Das #define R8A774B1_CLK_S1D2 13 25*54ce17ddSBiju Das #define R8A774B1_CLK_S1D4 14 26*54ce17ddSBiju Das #define R8A774B1_CLK_S2D1 15 27*54ce17ddSBiju Das #define R8A774B1_CLK_S2D2 16 28*54ce17ddSBiju Das #define R8A774B1_CLK_S2D4 17 29*54ce17ddSBiju Das #define R8A774B1_CLK_S3D1 18 30*54ce17ddSBiju Das #define R8A774B1_CLK_S3D2 19 31*54ce17ddSBiju Das #define R8A774B1_CLK_S3D4 20 32*54ce17ddSBiju Das #define R8A774B1_CLK_LB 21 33*54ce17ddSBiju Das #define R8A774B1_CLK_CL 22 34*54ce17ddSBiju Das #define R8A774B1_CLK_ZB3 23 35*54ce17ddSBiju Das #define R8A774B1_CLK_ZB3D2 24 36*54ce17ddSBiju Das #define R8A774B1_CLK_CR 25 37*54ce17ddSBiju Das #define R8A774B1_CLK_DDR 26 38*54ce17ddSBiju Das #define R8A774B1_CLK_SD0H 27 39*54ce17ddSBiju Das #define R8A774B1_CLK_SD0 28 40*54ce17ddSBiju Das #define R8A774B1_CLK_SD1H 29 41*54ce17ddSBiju Das #define R8A774B1_CLK_SD1 30 42*54ce17ddSBiju Das #define R8A774B1_CLK_SD2H 31 43*54ce17ddSBiju Das #define R8A774B1_CLK_SD2 32 44*54ce17ddSBiju Das #define R8A774B1_CLK_SD3H 33 45*54ce17ddSBiju Das #define R8A774B1_CLK_SD3 34 46*54ce17ddSBiju Das #define R8A774B1_CLK_RPC 35 47*54ce17ddSBiju Das #define R8A774B1_CLK_RPCD2 36 48*54ce17ddSBiju Das #define R8A774B1_CLK_MSO 37 49*54ce17ddSBiju Das #define R8A774B1_CLK_HDMI 38 50*54ce17ddSBiju Das #define R8A774B1_CLK_CSI0 39 51*54ce17ddSBiju Das #define R8A774B1_CLK_CP 40 52*54ce17ddSBiju Das #define R8A774B1_CLK_CPEX 41 53*54ce17ddSBiju Das #define R8A774B1_CLK_R 42 54*54ce17ddSBiju Das #define R8A774B1_CLK_OSC 43 55*54ce17ddSBiju Das #define R8A774B1_CLK_CANFD 44 56*54ce17ddSBiju Das 57*54ce17ddSBiju Das #endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ 58