1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H 7 #define _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H 8 9 /* AUDIO_CORE_CC clocks */ 10 #define AUDIO_CORE_CC_DIG_PLL_OUT_AUX 0 11 #define AUDIO_CORE_CC_DIG_PLL_OUT_AUX2 1 12 #define AUDIO_CORE_CC_DIG_PLL 2 13 #define AUDIO_CORE_CC_AIF_IF0_CLK_SRC 3 14 #define AUDIO_CORE_CC_AIF_IF0_EBIT_CLK 4 15 #define AUDIO_CORE_CC_AIF_IF0_IBIT_CLK 5 16 #define AUDIO_CORE_CC_AIF_IF1_CLK_SRC 6 17 #define AUDIO_CORE_CC_AIF_IF1_EBIT_CLK 7 18 #define AUDIO_CORE_CC_AIF_IF1_IBIT_CLK 8 19 #define AUDIO_CORE_CC_AIF_IF2_CLK_SRC 9 20 #define AUDIO_CORE_CC_AIF_IF2_EBIT_CLK 10 21 #define AUDIO_CORE_CC_AIF_IF2_IBIT_CLK 11 22 #define AUDIO_CORE_CC_AIF_IF3_CLK_SRC 12 23 #define AUDIO_CORE_CC_AIF_IF3_EBIT_CLK 13 24 #define AUDIO_CORE_CC_AIF_IF3_IBIT_CLK 14 25 #define AUDIO_CORE_CC_AUD_DMA_CLK 15 26 #define AUDIO_CORE_CC_AUD_DMA_CLK_SRC 16 27 #define AUDIO_CORE_CC_AUD_DMA_MEM_CLK 17 28 #define AUDIO_CORE_CC_BUS_CLK 18 29 #define AUDIO_CORE_CC_BUS_CLK_SRC 19 30 #define AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC 20 31 #define AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC 21 32 #define AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK 22 33 #define AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC 23 34 #define AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK 24 35 #define AUDIO_CORE_CC_IM_SLEEP_CLK 25 36 #define AUDIO_CORE_CC_LPAIF_PCMOE_CLK 26 37 #define AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC 27 38 #define AUDIO_CORE_CC_RX_MCLK_2X_CLK 28 39 #define AUDIO_CORE_CC_RX_MCLK_CLK 29 40 #define AUDIO_CORE_CC_SAMPLING_CLK 30 41 #define AUDIO_CORE_CC_TX_MCLK_2X_CLK 31 42 #define AUDIO_CORE_CC_TX_MCLK_CLK 32 43 #define AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC 33 44 45 /* AUDIO_CORE_CSR resets */ 46 #define AUDIO_CORE_CSR_RX_SWR_CGCR 0 47 #define AUDIO_CORE_CSR_TX_SWR_CGCR 1 48 49 #endif 50