1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H 7 #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H 8 9 /* VIDEO_CC clocks */ 10 #define VIDEO_CC_AHB_CLK 0 11 #define VIDEO_CC_AHB_CLK_SRC 1 12 #define VIDEO_CC_MVS0_CLK 2 13 #define VIDEO_CC_MVS0_CLK_SRC 3 14 #define VIDEO_CC_MVS0_FREERUN_CLK 4 15 #define VIDEO_CC_MVS0_SHIFT_CLK 5 16 #define VIDEO_CC_MVS0_VPP0_CLK 6 17 #define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 7 18 #define VIDEO_CC_MVS0_VPP1_CLK 8 19 #define VIDEO_CC_MVS0_VPP1_FREERUN_CLK 9 20 #define VIDEO_CC_MVS0A_CLK 10 21 #define VIDEO_CC_MVS0A_CLK_SRC 11 22 #define VIDEO_CC_MVS0A_FREERUN_CLK 12 23 #define VIDEO_CC_MVS0B_CLK 13 24 #define VIDEO_CC_MVS0B_CLK_SRC 14 25 #define VIDEO_CC_MVS0B_FREERUN_CLK 15 26 #define VIDEO_CC_MVS0C_CLK 16 27 #define VIDEO_CC_MVS0C_CLK_SRC 17 28 #define VIDEO_CC_MVS0C_FREERUN_CLK 18 29 #define VIDEO_CC_MVS0C_SHIFT_CLK 19 30 #define VIDEO_CC_PLL0 20 31 #define VIDEO_CC_PLL1 21 32 #define VIDEO_CC_PLL2 22 33 #define VIDEO_CC_PLL3 23 34 #define VIDEO_CC_SLEEP_CLK 24 35 #define VIDEO_CC_TS_XO_CLK 25 36 #define VIDEO_CC_XO_CLK 26 37 #define VIDEO_CC_XO_CLK_SRC 27 38 39 /* VIDEO_CC power domains */ 40 #define VIDEO_CC_MVS0A_GDSC 0 41 #define VIDEO_CC_MVS0_GDSC 1 42 #define VIDEO_CC_MVS0_VPP1_GDSC 2 43 #define VIDEO_CC_MVS0_VPP0_GDSC 3 44 #define VIDEO_CC_MVS0C_GDSC 4 45 46 /* VIDEO_CC resets */ 47 #define VIDEO_CC_INTERFACE_BCR 0 48 #define VIDEO_CC_MVS0_BCR 1 49 #define VIDEO_CC_MVS0_VPP0_BCR 2 50 #define VIDEO_CC_MVS0_VPP1_BCR 3 51 #define VIDEO_CC_MVS0A_BCR 4 52 #define VIDEO_CC_MVS0C_CLK_ARES 5 53 #define VIDEO_CC_MVS0C_BCR 6 54 #define VIDEO_CC_MVS0_FREERUN_CLK_ARES 7 55 #define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 8 56 #define VIDEO_CC_XO_CLK_ARES 9 57 58 #endif 59