1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2025 Samsung Electronics Co., Ltd. 4 * https://www.samsung.com 5 * Copyright (c) 2025 Axis Communications AB. 6 * https://www.axis.com 7 * 8 * Device Tree binding constants for ARTPEC-9 clock controller. 9 */ 10 11 #ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H 12 #define _DT_BINDINGS_CLOCK_ARTPEC9_H 13 14 /* CMU_CMU */ 15 #define CLK_FOUT_SHARED0_PLL 1 16 #define CLK_DOUT_SHARED0_DIV2 2 17 #define CLK_DOUT_SHARED0_DIV3 3 18 #define CLK_DOUT_SHARED0_DIV4 4 19 #define CLK_FOUT_SHARED1_PLL 5 20 #define CLK_DOUT_SHARED1_DIV2 6 21 #define CLK_DOUT_SHARED1_DIV3 7 22 #define CLK_DOUT_SHARED1_DIV4 8 23 #define CLK_FOUT_AUDIO_PLL 9 24 #define CLK_DOUT_CMU_ADD 10 25 #define CLK_DOUT_CMU_BUS 11 26 #define CLK_DOUT_CMU_CDC_CORE 12 27 #define CLK_DOUT_CMU_CORE_MAIN 13 28 #define CLK_DOUT_CMU_CPUCL_SWITCH 14 29 #define CLK_DOUT_CMU_DLP_CORE 15 30 #define CLK_DOUT_CMU_FSYS0_BUS 16 31 #define CLK_DOUT_CMU_FSYS0_IP 17 32 #define CLK_DOUT_CMU_FSYS1_BUS 18 33 #define CLK_DOUT_CMU_FSYS1_SCAN0 19 34 #define CLK_DOUT_CMU_FSYS1_SCAN1 20 35 #define CLK_DOUT_CMU_GPU_3D 21 36 #define CLK_DOUT_CMU_GPU_2D 22 37 #define CLK_DOUT_CMU_IMEM_ACLK 23 38 #define CLK_DOUT_CMU_IMEM_CA5 24 39 #define CLK_DOUT_CMU_IMEM_JPEG 25 40 #define CLK_DOUT_CMU_IMEM_SSS 26 41 #define CLK_DOUT_CMU_IPA_CORE 27 42 #define CLK_DOUT_CMU_LCPU 28 43 #define CLK_DOUT_CMU_MIF_SWITCH 29 44 #define CLK_DOUT_CMU_MIF_BUSP 30 45 #define CLK_DOUT_CMU_PERI_DISP 31 46 #define CLK_DOUT_CMU_PERI_IP 32 47 #define CLK_DOUT_CMU_RSP_CORE 33 48 #define CLK_DOUT_CMU_TRFM 34 49 #define CLK_DOUT_CMU_VIO_CORE_L 35 50 #define CLK_DOUT_CMU_VIO_CORE 36 51 #define CLK_DOUT_CMU_VIP0 37 52 #define CLK_DOUT_CMU_VIP1 38 53 #define CLK_DOUT_CMU_VPP_CORE 39 54 #define CLK_DOUT_CMU_VIO_AUDIO 40 55 56 /* CMU_BUS */ 57 #define CLK_MOUT_BUS_ACLK_USER 1 58 59 /* CMU_CORE */ 60 #define CLK_MOUT_CORE_ACLK_USER 1 61 62 /* CMU_CPUCL */ 63 #define CLK_FOUT_CPUCL_PLL0 1 64 #define CLK_MOUT_CPUCL_PLL0 2 65 #define CLK_FOUT_CPUCL_PLL1 3 66 #define CLK_MOUT_CPUCL_PLL_SCU 4 67 #define CLK_MOUT_CPUCL_SWITCH_SCU_USER 5 68 #define CLK_MOUT_CPUCL_SWITCH_USER 6 69 #define CLK_DOUT_CPUCL_CPU 7 70 #define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK 8 71 #define CLK_DOUT_CPUCL_CLUSTER_GICCLK 9 72 #define CLK_DOUT_CPUCL_CLUSTER_PCLK 10 73 #define CLK_DOUT_CPUCL_CMUREF 11 74 #define CLK_DOUT_CPUCL_CLUSTER_ATCLK 12 75 #define CLK_DOUT_CPUCL_CLUSTER_SCU 13 76 #define CLK_DOUT_CPUCL_DBG 14 77 #define CLK_GOUT_CPUCL_SHORTSTOP 15 78 #define CLK_GOUT_CPUCL_CLUSTER_CPU 16 79 #define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 17 80 #define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 18 81 82 /* CMU_FSYS0 */ 83 #define CLK_MOUT_FSYS0_BUS_USER 1 84 #define CLK_MOUT_FSYS0_IP_USER 2 85 #define CLK_MOUT_FSYS0_MAIN_USER 3 86 #define CLK_DOUT_FSYS0_125 4 87 #define CLK_DOUT_FSYS0_ADC 5 88 #define CLK_DOUT_FSYS0_BUS_300 6 89 #define CLK_DOUT_FSYS0_EQOS0 7 90 #define CLK_DOUT_FSYS0_EQOS1 8 91 #define CLK_DOUT_FSYS0_MMC_CARD0 9 92 #define CLK_DOUT_FSYS0_MMC_CARD1 10 93 #define CLK_DOUT_FSYS0_MMC_CARD2 11 94 #define CLK_DOUT_FSYS0_QSPI 12 95 #define CLK_DOUT_FSYS0_SFMC_NAND 13 96 #define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 14 97 #define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I 15 98 #define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250 16 99 #define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK 17 100 #define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250 18 101 #define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK 19 102 #define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I 20 103 #define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I 21 104 #define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK 22 105 #define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK 23 106 #define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK 24 107 #define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK 25 108 #define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK 26 109 #define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK 27 110 #define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK 28 111 #define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK 29 112 #define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN 30 113 #define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN 31 114 #define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN 32 115 #define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK 33 116 #define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK 34 117 #define CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND 35 118 #define CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK 36 119 #define CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK 37 120 #define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK 38 121 #define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK 39 122 #define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK 40 123 #define CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0 41 124 125 /* CMU_FSYS1 */ 126 #define CLK_FOUT_FSYS1_PLL 1 127 #define CLK_MOUT_FSYS1_SCAN0_USER 2 128 #define CLK_MOUT_FSYS1_SCAN1_USER 3 129 #define CLK_MOUT_FSYS1_BUS_USER 4 130 #define CLK_DOUT_FSYS1_200 5 131 #define CLK_DOUT_FSYS1_BUS_300 6 132 #define CLK_DOUT_FSYS1_OTP_MEM 7 133 #define CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL 8 134 #define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100 9 135 #define CLK_GOUT_FSYS1_UART0_PCLK 10 136 #define CLK_GOUT_FSYS1_UART0_SCLK_UART 11 137 #define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300 12 138 #define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC 13 139 #define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC 14 140 #define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC 15 141 #define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC 16 142 #define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC 17 143 #define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC 18 144 #define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 19 145 #define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 20 146 #define CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK 21 147 #define CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK 22 148 149 /* CMU_IMEM */ 150 #define CLK_MOUT_IMEM_ACLK_USER 1 151 #define CLK_MOUT_IMEM_CA5_USER 2 152 #define CLK_MOUT_IMEM_SSS_USER 3 153 #define CLK_MOUT_IMEM_JPEG_USER 4 154 #define CLK_DOUT_IMEM_PCLK 5 155 #define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK 6 156 #define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN 7 157 #define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG 8 158 #define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK 9 159 #define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN 10 160 #define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG 11 161 #define CLK_GOUT_IMEM_MCT0_PCLK 12 162 #define CLK_GOUT_IMEM_MCT1_PCLK 13 163 #define CLK_GOUT_IMEM_MCT2_PCLK 14 164 #define CLK_GOUT_IMEM_MCT3_PCLK 15 165 #define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 16 166 167 /* CMU_PERI */ 168 #define CLK_MOUT_PERI_IP_USER 1 169 #define CLK_MOUT_PERI_DISP_USER 2 170 #define CLK_DOUT_PERI_125 3 171 #define CLK_DOUT_PERI_PCLK 4 172 #define CLK_DOUT_PERI_SPI 5 173 #define CLK_DOUT_PERI_UART1 6 174 #define CLK_DOUT_PERI_UART2 7 175 #define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 8 176 #define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 9 177 #define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK 10 178 #define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK 11 179 #define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK 12 180 #define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK 13 181 #define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK 14 182 #define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK 15 183 #define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK 16 184 #define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK 17 185 #define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 18 186 #define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 19 187 #define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 20 188 #define CLK_GOUT_PERI_SPI0_PCLK 21 189 #define CLK_GOUT_PERI_SPI0_SCLK_SPI 22 190 #define CLK_GOUT_PERI_UART1_PCLK 23 191 #define CLK_GOUT_PERI_UART1_SCLK_UART 24 192 #define CLK_GOUT_PERI_UART2_PCLK 25 193 #define CLK_GOUT_PERI_UART2_SCLK_UART 26 194 195 #endif /* _DT_BINDINGS_CLOCK_ARTPEC9_H */ 196