1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 /* 3 * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved 4 */ 5 6 #ifndef __T7_PLL_CLKC_H 7 #define __T7_PLL_CLKC_H 8 9 /* GP0 */ 10 #define CLKID_GP0_PLL_DCO 0 11 #define CLKID_GP0_PLL 1 12 13 /* GP1 */ 14 #define CLKID_GP1_PLL_DCO 0 15 #define CLKID_GP1_PLL 1 16 17 /* HIFI */ 18 #define CLKID_HIFI_PLL_DCO 0 19 #define CLKID_HIFI_PLL 1 20 21 /* PCIE */ 22 #define CLKID_PCIE_PLL_DCO 0 23 #define CLKID_PCIE_PLL_DCO_DIV2 1 24 #define CLKID_PCIE_PLL_OD 2 25 #define CLKID_PCIE_PLL 3 26 27 /* MPLL */ 28 #define CLKID_MPLL_PREDIV 0 29 #define CLKID_MPLL0_DIV 1 30 #define CLKID_MPLL0 2 31 #define CLKID_MPLL1_DIV 3 32 #define CLKID_MPLL1 4 33 #define CLKID_MPLL2_DIV 5 34 #define CLKID_MPLL2 6 35 #define CLKID_MPLL3_DIV 7 36 #define CLKID_MPLL3 8 37 38 /* HDMI */ 39 #define CLKID_HDMI_PLL_DCO 0 40 #define CLKID_HDMI_PLL_OD 1 41 #define CLKID_HDMI_PLL 2 42 43 /* MCLK */ 44 #define CLKID_MCLK_PLL_DCO 0 45 #define CLKID_MCLK_PRE 1 46 #define CLKID_MCLK_PLL 2 47 #define CLKID_MCLK_0_SEL 3 48 #define CLKID_MCLK_0_DIV2 4 49 #define CLKID_MCLK_0_PRE 5 50 #define CLKID_MCLK_0 6 51 #define CLKID_MCLK_1_SEL 7 52 #define CLKID_MCLK_1_DIV2 8 53 #define CLKID_MCLK_1_PRE 9 54 #define CLKID_MCLK_1 10 55 56 #endif /* __T7_PLL_CLKC_H */ 57