xref: /linux/scripts/dtc/include-prefixes/arm64/xilinx/xlnx-versal-net-resets.h (revision 67f8bc848ee31831336bd478e57d2f993551902e)
1*e1ab33a3SMichal Simek /* SPDX-License-Identifier: GPL-2.0 */
2*e1ab33a3SMichal Simek /*
3*e1ab33a3SMichal Simek  * Copyright (C) 2022, Xilinx, Inc.
4*e1ab33a3SMichal Simek  * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
5*e1ab33a3SMichal Simek  */
6*e1ab33a3SMichal Simek 
7*e1ab33a3SMichal Simek #ifndef _XLNX_VERSAL_NET_RESETS_H
8*e1ab33a3SMichal Simek #define _XLNX_VERSAL_NET_RESETS_H
9*e1ab33a3SMichal Simek 
10*e1ab33a3SMichal Simek #include "xlnx-versal-resets.h"
11*e1ab33a3SMichal Simek 
12*e1ab33a3SMichal Simek #define VERSAL_RST_USB_1			(0xc1040c6U)
13*e1ab33a3SMichal Simek 
14*e1ab33a3SMichal Simek /* Remove Versal specific reset IDs */
15*e1ab33a3SMichal Simek #undef VERSAL_RST_ACPU_0_POR
16*e1ab33a3SMichal Simek #undef VERSAL_RST_ACPU_1_POR
17*e1ab33a3SMichal Simek #undef VERSAL_RST_OCM2_POR
18*e1ab33a3SMichal Simek #undef VERSAL_RST_APU
19*e1ab33a3SMichal Simek #undef VERSAL_RST_ACPU_0
20*e1ab33a3SMichal Simek #undef VERSAL_RST_ACPU_1
21*e1ab33a3SMichal Simek #undef VERSAL_RST_ACPU_L2
22*e1ab33a3SMichal Simek #undef VERSAL_RST_RPU_ISLAND
23*e1ab33a3SMichal Simek #undef VERSAL_RST_RPU_AMBA
24*e1ab33a3SMichal Simek #undef VERSAL_RST_R5_0
25*e1ab33a3SMichal Simek #undef VERSAL_RST_R5_1
26*e1ab33a3SMichal Simek #undef VERSAL_RST_OCM2_RST
27*e1ab33a3SMichal Simek #undef VERSAL_RST_I2C_PMC
28*e1ab33a3SMichal Simek #undef VERSAL_RST_I2C_0
29*e1ab33a3SMichal Simek #undef VERSAL_RST_I2C_1
30*e1ab33a3SMichal Simek #undef VERSAL_RST_SWDT_FPD
31*e1ab33a3SMichal Simek #undef VERSAL_RST_SWDT_LPD
32*e1ab33a3SMichal Simek #undef VERSAL_RST_USB
33*e1ab33a3SMichal Simek #undef VERSAL_RST_DPC
34*e1ab33a3SMichal Simek #undef VERSAL_RST_DBG_TRACE
35*e1ab33a3SMichal Simek #undef VERSAL_RST_DBG_TSTMP
36*e1ab33a3SMichal Simek #undef VERSAL_RST_RPU0_DBG
37*e1ab33a3SMichal Simek #undef VERSAL_RST_RPU1_DBG
38*e1ab33a3SMichal Simek #undef VERSAL_RST_HSDP
39*e1ab33a3SMichal Simek #undef VERSAL_RST_CPMDBG
40*e1ab33a3SMichal Simek #undef VERSAL_RST_PCIE_CFG
41*e1ab33a3SMichal Simek #undef VERSAL_RST_PCIE_CORE0
42*e1ab33a3SMichal Simek #undef VERSAL_RST_PCIE_CORE1
43*e1ab33a3SMichal Simek #undef VERSAL_RST_PCIE_DMA
44*e1ab33a3SMichal Simek #undef VERSAL_RST_L2_0
45*e1ab33a3SMichal Simek #undef VERSAL_RST_L2_1
46*e1ab33a3SMichal Simek #undef VERSAL_RST_ADDR_REMAP
47*e1ab33a3SMichal Simek #undef VERSAL_RST_CPI0
48*e1ab33a3SMichal Simek #undef VERSAL_RST_CPI1
49*e1ab33a3SMichal Simek #undef VERSAL_RST_XRAM
50*e1ab33a3SMichal Simek #undef VERSAL_RST_AIE_ARRAY
51*e1ab33a3SMichal Simek #undef VERSAL_RST_AIE_SHIM
52*e1ab33a3SMichal Simek 
53*e1ab33a3SMichal Simek #endif
54