1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx Versal NET 4 * 5 * (C) Copyright 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11/dts-v1/; 12 13/ { 14 compatible = "xlnx,versal-net"; 15 model = "Xilinx Versal NET"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 options { 21 u-boot { 22 compatible = "u-boot,config"; 23 bootscr-address = /bits/ 64 <0x20000000>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 cpu-map { 31 cluster0 { 32 core0 { 33 cpu = <&cpu0>; 34 }; 35 core1 { 36 cpu = <&cpu100>; 37 }; 38 core2 { 39 cpu = <&cpu200>; 40 }; 41 core3 { 42 cpu = <&cpu300>; 43 }; 44 }; 45 46 cluster1 { 47 core0 { 48 cpu = <&cpu10000>; 49 }; 50 51 core1 { 52 cpu = <&cpu10100>; 53 }; 54 55 core2 { 56 cpu = <&cpu10200>; 57 }; 58 59 core3 { 60 cpu = <&cpu10300>; 61 }; 62 }; 63 cluster2 { 64 core0 { 65 cpu = <&cpu20000>; 66 }; 67 68 core1 { 69 cpu = <&cpu20100>; 70 }; 71 72 core2 { 73 cpu = <&cpu20200>; 74 }; 75 76 core3 { 77 cpu = <&cpu20300>; 78 }; 79 }; 80 cluster3 { 81 core0 { 82 cpu = <&cpu30000>; 83 }; 84 85 core1 { 86 cpu = <&cpu30100>; 87 }; 88 89 core2 { 90 cpu = <&cpu30200>; 91 }; 92 93 core3 { 94 cpu = <&cpu30300>; 95 }; 96 }; 97 98 }; 99 100 cpu0: cpu@0 { 101 compatible = "arm,cortex-a78"; 102 device_type = "cpu"; 103 enable-method = "psci"; 104 reg = <0>; 105 operating-points-v2 = <&cpu_opp_table>; 106 cpu-idle-states = <&CPU_SLEEP_0>; 107 }; 108 cpu100: cpu@100 { 109 compatible = "arm,cortex-a78"; 110 device_type = "cpu"; 111 enable-method = "psci"; 112 reg = <0x100>; 113 operating-points-v2 = <&cpu_opp_table>; 114 cpu-idle-states = <&CPU_SLEEP_0>; 115 }; 116 cpu200: cpu@200 { 117 compatible = "arm,cortex-a78"; 118 device_type = "cpu"; 119 enable-method = "psci"; 120 reg = <0x200>; 121 operating-points-v2 = <&cpu_opp_table>; 122 cpu-idle-states = <&CPU_SLEEP_0>; 123 }; 124 cpu300: cpu@300 { 125 compatible = "arm,cortex-a78"; 126 device_type = "cpu"; 127 enable-method = "psci"; 128 reg = <0x300>; 129 operating-points-v2 = <&cpu_opp_table>; 130 cpu-idle-states = <&CPU_SLEEP_0>; 131 }; 132 cpu10000: cpu@10000 { 133 compatible = "arm,cortex-a78"; 134 device_type = "cpu"; 135 enable-method = "psci"; 136 reg = <0x10000>; 137 operating-points-v2 = <&cpu_opp_table>; 138 cpu-idle-states = <&CPU_SLEEP_0>; 139 }; 140 cpu10100: cpu@10100 { 141 compatible = "arm,cortex-a78"; 142 device_type = "cpu"; 143 enable-method = "psci"; 144 reg = <0x10100>; 145 operating-points-v2 = <&cpu_opp_table>; 146 cpu-idle-states = <&CPU_SLEEP_0>; 147 }; 148 cpu10200: cpu@10200 { 149 compatible = "arm,cortex-a78"; 150 device_type = "cpu"; 151 enable-method = "psci"; 152 reg = <0x10200>; 153 operating-points-v2 = <&cpu_opp_table>; 154 cpu-idle-states = <&CPU_SLEEP_0>; 155 }; 156 cpu10300: cpu@10300 { 157 compatible = "arm,cortex-a78"; 158 device_type = "cpu"; 159 enable-method = "psci"; 160 reg = <0x10300>; 161 operating-points-v2 = <&cpu_opp_table>; 162 cpu-idle-states = <&CPU_SLEEP_0>; 163 }; 164 cpu20000: cpu@20000 { 165 compatible = "arm,cortex-a78"; 166 device_type = "cpu"; 167 enable-method = "psci"; 168 reg = <0x20000>; 169 operating-points-v2 = <&cpu_opp_table>; 170 cpu-idle-states = <&CPU_SLEEP_0>; 171 }; 172 cpu20100: cpu@20100 { 173 compatible = "arm,cortex-a78"; 174 device_type = "cpu"; 175 enable-method = "psci"; 176 reg = <0x20100>; 177 operating-points-v2 = <&cpu_opp_table>; 178 cpu-idle-states = <&CPU_SLEEP_0>; 179 }; 180 cpu20200: cpu@20200 { 181 compatible = "arm,cortex-a78"; 182 device_type = "cpu"; 183 enable-method = "psci"; 184 reg = <0x20200>; 185 operating-points-v2 = <&cpu_opp_table>; 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 }; 188 cpu20300: cpu@20300 { 189 compatible = "arm,cortex-a78"; 190 device_type = "cpu"; 191 enable-method = "psci"; 192 reg = <0x20300>; 193 operating-points-v2 = <&cpu_opp_table>; 194 cpu-idle-states = <&CPU_SLEEP_0>; 195 }; 196 cpu30000: cpu@30000 { 197 compatible = "arm,cortex-a78"; 198 device_type = "cpu"; 199 enable-method = "psci"; 200 reg = <0x30000>; 201 operating-points-v2 = <&cpu_opp_table>; 202 cpu-idle-states = <&CPU_SLEEP_0>; 203 }; 204 cpu30100: cpu@30100 { 205 compatible = "arm,cortex-a78"; 206 device_type = "cpu"; 207 enable-method = "psci"; 208 reg = <0x30100>; 209 operating-points-v2 = <&cpu_opp_table>; 210 cpu-idle-states = <&CPU_SLEEP_0>; 211 }; 212 cpu30200: cpu@30200 { 213 compatible = "arm,cortex-a78"; 214 device_type = "cpu"; 215 enable-method = "psci"; 216 reg = <0x30200>; 217 operating-points-v2 = <&cpu_opp_table>; 218 cpu-idle-states = <&CPU_SLEEP_0>; 219 }; 220 cpu30300: cpu@30300 { 221 compatible = "arm,cortex-a78"; 222 device_type = "cpu"; 223 enable-method = "psci"; 224 reg = <0x30300>; 225 operating-points-v2 = <&cpu_opp_table>; 226 cpu-idle-states = <&CPU_SLEEP_0>; 227 }; 228 idle-states { 229 entry-method = "psci"; 230 231 CPU_SLEEP_0: cpu-sleep-0 { 232 compatible = "arm,idle-state"; 233 arm,psci-suspend-param = <0x40000000>; 234 local-timer-stop; 235 entry-latency-us = <300>; 236 exit-latency-us = <600>; 237 min-residency-us = <10000>; 238 }; 239 }; 240 }; 241 242 cpu_opp_table: opp-table { 243 compatible = "operating-points-v2"; 244 opp-1066000000 { 245 opp-hz = /bits/ 64 <1066000000>; 246 opp-microvolt = <1000000>; 247 clock-latency-ns = <500000>; 248 }; 249 opp-1866000000 { 250 opp-hz = /bits/ 64 <1866000000>; 251 opp-microvolt = <1000000>; 252 clock-latency-ns = <500000>; 253 }; 254 opp-1900000000 { 255 opp-hz = /bits/ 64 <1900000000>; 256 opp-microvolt = <1000000>; 257 clock-latency-ns = <500000>; 258 }; 259 opp-1999000000 { 260 opp-hz = /bits/ 64 <1999000000>; 261 opp-microvolt = <1000000>; 262 clock-latency-ns = <500000>; 263 }; 264 opp-2050000000 { 265 opp-hz = /bits/ 64 <2050000000>; 266 opp-microvolt = <1000000>; 267 clock-latency-ns = <500000>; 268 }; 269 opp-2100000000 { 270 opp-hz = /bits/ 64 <2100000000>; 271 opp-microvolt = <1000000>; 272 clock-latency-ns = <500000>; 273 }; 274 opp-2200000000 { 275 opp-hz = /bits/ 64 <2200000000>; 276 opp-microvolt = <1000000>; 277 clock-latency-ns = <500000>; 278 }; 279 opp-2400000000 { 280 opp-hz = /bits/ 64 <2400000000>; 281 opp-microvolt = <1000000>; 282 clock-latency-ns = <500000>; 283 }; 284 }; 285 286 aliases { 287 serial0 = &serial0; 288 serial1 = &serial1; 289 serial2 = &dcc; 290 mmc0 = &sdhci0; 291 mmc1 = &sdhci1; 292 i2c0 = &i2c0; 293 i2c1 = &i2c1; 294 rtc = &rtc; 295 usb0 = &usb0; 296 usb1 = &usb1; 297 spi0 = &ospi; 298 spi1 = &qspi; 299 }; 300 301 dcc: dcc { 302 compatible = "arm,dcc"; 303 status = "disabled"; 304 bootph-all; 305 }; 306 307 firmware { 308 psci { 309 compatible = "arm,psci-1.0"; 310 method = "smc"; 311 }; 312 }; 313 314 fpga: fpga-region { 315 compatible = "fpga-region"; 316 fpga-mgr = <&versal_fpga>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 }; 320 321 timer: timer { 322 compatible = "arm,armv8-timer"; 323 interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; 324 }; 325 326 versal_fpga: versal-fpga { 327 compatible = "xlnx,versal-fpga"; 328 }; 329 330 amba: axi { 331 compatible = "simple-bus"; 332 bootph-all; 333 #address-cells = <2>; 334 #size-cells = <2>; 335 ranges; 336 337 adma0: dma-controller@ebd00000 { 338 compatible = "xlnx,zynqmp-dma-1.0"; 339 status = "disabled"; 340 reg = <0 0xebd00000 0 0x1000>; 341 interrupts = <0 72 4>; 342 clock-names = "clk_main", "clk_apb"; 343 #dma-cells = <1>; 344 xlnx,bus-width = <64>; 345 }; 346 347 adma1: dma-controller@ebd10000 { 348 compatible = "xlnx,zynqmp-dma-1.0"; 349 status = "disabled"; 350 reg = <0 0xebd10000 0 0x1000>; 351 interrupts = <0 73 4>; 352 clock-names = "clk_main", "clk_apb"; 353 #dma-cells = <1>; 354 xlnx,bus-width = <64>; 355 }; 356 357 adma2: dma-controller@ebd20000 { 358 compatible = "xlnx,zynqmp-dma-1.0"; 359 status = "disabled"; 360 reg = <0 0xebd20000 0 0x1000>; 361 interrupts = <0 74 4>; 362 clock-names = "clk_main", "clk_apb"; 363 #dma-cells = <1>; 364 xlnx,bus-width = <64>; 365 }; 366 367 adma3: dma-controller@ebd30000 { 368 compatible = "xlnx,zynqmp-dma-1.0"; 369 status = "disabled"; 370 reg = <0 0xebd30000 0 0x1000>; 371 interrupts = <0 75 4>; 372 clock-names = "clk_main", "clk_apb"; 373 #dma-cells = <1>; 374 xlnx,bus-width = <64>; 375 }; 376 377 adma4: dma-controller@ebd40000 { 378 compatible = "xlnx,zynqmp-dma-1.0"; 379 status = "disabled"; 380 reg = <0 0xebd40000 0 0x1000>; 381 interrupts = <0 76 4>; 382 clock-names = "clk_main", "clk_apb"; 383 #dma-cells = <1>; 384 xlnx,bus-width = <64>; 385 }; 386 387 adma5: dma-controller@ebd50000 { 388 compatible = "xlnx,zynqmp-dma-1.0"; 389 status = "disabled"; 390 reg = <0 0xebd50000 0 0x1000>; 391 interrupts = <0 77 4>; 392 clock-names = "clk_main", "clk_apb"; 393 #dma-cells = <1>; 394 xlnx,bus-width = <64>; 395 }; 396 397 adma6: dma-controller@ebd60000 { 398 compatible = "xlnx,zynqmp-dma-1.0"; 399 status = "disabled"; 400 reg = <0 0xebd60000 0 0x1000>; 401 interrupts = <0 78 4>; 402 clock-names = "clk_main", "clk_apb"; 403 #dma-cells = <1>; 404 xlnx,bus-width = <64>; 405 }; 406 407 adma7: dma-controller@ebd70000 { 408 compatible = "xlnx,zynqmp-dma-1.0"; 409 status = "disabled"; 410 reg = <0 0xebd70000 0 0x1000>; 411 interrupts = <0 79 4>; 412 clock-names = "clk_main", "clk_apb"; 413 #dma-cells = <1>; 414 xlnx,bus-width = <64>; 415 }; 416 417 can0: can@f1980000 { 418 compatible = "xlnx,canfd-2.0"; 419 status = "disabled"; 420 reg = <0 0xf1980000 0 0x6000>; 421 interrupts = <0 27 4>; 422 clock-names = "can_clk", "s_axi_aclk"; 423 rx-fifo-depth = <64>; 424 tx-mailbox-count = <32>; 425 }; 426 427 can1: can@f1990000 { 428 compatible = "xlnx,canfd-2.0"; 429 status = "disabled"; 430 reg = <0 0xf1990000 0 0x6000>; 431 interrupts = <0 28 4>; 432 clock-names = "can_clk", "s_axi_aclk"; 433 rx-fifo-depth = <64>; 434 tx-mailbox-count = <32>; 435 }; 436 437 gem0: ethernet@f19e0000 { 438 compatible = "xlnx,versal-gem", "cdns,gem"; 439 status = "disabled"; 440 reg = <0 0xf19e0000 0 0x1000>; 441 interrupts = <0 39 4>, <0 39 4>; 442 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", 443 "tsu_clk"; 444 }; 445 446 gem1: ethernet@f19f0000 { 447 compatible = "xlnx,versal-gem", "cdns,gem"; 448 status = "disabled"; 449 reg = <0 0xf19f0000 0 0x1000>; 450 interrupts = <0 41 4>, <0 41 4>; 451 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", 452 "tsu_clk"; 453 }; 454 455 gic: interrupt-controller@e2000000 { 456 compatible = "arm,gic-v3"; 457 #interrupt-cells = <3>; 458 reg = <0 0xe2000000 0 0x10000>, 459 <0 0xe2060000 0 0x200000>; 460 interrupt-controller; 461 interrupts = <1 9 4>; 462 #address-cells = <2>; 463 #size-cells = <2>; 464 ranges; 465 its: msi-controller@e2040000 { 466 compatible = "arm,gic-v3-its"; 467 msi-controller; 468 #msi-cells = <1>; 469 reg = <0 0xe2040000 0 0x20000>; 470 }; 471 }; 472 473 gpio0: gpio@f19d0000 { 474 compatible = "xlnx,versal-gpio-1.0"; 475 status = "disabled"; 476 reg = <0 0xf19d0000 0 0x1000>; 477 interrupts = <0 20 4>; 478 #gpio-cells = <2>; 479 gpio-controller; 480 #interrupt-cells = <2>; 481 interrupt-controller; 482 }; 483 484 gpio1: gpio@f1020000 { 485 compatible = "xlnx,pmc-gpio-1.0"; 486 status = "disabled"; 487 reg = <0 0xf1020000 0 0x1000>; 488 interrupts = <0 180 4>; 489 #gpio-cells = <2>; 490 gpio-controller; 491 #interrupt-cells = <2>; 492 interrupt-controller; 493 }; 494 495 i2c0: i2c@f1940000 { 496 compatible = "cdns,i2c-r1p14"; 497 status = "disabled"; 498 reg = <0 0xf1940000 0 0x1000>; 499 interrupts = <0 21 4>; 500 clock-frequency = <400000>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 }; 504 505 i2c1: i2c@f1950000 { 506 compatible = "cdns,i2c-r1p14"; 507 status = "disabled"; 508 reg = <0 0xf1950000 0 0x1000>; 509 interrupts = <0 22 4>; 510 clock-frequency = <400000>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 }; 514 515 i3c0: i3c@f1948000 { 516 compatible = "snps,dw-i3c-master-1.00a"; 517 status = "disabled"; 518 reg = <0 0xf1948000 0 0x1000>; 519 #address-cells = <3>; 520 #size-cells = <0>; 521 interrupts = <0 21 4>; 522 }; 523 524 i3c1: i3c@f1958000 { 525 compatible = "snps,dw-i3c-master-1.00a"; 526 status = "disabled"; 527 reg = <0 0xf1958000 0 0x1000>; 528 #address-cells = <3>; 529 #size-cells = <0>; 530 interrupts = <0 22 4>; 531 }; 532 533 ospi: spi@f1010000 { 534 compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; 535 status = "disabled"; 536 reg = <0 0xf1010000 0 0x10000>, 537 <0 0xc0000000 0 0x20000000>; 538 interrupts = <0 182 4>; 539 cdns,fifo-depth = <256>; 540 cdns,fifo-width = <4>; 541 cdns,is-dma = <1>; /* u-boot specific */ 542 cdns,trigger-address = <0xc0000000>; 543 }; 544 545 qspi: spi@f1030000 { 546 compatible = "xlnx,versal-qspi-1.0"; 547 status = "disabled"; 548 reg = <0 0xf1030000 0 0x1000>; 549 interrupts = <0 183 4>; 550 clock-names = "ref_clk", "pclk"; 551 }; 552 553 rtc: rtc@f12a0000 { 554 compatible = "xlnx,zynqmp-rtc"; 555 status = "disabled"; 556 reg = <0 0xf12a0000 0 0x100>; 557 interrupts = <0 200 4>, <0 201 4>; 558 interrupt-names = "alarm", "sec"; 559 calibration = <0x8000>; 560 }; 561 562 sdhci0: mmc@f1040000 { 563 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; 564 status = "disabled"; 565 reg = <0 0xf1040000 0 0x10000>; 566 interrupts = <0 184 4>; 567 clock-names = "clk_xin", "clk_ahb", "gate"; 568 #clock-cells = <1>; 569 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 570 }; 571 572 sdhci1: mmc@f1050000 { 573 compatible = "xlnx,versal-net-emmc"; 574 status = "disabled"; 575 reg = <0 0xf1050000 0 0x10000>; 576 interrupts = <0 186 4>; 577 clock-names = "clk_xin", "clk_ahb", "gate"; 578 #clock-cells = <1>; 579 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 580 }; 581 582 serial0: serial@f1920000 { 583 bootph-all; 584 compatible = "arm,pl011", "arm,primecell"; 585 status = "disabled"; 586 reg = <0 0xf1920000 0 0x1000>; 587 interrupts = <0 25 4>; 588 reg-io-width = <4>; 589 clock-names = "uartclk", "apb_pclk"; 590 }; 591 592 serial1: serial@f1930000 { 593 bootph-all; 594 compatible = "arm,pl011", "arm,primecell"; 595 status = "disabled"; 596 reg = <0 0xf1930000 0 0x1000>; 597 interrupts = <0 26 4>; 598 reg-io-width = <4>; 599 clock-names = "uartclk", "apb_pclk"; 600 }; 601 602 smmu: iommu@ec000000 { 603 compatible = "arm,smmu-v3"; 604 status = "disabled"; 605 reg = <0 0xec000000 0 0x40000>; 606 #iommu-cells = <1>; 607 interrupt-names = "combined"; 608 interrupts = <0 169 4>; 609 dma-coherent; 610 }; 611 612 spi0: spi@f1960000 { 613 compatible = "cdns,spi-r1p6"; 614 status = "disabled"; 615 interrupts = <0 23 4>; 616 reg = <0 0xf1960000 0 0x1000>; 617 clock-names = "ref_clk", "pclk"; 618 }; 619 620 spi1: spi@f1970000 { 621 compatible = "cdns,spi-r1p6"; 622 status = "disabled"; 623 interrupts = <0 24 4>; 624 reg = <0 0xf1970000 0 0x1000>; 625 clock-names = "ref_clk", "pclk"; 626 }; 627 628 ttc0: timer@f1dc0000 { 629 compatible = "cdns,ttc"; 630 status = "disabled"; 631 interrupts = <0 43 4>, <0 44 4>, <0 45 4>; 632 timer-width = <32>; 633 reg = <0x0 0xf1dc0000 0x0 0x1000>; 634 }; 635 636 ttc1: timer@f1dd0000 { 637 compatible = "cdns,ttc"; 638 status = "disabled"; 639 interrupts = <0 46 4>, <0 47 4>, <0 48 4>; 640 timer-width = <32>; 641 reg = <0x0 0xf1dd0000 0x0 0x1000>; 642 }; 643 644 ttc2: timer@f1de0000 { 645 compatible = "cdns,ttc"; 646 status = "disabled"; 647 interrupts = <0 49 4>, <0 50 4>, <0 51 4>; 648 timer-width = <32>; 649 reg = <0x0 0xf1de0000 0x0 0x1000>; 650 }; 651 652 ttc3: timer@f1df0000 { 653 compatible = "cdns,ttc"; 654 status = "disabled"; 655 interrupts = <0 52 4>, <0 53 4>, <0 54 4>; 656 timer-width = <32>; 657 reg = <0x0 0xf1df0000 0x0 0x1000>; 658 }; 659 660 usb0: usb@f1e00000 { 661 compatible = "xlnx,versal-dwc3"; 662 status = "disabled"; 663 reg = <0 0xf1e00000 0 0x100>; 664 clock-names = "bus_clk", "ref_clk"; 665 ranges; 666 #address-cells = <2>; 667 #size-cells = <2>; 668 669 dwc3_0: usb@f1b00000 { 670 compatible = "snps,dwc3"; 671 status = "disabled"; 672 reg = <0 0xf1b00000 0 0x10000>; 673 interrupt-names = "host", "peripheral", "otg", "wakeup"; 674 interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; 675 snps,dis_u2_susphy_quirk; 676 snps,dis_u3_susphy_quirk; 677 snps,quirk-frame-length-adjustment = <0x20>; 678 dr_mode = "peripheral"; 679 maximum-speed = "high-speed"; 680 snps,usb3_lpm_capable; 681 clock-names = "ref"; 682 }; 683 }; 684 685 usb1: usb@f1e10000 { 686 compatible = "xlnx,versal-dwc3"; 687 status = "disabled"; 688 reg = <0x0 0xf1e10000 0x0 0x100>; 689 clock-names = "bus_clk", "ref_clk"; 690 ranges; 691 #address-cells = <2>; 692 #size-cells = <2>; 693 694 dwc3_1: usb@f1c00000 { 695 compatible = "snps,dwc3"; 696 status = "disabled"; 697 reg = <0x0 0xf1c00000 0x0 0x10000>; 698 interrupt-names = "host", "peripheral", "otg", "wakeup"; 699 interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; 700 snps,dis_u2_susphy_quirk; 701 snps,dis_u3_susphy_quirk; 702 snps,quirk-frame-length-adjustment = <0x20>; 703 dr_mode = "host"; 704 maximum-speed = "high-speed"; 705 snps,usb3_lpm_capable; 706 clock-names = "ref"; 707 }; 708 }; 709 710 wwdt0: watchdog@ecc10000 { 711 compatible = "xlnx,versal-wwdt"; 712 status = "disabled"; 713 reg = <0 0xecc10000 0 0x10000>; 714 timeout-sec = <30>; 715 }; 716 717 wwdt1: watchdog@ecd10000 { 718 compatible = "xlnx,versal-wwdt"; 719 status = "disabled"; 720 reg = <0 0xecd10000 0 0x10000>; 721 timeout-sec = <30>; 722 }; 723 724 wwdt2: watchdog@ece10000 { 725 compatible = "xlnx,versal-wwdt"; 726 status = "disabled"; 727 reg = <0 0xece10000 0 0x10000>; 728 timeout-sec = <30>; 729 }; 730 731 wwdt3: watchdog@ecf10000 { 732 compatible = "xlnx,versal-wwdt"; 733 status = "disabled"; 734 reg = <0 0xecf10000 0 0x10000>; 735 timeout-sec = <30>; 736 }; 737 738 lpd_wwdt0: watchdog@ea420000 { 739 compatible = "xlnx,versal-wwdt"; 740 status = "disabled"; 741 reg = <0 0xea420000 0 0x10000>; 742 timeout-sec = <30>; 743 }; 744 745 lpd_wwdt1: watchdog@ea430000 { 746 compatible = "xlnx,versal-wwdt"; 747 status = "disabled"; 748 reg = <0 0xea430000 0 0x10000>; 749 timeout-sec = <30>; 750 }; 751 }; 752}; 753