1// SPDX-License-Identifier: GPL-2.0-only or MIT 2/* 3 * Device Tree Source for AM62L SoC Family 4 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 7 */ 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13#include "k3-pinctrl.h" 14 15/ { 16 model = "Texas Instruments K3 AM62L3 SoC"; 17 compatible = "ti,am62l3"; 18 interrupt-parent = <&gic500>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 firmware { 23 optee { 24 compatible = "linaro,optee-tz"; 25 method = "smc"; 26 }; 27 28 psci: psci { 29 compatible = "arm,psci-1.0"; 30 method = "smc"; 31 }; 32 33 scmi: scmi { 34 compatible = "arm,scmi-smc"; 35 arm,smc-id = <0x82004000>; 36 shmem = <&scmi_shmem>; 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 scmi_clk: protocol@14 { 41 reg = <0x14>; 42 #clock-cells = <1>; 43 bootph-all; 44 }; 45 46 scmi_pds: protocol@11 { 47 reg = <0x11>; 48 #power-domain-cells = <1>; 49 bootph-all; 50 }; 51 }; 52 }; 53 54 a53_timer0: timer-cl0-cpu0 { 55 compatible = "arm,armv8-timer"; 56 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 57 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 58 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 59 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 60 }; 61 62 pmu: pmu { 63 compatible = "arm,cortex-a53-pmu"; 64 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 65 }; 66 67 cbass_main: bus@f0000 { 68 compatible = "simple-bus"; 69 ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */ 70 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral Window */ 71 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router */ 72 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */ 73 <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */ 74 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Peripheral Window */ 75 <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ 76 <0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */ 77 <0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */ 78 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */ 79 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core Window */ 80 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core Window */ 81 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */ 82 <0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */ 83 <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */ 84 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */ 85 <0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */ 86 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 87 <0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */ 88 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */ 89 90 /* Wakeup Domain Range */ 91 <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */ 92 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ 93 <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ 94 <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ 95 <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */ 96 <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ 97 <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ 98 #address-cells = <2>; 99 #size-cells = <2>; 100 101 cbass_wakeup: bus@a80000 { 102 compatible = "simple-bus"; 103 ranges = <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */ 104 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ 105 <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ 106 <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ 107 <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */ 108 <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ 109 <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ 110 #address-cells = <2>; 111 #size-cells = <2>; 112 }; 113 }; 114}; 115 116/* Now include peripherals for each bus segment */ 117#include "k3-am62l-main.dtsi" 118#include "k3-am62l-wakeup.dtsi" 119