1// SPDX-License-Identifier: GPL-2.0-only or MIT 2/* 3 * Device Tree file for the AM62L main domain peripherals 4 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 7 */ 8 9&cbass_main { 10 gic500: interrupt-controller@1800000 { 11 compatible = "arm,gic-v3"; 12 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 13 <0x00 0x01840000 0x00 0xc0000>, /* GICR */ 14 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 15 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 16 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 17 ranges; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 #interrupt-cells = <3>; 21 interrupt-controller; 22 /* 23 * vcpumntirq: 24 * virtual CPU interface maintenance interrupt 25 */ 26 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 27 28 gic_its: msi-controller@1820000 { 29 compatible = "arm,gic-v3-its"; 30 reg = <0x00 0x01820000 0x00 0x10000>; 31 socionext,synquacer-pre-its = <0x1000000 0x400000>; 32 msi-controller; 33 #msi-cells = <1>; 34 }; 35 }; 36 37 gpio0: gpio@600000 { 38 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 39 reg = <0x00 0x00600000 0x00 0x100>; 40 gpio-controller; 41 #gpio-cells = <2>; 42 interrupt-parent = <&gic500>; 43 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>, 44 <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>, 45 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 46 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 47 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 48 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 49 <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 50 <GIC_SPI 267 IRQ_TYPE_EDGE_RISING>; 51 interrupt-controller; 52 #interrupt-cells = <2>; 53 power-domains = <&scmi_pds 34>; 54 clocks = <&scmi_clk 140>; 55 clock-names = "gpio"; 56 ti,ngpio = <126>; 57 ti,davinci-gpio-unbanked = <0>; 58 }; 59 60 gpio2: gpio@610000 { 61 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 62 reg = <0x00 0x00610000 0x00 0x100>; 63 gpio-controller; 64 #gpio-cells = <2>; 65 interrupt-parent = <&gic500>; 66 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>, 67 <GIC_SPI 281 IRQ_TYPE_EDGE_RISING>, 68 <GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 69 <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>, 70 <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>, 71 <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>, 72 <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>, 73 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>; 74 interrupt-controller; 75 #interrupt-cells = <2>; 76 power-domains = <&scmi_pds 35>; 77 clocks = <&scmi_clk 141>; 78 clock-names = "gpio"; 79 ti,ngpio = <79>; 80 ti,davinci-gpio-unbanked = <0>; 81 }; 82 83 timer0: timer@2400000 { 84 compatible = "ti,am654-timer"; 85 reg = <0x00 0x2400000 0x00 0x400>; 86 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 87 clocks = <&scmi_clk 58>; 88 clock-names = "fck"; 89 power-domains = <&scmi_pds 15>; 90 ti,timer-pwm; 91 }; 92 93 timer1: timer@2410000 { 94 compatible = "ti,am654-timer"; 95 reg = <0x00 0x2410000 0x00 0x400>; 96 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&scmi_clk 63>; 98 clock-names = "fck"; 99 power-domains = <&scmi_pds 16>; 100 ti,timer-pwm; 101 }; 102 103 timer2: timer@2420000 { 104 compatible = "ti,am654-timer"; 105 reg = <0x00 0x2420000 0x00 0x400>; 106 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&scmi_clk 77>; 108 clock-names = "fck"; 109 power-domains = <&scmi_pds 17>; 110 ti,timer-pwm; 111 }; 112 113 timer3: timer@2430000 { 114 compatible = "ti,am654-timer"; 115 reg = <0x00 0x2430000 0x00 0x400>; 116 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&scmi_clk 82>; 118 clock-names = "fck"; 119 power-domains = <&scmi_pds 18>; 120 ti,timer-pwm; 121 }; 122 123 uart0: serial@2800000 { 124 compatible = "ti,am64-uart", "ti,am654-uart"; 125 reg = <0x00 0x02800000 0x00 0x100>; 126 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 127 power-domains = <&scmi_pds 89>; 128 clocks = <&scmi_clk 358>; 129 clock-names = "fclk"; 130 status = "disabled"; 131 }; 132 133 uart1: serial@2810000 { 134 compatible = "ti,am64-uart", "ti,am654-uart"; 135 reg = <0x00 0x02810000 0x00 0x100>; 136 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 137 power-domains = <&scmi_pds 77>; 138 clocks = <&scmi_clk 312>; 139 clock-names = "fclk"; 140 status = "disabled"; 141 }; 142 143 uart2: serial@2820000 { 144 compatible = "ti,am64-uart", "ti,am654-uart"; 145 reg = <0x00 0x02820000 0x00 0x100>; 146 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 147 power-domains = <&scmi_pds 78>; 148 clocks = <&scmi_clk 314>; 149 clock-names = "fclk"; 150 status = "disabled"; 151 }; 152 153 uart3: serial@2830000 { 154 compatible = "ti,am64-uart", "ti,am654-uart"; 155 reg = <0x00 0x02830000 0x00 0x100>; 156 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 157 power-domains = <&scmi_pds 79>; 158 clocks = <&scmi_clk 316>; 159 clock-names = "fclk"; 160 status = "disabled"; 161 }; 162 163 uart4: serial@2840000 { 164 compatible = "ti,am64-uart", "ti,am654-uart"; 165 reg = <0x00 0x02840000 0x00 0x100>; 166 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 167 power-domains = <&scmi_pds 80>; 168 clocks = <&scmi_clk 318>; 169 clock-names = "fclk"; 170 status = "disabled"; 171 }; 172 173 uart5: serial@2850000 { 174 compatible = "ti,am64-uart", "ti,am654-uart"; 175 reg = <0x00 0x02850000 0x00 0x100>; 176 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 177 power-domains = <&scmi_pds 81>; 178 clocks = <&scmi_clk 320>; 179 clock-names = "fclk"; 180 status = "disabled"; 181 }; 182 183 uart6: serial@2860000 { 184 compatible = "ti,am64-uart", "ti,am654-uart"; 185 reg = <0x00 0x02860000 0x00 0x100>; 186 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 187 power-domains = <&scmi_pds 82>; 188 clocks = <&scmi_clk 322>; 189 clock-names = "fclk"; 190 status = "disabled"; 191 }; 192 193 conf: bus@9000000 { 194 compatible = "simple-bus"; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges = <0x00 0x00 0x09000000 0x380000>; 198 199 phy_gmii_sel: phy@1be000 { 200 compatible = "ti,am654-phy-gmii-sel"; 201 reg = <0x1be000 0x8>; 202 #phy-cells = <1>; 203 }; 204 205 epwm_tbclk: clock-controller@1e9100 { 206 compatible = "ti,am62-epwm-tbclk"; 207 reg = <0x1e9100 0x4>; 208 #clock-cells = <1>; 209 }; 210 }; 211 212 usbss0: dwc3-usb@f900000 { 213 compatible = "ti,am62-usb"; 214 reg = <0x00 0x0f900000 0x00 0x800>, 215 <0x00 0x0f908000 0x00 0x400>; 216 clocks = <&scmi_clk 331>; 217 clock-names = "ref"; 218 ti,syscon-phy-pll-refclk = <&usb_phy_ctrl 0x0>; 219 #address-cells = <2>; 220 #size-cells = <2>; 221 power-domains = <&scmi_pds 95>; 222 ranges; 223 status = "disabled"; 224 225 usb0: usb@31000000 { 226 compatible = "snps,dwc3"; 227 reg = <0x00 0x31000000 0x00 0x50000>; 228 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 229 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 230 interrupt-names = "host", "peripheral"; 231 maximum-speed = "high-speed"; 232 dr_mode = "otg"; 233 snps,usb2-gadget-lpm-disable; 234 snps,usb2-lpm-disable; 235 }; 236 }; 237 238 usbss1: dwc3-usb@f910000 { 239 compatible = "ti,am62-usb"; 240 reg = <0x00 0x0f910000 0x00 0x800>, 241 <0x00 0x0f918000 0x00 0x400>; 242 clocks = <&scmi_clk 338>; 243 clock-names = "ref"; 244 ti,syscon-phy-pll-refclk = <&usb_phy_ctrl 0x4>; 245 #address-cells = <2>; 246 #size-cells = <2>; 247 power-domains = <&scmi_pds 96>; 248 ranges; 249 status = "disabled"; 250 251 usb1: usb@31100000 { 252 compatible = "snps,dwc3"; 253 reg = <0x00 0x31100000 0x00 0x50000>; 254 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 255 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 256 interrupt-names = "host", "peripheral"; 257 maximum-speed = "high-speed"; 258 dr_mode = "otg"; 259 snps,usb2-gadget-lpm-disable; 260 snps,usb2-lpm-disable; 261 }; 262 }; 263 264 sdhci1: mmc@fa00000 { 265 compatible = "ti,j721e-sdhci-4bit"; 266 reg = <0x00 0x0fa00000 0x00 0x1000>, 267 <0x00 0x0fa08000 0x00 0x400>; 268 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 269 power-domains = <&scmi_pds 26>; 270 clocks = <&scmi_clk 106>, <&scmi_clk 109>; 271 clock-names = "clk_ahb", "clk_xin"; 272 assigned-clocks = <&scmi_clk 109>; 273 bus-width = <4>; 274 ti,clkbuf-sel = <0x7>; 275 ti,otap-del-sel-legacy = <0x0>; 276 ti,itap-del-sel-legacy = <0x0>; 277 status = "disabled"; 278 }; 279 280 sdhci0: mmc@fa10000 { 281 compatible = "ti,am62-sdhci"; 282 reg = <0x00 0xfa10000 0x00 0x1000>, 283 <0x00 0xfa18000 0x00 0x400>; 284 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 285 power-domains = <&scmi_pds 28>; 286 clocks = <&scmi_clk 122>, <&scmi_clk 125>; 287 clock-names = "clk_ahb", "clk_xin"; 288 assigned-clocks = <&scmi_clk 125>; 289 bus-width = <8>; 290 ti,clkbuf-sel = <0x7>; 291 ti,otap-del-sel-legacy = <0x0>; 292 ti,otap-del-sel-mmc-hs = <0x0>; 293 ti,otap-del-sel-hs200 = <0x6>; 294 status = "disabled"; 295 }; 296 297 sdhci2: mmc@fa20000 { 298 compatible = "ti,am62-sdhci"; 299 reg = <0x00 0x0fa20000 0x00 0x1000>, 300 <0x00 0x0fa28000 0x00 0x400>; 301 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 302 power-domains = <&scmi_pds 27>; 303 clocks = <&scmi_clk 114>, <&scmi_clk 117>; 304 clock-names = "clk_ahb", "clk_xin"; 305 assigned-clocks = <&scmi_clk 117>; 306 bus-width = <4>; 307 ti,clkbuf-sel = <0x7>; 308 ti,otap-del-sel-legacy = <0x0>; 309 ti,itap-del-sel-legacy = <0x0>; 310 status = "disabled"; 311 }; 312 313 i2c0: i2c@20000000 { 314 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 315 reg = <0x00 0x20000000 0x00 0x100>; 316 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 power-domains = <&scmi_pds 53>; 320 clocks = <&scmi_clk 246>; 321 clock-names = "fck"; 322 status = "disabled"; 323 }; 324 325 i2c1: i2c@20010000 { 326 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 327 reg = <0x00 0x20010000 0x00 0x100>; 328 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 power-domains = <&scmi_pds 54>; 332 clocks = <&scmi_clk 250>; 333 clock-names = "fck"; 334 status = "disabled"; 335 }; 336 337 i2c2: i2c@20020000 { 338 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 339 reg = <0x00 0x20020000 0x00 0x100>; 340 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 power-domains = <&scmi_pds 55>; 344 clocks = <&scmi_clk 254>; 345 clock-names = "fck"; 346 status = "disabled"; 347 }; 348 349 i2c3: i2c@20030000 { 350 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 351 reg = <0x00 0x20030000 0x00 0x100>; 352 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 power-domains = <&scmi_pds 56>; 356 clocks = <&scmi_clk 258>; 357 clock-names = "fck"; 358 status = "disabled"; 359 }; 360 361 mcan0: can@20701000 { 362 compatible = "bosch,m_can"; 363 reg = <0x00 0x20701000 0x00 0x200>, 364 <0x00 0x20708000 0x00 0x8000>; 365 reg-names = "m_can", "message_ram"; 366 power-domains = <&scmi_pds 47>; 367 clocks = <&scmi_clk 179>, <&scmi_clk 178>; 368 clock-names = "hclk", "cclk"; 369 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 371 interrupt-names = "int0", "int1"; 372 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 373 status = "disabled"; 374 }; 375 376 mcan1: can@20711000 { 377 compatible = "bosch,m_can"; 378 reg = <0x00 0x20711000 0x00 0x200>, 379 <0x00 0x20718000 0x00 0x8000>; 380 reg-names = "m_can", "message_ram"; 381 power-domains = <&scmi_pds 48>; 382 clocks = <&scmi_clk 185>, <&scmi_clk 184>; 383 clock-names = "hclk", "cclk"; 384 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 386 interrupt-names = "int0", "int1"; 387 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 388 status = "disabled"; 389 }; 390 391 mcan2: can@20721000 { 392 compatible = "bosch,m_can"; 393 reg = <0x00 0x20721000 0x00 0x200>, 394 <0x00 0x20728000 0x00 0x8000>; 395 reg-names = "m_can", "message_ram"; 396 power-domains = <&scmi_pds 49>; 397 clocks = <&scmi_clk 191>, <&scmi_clk 190>; 398 clock-names = "hclk", "cclk"; 399 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 401 interrupt-names = "int0", "int1"; 402 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 403 status = "disabled"; 404 }; 405 406 spi0: spi@20100000 { 407 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 408 reg = <0x00 0x20100000 0x00 0x400>; 409 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 power-domains = <&scmi_pds 72>; 413 clocks = <&scmi_clk 299>; 414 status = "disabled"; 415 }; 416 417 spi1: spi@20110000 { 418 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 419 reg = <0x00 0x20110000 0x00 0x400>; 420 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 power-domains = <&scmi_pds 73>; 424 clocks = <&scmi_clk 302>; 425 status = "disabled"; 426 }; 427 428 spi2: spi@20120000 { 429 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 430 reg = <0x00 0x20120000 0x00 0x400>; 431 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 power-domains = <&scmi_pds 74>; 435 clocks = <&scmi_clk 305>; 436 status = "disabled"; 437 }; 438 439 spi3: spi@20130000 { 440 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 441 reg = <0x00 0x20130000 0x00 0x400>; 442 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 power-domains = <&scmi_pds 75>; 446 clocks = <&scmi_clk 308>; 447 status = "disabled"; 448 }; 449 450 epwm0: pwm@23000000 { 451 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 452 reg = <0x00 0x23000000 0x00 0x100>; 453 power-domains = <&scmi_pds 40>; 454 clocks = <&epwm_tbclk 0>, <&scmi_clk 164>; 455 clock-names = "tbclk", "fck"; 456 #pwm-cells = <3>; 457 status = "disabled"; 458 }; 459 460 epwm1: pwm@23010000 { 461 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 462 reg = <0x00 0x23010000 0x00 0x100>; 463 power-domains = <&scmi_pds 41>; 464 clocks = <&epwm_tbclk 1>, <&scmi_clk 165>; 465 clock-names = "tbclk", "fck"; 466 #pwm-cells = <3>; 467 status = "disabled"; 468 }; 469 470 epwm2: pwm@23020000 { 471 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 472 reg = <0x00 0x23020000 0x00 0x100>; 473 power-domains = <&scmi_pds 42>; 474 clocks = <&epwm_tbclk 2>, <&scmi_clk 166>; 475 clock-names = "tbclk", "fck"; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 ecap0: pwm@23100000 { 481 compatible = "ti,am3352-ecap"; 482 reg = <0x00 0x23100000 0x00 0x100>; 483 power-domains = <&scmi_pds 23>; 484 clocks = <&scmi_clk 99>; 485 clock-names = "fck"; 486 #pwm-cells = <3>; 487 status = "disabled"; 488 }; 489 490 ecap1: pwm@23110000 { 491 compatible = "ti,am3352-ecap"; 492 reg = <0x00 0x23110000 0x00 0x100>; 493 power-domains = <&scmi_pds 24>; 494 clocks = <&scmi_clk 100>; 495 clock-names = "fck"; 496 #pwm-cells = <3>; 497 status = "disabled"; 498 }; 499 500 ecap2: pwm@23120000 { 501 compatible = "ti,am3352-ecap"; 502 reg = <0x00 0x23120000 0x00 0x100>; 503 power-domains = <&scmi_pds 25>; 504 clocks = <&scmi_clk 101>; 505 clock-names = "fck"; 506 #pwm-cells = <3>; 507 status = "disabled"; 508 }; 509 510 eqep0: counter@23200000 { 511 compatible = "ti,am62-eqep"; 512 reg = <0x00 0x23200000 0x00 0x100>; 513 power-domains = <&scmi_pds 29>; 514 clocks = <&scmi_clk 127>; 515 interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; 516 status = "disabled"; 517 }; 518 519 eqep1: counter@23210000 { 520 compatible = "ti,am62-eqep"; 521 reg = <0x00 0x23210000 0x00 0x100>; 522 power-domains = <&scmi_pds 30>; 523 clocks = <&scmi_clk 128>; 524 interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>; 525 status = "disabled"; 526 }; 527 528 eqep2: counter@23220000 { 529 compatible = "ti,am62-eqep"; 530 reg = <0x00 0x23220000 0x00 0x100>; 531 power-domains = <&scmi_pds 31>; 532 clocks = <&scmi_clk 129>; 533 interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; 534 status = "disabled"; 535 }; 536 537 elm0: ecc@25010000 { 538 compatible = "ti,am64-elm"; 539 reg = <0x00 0x25010000 0x00 0x2000>; 540 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 541 power-domains = <&scmi_pds 25>; 542 clocks = <&scmi_clk 102>; 543 clock-names = "fck"; 544 status = "disabled"; 545 }; 546 547 gpmc0: memory-controller@3b000000 { 548 compatible = "ti,am64-gpmc"; 549 power-domains = <&scmi_pds 37>; 550 clocks = <&scmi_clk 149>; 551 clock-names = "fck"; 552 reg = <0x00 0x3b000000 0x00 0x400>, 553 <0x00 0x50000000 0x00 0x8000000>; 554 reg-names = "cfg", "data"; 555 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 556 gpmc,num-cs = <3>; 557 gpmc,num-waitpins = <2>; 558 #address-cells = <2>; 559 #size-cells = <1>; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 gpio-controller; 563 #gpio-cells = <2>; 564 status = "disabled"; 565 }; 566 567 oc_sram: sram@70800000 { 568 compatible = "mmio-sram"; 569 reg = <0x00 0x70800000 0x00 0x10000>; 570 ranges = <0x00 0x00 0x70800000 0x10000>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 574 scmi_shmem: sram@0 { 575 compatible = "arm,scmi-shmem"; 576 reg = <0x00 0x100>; 577 bootph-all; 578 }; 579 }; 580}; 581