1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 3#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <riscv/sophgo/cv180x.dtsi> 7#include <riscv/sophgo/cv181x.dtsi> 8 9/ { 10 compatible = "sophgo,sg2000"; 11 interrupt-parent = <&gic>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 compatible = "arm,cortex-a53"; 19 device_type = "cpu"; 20 reg = <0>; 21 enable-method = "psci"; 22 i-cache-size = <32768>; 23 d-cache-size = <32768>; 24 next-level-cache = <&l2>; 25 }; 26 27 l2: l2-cache { 28 compatible = "cache"; 29 cache-level = <2>; 30 cache-unified; 31 cache-size = <0x20000>; 32 }; 33 }; 34 35 memory@80000000 { 36 device_type = "memory"; 37 reg = <0x80000000 0x20000000>; /* 512MiB */ 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a53-pmu"; 42 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 44 }; 45 46 psci { 47 compatible = "arm,psci-0.2"; 48 method = "smc"; 49 cpu_on = <0xc4000003>; 50 cpu_off = <0x84000002>; 51 }; 52 53 soc { 54 gic: interrupt-controller@1f01000 { 55 compatible = "arm,cortex-a15-gic"; 56 interrupt-controller; 57 #interrupt-cells = <3>; 58 reg = <0x01f01000 0x1000>, 59 <0x01f02000 0x2000>; 60 }; 61 62 pinctrl: pinctrl@3001000 { 63 compatible = "sophgo,sg2000-pinctrl"; 64 reg = <0x03001000 0x1000>, 65 <0x05027000 0x1000>; 66 reg-names = "sys", "rtc"; 67 }; 68 69 clk: clock-controller@3002000 { 70 compatible = "sophgo,sg2000-clk"; 71 reg = <0x03002000 0x1000>; 72 clocks = <&osc>; 73 #clock-cells = <1>; 74 }; 75 }; 76 77 timer { 78 compatible = "arm,armv8-timer"; 79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 80 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 82 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 83 always-on; 84 clock-frequency = <25000000>; 85 }; 86}; 87