1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/gpio/uniphier-gpio.h> 12 13/memreserve/ 0x80000000 0x02000000; 14 15/ { 16 compatible = "socionext,uniphier-ld11"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 interrupt-parent = <&gic>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 }; 34 }; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53", "arm,armv8"; 39 reg = <0 0x000>; 40 clocks = <&sys_clk 33>; 41 enable-method = "psci"; 42 operating-points-v2 = <&cluster0_opp>; 43 }; 44 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0 0x001>; 49 clocks = <&sys_clk 33>; 50 enable-method = "psci"; 51 operating-points-v2 = <&cluster0_opp>; 52 }; 53 }; 54 55 cluster0_opp: opp-table { 56 compatible = "operating-points-v2"; 57 opp-shared; 58 59 opp-245000000 { 60 opp-hz = /bits/ 64 <245000000>; 61 clock-latency-ns = <300>; 62 }; 63 opp-250000000 { 64 opp-hz = /bits/ 64 <250000000>; 65 clock-latency-ns = <300>; 66 }; 67 opp-490000000 { 68 opp-hz = /bits/ 64 <490000000>; 69 clock-latency-ns = <300>; 70 }; 71 opp-500000000 { 72 opp-hz = /bits/ 64 <500000000>; 73 clock-latency-ns = <300>; 74 }; 75 opp-653334000 { 76 opp-hz = /bits/ 64 <653334000>; 77 clock-latency-ns = <300>; 78 }; 79 opp-666667000 { 80 opp-hz = /bits/ 64 <666667000>; 81 clock-latency-ns = <300>; 82 }; 83 opp-980000000 { 84 opp-hz = /bits/ 64 <980000000>; 85 clock-latency-ns = <300>; 86 }; 87 }; 88 89 psci { 90 compatible = "arm,psci-1.0"; 91 method = "smc"; 92 }; 93 94 clocks { 95 refclk: ref { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <25000000>; 99 }; 100 }; 101 102 emmc_pwrseq: emmc-pwrseq { 103 compatible = "mmc-pwrseq-emmc"; 104 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 105 }; 106 107 timer { 108 compatible = "arm,armv8-timer"; 109 interrupts = <1 13 4>, 110 <1 14 4>, 111 <1 11 4>, 112 <1 10 4>; 113 }; 114 115 soc@0 { 116 compatible = "simple-bus"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges = <0 0 0 0xffffffff>; 120 121 serial0: serial@54006800 { 122 compatible = "socionext,uniphier-uart"; 123 status = "disabled"; 124 reg = <0x54006800 0x40>; 125 interrupts = <0 33 4>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_uart0>; 128 clocks = <&peri_clk 0>; 129 resets = <&peri_rst 0>; 130 }; 131 132 serial1: serial@54006900 { 133 compatible = "socionext,uniphier-uart"; 134 status = "disabled"; 135 reg = <0x54006900 0x40>; 136 interrupts = <0 35 4>; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_uart1>; 139 clocks = <&peri_clk 1>; 140 resets = <&peri_rst 1>; 141 }; 142 143 serial2: serial@54006a00 { 144 compatible = "socionext,uniphier-uart"; 145 status = "disabled"; 146 reg = <0x54006a00 0x40>; 147 interrupts = <0 37 4>; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_uart2>; 150 clocks = <&peri_clk 2>; 151 resets = <&peri_rst 2>; 152 }; 153 154 serial3: serial@54006b00 { 155 compatible = "socionext,uniphier-uart"; 156 status = "disabled"; 157 reg = <0x54006b00 0x40>; 158 interrupts = <0 177 4>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_uart3>; 161 clocks = <&peri_clk 3>; 162 resets = <&peri_rst 3>; 163 }; 164 165 gpio: gpio@55000000 { 166 compatible = "socionext,uniphier-gpio"; 167 reg = <0x55000000 0x200>; 168 interrupt-parent = <&aidet>; 169 interrupt-controller; 170 #interrupt-cells = <2>; 171 gpio-controller; 172 #gpio-cells = <2>; 173 gpio-ranges = <&pinctrl 0 0 0>, 174 <&pinctrl 43 0 0>, 175 <&pinctrl 51 0 0>, 176 <&pinctrl 96 0 0>, 177 <&pinctrl 160 0 0>, 178 <&pinctrl 184 0 0>; 179 gpio-ranges-group-names = "gpio_range0", 180 "gpio_range1", 181 "gpio_range2", 182 "gpio_range3", 183 "gpio_range4", 184 "gpio_range5"; 185 ngpios = <200>; 186 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 187 <21 217 3>; 188 }; 189 190 audio@56000000 { 191 compatible = "socionext,uniphier-ld11-aio"; 192 reg = <0x56000000 0x80000>; 193 interrupts = <0 144 4>; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_aout1>, 196 <&pinctrl_aoutiec1>; 197 clock-names = "aio"; 198 clocks = <&sys_clk 40>; 199 reset-names = "aio"; 200 resets = <&sys_rst 40>; 201 #sound-dai-cells = <1>; 202 203 i2s_port0: port@0 { 204 i2s_hdmi: endpoint { 205 }; 206 }; 207 208 i2s_port1: port@1 { 209 i2s_pcmin2: endpoint { 210 }; 211 }; 212 213 i2s_port2: port@2 { 214 i2s_line: endpoint { 215 dai-format = "i2s"; 216 remote-endpoint = <&evea_line>; 217 }; 218 }; 219 220 i2s_port3: port@3 { 221 i2s_hpcmout1: endpoint { 222 }; 223 }; 224 225 i2s_port4: port@4 { 226 i2s_hp: endpoint { 227 dai-format = "i2s"; 228 remote-endpoint = <&evea_hp>; 229 }; 230 }; 231 232 spdif_port0: port@5 { 233 spdif_hiecout1: endpoint { 234 }; 235 }; 236 237 src_port0: port@6 { 238 i2s_epcmout2: endpoint { 239 }; 240 }; 241 242 src_port1: port@7 { 243 i2s_epcmout3: endpoint { 244 }; 245 }; 246 247 comp_spdif_port0: port@8 { 248 comp_spdif_hiecout1: endpoint { 249 }; 250 }; 251 }; 252 253 codec@57900000 { 254 compatible = "socionext,uniphier-evea"; 255 reg = <0x57900000 0x1000>; 256 clock-names = "evea", "exiv"; 257 clocks = <&sys_clk 41>, <&sys_clk 42>; 258 reset-names = "evea", "exiv", "adamv"; 259 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; 260 #sound-dai-cells = <1>; 261 262 port@0 { 263 evea_line: endpoint { 264 remote-endpoint = <&i2s_line>; 265 }; 266 }; 267 268 port@1 { 269 evea_hp: endpoint { 270 remote-endpoint = <&i2s_hp>; 271 }; 272 }; 273 }; 274 275 adamv@57920000 { 276 compatible = "socionext,uniphier-ld11-adamv", 277 "simple-mfd", "syscon"; 278 reg = <0x57920000 0x1000>; 279 280 adamv_rst: reset { 281 compatible = "socionext,uniphier-ld11-adamv-reset"; 282 #reset-cells = <1>; 283 }; 284 }; 285 286 i2c0: i2c@58780000 { 287 compatible = "socionext,uniphier-fi2c"; 288 status = "disabled"; 289 reg = <0x58780000 0x80>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 interrupts = <0 41 4>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_i2c0>; 295 clocks = <&peri_clk 4>; 296 resets = <&peri_rst 4>; 297 clock-frequency = <100000>; 298 }; 299 300 i2c1: i2c@58781000 { 301 compatible = "socionext,uniphier-fi2c"; 302 status = "disabled"; 303 reg = <0x58781000 0x80>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 interrupts = <0 42 4>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_i2c1>; 309 clocks = <&peri_clk 5>; 310 resets = <&peri_rst 5>; 311 clock-frequency = <100000>; 312 }; 313 314 i2c2: i2c@58782000 { 315 compatible = "socionext,uniphier-fi2c"; 316 reg = <0x58782000 0x80>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 interrupts = <0 43 4>; 320 clocks = <&peri_clk 6>; 321 resets = <&peri_rst 6>; 322 clock-frequency = <400000>; 323 }; 324 325 i2c3: i2c@58783000 { 326 compatible = "socionext,uniphier-fi2c"; 327 status = "disabled"; 328 reg = <0x58783000 0x80>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 interrupts = <0 44 4>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_i2c3>; 334 clocks = <&peri_clk 7>; 335 resets = <&peri_rst 7>; 336 clock-frequency = <100000>; 337 }; 338 339 i2c4: i2c@58784000 { 340 compatible = "socionext,uniphier-fi2c"; 341 status = "disabled"; 342 reg = <0x58784000 0x80>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 interrupts = <0 45 4>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_i2c4>; 348 clocks = <&peri_clk 8>; 349 resets = <&peri_rst 8>; 350 clock-frequency = <100000>; 351 }; 352 353 i2c5: i2c@58785000 { 354 compatible = "socionext,uniphier-fi2c"; 355 reg = <0x58785000 0x80>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 interrupts = <0 25 4>; 359 clocks = <&peri_clk 9>; 360 resets = <&peri_rst 9>; 361 clock-frequency = <400000>; 362 }; 363 364 system_bus: system-bus@58c00000 { 365 compatible = "socionext,uniphier-system-bus"; 366 status = "disabled"; 367 reg = <0x58c00000 0x400>; 368 #address-cells = <2>; 369 #size-cells = <1>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_system_bus>; 372 }; 373 374 smpctrl@59801000 { 375 compatible = "socionext,uniphier-smpctrl"; 376 reg = <0x59801000 0x400>; 377 }; 378 379 sdctrl@59810000 { 380 compatible = "socionext,uniphier-ld11-sdctrl", 381 "simple-mfd", "syscon"; 382 reg = <0x59810000 0x400>; 383 384 sd_rst: reset { 385 compatible = "socionext,uniphier-ld11-sd-reset"; 386 #reset-cells = <1>; 387 }; 388 }; 389 390 perictrl@59820000 { 391 compatible = "socionext,uniphier-ld11-perictrl", 392 "simple-mfd", "syscon"; 393 reg = <0x59820000 0x200>; 394 395 peri_clk: clock { 396 compatible = "socionext,uniphier-ld11-peri-clock"; 397 #clock-cells = <1>; 398 }; 399 400 peri_rst: reset { 401 compatible = "socionext,uniphier-ld11-peri-reset"; 402 #reset-cells = <1>; 403 }; 404 }; 405 406 emmc: sdhc@5a000000 { 407 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 408 reg = <0x5a000000 0x400>; 409 interrupts = <0 78 4>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_emmc>; 412 clocks = <&sys_clk 4>; 413 resets = <&sys_rst 4>; 414 bus-width = <8>; 415 mmc-ddr-1_8v; 416 mmc-hs200-1_8v; 417 mmc-pwrseq = <&emmc_pwrseq>; 418 cdns,phy-input-delay-legacy = <4>; 419 cdns,phy-input-delay-mmc-highspeed = <2>; 420 cdns,phy-input-delay-mmc-ddr = <3>; 421 cdns,phy-dll-delay-sdclk = <21>; 422 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 423 }; 424 425 usb0: usb@5a800100 { 426 compatible = "socionext,uniphier-ehci", "generic-ehci"; 427 status = "disabled"; 428 reg = <0x5a800100 0x100>; 429 interrupts = <0 243 4>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pinctrl_usb0>; 432 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 433 <&mio_clk 12>; 434 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 435 <&mio_rst 12>; 436 has-transaction-translator; 437 }; 438 439 usb1: usb@5a810100 { 440 compatible = "socionext,uniphier-ehci", "generic-ehci"; 441 status = "disabled"; 442 reg = <0x5a810100 0x100>; 443 interrupts = <0 244 4>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_usb1>; 446 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 447 <&mio_clk 13>; 448 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 449 <&mio_rst 13>; 450 has-transaction-translator; 451 }; 452 453 usb2: usb@5a820100 { 454 compatible = "socionext,uniphier-ehci", "generic-ehci"; 455 status = "disabled"; 456 reg = <0x5a820100 0x100>; 457 interrupts = <0 245 4>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&pinctrl_usb2>; 460 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 461 <&mio_clk 14>; 462 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 463 <&mio_rst 14>; 464 has-transaction-translator; 465 }; 466 467 mioctrl@5b3e0000 { 468 compatible = "socionext,uniphier-ld11-mioctrl", 469 "simple-mfd", "syscon"; 470 reg = <0x5b3e0000 0x800>; 471 472 mio_clk: clock { 473 compatible = "socionext,uniphier-ld11-mio-clock"; 474 #clock-cells = <1>; 475 }; 476 477 mio_rst: reset { 478 compatible = "socionext,uniphier-ld11-mio-reset"; 479 #reset-cells = <1>; 480 resets = <&sys_rst 7>; 481 }; 482 }; 483 484 soc-glue@5f800000 { 485 compatible = "socionext,uniphier-ld11-soc-glue", 486 "simple-mfd", "syscon"; 487 reg = <0x5f800000 0x2000>; 488 489 pinctrl: pinctrl { 490 compatible = "socionext,uniphier-ld11-pinctrl"; 491 }; 492 }; 493 494 soc-glue@5f900000 { 495 compatible = "socionext,uniphier-ld11-soc-glue-debug", 496 "simple-mfd"; 497 #address-cells = <1>; 498 #size-cells = <1>; 499 ranges = <0 0x5f900000 0x2000>; 500 501 efuse@100 { 502 compatible = "socionext,uniphier-efuse"; 503 reg = <0x100 0x28>; 504 }; 505 506 efuse@200 { 507 compatible = "socionext,uniphier-efuse"; 508 reg = <0x200 0x68>; 509 }; 510 }; 511 512 aidet: aidet@5fc20000 { 513 compatible = "socionext,uniphier-ld11-aidet"; 514 reg = <0x5fc20000 0x200>; 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 }; 518 519 gic: interrupt-controller@5fe00000 { 520 compatible = "arm,gic-v3"; 521 reg = <0x5fe00000 0x10000>, /* GICD */ 522 <0x5fe40000 0x80000>; /* GICR */ 523 interrupt-controller; 524 #interrupt-cells = <3>; 525 interrupts = <1 9 4>; 526 }; 527 528 sysctrl@61840000 { 529 compatible = "socionext,uniphier-ld11-sysctrl", 530 "simple-mfd", "syscon"; 531 reg = <0x61840000 0x10000>; 532 533 sys_clk: clock { 534 compatible = "socionext,uniphier-ld11-clock"; 535 #clock-cells = <1>; 536 }; 537 538 sys_rst: reset { 539 compatible = "socionext,uniphier-ld11-reset"; 540 #reset-cells = <1>; 541 }; 542 543 watchdog { 544 compatible = "socionext,uniphier-wdt"; 545 }; 546 }; 547 548 eth: ethernet@65000000 { 549 compatible = "socionext,uniphier-ld11-ave4"; 550 status = "disabled"; 551 reg = <0x65000000 0x8500>; 552 interrupts = <0 66 4>; 553 clocks = <&sys_clk 6>; 554 resets = <&sys_rst 6>; 555 phy-mode = "rmii"; 556 local-mac-address = [00 00 00 00 00 00]; 557 558 mdio: mdio { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 }; 562 }; 563 564 nand: nand@68000000 { 565 compatible = "socionext,uniphier-denali-nand-v5b"; 566 status = "disabled"; 567 reg-names = "nand_data", "denali_reg"; 568 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 569 interrupts = <0 65 4>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&pinctrl_nand>; 572 clocks = <&sys_clk 2>; 573 resets = <&sys_rst 2>; 574 }; 575 }; 576}; 577 578#include "uniphier-pinctrl.dtsi" 579 580&pinctrl_aoutiec1 { 581 drive-strength = <4>; /* default: 4mA */ 582 583 ao1arc { 584 pins = "AO1ARC"; 585 drive-strength = <8>; /* 8mA */ 586 }; 587}; 588