1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD11 SoC 4// 5// Copyright (C) 2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "socionext,uniphier-ld11"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 }; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0 0x000>; 37 clocks = <&sys_clk 33>; 38 enable-method = "psci"; 39 next-level-cache = <&l2>; 40 operating-points-v2 = <&cluster0_opp>; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0 0x001>; 47 clocks = <&sys_clk 33>; 48 enable-method = "psci"; 49 next-level-cache = <&l2>; 50 operating-points-v2 = <&cluster0_opp>; 51 }; 52 53 l2: l2-cache { 54 compatible = "cache"; 55 cache-level = <2>; 56 cache-unified; 57 }; 58 }; 59 60 cluster0_opp: opp-table { 61 compatible = "operating-points-v2"; 62 opp-shared; 63 64 opp-245000000 { 65 opp-hz = /bits/ 64 <245000000>; 66 clock-latency-ns = <300>; 67 }; 68 opp-250000000 { 69 opp-hz = /bits/ 64 <250000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-490000000 { 73 opp-hz = /bits/ 64 <490000000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-500000000 { 77 opp-hz = /bits/ 64 <500000000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-653334000 { 81 opp-hz = /bits/ 64 <653334000>; 82 clock-latency-ns = <300>; 83 }; 84 opp-666667000 { 85 opp-hz = /bits/ 64 <666667000>; 86 clock-latency-ns = <300>; 87 }; 88 opp-980000000 { 89 opp-hz = /bits/ 64 <980000000>; 90 clock-latency-ns = <300>; 91 }; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0"; 96 method = "smc"; 97 }; 98 99 clocks { 100 refclk: ref { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <25000000>; 104 }; 105 }; 106 107 emmc_pwrseq: emmc-pwrseq { 108 compatible = "mmc-pwrseq-emmc"; 109 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 110 }; 111 112 timer { 113 compatible = "arm,armv8-timer"; 114 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 118 }; 119 120 reserved-memory { 121 #address-cells = <2>; 122 #size-cells = <2>; 123 ranges; 124 125 secure-memory@81000000 { 126 reg = <0x0 0x81000000 0x0 0x01000000>; 127 no-map; 128 }; 129 }; 130 131 soc@0 { 132 compatible = "simple-bus"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 ranges = <0 0 0 0xffffffff>; 136 137 spi0: spi@54006000 { 138 compatible = "socionext,uniphier-scssi"; 139 status = "disabled"; 140 reg = <0x54006000 0x100>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_spi0>; 146 clocks = <&peri_clk 11>; 147 resets = <&peri_rst 11>; 148 }; 149 150 spi1: spi@54006100 { 151 compatible = "socionext,uniphier-scssi"; 152 status = "disabled"; 153 reg = <0x54006100 0x100>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_spi1>; 159 clocks = <&peri_clk 12>; 160 resets = <&peri_rst 12>; 161 }; 162 163 serial0: serial@54006800 { 164 compatible = "socionext,uniphier-uart"; 165 status = "disabled"; 166 reg = <0x54006800 0x40>; 167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_uart0>; 170 clocks = <&peri_clk 0>; 171 resets = <&peri_rst 0>; 172 }; 173 174 serial1: serial@54006900 { 175 compatible = "socionext,uniphier-uart"; 176 status = "disabled"; 177 reg = <0x54006900 0x40>; 178 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_uart1>; 181 clocks = <&peri_clk 1>; 182 resets = <&peri_rst 1>; 183 }; 184 185 serial2: serial@54006a00 { 186 compatible = "socionext,uniphier-uart"; 187 status = "disabled"; 188 reg = <0x54006a00 0x40>; 189 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_uart2>; 192 clocks = <&peri_clk 2>; 193 resets = <&peri_rst 2>; 194 }; 195 196 serial3: serial@54006b00 { 197 compatible = "socionext,uniphier-uart"; 198 status = "disabled"; 199 reg = <0x54006b00 0x40>; 200 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_uart3>; 203 clocks = <&peri_clk 3>; 204 resets = <&peri_rst 3>; 205 }; 206 207 gpio: gpio@55000000 { 208 compatible = "socionext,uniphier-gpio"; 209 reg = <0x55000000 0x200>; 210 interrupt-parent = <&aidet>; 211 interrupt-controller; 212 #interrupt-cells = <2>; 213 gpio-controller; 214 #gpio-cells = <2>; 215 gpio-ranges = <&pinctrl 0 0 0>, 216 <&pinctrl 43 0 0>, 217 <&pinctrl 51 0 0>, 218 <&pinctrl 96 0 0>, 219 <&pinctrl 160 0 0>, 220 <&pinctrl 184 0 0>; 221 gpio-ranges-group-names = "gpio_range0", 222 "gpio_range1", 223 "gpio_range2", 224 "gpio_range3", 225 "gpio_range4", 226 "gpio_range5"; 227 ngpios = <200>; 228 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 229 <21 217 3>; 230 }; 231 232 audio@56000000 { 233 compatible = "socionext,uniphier-ld11-aio"; 234 reg = <0x56000000 0x80000>; 235 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_aout1>, 238 <&pinctrl_aoutiec1>; 239 clock-names = "aio"; 240 clocks = <&sys_clk 40>; 241 reset-names = "aio"; 242 resets = <&sys_rst 40>; 243 #sound-dai-cells = <1>; 244 socionext,syscon = <&soc_glue>; 245 246 i2s_port0: port@0 { 247 i2s_hdmi: endpoint { 248 }; 249 }; 250 251 i2s_port1: port@1 { 252 i2s_pcmin2: endpoint { 253 }; 254 }; 255 256 i2s_port2: port@2 { 257 i2s_line: endpoint { 258 dai-format = "i2s"; 259 remote-endpoint = <&evea_line>; 260 }; 261 }; 262 263 i2s_port3: port@3 { 264 i2s_hpcmout1: endpoint { 265 }; 266 }; 267 268 i2s_port4: port@4 { 269 i2s_hp: endpoint { 270 dai-format = "i2s"; 271 remote-endpoint = <&evea_hp>; 272 }; 273 }; 274 275 spdif_port0: port@5 { 276 spdif_hiecout1: endpoint { 277 }; 278 }; 279 280 src_port0: port@6 { 281 i2s_epcmout2: endpoint { 282 }; 283 }; 284 285 src_port1: port@7 { 286 i2s_epcmout3: endpoint { 287 }; 288 }; 289 290 comp_spdif_port0: port@8 { 291 comp_spdif_hiecout1: endpoint { 292 }; 293 }; 294 }; 295 296 codec@57900000 { 297 compatible = "socionext,uniphier-evea"; 298 reg = <0x57900000 0x1000>; 299 clock-names = "evea", "exiv"; 300 clocks = <&sys_clk 41>, <&sys_clk 42>; 301 reset-names = "evea", "exiv", "adamv"; 302 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; 303 #sound-dai-cells = <1>; 304 305 port@0 { 306 evea_line: endpoint { 307 remote-endpoint = <&i2s_line>; 308 }; 309 }; 310 311 port@1 { 312 evea_hp: endpoint { 313 remote-endpoint = <&i2s_hp>; 314 }; 315 }; 316 }; 317 318 syscon@57920000 { 319 compatible = "socionext,uniphier-ld11-adamv", 320 "simple-mfd", "syscon"; 321 reg = <0x57920000 0x1000>; 322 323 adamv_rst: reset-controller { 324 compatible = "socionext,uniphier-ld11-adamv-reset"; 325 #reset-cells = <1>; 326 }; 327 }; 328 329 i2c0: i2c@58780000 { 330 compatible = "socionext,uniphier-fi2c"; 331 status = "disabled"; 332 reg = <0x58780000 0x80>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_i2c0>; 338 clocks = <&peri_clk 4>; 339 resets = <&peri_rst 4>; 340 clock-frequency = <100000>; 341 }; 342 343 i2c1: i2c@58781000 { 344 compatible = "socionext,uniphier-fi2c"; 345 status = "disabled"; 346 reg = <0x58781000 0x80>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_i2c1>; 352 clocks = <&peri_clk 5>; 353 resets = <&peri_rst 5>; 354 clock-frequency = <100000>; 355 }; 356 357 i2c2: i2c@58782000 { 358 compatible = "socionext,uniphier-fi2c"; 359 reg = <0x58782000 0x80>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&peri_clk 6>; 364 resets = <&peri_rst 6>; 365 clock-frequency = <400000>; 366 }; 367 368 i2c3: i2c@58783000 { 369 compatible = "socionext,uniphier-fi2c"; 370 status = "disabled"; 371 reg = <0x58783000 0x80>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_i2c3>; 377 clocks = <&peri_clk 7>; 378 resets = <&peri_rst 7>; 379 clock-frequency = <100000>; 380 }; 381 382 i2c4: i2c@58784000 { 383 compatible = "socionext,uniphier-fi2c"; 384 status = "disabled"; 385 reg = <0x58784000 0x80>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_i2c4>; 391 clocks = <&peri_clk 8>; 392 resets = <&peri_rst 8>; 393 clock-frequency = <100000>; 394 }; 395 396 i2c5: i2c@58785000 { 397 compatible = "socionext,uniphier-fi2c"; 398 reg = <0x58785000 0x80>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&peri_clk 9>; 403 resets = <&peri_rst 9>; 404 clock-frequency = <400000>; 405 }; 406 407 system_bus: system-bus@58c00000 { 408 compatible = "socionext,uniphier-system-bus"; 409 status = "disabled"; 410 reg = <0x58c00000 0x400>; 411 #address-cells = <2>; 412 #size-cells = <1>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_system_bus>; 415 }; 416 417 smpctrl@59801000 { 418 compatible = "socionext,uniphier-smpctrl"; 419 reg = <0x59801000 0x400>; 420 }; 421 422 syscon@59810000 { 423 compatible = "socionext,uniphier-ld11-sdctrl", 424 "simple-mfd", "syscon"; 425 reg = <0x59810000 0x400>; 426 427 sd_rst: reset-controller { 428 compatible = "socionext,uniphier-ld11-sd-reset"; 429 #reset-cells = <1>; 430 }; 431 }; 432 433 syscon@59820000 { 434 compatible = "socionext,uniphier-ld11-perictrl", 435 "simple-mfd", "syscon"; 436 reg = <0x59820000 0x200>; 437 438 peri_clk: clock-controller { 439 compatible = "socionext,uniphier-ld11-peri-clock"; 440 #clock-cells = <1>; 441 }; 442 443 peri_rst: reset-controller { 444 compatible = "socionext,uniphier-ld11-peri-reset"; 445 #reset-cells = <1>; 446 }; 447 }; 448 449 emmc: mmc@5a000000 { 450 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 451 reg = <0x5a000000 0x400>; 452 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_emmc>; 455 clocks = <&sys_clk 4>; 456 resets = <&sys_rst 4>; 457 bus-width = <8>; 458 mmc-ddr-1_8v; 459 mmc-hs200-1_8v; 460 mmc-pwrseq = <&emmc_pwrseq>; 461 cdns,phy-input-delay-legacy = <9>; 462 cdns,phy-input-delay-mmc-highspeed = <2>; 463 cdns,phy-input-delay-mmc-ddr = <3>; 464 cdns,phy-dll-delay-sdclk = <21>; 465 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 466 }; 467 468 usb0: usb@5a800100 { 469 compatible = "socionext,uniphier-ehci", "generic-ehci"; 470 status = "disabled"; 471 reg = <0x5a800100 0x100>; 472 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pinctrl_usb0>; 475 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 476 <&mio_clk 12>; 477 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 478 <&mio_rst 12>; 479 phy-names = "usb"; 480 phys = <&usb_phy0>; 481 has-transaction-translator; 482 }; 483 484 usb1: usb@5a810100 { 485 compatible = "socionext,uniphier-ehci", "generic-ehci"; 486 status = "disabled"; 487 reg = <0x5a810100 0x100>; 488 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_usb1>; 491 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 492 <&mio_clk 13>; 493 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 494 <&mio_rst 13>; 495 phy-names = "usb"; 496 phys = <&usb_phy1>; 497 has-transaction-translator; 498 }; 499 500 usb2: usb@5a820100 { 501 compatible = "socionext,uniphier-ehci", "generic-ehci"; 502 status = "disabled"; 503 reg = <0x5a820100 0x100>; 504 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pinctrl_usb2>; 507 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 508 <&mio_clk 14>; 509 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 510 <&mio_rst 14>; 511 phy-names = "usb"; 512 phys = <&usb_phy2>; 513 has-transaction-translator; 514 }; 515 516 syscon@5b3e0000 { 517 compatible = "socionext,uniphier-ld11-mioctrl", 518 "simple-mfd", "syscon"; 519 reg = <0x5b3e0000 0x800>; 520 521 mio_clk: clock-controller { 522 compatible = "socionext,uniphier-ld11-mio-clock"; 523 #clock-cells = <1>; 524 }; 525 526 mio_rst: reset-controller { 527 compatible = "socionext,uniphier-ld11-mio-reset"; 528 #reset-cells = <1>; 529 resets = <&sys_rst 7>; 530 }; 531 }; 532 533 soc_glue: syscon@5f800000 { 534 compatible = "socionext,uniphier-ld11-soc-glue", 535 "simple-mfd", "syscon"; 536 reg = <0x5f800000 0x2000>; 537 538 pinctrl: pinctrl { 539 compatible = "socionext,uniphier-ld11-pinctrl"; 540 }; 541 542 usb-hub { 543 compatible = "socionext,uniphier-ld11-usb2-phy"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 547 usb_phy0: phy@0 { 548 reg = <0>; 549 #phy-cells = <0>; 550 }; 551 552 usb_phy1: phy@1 { 553 reg = <1>; 554 #phy-cells = <0>; 555 }; 556 557 usb_phy2: phy@2 { 558 reg = <2>; 559 #phy-cells = <0>; 560 }; 561 }; 562 }; 563 564 syscon@5f900000 { 565 compatible = "socionext,uniphier-ld11-soc-glue-debug", 566 "simple-mfd", "syscon"; 567 reg = <0x5f900000 0x2000>; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 ranges = <0 0x5f900000 0x2000>; 571 572 efuse@100 { 573 compatible = "socionext,uniphier-efuse"; 574 reg = <0x100 0x28>; 575 }; 576 577 efuse@200 { 578 compatible = "socionext,uniphier-efuse"; 579 reg = <0x200 0x68>; 580 }; 581 }; 582 583 xdmac: dma-controller@5fc10000 { 584 compatible = "socionext,uniphier-xdmac"; 585 reg = <0x5fc10000 0x5300>; 586 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 587 dma-channels = <16>; 588 #dma-cells = <2>; 589 }; 590 591 aidet: interrupt-controller@5fc20000 { 592 compatible = "socionext,uniphier-ld11-aidet"; 593 reg = <0x5fc20000 0x200>; 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 }; 597 598 gic: interrupt-controller@5fe00000 { 599 compatible = "arm,gic-v3"; 600 reg = <0x5fe00000 0x10000>, /* GICD */ 601 <0x5fe40000 0x80000>; /* GICR */ 602 interrupt-controller; 603 #interrupt-cells = <3>; 604 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 605 }; 606 607 syscon@61840000 { 608 compatible = "socionext,uniphier-ld11-sysctrl", 609 "simple-mfd", "syscon"; 610 reg = <0x61840000 0x10000>; 611 612 sys_clk: clock-controller { 613 compatible = "socionext,uniphier-ld11-clock"; 614 #clock-cells = <1>; 615 }; 616 617 sys_rst: reset-controller { 618 compatible = "socionext,uniphier-ld11-reset"; 619 #reset-cells = <1>; 620 }; 621 622 watchdog { 623 compatible = "socionext,uniphier-wdt"; 624 }; 625 }; 626 627 eth: ethernet@65000000 { 628 compatible = "socionext,uniphier-ld11-ave4"; 629 status = "disabled"; 630 reg = <0x65000000 0x8500>; 631 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 632 clock-names = "ether"; 633 clocks = <&sys_clk 6>; 634 reset-names = "ether"; 635 resets = <&sys_rst 6>; 636 phy-mode = "internal"; 637 local-mac-address = [00 00 00 00 00 00]; 638 socionext,syscon-phy-mode = <&soc_glue 0>; 639 640 mdio: mdio { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 }; 644 }; 645 646 nand: nand-controller@68000000 { 647 compatible = "socionext,uniphier-denali-nand-v5b"; 648 status = "disabled"; 649 reg-names = "nand_data", "denali_reg"; 650 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&pinctrl_nand>; 656 clock-names = "nand", "nand_x", "ecc"; 657 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 658 reset-names = "nand", "reg"; 659 resets = <&sys_rst 2>, <&sys_rst 2>; 660 }; 661 }; 662}; 663 664#include "uniphier-pinctrl.dtsi" 665 666&pinctrl_aoutiec1 { 667 drive-strength = <4>; /* default: 4mA */ 668 669 ao1arc { 670 pins = "AO1ARC"; 671 drive-strength = <8>; /* 8mA */ 672 }; 673}; 674