1*86a504b8SChukun Pan// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*86a504b8SChukun Pan 3*86a504b8SChukun Pan/dts-v1/; 4*86a504b8SChukun Pan 5*86a504b8SChukun Pan#include "rk3568-hinlink-opc.dtsi" 6*86a504b8SChukun Pan 7*86a504b8SChukun Pan/ { 8*86a504b8SChukun Pan model = "HINLINK H68K"; 9*86a504b8SChukun Pan compatible = "hinlink,h68k", "rockchip,rk3568"; 10*86a504b8SChukun Pan 11*86a504b8SChukun Pan aliases { 12*86a504b8SChukun Pan ethernet0 = &gmac0; 13*86a504b8SChukun Pan ethernet1 = &gmac1; 14*86a504b8SChukun Pan }; 15*86a504b8SChukun Pan}; 16*86a504b8SChukun Pan 17*86a504b8SChukun Pan&gmac0 { 18*86a504b8SChukun Pan assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 19*86a504b8SChukun Pan assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 20*86a504b8SChukun Pan assigned-clock-rates = <0>, <125000000>; 21*86a504b8SChukun Pan clock_in_out = "output"; 22*86a504b8SChukun Pan phy-handle = <&rgmii_phy0>; 23*86a504b8SChukun Pan phy-mode = "rgmii-id"; 24*86a504b8SChukun Pan phy-supply = <&vcc3v3_sys>; 25*86a504b8SChukun Pan pinctrl-names = "default"; 26*86a504b8SChukun Pan pinctrl-0 = <&gmac0_miim 27*86a504b8SChukun Pan &gmac0_tx_bus2 28*86a504b8SChukun Pan &gmac0_rx_bus2 29*86a504b8SChukun Pan &gmac0_rgmii_clk 30*86a504b8SChukun Pan &gmac0_rgmii_bus 31*86a504b8SChukun Pan &gmac0_rstn>; 32*86a504b8SChukun Pan status = "okay"; 33*86a504b8SChukun Pan}; 34*86a504b8SChukun Pan 35*86a504b8SChukun Pan&gmac1 { 36*86a504b8SChukun Pan assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 37*86a504b8SChukun Pan assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 38*86a504b8SChukun Pan assigned-clock-rates = <0>, <125000000>; 39*86a504b8SChukun Pan clock_in_out = "output"; 40*86a504b8SChukun Pan phy-handle = <&rgmii_phy1>; 41*86a504b8SChukun Pan phy-mode = "rgmii-id"; 42*86a504b8SChukun Pan phy-supply = <&vcc3v3_sys>; 43*86a504b8SChukun Pan pinctrl-names = "default"; 44*86a504b8SChukun Pan pinctrl-0 = <&gmac1m1_miim 45*86a504b8SChukun Pan &gmac1m1_tx_bus2 46*86a504b8SChukun Pan &gmac1m1_rx_bus2 47*86a504b8SChukun Pan &gmac1m1_rgmii_clk 48*86a504b8SChukun Pan &gmac1m1_rgmii_bus 49*86a504b8SChukun Pan &gmac1_rstn>; 50*86a504b8SChukun Pan status = "okay"; 51*86a504b8SChukun Pan}; 52*86a504b8SChukun Pan 53*86a504b8SChukun Pan&mdio0 { 54*86a504b8SChukun Pan rgmii_phy0: ethernet-phy@1 { 55*86a504b8SChukun Pan compatible = "ethernet-phy-ieee802.3-c22"; 56*86a504b8SChukun Pan reg = <0x1>; 57*86a504b8SChukun Pan reset-assert-us = <20000>; 58*86a504b8SChukun Pan reset-deassert-us = <100000>; 59*86a504b8SChukun Pan reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 60*86a504b8SChukun Pan }; 61*86a504b8SChukun Pan}; 62*86a504b8SChukun Pan 63*86a504b8SChukun Pan&mdio1 { 64*86a504b8SChukun Pan rgmii_phy1: ethernet-phy@1 { 65*86a504b8SChukun Pan compatible = "ethernet-phy-ieee802.3-c22"; 66*86a504b8SChukun Pan reg = <0x1>; 67*86a504b8SChukun Pan reset-assert-us = <20000>; 68*86a504b8SChukun Pan reset-deassert-us = <100000>; 69*86a504b8SChukun Pan reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; 70*86a504b8SChukun Pan }; 71*86a504b8SChukun Pan}; 72*86a504b8SChukun Pan 73*86a504b8SChukun Pan&pinctrl { 74*86a504b8SChukun Pan gmac { 75*86a504b8SChukun Pan gmac0_rstn: gmac0-rstn { 76*86a504b8SChukun Pan rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 77*86a504b8SChukun Pan }; 78*86a504b8SChukun Pan 79*86a504b8SChukun Pan gmac1_rstn: gmac1-rstn { 80*86a504b8SChukun Pan rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 81*86a504b8SChukun Pan }; 82*86a504b8SChukun Pan }; 83*86a504b8SChukun Pan}; 84