1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3/dts-v1/; 4 5#include "rk3568-hinlink-opc.dtsi" 6 7/ { 8 model = "HINLINK H68K"; 9 compatible = "hinlink,h68k", "rockchip,rk3568"; 10 11 aliases { 12 ethernet0 = &gmac0; 13 ethernet1 = &gmac1; 14 }; 15}; 16 17&gmac0 { 18 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 19 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 20 assigned-clock-rates = <0>, <125000000>; 21 clock_in_out = "output"; 22 phy-handle = <&rgmii_phy0>; 23 phy-mode = "rgmii-id"; 24 phy-supply = <&vcc3v3_sys>; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&gmac0_miim 27 &gmac0_tx_bus2 28 &gmac0_rx_bus2 29 &gmac0_rgmii_clk 30 &gmac0_rgmii_bus 31 &gmac0_rstn>; 32 status = "okay"; 33}; 34 35&gmac1 { 36 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 37 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 38 assigned-clock-rates = <0>, <125000000>; 39 clock_in_out = "output"; 40 phy-handle = <&rgmii_phy1>; 41 phy-mode = "rgmii-id"; 42 phy-supply = <&vcc3v3_sys>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&gmac1m1_miim 45 &gmac1m1_tx_bus2 46 &gmac1m1_rx_bus2 47 &gmac1m1_rgmii_clk 48 &gmac1m1_rgmii_bus 49 &gmac1_rstn>; 50 status = "okay"; 51}; 52 53&mdio0 { 54 rgmii_phy0: ethernet-phy@1 { 55 compatible = "ethernet-phy-ieee802.3-c22"; 56 reg = <0x1>; 57 reset-assert-us = <20000>; 58 reset-deassert-us = <100000>; 59 reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 60 }; 61}; 62 63&mdio1 { 64 rgmii_phy1: ethernet-phy@1 { 65 compatible = "ethernet-phy-ieee802.3-c22"; 66 reg = <0x1>; 67 reset-assert-us = <20000>; 68 reset-deassert-us = <100000>; 69 reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; 70 }; 71}; 72 73&pinctrl { 74 gmac { 75 gmac0_rstn: gmac0-rstn { 76 rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 77 }; 78 79 gmac1_rstn: gmac1-rstn { 80 rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 81 }; 82 }; 83}; 84