1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/N2H SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g087"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a55"; 22 reg = <0>; 23 device_type = "cpu"; 24 next-level-cache = <&L3_CA55>; 25 enable-method = "psci"; 26 }; 27 28 cpu1: cpu@100 { 29 compatible = "arm,cortex-a55"; 30 reg = <0x100>; 31 device_type = "cpu"; 32 next-level-cache = <&L3_CA55>; 33 enable-method = "psci"; 34 }; 35 36 cpu2: cpu@200 { 37 compatible = "arm,cortex-a55"; 38 reg = <0x200>; 39 device_type = "cpu"; 40 next-level-cache = <&L3_CA55>; 41 enable-method = "psci"; 42 }; 43 44 cpu3: cpu@300 { 45 compatible = "arm,cortex-a55"; 46 reg = <0x300>; 47 device_type = "cpu"; 48 next-level-cache = <&L3_CA55>; 49 enable-method = "psci"; 50 }; 51 52 L3_CA55: cache-controller-0 { 53 compatible = "cache"; 54 cache-unified; 55 cache-size = <0x100000>; 56 cache-level = <3>; 57 }; 58 }; 59 60 extal_clk: extal { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 /* This value must be overridden by the board */ 64 clock-frequency = <0>; 65 }; 66 67 psci { 68 compatible = "arm,psci-1.0", "arm,psci-0.2"; 69 method = "smc"; 70 }; 71 72 soc: soc { 73 compatible = "simple-bus"; 74 interrupt-parent = <&gic>; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 sci0: serial@80005000 { 80 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 81 reg = <0 0x80005000 0 0x400>; 82 interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, 84 <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, 85 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; 86 interrupt-names = "eri", "rxi", "txi", "tei"; 87 clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 88 clock-names = "operation", "bus"; 89 power-domains = <&cpg>; 90 status = "disabled"; 91 }; 92 93 sci1: serial@80005400 { 94 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 95 reg = <0 0x80005400 0 0x400>; 96 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, 98 <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, 99 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 100 interrupt-names = "eri", "rxi", "txi", "tei"; 101 clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 102 clock-names = "operation", "bus"; 103 power-domains = <&cpg>; 104 status = "disabled"; 105 }; 106 107 sci2: serial@80005800 { 108 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 109 reg = <0 0x80005800 0 0x400>; 110 interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, 112 <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, 113 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-names = "eri", "rxi", "txi", "tei"; 115 clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 116 clock-names = "operation", "bus"; 117 power-domains = <&cpg>; 118 status = "disabled"; 119 }; 120 121 sci3: serial@80005c00 { 122 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 123 reg = <0 0x80005c00 0 0x400>; 124 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 126 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 127 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 128 interrupt-names = "eri", "rxi", "txi", "tei"; 129 clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 130 clock-names = "operation", "bus"; 131 power-domains = <&cpg>; 132 status = "disabled"; 133 }; 134 135 sci4: serial@80006000 { 136 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 137 reg = <0 0x80006000 0 0x400>; 138 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, 140 <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, 141 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-names = "eri", "rxi", "txi", "tei"; 143 clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 144 clock-names = "operation", "bus"; 145 power-domains = <&cpg>; 146 status = "disabled"; 147 }; 148 149 sci5: serial@81005000 { 150 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 151 reg = <0 0x81005000 0 0x400>; 152 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, 154 <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, 155 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 156 interrupt-names = "eri", "rxi", "txi", "tei"; 157 clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 158 clock-names = "operation", "bus"; 159 power-domains = <&cpg>; 160 status = "disabled"; 161 }; 162 163 wdt0: watchdog@80082000 { 164 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 165 reg = <0 0x80082000 0 0x400>, 166 <0 0x81295100 0 0x04>; 167 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 168 clock-names = "pclk"; 169 power-domains = <&cpg>; 170 status = "disabled"; 171 }; 172 173 wdt1: watchdog@80082400 { 174 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 175 reg = <0 0x80082400 0 0x400>, 176 <0 0x81295104 0 0x04>; 177 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 178 clock-names = "pclk"; 179 power-domains = <&cpg>; 180 status = "disabled"; 181 }; 182 183 wdt2: watchdog@80082800 { 184 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 185 reg = <0 0x80082800 0 0x400>, 186 <0 0x81295108 0 0x04>; 187 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 188 clock-names = "pclk"; 189 power-domains = <&cpg>; 190 status = "disabled"; 191 }; 192 193 wdt3: watchdog@80082c00 { 194 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 195 reg = <0 0x80082c00 0 0x400>, 196 <0 0x8129510c 0 0x04>; 197 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 198 clock-names = "pclk"; 199 power-domains = <&cpg>; 200 status = "disabled"; 201 }; 202 203 wdt4: watchdog@80083000 { 204 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 205 reg = <0 0x80083000 0 0x400>, 206 <0 0x81295110 0 0x04>; 207 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 208 clock-names = "pclk"; 209 power-domains = <&cpg>; 210 status = "disabled"; 211 }; 212 213 wdt5: watchdog@80083400 { 214 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 215 reg = <0 0x80083400 0 0x400>, 216 <0 0x81295114 0 0x04>; 217 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 218 clock-names = "pclk"; 219 power-domains = <&cpg>; 220 status = "disabled"; 221 }; 222 223 i2c0: i2c@80088000 { 224 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 225 reg = <0 0x80088000 0 0x400>; 226 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, 228 <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, 229 <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "eei", "rxi", "txi", "tei"; 231 clocks = <&cpg CPG_MOD 100>; 232 power-domains = <&cpg>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 status = "disabled"; 236 }; 237 238 i2c1: i2c@80088400 { 239 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 240 reg = <0 0x80088400 0 0x400>; 241 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, 243 <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, 244 <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; 245 interrupt-names = "eei", "rxi", "txi", "tei"; 246 clocks = <&cpg CPG_MOD 101>; 247 power-domains = <&cpg>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 i2c2: i2c@81008000 { 254 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 255 reg = <0 0x81008000 0 0x400>; 256 interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, 258 <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 259 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-names = "eei", "rxi", "txi", "tei"; 261 clocks = <&cpg CPG_MOD 601>; 262 power-domains = <&cpg>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 status = "disabled"; 266 }; 267 268 cpg: clock-controller@80280000 { 269 compatible = "renesas,r9a09g087-cpg-mssr"; 270 reg = <0 0x80280000 0 0x1000>, 271 <0 0x81280000 0 0x9000>; 272 clocks = <&extal_clk>; 273 clock-names = "extal"; 274 #clock-cells = <2>; 275 #reset-cells = <1>; 276 #power-domain-cells = <0>; 277 }; 278 279 pinctrl: pinctrl@802c0000 { 280 compatible = "renesas,r9a09g087-pinctrl"; 281 reg = <0 0x802c0000 0 0x10000>, 282 <0 0x812c0000 0 0x10000>, 283 <0 0x802b0000 0 0x10000>; 284 reg-names = "nsr", "srs", "srn"; 285 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 286 gpio-controller; 287 #gpio-cells = <2>; 288 gpio-ranges = <&pinctrl 0 0 280>; 289 power-domains = <&cpg>; 290 }; 291 292 gic: interrupt-controller@83000000 { 293 compatible = "arm,gic-v3"; 294 reg = <0x0 0x83000000 0 0x40000>, 295 <0x0 0x83040000 0 0x160000>; 296 #interrupt-cells = <3>; 297 #address-cells = <0>; 298 interrupt-controller; 299 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 300 }; 301 302 ohci: usb@92040000 { 303 compatible = "generic-ohci"; 304 reg = <0 0x92040000 0 0x100>; 305 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&cpg CPG_MOD 408>; 307 phys = <&usb2_phy 1>; 308 phy-names = "usb"; 309 power-domains = <&cpg>; 310 status = "disabled"; 311 }; 312 313 ehci: usb@92040100 { 314 compatible = "generic-ehci"; 315 reg = <0 0x92040100 0 0x100>; 316 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&cpg CPG_MOD 408>; 318 phys = <&usb2_phy 2>; 319 phy-names = "usb"; 320 companion = <&ohci>; 321 power-domains = <&cpg>; 322 status = "disabled"; 323 }; 324 325 usb2_phy: usb-phy@92040200 { 326 compatible = "renesas,usb2-phy-r9a09g087", "renesas,usb2-phy-r9a09g077"; 327 reg = <0 0x92040200 0 0x700>; 328 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&cpg CPG_MOD 408>, 330 <&cpg CPG_CORE R9A09G087_USB_CLK>; 331 #phy-cells = <1>; 332 power-domains = <&cpg>; 333 status = "disabled"; 334 }; 335 336 hsusb: usb@92041000 { 337 compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077"; 338 reg = <0 0x92041000 0 0x1000>; 339 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&cpg CPG_MOD 408>; 343 phys = <&usb2_phy 3>; 344 phy-names = "usb"; 345 power-domains = <&cpg>; 346 status = "disabled"; 347 }; 348 349 sdhi0: mmc@92080000 { 350 compatible = "renesas,sdhi-r9a09g087", 351 "renesas,sdhi-r9a09g057"; 352 reg = <0x0 0x92080000 0 0x10000>; 353 interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&cpg CPG_MOD 1212>, 356 <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; 357 clock-names = "aclk", "clkh"; 358 power-domains = <&cpg>; 359 status = "disabled"; 360 361 sdhi0_vqmmc: vqmmc-regulator { 362 regulator-name = "SDHI0-VQMMC"; 363 regulator-min-microvolt = <1800000>; 364 regulator-max-microvolt = <3300000>; 365 status = "disabled"; 366 }; 367 }; 368 369 sdhi1: mmc@92090000 { 370 compatible = "renesas,sdhi-r9a09g087", 371 "renesas,sdhi-r9a09g057"; 372 reg = <0x0 0x92090000 0 0x10000>; 373 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 1213>, 376 <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; 377 clock-names = "aclk", "clkh"; 378 power-domains = <&cpg>; 379 status = "disabled"; 380 381 sdhi1_vqmmc: vqmmc-regulator { 382 regulator-name = "SDHI1-VQMMC"; 383 regulator-min-microvolt = <1800000>; 384 regulator-max-microvolt = <3300000>; 385 status = "disabled"; 386 }; 387 }; 388 }; 389 390 timer { 391 compatible = "arm,armv8-timer"; 392 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 393 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 394 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 395 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 396 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 397 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 398 }; 399}; 400