1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) 4 * 5 * Copyright (C) 2019 Renesas Electronics Corp. 6 */ 7 8/dts-v1/; 9#include "r8a774c0.dtsi" 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; 14 compatible = "si-linux,cat874", "renesas,r8a774c0"; 15 16 aliases { 17 serial0 = &scif2; 18 }; 19 20 chosen { 21 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 hdmi-out { 26 compatible = "hdmi-connector"; 27 type = "a"; 28 29 port { 30 hdmi_con_out: endpoint { 31 remote-endpoint = <&tda19988_out>; 32 }; 33 }; 34 }; 35 36 leds { 37 compatible = "gpio-leds"; 38 39 led0 { 40 gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 41 label = "LED0"; 42 }; 43 44 led1 { 45 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 46 label = "LED1"; 47 }; 48 49 led2 { 50 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; 51 label = "LED2"; 52 }; 53 54 led3 { 55 gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; 56 label = "LED3"; 57 }; 58 }; 59 60 memory@48000000 { 61 device_type = "memory"; 62 /* first 128MB is reserved for secure area. */ 63 reg = <0x0 0x48000000 0x0 0x78000000>; 64 }; 65 66 vcc_sdhi0: regulator-vcc-sdhi0 { 67 compatible = "regulator-fixed"; 68 69 regulator-name = "SDHI0 Vcc"; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 regulator-always-on; 73 regulator-boot-on; 74 }; 75 76 vccq_sdhi0: regulator-vccq-sdhi0 { 77 compatible = "regulator-gpio"; 78 79 regulator-name = "SDHI0 VccQ"; 80 regulator-min-microvolt = <1800000>; 81 regulator-max-microvolt = <3300000>; 82 83 gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 84 gpios-states = <1>; 85 states = <3300000 1 86 1800000 0>; 87 }; 88 89 x13_clk: x13 { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <74250000>; 93 }; 94}; 95 96&du { 97 pinctrl-0 = <&du_pins>; 98 pinctrl-names = "default"; 99 status = "okay"; 100 101 clocks = <&cpg CPG_MOD 724>, 102 <&cpg CPG_MOD 723>, 103 <&x13_clk>; 104 clock-names = "du.0", "du.1", "dclkin.0"; 105 106 ports { 107 port@0 { 108 endpoint { 109 remote-endpoint = <&tda19988_in>; 110 }; 111 }; 112 }; 113}; 114 115&ehci0 { 116 dr_mode = "host"; 117 status = "okay"; 118}; 119 120&extal_clk { 121 clock-frequency = <48000000>; 122}; 123 124&i2c0 { 125 status = "okay"; 126 clock-frequency = <100000>; 127 128 tda19988: tda19988@70 { 129 compatible = "nxp,tda998x"; 130 reg = <0x70>; 131 interrupt-parent = <&gpio1>; 132 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 133 134 video-ports = <0x234501>; 135 136 ports { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 port@0 { 141 reg = <0>; 142 tda19988_in: endpoint { 143 remote-endpoint = <&du_out_rgb>; 144 }; 145 }; 146 147 port@1 { 148 reg = <1>; 149 tda19988_out: endpoint { 150 remote-endpoint = <&hdmi_con_out>; 151 }; 152 }; 153 }; 154 }; 155}; 156 157&i2c1 { 158 pinctrl-0 = <&i2c1_pins>; 159 pinctrl-names = "default"; 160 161 status = "okay"; 162 clock-frequency = <400000>; 163 164 rtc@32 { 165 compatible = "epson,rx8571"; 166 reg = <0x32>; 167 }; 168}; 169 170&lvds0 { 171 status = "okay"; 172 173 clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; 174 clock-names = "fck", "dclkin.0", "extal"; 175}; 176 177&ohci0 { 178 dr_mode = "host"; 179 status = "okay"; 180}; 181 182&pcie_bus_clk { 183 clock-frequency = <100000000>; 184}; 185 186&pciec0 { 187 /* Map all possible DDR as inbound ranges */ 188 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 189}; 190 191&pfc { 192 du_pins: du { 193 groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp", 194 "du_clk_in_0"; 195 function = "du"; 196 }; 197 198 i2c1_pins: i2c1 { 199 groups = "i2c1_b"; 200 function = "i2c1"; 201 }; 202 203 scif2_pins: scif2 { 204 groups = "scif2_data_a"; 205 function = "scif2"; 206 }; 207 208 sdhi0_pins: sd0 { 209 groups = "sdhi0_data4", "sdhi0_ctrl"; 210 function = "sdhi0"; 211 power-source = <3300>; 212 }; 213 214 sdhi0_pins_uhs: sd0_uhs { 215 groups = "sdhi0_data4", "sdhi0_ctrl"; 216 function = "sdhi0"; 217 power-source = <1800>; 218 }; 219}; 220 221&rwdt { 222 timeout-sec = <60>; 223 status = "okay"; 224}; 225 226&scif2 { 227 pinctrl-0 = <&scif2_pins>; 228 pinctrl-names = "default"; 229 230 status = "okay"; 231}; 232 233&sdhi0 { 234 pinctrl-0 = <&sdhi0_pins>; 235 pinctrl-1 = <&sdhi0_pins_uhs>; 236 pinctrl-names = "default", "state_uhs"; 237 238 vmmc-supply = <&vcc_sdhi0>; 239 vqmmc-supply = <&vccq_sdhi0>; 240 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; 241 bus-width = <4>; 242 sd-uhs-sdr50; 243 sd-uhs-sdr104; 244 status = "okay"; 245}; 246 247&usb2_phy0 { 248 renesas,no-otg-pins; 249 status = "okay"; 250}; 251