// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) * * Copyright (C) 2019 Renesas Electronics Corp. */ /dts-v1/; #include "r8a774c0.dtsi" #include / { model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; compatible = "si-linux,cat874", "renesas,r8a774c0"; aliases { serial0 = &scif2; }; chosen { bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; hdmi-out { compatible = "hdmi-connector"; type = "a"; port { hdmi_con_out: endpoint { remote-endpoint = <&tda19988_out>; }; }; }; leds { compatible = "gpio-leds"; led0 { gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; label = "LED0"; }; led1 { gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; label = "LED1"; }; led2 { gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; label = "LED2"; }; led3 { gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; label = "LED3"; }; }; memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; }; vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1 1800000 0>; }; x13_clk: x13 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <74250000>; }; }; &du { pinctrl-0 = <&du_pins>; pinctrl-names = "default"; status = "okay"; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x13_clk>; clock-names = "du.0", "du.1", "dclkin.0"; ports { port@0 { endpoint { remote-endpoint = <&tda19988_in>; }; }; }; }; &ehci0 { dr_mode = "host"; status = "okay"; }; &extal_clk { clock-frequency = <48000000>; }; &i2c0 { status = "okay"; clock-frequency = <100000>; tda19988: tda19988@70 { compatible = "nxp,tda998x"; reg = <0x70>; interrupt-parent = <&gpio1>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; video-ports = <0x234501>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tda19988_in: endpoint { remote-endpoint = <&du_out_rgb>; }; }; port@1 { reg = <1>; tda19988_out: endpoint { remote-endpoint = <&hdmi_con_out>; }; }; }; }; }; &i2c1 { pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; status = "okay"; clock-frequency = <400000>; rtc@32 { compatible = "epson,rx8571"; reg = <0x32>; }; }; &lvds0 { status = "okay"; clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; clock-names = "fck", "dclkin.0", "extal"; }; &ohci0 { dr_mode = "host"; status = "okay"; }; &pcie_bus_clk { clock-frequency = <100000000>; }; &pciec0 { /* Map all possible DDR as inbound ranges */ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; }; &pfc { du_pins: du { groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp", "du_clk_in_0"; function = "du"; }; i2c1_pins: i2c1 { groups = "i2c1_b"; function = "i2c1"; }; scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; }; sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; power-source = <3300>; }; sdhi0_pins_uhs: sd0_uhs { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; power-source = <1800>; }; }; &rwdt { timeout-sec = <60>; status = "okay"; }; &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; status = "okay"; }; &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-1 = <&sdhi0_pins_uhs>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; bus-width = <4>; sd-uhs-sdr50; sd-uhs-sdr104; status = "okay"; }; &usb2_phy0 { renesas,no-otg-pins; status = "okay"; };