1*ceff7d21SGeert Uytterhoeven// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*ceff7d21SGeert Uytterhoeven/* 3*ceff7d21SGeert Uytterhoeven * Device Tree Source for the Gray Hawk Single board 4*ceff7d21SGeert Uytterhoeven * 5*ceff7d21SGeert Uytterhoeven * Copyright (C) 2023 Renesas Electronics Corp. 6*ceff7d21SGeert Uytterhoeven * Copyright (C) 2024-2025 Glider bv 7*ceff7d21SGeert Uytterhoeven */ 8*ceff7d21SGeert Uytterhoeven/* 9*ceff7d21SGeert Uytterhoeven * [How to use Sound] 10*ceff7d21SGeert Uytterhoeven * 11*ceff7d21SGeert Uytterhoeven * Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture 12*ceff7d21SGeert Uytterhoeven * at the same time. You need to switch the direction which is controlled 13*ceff7d21SGeert Uytterhoeven * by the GP0_01 pin via amixer. 14*ceff7d21SGeert Uytterhoeven * 15*ceff7d21SGeert Uytterhoeven * Playback (CN9500) 16*ceff7d21SGeert Uytterhoeven * > amixer set "MUX" "Playback" // for GP0_01 17*ceff7d21SGeert Uytterhoeven * > amixer set "DAC 1" 85% 18*ceff7d21SGeert Uytterhoeven * > aplay xxx.wav 19*ceff7d21SGeert Uytterhoeven * 20*ceff7d21SGeert Uytterhoeven * Capture (CN9501) 21*ceff7d21SGeert Uytterhoeven * > amixer set "MUX" "Capture" // for GP0_01 22*ceff7d21SGeert Uytterhoeven * > amixer set "Mic 1" 80% 23*ceff7d21SGeert Uytterhoeven * > amixer set "ADC 1" on 24*ceff7d21SGeert Uytterhoeven * > amixer set 'ADC 1' 80% 25*ceff7d21SGeert Uytterhoeven * > arecord xxx hoge.wav 26*ceff7d21SGeert Uytterhoeven */ 27*ceff7d21SGeert Uytterhoeven 28*ceff7d21SGeert Uytterhoeven#include <dt-bindings/gpio/gpio.h> 29*ceff7d21SGeert Uytterhoeven#include <dt-bindings/input/input.h> 30*ceff7d21SGeert Uytterhoeven#include <dt-bindings/leds/common.h> 31*ceff7d21SGeert Uytterhoeven#include <dt-bindings/media/video-interfaces.h> 32*ceff7d21SGeert Uytterhoeven 33*ceff7d21SGeert Uytterhoeven/ { 34*ceff7d21SGeert Uytterhoeven model = "Renesas Gray Hawk Single board"; 35*ceff7d21SGeert Uytterhoeven compatible = "renesas,gray-hawk-single"; 36*ceff7d21SGeert Uytterhoeven 37*ceff7d21SGeert Uytterhoeven aliases { 38*ceff7d21SGeert Uytterhoeven i2c0 = &i2c0; 39*ceff7d21SGeert Uytterhoeven i2c1 = &i2c1; 40*ceff7d21SGeert Uytterhoeven i2c2 = &i2c2; 41*ceff7d21SGeert Uytterhoeven i2c3 = &i2c3; 42*ceff7d21SGeert Uytterhoeven serial0 = &hscif0; 43*ceff7d21SGeert Uytterhoeven serial1 = &hscif2; 44*ceff7d21SGeert Uytterhoeven ethernet0 = &avb0; 45*ceff7d21SGeert Uytterhoeven ethernet1 = &avb1; 46*ceff7d21SGeert Uytterhoeven ethernet2 = &avb2; 47*ceff7d21SGeert Uytterhoeven }; 48*ceff7d21SGeert Uytterhoeven 49*ceff7d21SGeert Uytterhoeven can_transceiver0: can-phy0 { 50*ceff7d21SGeert Uytterhoeven compatible = "nxp,tjr1443"; 51*ceff7d21SGeert Uytterhoeven #phy-cells = <0>; 52*ceff7d21SGeert Uytterhoeven enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 53*ceff7d21SGeert Uytterhoeven max-bitrate = <5000000>; 54*ceff7d21SGeert Uytterhoeven }; 55*ceff7d21SGeert Uytterhoeven 56*ceff7d21SGeert Uytterhoeven chosen { 57*ceff7d21SGeert Uytterhoeven bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 58*ceff7d21SGeert Uytterhoeven stdout-path = "serial0:921600n8"; 59*ceff7d21SGeert Uytterhoeven }; 60*ceff7d21SGeert Uytterhoeven 61*ceff7d21SGeert Uytterhoeven sn65dsi86_refclk: clk-x6 { 62*ceff7d21SGeert Uytterhoeven compatible = "fixed-clock"; 63*ceff7d21SGeert Uytterhoeven #clock-cells = <0>; 64*ceff7d21SGeert Uytterhoeven clock-frequency = <38400000>; 65*ceff7d21SGeert Uytterhoeven }; 66*ceff7d21SGeert Uytterhoeven 67*ceff7d21SGeert Uytterhoeven keys { 68*ceff7d21SGeert Uytterhoeven compatible = "gpio-keys"; 69*ceff7d21SGeert Uytterhoeven 70*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&keys_pins>; 71*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 72*ceff7d21SGeert Uytterhoeven 73*ceff7d21SGeert Uytterhoeven key-1 { 74*ceff7d21SGeert Uytterhoeven gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 75*ceff7d21SGeert Uytterhoeven linux,code = <KEY_1>; 76*ceff7d21SGeert Uytterhoeven label = "SW47"; 77*ceff7d21SGeert Uytterhoeven wakeup-source; 78*ceff7d21SGeert Uytterhoeven debounce-interval = <20>; 79*ceff7d21SGeert Uytterhoeven }; 80*ceff7d21SGeert Uytterhoeven 81*ceff7d21SGeert Uytterhoeven key-2 { 82*ceff7d21SGeert Uytterhoeven gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; 83*ceff7d21SGeert Uytterhoeven linux,code = <KEY_2>; 84*ceff7d21SGeert Uytterhoeven label = "SW48"; 85*ceff7d21SGeert Uytterhoeven wakeup-source; 86*ceff7d21SGeert Uytterhoeven debounce-interval = <20>; 87*ceff7d21SGeert Uytterhoeven }; 88*ceff7d21SGeert Uytterhoeven 89*ceff7d21SGeert Uytterhoeven key-3 { 90*ceff7d21SGeert Uytterhoeven gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 91*ceff7d21SGeert Uytterhoeven linux,code = <KEY_3>; 92*ceff7d21SGeert Uytterhoeven label = "SW49"; 93*ceff7d21SGeert Uytterhoeven wakeup-source; 94*ceff7d21SGeert Uytterhoeven debounce-interval = <20>; 95*ceff7d21SGeert Uytterhoeven }; 96*ceff7d21SGeert Uytterhoeven }; 97*ceff7d21SGeert Uytterhoeven 98*ceff7d21SGeert Uytterhoeven leds { 99*ceff7d21SGeert Uytterhoeven compatible = "gpio-leds"; 100*ceff7d21SGeert Uytterhoeven 101*ceff7d21SGeert Uytterhoeven led-1 { 102*ceff7d21SGeert Uytterhoeven gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 103*ceff7d21SGeert Uytterhoeven color = <LED_COLOR_ID_GREEN>; 104*ceff7d21SGeert Uytterhoeven function = LED_FUNCTION_INDICATOR; 105*ceff7d21SGeert Uytterhoeven function-enumerator = <1>; 106*ceff7d21SGeert Uytterhoeven }; 107*ceff7d21SGeert Uytterhoeven 108*ceff7d21SGeert Uytterhoeven led-2 { 109*ceff7d21SGeert Uytterhoeven gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 110*ceff7d21SGeert Uytterhoeven color = <LED_COLOR_ID_GREEN>; 111*ceff7d21SGeert Uytterhoeven function = LED_FUNCTION_INDICATOR; 112*ceff7d21SGeert Uytterhoeven function-enumerator = <2>; 113*ceff7d21SGeert Uytterhoeven }; 114*ceff7d21SGeert Uytterhoeven 115*ceff7d21SGeert Uytterhoeven led-3 { 116*ceff7d21SGeert Uytterhoeven gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 117*ceff7d21SGeert Uytterhoeven color = <LED_COLOR_ID_GREEN>; 118*ceff7d21SGeert Uytterhoeven function = LED_FUNCTION_INDICATOR; 119*ceff7d21SGeert Uytterhoeven function-enumerator = <3>; 120*ceff7d21SGeert Uytterhoeven }; 121*ceff7d21SGeert Uytterhoeven }; 122*ceff7d21SGeert Uytterhoeven 123*ceff7d21SGeert Uytterhoeven memory@48000000 { 124*ceff7d21SGeert Uytterhoeven device_type = "memory"; 125*ceff7d21SGeert Uytterhoeven /* first 128MB is reserved for secure area. */ 126*ceff7d21SGeert Uytterhoeven reg = <0x0 0x48000000 0x0 0x78000000>; 127*ceff7d21SGeert Uytterhoeven }; 128*ceff7d21SGeert Uytterhoeven 129*ceff7d21SGeert Uytterhoeven memory@480000000 { 130*ceff7d21SGeert Uytterhoeven device_type = "memory"; 131*ceff7d21SGeert Uytterhoeven reg = <0x4 0x80000000 0x1 0x80000000>; 132*ceff7d21SGeert Uytterhoeven }; 133*ceff7d21SGeert Uytterhoeven 134*ceff7d21SGeert Uytterhoeven pcie_clk: clk-9fgv0841-pci { 135*ceff7d21SGeert Uytterhoeven compatible = "fixed-clock"; 136*ceff7d21SGeert Uytterhoeven clock-frequency = <100000000>; 137*ceff7d21SGeert Uytterhoeven #clock-cells = <0>; 138*ceff7d21SGeert Uytterhoeven }; 139*ceff7d21SGeert Uytterhoeven 140*ceff7d21SGeert Uytterhoeven mini-dp-con { 141*ceff7d21SGeert Uytterhoeven compatible = "dp-connector"; 142*ceff7d21SGeert Uytterhoeven label = "CN5"; 143*ceff7d21SGeert Uytterhoeven type = "mini"; 144*ceff7d21SGeert Uytterhoeven 145*ceff7d21SGeert Uytterhoeven port { 146*ceff7d21SGeert Uytterhoeven mini_dp_con_in: endpoint { 147*ceff7d21SGeert Uytterhoeven remote-endpoint = <&sn65dsi86_out0>; 148*ceff7d21SGeert Uytterhoeven }; 149*ceff7d21SGeert Uytterhoeven }; 150*ceff7d21SGeert Uytterhoeven }; 151*ceff7d21SGeert Uytterhoeven 152*ceff7d21SGeert Uytterhoeven reg_1p2v: regulator-1p2v { 153*ceff7d21SGeert Uytterhoeven compatible = "regulator-fixed"; 154*ceff7d21SGeert Uytterhoeven regulator-name = "fixed-1.2V"; 155*ceff7d21SGeert Uytterhoeven regulator-min-microvolt = <1200000>; 156*ceff7d21SGeert Uytterhoeven regulator-max-microvolt = <1200000>; 157*ceff7d21SGeert Uytterhoeven regulator-boot-on; 158*ceff7d21SGeert Uytterhoeven regulator-always-on; 159*ceff7d21SGeert Uytterhoeven }; 160*ceff7d21SGeert Uytterhoeven 161*ceff7d21SGeert Uytterhoeven reg_1p8v: regulator-1p8v { 162*ceff7d21SGeert Uytterhoeven compatible = "regulator-fixed"; 163*ceff7d21SGeert Uytterhoeven regulator-name = "fixed-1.8V"; 164*ceff7d21SGeert Uytterhoeven regulator-min-microvolt = <1800000>; 165*ceff7d21SGeert Uytterhoeven regulator-max-microvolt = <1800000>; 166*ceff7d21SGeert Uytterhoeven regulator-boot-on; 167*ceff7d21SGeert Uytterhoeven regulator-always-on; 168*ceff7d21SGeert Uytterhoeven }; 169*ceff7d21SGeert Uytterhoeven 170*ceff7d21SGeert Uytterhoeven reg_3p3v: regulator-3p3v { 171*ceff7d21SGeert Uytterhoeven compatible = "regulator-fixed"; 172*ceff7d21SGeert Uytterhoeven regulator-name = "fixed-3.3V"; 173*ceff7d21SGeert Uytterhoeven regulator-min-microvolt = <3300000>; 174*ceff7d21SGeert Uytterhoeven regulator-max-microvolt = <3300000>; 175*ceff7d21SGeert Uytterhoeven regulator-boot-on; 176*ceff7d21SGeert Uytterhoeven regulator-always-on; 177*ceff7d21SGeert Uytterhoeven }; 178*ceff7d21SGeert Uytterhoeven 179*ceff7d21SGeert Uytterhoeven sound_mux: sound-mux { 180*ceff7d21SGeert Uytterhoeven compatible = "simple-audio-mux"; 181*ceff7d21SGeert Uytterhoeven mux-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; 182*ceff7d21SGeert Uytterhoeven state-labels = "Playback", "Capture"; 183*ceff7d21SGeert Uytterhoeven }; 184*ceff7d21SGeert Uytterhoeven 185*ceff7d21SGeert Uytterhoeven sound_card: sound { 186*ceff7d21SGeert Uytterhoeven compatible = "audio-graph-card2"; 187*ceff7d21SGeert Uytterhoeven label = "rcar-sound"; 188*ceff7d21SGeert Uytterhoeven aux-devs = <&sound_mux>; // for GP0_01 189*ceff7d21SGeert Uytterhoeven 190*ceff7d21SGeert Uytterhoeven links = <&rsnd_port>; // AK4619 Audio Codec 191*ceff7d21SGeert Uytterhoeven }; 192*ceff7d21SGeert Uytterhoeven}; 193*ceff7d21SGeert Uytterhoeven 194*ceff7d21SGeert Uytterhoeven&audio_clkin { 195*ceff7d21SGeert Uytterhoeven clock-frequency = <24576000>; 196*ceff7d21SGeert Uytterhoeven}; 197*ceff7d21SGeert Uytterhoeven 198*ceff7d21SGeert Uytterhoeven&avb0 { 199*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&avb0_pins>; 200*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 201*ceff7d21SGeert Uytterhoeven phy-handle = <&avb0_phy>; 202*ceff7d21SGeert Uytterhoeven tx-internal-delay-ps = <2000>; 203*ceff7d21SGeert Uytterhoeven status = "okay"; 204*ceff7d21SGeert Uytterhoeven 205*ceff7d21SGeert Uytterhoeven mdio { 206*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 207*ceff7d21SGeert Uytterhoeven #size-cells = <0>; 208*ceff7d21SGeert Uytterhoeven 209*ceff7d21SGeert Uytterhoeven avb0_phy: ethernet-phy@0 { 210*ceff7d21SGeert Uytterhoeven compatible = "ethernet-phy-id0022.1622", 211*ceff7d21SGeert Uytterhoeven "ethernet-phy-ieee802.3-c22"; 212*ceff7d21SGeert Uytterhoeven rxc-skew-ps = <1500>; 213*ceff7d21SGeert Uytterhoeven reg = <0>; 214*ceff7d21SGeert Uytterhoeven interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; 215*ceff7d21SGeert Uytterhoeven reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 216*ceff7d21SGeert Uytterhoeven }; 217*ceff7d21SGeert Uytterhoeven }; 218*ceff7d21SGeert Uytterhoeven}; 219*ceff7d21SGeert Uytterhoeven 220*ceff7d21SGeert Uytterhoeven&avb1 { 221*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&avb1_pins>; 222*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 223*ceff7d21SGeert Uytterhoeven phy-handle = <&avb1_phy>; 224*ceff7d21SGeert Uytterhoeven status = "okay"; 225*ceff7d21SGeert Uytterhoeven 226*ceff7d21SGeert Uytterhoeven mdio { 227*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 228*ceff7d21SGeert Uytterhoeven #size-cells = <0>; 229*ceff7d21SGeert Uytterhoeven 230*ceff7d21SGeert Uytterhoeven reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; 231*ceff7d21SGeert Uytterhoeven reset-post-delay-us = <4000>; 232*ceff7d21SGeert Uytterhoeven 233*ceff7d21SGeert Uytterhoeven avb1_phy: ethernet-phy@0 { 234*ceff7d21SGeert Uytterhoeven compatible = "ethernet-phy-ieee802.3-c45"; 235*ceff7d21SGeert Uytterhoeven reg = <0>; 236*ceff7d21SGeert Uytterhoeven interrupts-extended = <&gpio6 3 IRQ_TYPE_LEVEL_LOW>; 237*ceff7d21SGeert Uytterhoeven }; 238*ceff7d21SGeert Uytterhoeven }; 239*ceff7d21SGeert Uytterhoeven}; 240*ceff7d21SGeert Uytterhoeven 241*ceff7d21SGeert Uytterhoeven&avb2 { 242*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&avb2_pins>; 243*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 244*ceff7d21SGeert Uytterhoeven phy-handle = <&avb2_phy>; 245*ceff7d21SGeert Uytterhoeven status = "okay"; 246*ceff7d21SGeert Uytterhoeven 247*ceff7d21SGeert Uytterhoeven mdio { 248*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 249*ceff7d21SGeert Uytterhoeven #size-cells = <0>; 250*ceff7d21SGeert Uytterhoeven 251*ceff7d21SGeert Uytterhoeven reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; 252*ceff7d21SGeert Uytterhoeven reset-post-delay-us = <4000>; 253*ceff7d21SGeert Uytterhoeven 254*ceff7d21SGeert Uytterhoeven avb2_phy: ethernet-phy@0 { 255*ceff7d21SGeert Uytterhoeven compatible = "ethernet-phy-ieee802.3-c45"; 256*ceff7d21SGeert Uytterhoeven reg = <0>; 257*ceff7d21SGeert Uytterhoeven interrupts-extended = <&gpio5 4 IRQ_TYPE_LEVEL_LOW>; 258*ceff7d21SGeert Uytterhoeven }; 259*ceff7d21SGeert Uytterhoeven }; 260*ceff7d21SGeert Uytterhoeven}; 261*ceff7d21SGeert Uytterhoeven 262*ceff7d21SGeert Uytterhoeven&can_clk { 263*ceff7d21SGeert Uytterhoeven clock-frequency = <40000000>; 264*ceff7d21SGeert Uytterhoeven}; 265*ceff7d21SGeert Uytterhoeven 266*ceff7d21SGeert Uytterhoeven&canfd { 267*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; 268*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 269*ceff7d21SGeert Uytterhoeven status = "okay"; 270*ceff7d21SGeert Uytterhoeven 271*ceff7d21SGeert Uytterhoeven channel0 { 272*ceff7d21SGeert Uytterhoeven status = "okay"; 273*ceff7d21SGeert Uytterhoeven phys = <&can_transceiver0>; 274*ceff7d21SGeert Uytterhoeven }; 275*ceff7d21SGeert Uytterhoeven 276*ceff7d21SGeert Uytterhoeven channel1 { 277*ceff7d21SGeert Uytterhoeven status = "okay"; 278*ceff7d21SGeert Uytterhoeven }; 279*ceff7d21SGeert Uytterhoeven}; 280*ceff7d21SGeert Uytterhoeven 281*ceff7d21SGeert Uytterhoeven&csi40 { 282*ceff7d21SGeert Uytterhoeven status = "okay"; 283*ceff7d21SGeert Uytterhoeven 284*ceff7d21SGeert Uytterhoeven ports { 285*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 286*ceff7d21SGeert Uytterhoeven #size-cells = <0>; 287*ceff7d21SGeert Uytterhoeven 288*ceff7d21SGeert Uytterhoeven port@0 { 289*ceff7d21SGeert Uytterhoeven reg = <0>; 290*ceff7d21SGeert Uytterhoeven 291*ceff7d21SGeert Uytterhoeven csi40_in: endpoint { 292*ceff7d21SGeert Uytterhoeven bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; 293*ceff7d21SGeert Uytterhoeven clock-lanes = <0>; 294*ceff7d21SGeert Uytterhoeven data-lanes = <1 2 3 4>; 295*ceff7d21SGeert Uytterhoeven remote-endpoint = <&max96724_out0>; 296*ceff7d21SGeert Uytterhoeven }; 297*ceff7d21SGeert Uytterhoeven }; 298*ceff7d21SGeert Uytterhoeven }; 299*ceff7d21SGeert Uytterhoeven}; 300*ceff7d21SGeert Uytterhoeven 301*ceff7d21SGeert Uytterhoeven&csi41 { 302*ceff7d21SGeert Uytterhoeven status = "okay"; 303*ceff7d21SGeert Uytterhoeven 304*ceff7d21SGeert Uytterhoeven ports { 305*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 306*ceff7d21SGeert Uytterhoeven #size-cells = <0>; 307*ceff7d21SGeert Uytterhoeven 308*ceff7d21SGeert Uytterhoeven port@0 { 309*ceff7d21SGeert Uytterhoeven reg = <0>; 310*ceff7d21SGeert Uytterhoeven 311*ceff7d21SGeert Uytterhoeven csi41_in: endpoint { 312*ceff7d21SGeert Uytterhoeven bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; 313*ceff7d21SGeert Uytterhoeven clock-lanes = <0>; 314*ceff7d21SGeert Uytterhoeven data-lanes = <1 2 3 4>; 315*ceff7d21SGeert Uytterhoeven remote-endpoint = <&max96724_out1>; 316*ceff7d21SGeert Uytterhoeven }; 317*ceff7d21SGeert Uytterhoeven }; 318*ceff7d21SGeert Uytterhoeven }; 319*ceff7d21SGeert Uytterhoeven}; 320*ceff7d21SGeert Uytterhoeven 321*ceff7d21SGeert Uytterhoeven&dsi0 { 322*ceff7d21SGeert Uytterhoeven status = "okay"; 323*ceff7d21SGeert Uytterhoeven 324*ceff7d21SGeert Uytterhoeven ports { 325*ceff7d21SGeert Uytterhoeven port@1 { 326*ceff7d21SGeert Uytterhoeven reg = <1>; 327*ceff7d21SGeert Uytterhoeven 328*ceff7d21SGeert Uytterhoeven dsi0_out: endpoint { 329*ceff7d21SGeert Uytterhoeven remote-endpoint = <&sn65dsi86_in0>; 330*ceff7d21SGeert Uytterhoeven data-lanes = <1 2 3 4>; 331*ceff7d21SGeert Uytterhoeven }; 332*ceff7d21SGeert Uytterhoeven }; 333*ceff7d21SGeert Uytterhoeven }; 334*ceff7d21SGeert Uytterhoeven}; 335*ceff7d21SGeert Uytterhoeven 336*ceff7d21SGeert Uytterhoeven&du { 337*ceff7d21SGeert Uytterhoeven status = "okay"; 338*ceff7d21SGeert Uytterhoeven}; 339*ceff7d21SGeert Uytterhoeven 340*ceff7d21SGeert Uytterhoeven&extal_clk { 341*ceff7d21SGeert Uytterhoeven clock-frequency = <16666666>; 342*ceff7d21SGeert Uytterhoeven}; 343*ceff7d21SGeert Uytterhoeven 344*ceff7d21SGeert Uytterhoeven&extalr_clk { 345*ceff7d21SGeert Uytterhoeven clock-frequency = <32768>; 346*ceff7d21SGeert Uytterhoeven}; 347*ceff7d21SGeert Uytterhoeven 348*ceff7d21SGeert Uytterhoeven&gpio1 { 349*ceff7d21SGeert Uytterhoeven audio-power-hog { 350*ceff7d21SGeert Uytterhoeven gpio-hog; 351*ceff7d21SGeert Uytterhoeven gpios = <8 GPIO_ACTIVE_HIGH>; 352*ceff7d21SGeert Uytterhoeven output-high; 353*ceff7d21SGeert Uytterhoeven line-name = "Audio-Power"; 354*ceff7d21SGeert Uytterhoeven }; 355*ceff7d21SGeert Uytterhoeven}; 356*ceff7d21SGeert Uytterhoeven 357*ceff7d21SGeert Uytterhoeven&hscif0 { 358*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&hscif0_pins>; 359*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 360*ceff7d21SGeert Uytterhoeven bootph-all; 361*ceff7d21SGeert Uytterhoeven 362*ceff7d21SGeert Uytterhoeven uart-has-rtscts; 363*ceff7d21SGeert Uytterhoeven status = "okay"; 364*ceff7d21SGeert Uytterhoeven}; 365*ceff7d21SGeert Uytterhoeven 366*ceff7d21SGeert Uytterhoeven&hscif2 { 367*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&hscif2_pins>; 368*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 369*ceff7d21SGeert Uytterhoeven 370*ceff7d21SGeert Uytterhoeven uart-has-rtscts; 371*ceff7d21SGeert Uytterhoeven status = "okay"; 372*ceff7d21SGeert Uytterhoeven}; 373*ceff7d21SGeert Uytterhoeven 374*ceff7d21SGeert Uytterhoeven&i2c0 { 375*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&i2c0_pins>; 376*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 377*ceff7d21SGeert Uytterhoeven 378*ceff7d21SGeert Uytterhoeven status = "okay"; 379*ceff7d21SGeert Uytterhoeven clock-frequency = <400000>; 380*ceff7d21SGeert Uytterhoeven 381*ceff7d21SGeert Uytterhoeven io_expander_a: gpio@20 { 382*ceff7d21SGeert Uytterhoeven compatible = "onnn,pca9654"; 383*ceff7d21SGeert Uytterhoeven reg = <0x20>; 384*ceff7d21SGeert Uytterhoeven interrupts-extended = <&gpio0 0 IRQ_TYPE_LEVEL_LOW>; 385*ceff7d21SGeert Uytterhoeven gpio-controller; 386*ceff7d21SGeert Uytterhoeven #gpio-cells = <2>; 387*ceff7d21SGeert Uytterhoeven interrupt-controller; 388*ceff7d21SGeert Uytterhoeven #interrupt-cells = <2>; 389*ceff7d21SGeert Uytterhoeven }; 390*ceff7d21SGeert Uytterhoeven 391*ceff7d21SGeert Uytterhoeven io_expander_b: gpio@21 { 392*ceff7d21SGeert Uytterhoeven compatible = "onnn,pca9654"; 393*ceff7d21SGeert Uytterhoeven reg = <0x21>; 394*ceff7d21SGeert Uytterhoeven gpio-controller; 395*ceff7d21SGeert Uytterhoeven #gpio-cells = <2>; 396*ceff7d21SGeert Uytterhoeven }; 397*ceff7d21SGeert Uytterhoeven 398*ceff7d21SGeert Uytterhoeven io_expander_c: gpio@22 { 399*ceff7d21SGeert Uytterhoeven compatible = "onnn,pca9654"; 400*ceff7d21SGeert Uytterhoeven reg = <0x22>; 401*ceff7d21SGeert Uytterhoeven gpio-controller; 402*ceff7d21SGeert Uytterhoeven #gpio-cells = <2>; 403*ceff7d21SGeert Uytterhoeven }; 404*ceff7d21SGeert Uytterhoeven 405*ceff7d21SGeert Uytterhoeven eeprom@50 { 406*ceff7d21SGeert Uytterhoeven compatible = "rohm,br24g01", "atmel,24c01"; 407*ceff7d21SGeert Uytterhoeven label = "cpu-board"; 408*ceff7d21SGeert Uytterhoeven reg = <0x50>; 409*ceff7d21SGeert Uytterhoeven pagesize = <8>; 410*ceff7d21SGeert Uytterhoeven }; 411*ceff7d21SGeert Uytterhoeven 412*ceff7d21SGeert Uytterhoeven eeprom@51 { 413*ceff7d21SGeert Uytterhoeven compatible = "rohm,br24g01", "atmel,24c01"; 414*ceff7d21SGeert Uytterhoeven label = "breakout-board"; 415*ceff7d21SGeert Uytterhoeven reg = <0x51>; 416*ceff7d21SGeert Uytterhoeven pagesize = <8>; 417*ceff7d21SGeert Uytterhoeven }; 418*ceff7d21SGeert Uytterhoeven 419*ceff7d21SGeert Uytterhoeven eeprom@52 { 420*ceff7d21SGeert Uytterhoeven compatible = "rohm,br24g01", "atmel,24c01"; 421*ceff7d21SGeert Uytterhoeven label = "csi-dsi-sub-board-id"; 422*ceff7d21SGeert Uytterhoeven reg = <0x52>; 423*ceff7d21SGeert Uytterhoeven pagesize = <8>; 424*ceff7d21SGeert Uytterhoeven }; 425*ceff7d21SGeert Uytterhoeven 426*ceff7d21SGeert Uytterhoeven eeprom@53 { 427*ceff7d21SGeert Uytterhoeven compatible = "rohm,br24g01", "atmel,24c01"; 428*ceff7d21SGeert Uytterhoeven label = "ethernet-sub-board-id"; 429*ceff7d21SGeert Uytterhoeven reg = <0x53>; 430*ceff7d21SGeert Uytterhoeven pagesize = <8>; 431*ceff7d21SGeert Uytterhoeven }; 432*ceff7d21SGeert Uytterhoeven}; 433*ceff7d21SGeert Uytterhoeven 434*ceff7d21SGeert Uytterhoeven&i2c1 { 435*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&i2c1_pins>; 436*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 437*ceff7d21SGeert Uytterhoeven 438*ceff7d21SGeert Uytterhoeven status = "okay"; 439*ceff7d21SGeert Uytterhoeven clock-frequency = <400000>; 440*ceff7d21SGeert Uytterhoeven 441*ceff7d21SGeert Uytterhoeven bridge@2c { 442*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&irq0_pins>; 443*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 444*ceff7d21SGeert Uytterhoeven 445*ceff7d21SGeert Uytterhoeven compatible = "ti,sn65dsi86"; 446*ceff7d21SGeert Uytterhoeven reg = <0x2c>; 447*ceff7d21SGeert Uytterhoeven 448*ceff7d21SGeert Uytterhoeven clocks = <&sn65dsi86_refclk>; 449*ceff7d21SGeert Uytterhoeven clock-names = "refclk"; 450*ceff7d21SGeert Uytterhoeven 451*ceff7d21SGeert Uytterhoeven interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; 452*ceff7d21SGeert Uytterhoeven 453*ceff7d21SGeert Uytterhoeven enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 454*ceff7d21SGeert Uytterhoeven 455*ceff7d21SGeert Uytterhoeven vccio-supply = <®_1p8v>; 456*ceff7d21SGeert Uytterhoeven vpll-supply = <®_1p8v>; 457*ceff7d21SGeert Uytterhoeven vcca-supply = <®_1p2v>; 458*ceff7d21SGeert Uytterhoeven vcc-supply = <®_1p2v>; 459*ceff7d21SGeert Uytterhoeven 460*ceff7d21SGeert Uytterhoeven ports { 461*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 462*ceff7d21SGeert Uytterhoeven #size-cells = <0>; 463*ceff7d21SGeert Uytterhoeven 464*ceff7d21SGeert Uytterhoeven port@0 { 465*ceff7d21SGeert Uytterhoeven reg = <0>; 466*ceff7d21SGeert Uytterhoeven 467*ceff7d21SGeert Uytterhoeven sn65dsi86_in0: endpoint { 468*ceff7d21SGeert Uytterhoeven remote-endpoint = <&dsi0_out>; 469*ceff7d21SGeert Uytterhoeven }; 470*ceff7d21SGeert Uytterhoeven }; 471*ceff7d21SGeert Uytterhoeven 472*ceff7d21SGeert Uytterhoeven port@1 { 473*ceff7d21SGeert Uytterhoeven reg = <1>; 474*ceff7d21SGeert Uytterhoeven 475*ceff7d21SGeert Uytterhoeven sn65dsi86_out0: endpoint { 476*ceff7d21SGeert Uytterhoeven remote-endpoint = <&mini_dp_con_in>; 477*ceff7d21SGeert Uytterhoeven }; 478*ceff7d21SGeert Uytterhoeven }; 479*ceff7d21SGeert Uytterhoeven }; 480*ceff7d21SGeert Uytterhoeven }; 481*ceff7d21SGeert Uytterhoeven 482*ceff7d21SGeert Uytterhoeven gmsl0: gmsl-deserializer@4e { 483*ceff7d21SGeert Uytterhoeven compatible = "maxim,max96724"; 484*ceff7d21SGeert Uytterhoeven reg = <0x4e>; 485*ceff7d21SGeert Uytterhoeven enable-gpios = <&io_expander_b 0 GPIO_ACTIVE_HIGH>; 486*ceff7d21SGeert Uytterhoeven 487*ceff7d21SGeert Uytterhoeven ports { 488*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 489*ceff7d21SGeert Uytterhoeven #size-cells = <0>; 490*ceff7d21SGeert Uytterhoeven 491*ceff7d21SGeert Uytterhoeven port@4 { 492*ceff7d21SGeert Uytterhoeven reg = <4>; 493*ceff7d21SGeert Uytterhoeven max96724_out0: endpoint { 494*ceff7d21SGeert Uytterhoeven bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; 495*ceff7d21SGeert Uytterhoeven clock-lanes = <0>; 496*ceff7d21SGeert Uytterhoeven data-lanes = <1 2 3 4>; 497*ceff7d21SGeert Uytterhoeven remote-endpoint = <&csi40_in>; 498*ceff7d21SGeert Uytterhoeven }; 499*ceff7d21SGeert Uytterhoeven }; 500*ceff7d21SGeert Uytterhoeven }; 501*ceff7d21SGeert Uytterhoeven }; 502*ceff7d21SGeert Uytterhoeven 503*ceff7d21SGeert Uytterhoeven gmsl1: gmsl-deserializer@4f { 504*ceff7d21SGeert Uytterhoeven compatible = "maxim,max96724"; 505*ceff7d21SGeert Uytterhoeven reg = <0x4f>; 506*ceff7d21SGeert Uytterhoeven enable-gpios = <&io_expander_c 0 GPIO_ACTIVE_HIGH>; 507*ceff7d21SGeert Uytterhoeven 508*ceff7d21SGeert Uytterhoeven ports { 509*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 510*ceff7d21SGeert Uytterhoeven #size-cells = <0>; 511*ceff7d21SGeert Uytterhoeven 512*ceff7d21SGeert Uytterhoeven port@4 { 513*ceff7d21SGeert Uytterhoeven reg = <4>; 514*ceff7d21SGeert Uytterhoeven max96724_out1: endpoint { 515*ceff7d21SGeert Uytterhoeven bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; 516*ceff7d21SGeert Uytterhoeven clock-lanes = <0>; 517*ceff7d21SGeert Uytterhoeven data-lanes = <1 2 3 4>; 518*ceff7d21SGeert Uytterhoeven remote-endpoint = <&csi41_in>; 519*ceff7d21SGeert Uytterhoeven }; 520*ceff7d21SGeert Uytterhoeven }; 521*ceff7d21SGeert Uytterhoeven }; 522*ceff7d21SGeert Uytterhoeven }; 523*ceff7d21SGeert Uytterhoeven}; 524*ceff7d21SGeert Uytterhoeven 525*ceff7d21SGeert Uytterhoeven&i2c3 { 526*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&i2c3_pins>; 527*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 528*ceff7d21SGeert Uytterhoeven 529*ceff7d21SGeert Uytterhoeven status = "okay"; 530*ceff7d21SGeert Uytterhoeven clock-frequency = <400000>; 531*ceff7d21SGeert Uytterhoeven 532*ceff7d21SGeert Uytterhoeven codec@10 { 533*ceff7d21SGeert Uytterhoeven compatible = "asahi-kasei,ak4619"; 534*ceff7d21SGeert Uytterhoeven reg = <0x10>; 535*ceff7d21SGeert Uytterhoeven 536*ceff7d21SGeert Uytterhoeven clocks = <&rcar_sound>; 537*ceff7d21SGeert Uytterhoeven clock-names = "mclk"; 538*ceff7d21SGeert Uytterhoeven 539*ceff7d21SGeert Uytterhoeven #sound-dai-cells = <0>; 540*ceff7d21SGeert Uytterhoeven port { 541*ceff7d21SGeert Uytterhoeven ak4619_endpoint: endpoint { 542*ceff7d21SGeert Uytterhoeven remote-endpoint = <&rsnd_endpoint>; 543*ceff7d21SGeert Uytterhoeven }; 544*ceff7d21SGeert Uytterhoeven }; 545*ceff7d21SGeert Uytterhoeven }; 546*ceff7d21SGeert Uytterhoeven}; 547*ceff7d21SGeert Uytterhoeven 548*ceff7d21SGeert Uytterhoeven&isp0 { 549*ceff7d21SGeert Uytterhoeven status = "okay"; 550*ceff7d21SGeert Uytterhoeven}; 551*ceff7d21SGeert Uytterhoeven 552*ceff7d21SGeert Uytterhoeven&isp1 { 553*ceff7d21SGeert Uytterhoeven status = "okay"; 554*ceff7d21SGeert Uytterhoeven}; 555*ceff7d21SGeert Uytterhoeven 556*ceff7d21SGeert Uytterhoeven&mmc0 { 557*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&mmc_pins>; 558*ceff7d21SGeert Uytterhoeven pinctrl-1 = <&mmc_pins>; 559*ceff7d21SGeert Uytterhoeven pinctrl-names = "default", "state_uhs"; 560*ceff7d21SGeert Uytterhoeven 561*ceff7d21SGeert Uytterhoeven vmmc-supply = <®_3p3v>; 562*ceff7d21SGeert Uytterhoeven vqmmc-supply = <®_1p8v>; 563*ceff7d21SGeert Uytterhoeven mmc-hs200-1_8v; 564*ceff7d21SGeert Uytterhoeven mmc-hs400-1_8v; 565*ceff7d21SGeert Uytterhoeven bus-width = <8>; 566*ceff7d21SGeert Uytterhoeven no-sd; 567*ceff7d21SGeert Uytterhoeven no-sdio; 568*ceff7d21SGeert Uytterhoeven non-removable; 569*ceff7d21SGeert Uytterhoeven full-pwr-cycle-in-suspend; 570*ceff7d21SGeert Uytterhoeven status = "okay"; 571*ceff7d21SGeert Uytterhoeven}; 572*ceff7d21SGeert Uytterhoeven 573*ceff7d21SGeert Uytterhoeven&pcie0_clkref { 574*ceff7d21SGeert Uytterhoeven compatible = "gpio-gate-clock"; 575*ceff7d21SGeert Uytterhoeven clocks = <&pcie_clk>; 576*ceff7d21SGeert Uytterhoeven enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 577*ceff7d21SGeert Uytterhoeven /delete-property/ clock-frequency; 578*ceff7d21SGeert Uytterhoeven}; 579*ceff7d21SGeert Uytterhoeven 580*ceff7d21SGeert Uytterhoeven&pciec0 { 581*ceff7d21SGeert Uytterhoeven reset-gpios = <&io_expander_a 0 GPIO_ACTIVE_LOW>; 582*ceff7d21SGeert Uytterhoeven status = "okay"; 583*ceff7d21SGeert Uytterhoeven}; 584*ceff7d21SGeert Uytterhoeven 585*ceff7d21SGeert Uytterhoeven&pfc { 586*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&scif_clk_pins>, <&scif_clk2_pins>; 587*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 588*ceff7d21SGeert Uytterhoeven 589*ceff7d21SGeert Uytterhoeven avb0_pins: avb0 { 590*ceff7d21SGeert Uytterhoeven mux { 591*ceff7d21SGeert Uytterhoeven groups = "avb0_link", "avb0_mdio", "avb0_rgmii", 592*ceff7d21SGeert Uytterhoeven "avb0_txcrefclk"; 593*ceff7d21SGeert Uytterhoeven function = "avb0"; 594*ceff7d21SGeert Uytterhoeven }; 595*ceff7d21SGeert Uytterhoeven 596*ceff7d21SGeert Uytterhoeven pins_mdio { 597*ceff7d21SGeert Uytterhoeven groups = "avb0_mdio"; 598*ceff7d21SGeert Uytterhoeven drive-strength = <21>; 599*ceff7d21SGeert Uytterhoeven }; 600*ceff7d21SGeert Uytterhoeven 601*ceff7d21SGeert Uytterhoeven pins_mii { 602*ceff7d21SGeert Uytterhoeven groups = "avb0_rgmii"; 603*ceff7d21SGeert Uytterhoeven drive-strength = <21>; 604*ceff7d21SGeert Uytterhoeven }; 605*ceff7d21SGeert Uytterhoeven }; 606*ceff7d21SGeert Uytterhoeven 607*ceff7d21SGeert Uytterhoeven avb1_pins: avb1 { 608*ceff7d21SGeert Uytterhoeven mux { 609*ceff7d21SGeert Uytterhoeven groups = "avb1_link", "avb1_mdio", "avb1_rgmii", 610*ceff7d21SGeert Uytterhoeven "avb1_txcrefclk"; 611*ceff7d21SGeert Uytterhoeven function = "avb1"; 612*ceff7d21SGeert Uytterhoeven }; 613*ceff7d21SGeert Uytterhoeven 614*ceff7d21SGeert Uytterhoeven link { 615*ceff7d21SGeert Uytterhoeven groups = "avb1_link"; 616*ceff7d21SGeert Uytterhoeven bias-disable; 617*ceff7d21SGeert Uytterhoeven }; 618*ceff7d21SGeert Uytterhoeven 619*ceff7d21SGeert Uytterhoeven mdio { 620*ceff7d21SGeert Uytterhoeven groups = "avb1_mdio"; 621*ceff7d21SGeert Uytterhoeven drive-strength = <24>; 622*ceff7d21SGeert Uytterhoeven bias-disable; 623*ceff7d21SGeert Uytterhoeven }; 624*ceff7d21SGeert Uytterhoeven 625*ceff7d21SGeert Uytterhoeven rgmii { 626*ceff7d21SGeert Uytterhoeven groups = "avb1_rgmii"; 627*ceff7d21SGeert Uytterhoeven drive-strength = <24>; 628*ceff7d21SGeert Uytterhoeven bias-disable; 629*ceff7d21SGeert Uytterhoeven }; 630*ceff7d21SGeert Uytterhoeven }; 631*ceff7d21SGeert Uytterhoeven 632*ceff7d21SGeert Uytterhoeven avb2_pins: avb2 { 633*ceff7d21SGeert Uytterhoeven mux { 634*ceff7d21SGeert Uytterhoeven groups = "avb2_link", "avb2_mdio", "avb2_rgmii", 635*ceff7d21SGeert Uytterhoeven "avb2_txcrefclk"; 636*ceff7d21SGeert Uytterhoeven function = "avb2"; 637*ceff7d21SGeert Uytterhoeven }; 638*ceff7d21SGeert Uytterhoeven 639*ceff7d21SGeert Uytterhoeven link { 640*ceff7d21SGeert Uytterhoeven groups = "avb2_link"; 641*ceff7d21SGeert Uytterhoeven bias-disable; 642*ceff7d21SGeert Uytterhoeven }; 643*ceff7d21SGeert Uytterhoeven 644*ceff7d21SGeert Uytterhoeven mdio { 645*ceff7d21SGeert Uytterhoeven groups = "avb2_mdio"; 646*ceff7d21SGeert Uytterhoeven drive-strength = <24>; 647*ceff7d21SGeert Uytterhoeven bias-disable; 648*ceff7d21SGeert Uytterhoeven }; 649*ceff7d21SGeert Uytterhoeven 650*ceff7d21SGeert Uytterhoeven rgmii { 651*ceff7d21SGeert Uytterhoeven groups = "avb2_rgmii"; 652*ceff7d21SGeert Uytterhoeven drive-strength = <24>; 653*ceff7d21SGeert Uytterhoeven bias-disable; 654*ceff7d21SGeert Uytterhoeven }; 655*ceff7d21SGeert Uytterhoeven }; 656*ceff7d21SGeert Uytterhoeven 657*ceff7d21SGeert Uytterhoeven can_clk_pins: can-clk { 658*ceff7d21SGeert Uytterhoeven groups = "can_clk"; 659*ceff7d21SGeert Uytterhoeven function = "can_clk"; 660*ceff7d21SGeert Uytterhoeven }; 661*ceff7d21SGeert Uytterhoeven 662*ceff7d21SGeert Uytterhoeven canfd0_pins: canfd0 { 663*ceff7d21SGeert Uytterhoeven groups = "canfd0_data"; 664*ceff7d21SGeert Uytterhoeven function = "canfd0"; 665*ceff7d21SGeert Uytterhoeven }; 666*ceff7d21SGeert Uytterhoeven 667*ceff7d21SGeert Uytterhoeven canfd1_pins: canfd1 { 668*ceff7d21SGeert Uytterhoeven groups = "canfd1_data"; 669*ceff7d21SGeert Uytterhoeven function = "canfd1"; 670*ceff7d21SGeert Uytterhoeven }; 671*ceff7d21SGeert Uytterhoeven 672*ceff7d21SGeert Uytterhoeven hscif0_pins: hscif0 { 673*ceff7d21SGeert Uytterhoeven groups = "hscif0_data", "hscif0_ctrl"; 674*ceff7d21SGeert Uytterhoeven function = "hscif0"; 675*ceff7d21SGeert Uytterhoeven }; 676*ceff7d21SGeert Uytterhoeven 677*ceff7d21SGeert Uytterhoeven hscif2_pins: hscif2 { 678*ceff7d21SGeert Uytterhoeven groups = "hscif2_data", "hscif2_ctrl"; 679*ceff7d21SGeert Uytterhoeven function = "hscif2"; 680*ceff7d21SGeert Uytterhoeven }; 681*ceff7d21SGeert Uytterhoeven 682*ceff7d21SGeert Uytterhoeven i2c0_pins: i2c0 { 683*ceff7d21SGeert Uytterhoeven groups = "i2c0"; 684*ceff7d21SGeert Uytterhoeven function = "i2c0"; 685*ceff7d21SGeert Uytterhoeven }; 686*ceff7d21SGeert Uytterhoeven 687*ceff7d21SGeert Uytterhoeven i2c1_pins: i2c1 { 688*ceff7d21SGeert Uytterhoeven groups = "i2c1"; 689*ceff7d21SGeert Uytterhoeven function = "i2c1"; 690*ceff7d21SGeert Uytterhoeven }; 691*ceff7d21SGeert Uytterhoeven 692*ceff7d21SGeert Uytterhoeven i2c3_pins: i2c3 { 693*ceff7d21SGeert Uytterhoeven groups = "i2c3"; 694*ceff7d21SGeert Uytterhoeven function = "i2c3"; 695*ceff7d21SGeert Uytterhoeven }; 696*ceff7d21SGeert Uytterhoeven 697*ceff7d21SGeert Uytterhoeven irq0_pins: irq0_pins { 698*ceff7d21SGeert Uytterhoeven groups = "intc_ex_irq0_a"; 699*ceff7d21SGeert Uytterhoeven function = "intc_ex"; 700*ceff7d21SGeert Uytterhoeven }; 701*ceff7d21SGeert Uytterhoeven 702*ceff7d21SGeert Uytterhoeven keys_pins: keys { 703*ceff7d21SGeert Uytterhoeven pins = "GP_5_0", "GP_5_1", "GP_5_2"; 704*ceff7d21SGeert Uytterhoeven bias-pull-up; 705*ceff7d21SGeert Uytterhoeven }; 706*ceff7d21SGeert Uytterhoeven 707*ceff7d21SGeert Uytterhoeven mmc_pins: mmc { 708*ceff7d21SGeert Uytterhoeven groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 709*ceff7d21SGeert Uytterhoeven function = "mmc"; 710*ceff7d21SGeert Uytterhoeven power-source = <1800>; 711*ceff7d21SGeert Uytterhoeven }; 712*ceff7d21SGeert Uytterhoeven 713*ceff7d21SGeert Uytterhoeven qspi0_pins: qspi0 { 714*ceff7d21SGeert Uytterhoeven groups = "qspi0_ctrl", "qspi0_data4"; 715*ceff7d21SGeert Uytterhoeven function = "qspi0"; 716*ceff7d21SGeert Uytterhoeven }; 717*ceff7d21SGeert Uytterhoeven 718*ceff7d21SGeert Uytterhoeven scif_clk_pins: scif-clk { 719*ceff7d21SGeert Uytterhoeven groups = "scif_clk"; 720*ceff7d21SGeert Uytterhoeven function = "scif_clk"; 721*ceff7d21SGeert Uytterhoeven }; 722*ceff7d21SGeert Uytterhoeven 723*ceff7d21SGeert Uytterhoeven scif_clk2_pins: scif-clk2 { 724*ceff7d21SGeert Uytterhoeven groups = "scif_clk2"; 725*ceff7d21SGeert Uytterhoeven function = "scif_clk2"; 726*ceff7d21SGeert Uytterhoeven }; 727*ceff7d21SGeert Uytterhoeven 728*ceff7d21SGeert Uytterhoeven sound_clk_pins: sound_clk { 729*ceff7d21SGeert Uytterhoeven groups = "audio_clkin", "audio_clkout"; 730*ceff7d21SGeert Uytterhoeven function = "audio_clk"; 731*ceff7d21SGeert Uytterhoeven }; 732*ceff7d21SGeert Uytterhoeven 733*ceff7d21SGeert Uytterhoeven sound_pins: sound { 734*ceff7d21SGeert Uytterhoeven groups = "ssi_ctrl", "ssi_data"; 735*ceff7d21SGeert Uytterhoeven function = "ssi"; 736*ceff7d21SGeert Uytterhoeven }; 737*ceff7d21SGeert Uytterhoeven}; 738*ceff7d21SGeert Uytterhoeven 739*ceff7d21SGeert Uytterhoeven&rcar_sound { 740*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&sound_clk_pins>, <&sound_pins>; 741*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 742*ceff7d21SGeert Uytterhoeven 743*ceff7d21SGeert Uytterhoeven status = "okay"; 744*ceff7d21SGeert Uytterhoeven 745*ceff7d21SGeert Uytterhoeven /* audio_clkout */ 746*ceff7d21SGeert Uytterhoeven clock-frequency = <12288000>; 747*ceff7d21SGeert Uytterhoeven 748*ceff7d21SGeert Uytterhoeven ports { 749*ceff7d21SGeert Uytterhoeven rsnd_port: port { 750*ceff7d21SGeert Uytterhoeven rsnd_endpoint: endpoint { 751*ceff7d21SGeert Uytterhoeven remote-endpoint = <&ak4619_endpoint>; 752*ceff7d21SGeert Uytterhoeven bitclock-master; 753*ceff7d21SGeert Uytterhoeven frame-master; 754*ceff7d21SGeert Uytterhoeven 755*ceff7d21SGeert Uytterhoeven /* see above [How to use Sound] */ 756*ceff7d21SGeert Uytterhoeven playback = <&ssi0>; 757*ceff7d21SGeert Uytterhoeven capture = <&ssi0>; 758*ceff7d21SGeert Uytterhoeven }; 759*ceff7d21SGeert Uytterhoeven }; 760*ceff7d21SGeert Uytterhoeven }; 761*ceff7d21SGeert Uytterhoeven}; 762*ceff7d21SGeert Uytterhoeven 763*ceff7d21SGeert Uytterhoeven&rpc { 764*ceff7d21SGeert Uytterhoeven pinctrl-0 = <&qspi0_pins>; 765*ceff7d21SGeert Uytterhoeven pinctrl-names = "default"; 766*ceff7d21SGeert Uytterhoeven 767*ceff7d21SGeert Uytterhoeven status = "okay"; 768*ceff7d21SGeert Uytterhoeven 769*ceff7d21SGeert Uytterhoeven flash@0 { 770*ceff7d21SGeert Uytterhoeven compatible = "spansion,s25fs512s", "jedec,spi-nor"; 771*ceff7d21SGeert Uytterhoeven reg = <0>; 772*ceff7d21SGeert Uytterhoeven spi-max-frequency = <40000000>; 773*ceff7d21SGeert Uytterhoeven spi-rx-bus-width = <4>; 774*ceff7d21SGeert Uytterhoeven 775*ceff7d21SGeert Uytterhoeven partitions { 776*ceff7d21SGeert Uytterhoeven compatible = "fixed-partitions"; 777*ceff7d21SGeert Uytterhoeven #address-cells = <1>; 778*ceff7d21SGeert Uytterhoeven #size-cells = <1>; 779*ceff7d21SGeert Uytterhoeven 780*ceff7d21SGeert Uytterhoeven boot@0 { 781*ceff7d21SGeert Uytterhoeven reg = <0x0 0x1200000>; 782*ceff7d21SGeert Uytterhoeven read-only; 783*ceff7d21SGeert Uytterhoeven }; 784*ceff7d21SGeert Uytterhoeven user@1200000 { 785*ceff7d21SGeert Uytterhoeven reg = <0x1200000 0x2e00000>; 786*ceff7d21SGeert Uytterhoeven }; 787*ceff7d21SGeert Uytterhoeven }; 788*ceff7d21SGeert Uytterhoeven }; 789*ceff7d21SGeert Uytterhoeven}; 790*ceff7d21SGeert Uytterhoeven 791*ceff7d21SGeert Uytterhoeven&rwdt { 792*ceff7d21SGeert Uytterhoeven timeout-sec = <60>; 793*ceff7d21SGeert Uytterhoeven status = "okay"; 794*ceff7d21SGeert Uytterhoeven}; 795*ceff7d21SGeert Uytterhoeven 796*ceff7d21SGeert Uytterhoeven&scif_clk { 797*ceff7d21SGeert Uytterhoeven clock-frequency = <24000000>; 798*ceff7d21SGeert Uytterhoeven}; 799*ceff7d21SGeert Uytterhoeven 800*ceff7d21SGeert Uytterhoeven&scif_clk2 { 801*ceff7d21SGeert Uytterhoeven clock-frequency = <24000000>; 802*ceff7d21SGeert Uytterhoeven}; 803*ceff7d21SGeert Uytterhoeven 804*ceff7d21SGeert Uytterhoeven&vin00 { 805*ceff7d21SGeert Uytterhoeven status = "okay"; 806*ceff7d21SGeert Uytterhoeven}; 807*ceff7d21SGeert Uytterhoeven 808*ceff7d21SGeert Uytterhoeven&vin01 { 809*ceff7d21SGeert Uytterhoeven status = "okay"; 810*ceff7d21SGeert Uytterhoeven}; 811*ceff7d21SGeert Uytterhoeven 812*ceff7d21SGeert Uytterhoeven&vin02 { 813*ceff7d21SGeert Uytterhoeven status = "okay"; 814*ceff7d21SGeert Uytterhoeven}; 815*ceff7d21SGeert Uytterhoeven 816*ceff7d21SGeert Uytterhoeven&vin03 { 817*ceff7d21SGeert Uytterhoeven status = "okay"; 818*ceff7d21SGeert Uytterhoeven}; 819*ceff7d21SGeert Uytterhoeven 820*ceff7d21SGeert Uytterhoeven&vin04 { 821*ceff7d21SGeert Uytterhoeven status = "okay"; 822*ceff7d21SGeert Uytterhoeven}; 823*ceff7d21SGeert Uytterhoeven 824*ceff7d21SGeert Uytterhoeven&vin05 { 825*ceff7d21SGeert Uytterhoeven status = "okay"; 826*ceff7d21SGeert Uytterhoeven}; 827*ceff7d21SGeert Uytterhoeven 828*ceff7d21SGeert Uytterhoeven&vin06 { 829*ceff7d21SGeert Uytterhoeven status = "okay"; 830*ceff7d21SGeert Uytterhoeven}; 831*ceff7d21SGeert Uytterhoeven 832*ceff7d21SGeert Uytterhoeven&vin07 { 833*ceff7d21SGeert Uytterhoeven status = "okay"; 834*ceff7d21SGeert Uytterhoeven}; 835*ceff7d21SGeert Uytterhoeven 836*ceff7d21SGeert Uytterhoeven&vin08 { 837*ceff7d21SGeert Uytterhoeven status = "okay"; 838*ceff7d21SGeert Uytterhoeven}; 839*ceff7d21SGeert Uytterhoeven 840*ceff7d21SGeert Uytterhoeven&vin09 { 841*ceff7d21SGeert Uytterhoeven status = "okay"; 842*ceff7d21SGeert Uytterhoeven}; 843*ceff7d21SGeert Uytterhoeven 844*ceff7d21SGeert Uytterhoeven&vin10 { 845*ceff7d21SGeert Uytterhoeven status = "okay"; 846*ceff7d21SGeert Uytterhoeven}; 847*ceff7d21SGeert Uytterhoeven 848*ceff7d21SGeert Uytterhoeven&vin11 { 849*ceff7d21SGeert Uytterhoeven status = "okay"; 850*ceff7d21SGeert Uytterhoeven}; 851*ceff7d21SGeert Uytterhoeven 852*ceff7d21SGeert Uytterhoeven&vin12 { 853*ceff7d21SGeert Uytterhoeven status = "okay"; 854*ceff7d21SGeert Uytterhoeven}; 855*ceff7d21SGeert Uytterhoeven 856*ceff7d21SGeert Uytterhoeven&vin13 { 857*ceff7d21SGeert Uytterhoeven status = "okay"; 858*ceff7d21SGeert Uytterhoeven}; 859*ceff7d21SGeert Uytterhoeven 860*ceff7d21SGeert Uytterhoeven&vin14 { 861*ceff7d21SGeert Uytterhoeven status = "okay"; 862*ceff7d21SGeert Uytterhoeven}; 863*ceff7d21SGeert Uytterhoeven 864*ceff7d21SGeert Uytterhoeven&vin15 { 865*ceff7d21SGeert Uytterhoeven status = "okay"; 866*ceff7d21SGeert Uytterhoeven}; 867