1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Realtek Kent SoC family 4 * 5 * Copyright (c) 2024 Realtek Semiconductor Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10 11/ { 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 serial0 = &uart0; 18 }; 19 20 timer { 21 compatible = "arm,armv8-timer"; 22 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 23 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 24 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 25 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 26 <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a78"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&l2_0>; 39 dynamic-power-coefficient = <454>; 40 #cooling-cells = <2>; 41 42 l2_0: l2-cache { 43 compatible = "cache"; 44 cache-level = <2>; 45 cache-line-size = <64>; 46 cache-sets = <256>; 47 cache-size = <0x40000>; 48 cache-unified; 49 next-level-cache = <&l3>; 50 }; 51 }; 52 53 cpu1: cpu@100 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a78"; 56 reg = <0x100>; 57 enable-method = "psci"; 58 next-level-cache = <&l2_1>; 59 dynamic-power-coefficient = <454>; 60 #cooling-cells = <2>; 61 62 l2_1: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-line-size = <64>; 66 cache-sets = <256>; 67 cache-size = <0x40000>; 68 cache-unified; 69 next-level-cache = <&l3>; 70 }; 71 }; 72 73 cpu2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a78"; 76 reg = <0x200>; 77 enable-method = "psci"; 78 next-level-cache = <&l2_2>; 79 dynamic-power-coefficient = <454>; 80 #cooling-cells = <2>; 81 82 l2_2: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-line-size = <64>; 86 cache-sets = <256>; 87 cache-size = <0x40000>; 88 cache-unified; 89 next-level-cache = <&l3>; 90 }; 91 }; 92 93 cpu3: cpu@300 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a78"; 96 reg = <0x300>; 97 enable-method = "psci"; 98 next-level-cache = <&l2_3>; 99 dynamic-power-coefficient = <454>; 100 #cooling-cells = <2>; 101 102 l2_3: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-line-size = <64>; 106 cache-sets = <256>; 107 cache-size = <0x40000>; 108 cache-unified; 109 next-level-cache = <&l3>; 110 }; 111 }; 112 113 l3: l3-cache { 114 compatible = "cache"; 115 cache-level = <3>; 116 cache-line-size = <64>; 117 cache-sets = <512>; 118 cache-size = <0x200000>; 119 cache-unified; 120 }; 121 }; 122 123 psci: psci { 124 compatible = "arm,psci-1.0"; 125 method = "smc"; 126 }; 127 128 soc@0 { 129 compatible = "simple-bus"; 130 ranges = <0x0 0x0 0x0 0x40000>, /* boot code */ 131 <0x98000000 0x0 0x98000000 0xef0000>, /* rbus */ 132 <0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */ 133 <0xff000000 0x0 0xff000000 0x200000>; /* GIC */ 134 #address-cells = <1>; 135 #size-cells = <1>; 136 137 rbus: bus@98000000 { 138 compatible = "simple-bus"; 139 ranges = <0x0 0x98000000 0xef0000>, 140 <0xa0000000 0xa0000000 0x10000000>; /* PCIE */ 141 #address-cells = <1>; 142 #size-cells = <1>; 143 144 uart0: serial@7800 { 145 compatible = "snps,dw-apb-uart"; 146 reg = <0x7800 0x100>; 147 clock-frequency = <432000000>; 148 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 149 reg-io-width = <4>; 150 reg-shift = <2>; 151 status = "disabled"; 152 }; 153 }; 154 155 gic: interrupt-controller@ff100000 { 156 compatible = "arm,gic-v3"; 157 reg = <0xff100000 0x10000>, 158 <0xff140000 0x80000>; 159 interrupt-controller; 160 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 161 #address-cells = <1>; 162 #interrupt-cells = <3>; 163 #size-cells = <1>; 164 }; 165 }; 166}; 167