1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 9#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 11#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 clock-frequency = <76800000>; 37 #clock-cells = <0>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32764>; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 compatible = "fixed-factor-clock"; 48 #clock-cells = <0>; 49 50 clocks = <&rpmhcc RPMH_CXO_CLK>; 51 clock-mult = <1>; 52 clock-div = <2>; 53 }; 54 55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 56 compatible = "fixed-factor-clock"; 57 #clock-cells = <0>; 58 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "qcom,oryon"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 next-level-cache = <&l2_0>; 75 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; 76 power-domain-names = "psci", "perf"; 77 cpu-idle-states = <&cluster_c4>; 78 79 l2_0: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 cache-unified; 83 }; 84 }; 85 86 cpu1: cpu@100 { 87 device_type = "cpu"; 88 compatible = "qcom,oryon"; 89 reg = <0x0 0x100>; 90 enable-method = "psci"; 91 next-level-cache = <&l2_0>; 92 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; 93 power-domain-names = "psci", "perf"; 94 cpu-idle-states = <&cluster_c4>; 95 }; 96 97 cpu2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,oryon"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 next-level-cache = <&l2_0>; 103 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; 104 power-domain-names = "psci", "perf"; 105 cpu-idle-states = <&cluster_c4>; 106 }; 107 108 cpu3: cpu@300 { 109 device_type = "cpu"; 110 compatible = "qcom,oryon"; 111 reg = <0x0 0x300>; 112 enable-method = "psci"; 113 next-level-cache = <&l2_0>; 114 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; 115 power-domain-names = "psci", "perf"; 116 cpu-idle-states = <&cluster_c4>; 117 }; 118 119 cpu4: cpu@10000 { 120 device_type = "cpu"; 121 compatible = "qcom,oryon"; 122 reg = <0x0 0x10000>; 123 enable-method = "psci"; 124 next-level-cache = <&l2_1>; 125 power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; 126 power-domain-names = "psci", "perf"; 127 cpu-idle-states = <&cluster_c4>; 128 129 l2_1: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 }; 134 }; 135 136 cpu5: cpu@10100 { 137 device_type = "cpu"; 138 compatible = "qcom,oryon"; 139 reg = <0x0 0x10100>; 140 enable-method = "psci"; 141 next-level-cache = <&l2_1>; 142 power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; 143 power-domain-names = "psci", "perf"; 144 cpu-idle-states = <&cluster_c4>; 145 }; 146 147 cpu6: cpu@10200 { 148 device_type = "cpu"; 149 compatible = "qcom,oryon"; 150 reg = <0x0 0x10200>; 151 enable-method = "psci"; 152 next-level-cache = <&l2_1>; 153 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; 154 power-domain-names = "psci", "perf"; 155 cpu-idle-states = <&cluster_c4>; 156 }; 157 158 cpu7: cpu@10300 { 159 device_type = "cpu"; 160 compatible = "qcom,oryon"; 161 reg = <0x0 0x10300>; 162 enable-method = "psci"; 163 next-level-cache = <&l2_1>; 164 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; 165 power-domain-names = "psci", "perf"; 166 cpu-idle-states = <&cluster_c4>; 167 }; 168 169 cpu8: cpu@20000 { 170 device_type = "cpu"; 171 compatible = "qcom,oryon"; 172 reg = <0x0 0x20000>; 173 enable-method = "psci"; 174 next-level-cache = <&l2_2>; 175 power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; 176 power-domain-names = "psci", "perf"; 177 cpu-idle-states = <&cluster_c4>; 178 179 l2_2: l2-cache { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 }; 184 }; 185 186 cpu9: cpu@20100 { 187 device_type = "cpu"; 188 compatible = "qcom,oryon"; 189 reg = <0x0 0x20100>; 190 enable-method = "psci"; 191 next-level-cache = <&l2_2>; 192 power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; 193 power-domain-names = "psci", "perf"; 194 cpu-idle-states = <&cluster_c4>; 195 }; 196 197 cpu10: cpu@20200 { 198 device_type = "cpu"; 199 compatible = "qcom,oryon"; 200 reg = <0x0 0x20200>; 201 enable-method = "psci"; 202 next-level-cache = <&l2_2>; 203 power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; 204 power-domain-names = "psci", "perf"; 205 cpu-idle-states = <&cluster_c4>; 206 }; 207 208 cpu11: cpu@20300 { 209 device_type = "cpu"; 210 compatible = "qcom,oryon"; 211 reg = <0x0 0x20300>; 212 enable-method = "psci"; 213 next-level-cache = <&l2_2>; 214 power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; 215 power-domain-names = "psci", "perf"; 216 cpu-idle-states = <&cluster_c4>; 217 }; 218 219 cpu-map { 220 cluster0 { 221 core0 { 222 cpu = <&cpu0>; 223 }; 224 225 core1 { 226 cpu = <&cpu1>; 227 }; 228 229 core2 { 230 cpu = <&cpu2>; 231 }; 232 233 core3 { 234 cpu = <&cpu3>; 235 }; 236 }; 237 238 cluster1 { 239 core0 { 240 cpu = <&cpu4>; 241 }; 242 243 core1 { 244 cpu = <&cpu5>; 245 }; 246 247 core2 { 248 cpu = <&cpu6>; 249 }; 250 251 core3 { 252 cpu = <&cpu7>; 253 }; 254 }; 255 256 cpu_map_cluster2: cluster2 { 257 core0 { 258 cpu = <&cpu8>; 259 }; 260 261 core1 { 262 cpu = <&cpu9>; 263 }; 264 265 core2 { 266 cpu = <&cpu10>; 267 }; 268 269 core3 { 270 cpu = <&cpu11>; 271 }; 272 }; 273 }; 274 275 idle-states { 276 entry-method = "psci"; 277 278 cluster_c4: cpu-sleep-0 { 279 compatible = "arm,idle-state"; 280 idle-state-name = "ret"; 281 arm,psci-suspend-param = <0x00000004>; 282 entry-latency-us = <180>; 283 exit-latency-us = <500>; 284 min-residency-us = <600>; 285 }; 286 }; 287 288 domain-idle-states { 289 cluster_cl4: cluster-sleep-0 { 290 compatible = "domain-idle-state"; 291 arm,psci-suspend-param = <0x01000044>; 292 entry-latency-us = <350>; 293 exit-latency-us = <500>; 294 min-residency-us = <2500>; 295 }; 296 297 cluster_cl5: cluster-sleep-1 { 298 compatible = "domain-idle-state"; 299 arm,psci-suspend-param = <0x01000054>; 300 entry-latency-us = <2200>; 301 exit-latency-us = <4000>; 302 min-residency-us = <7000>; 303 }; 304 }; 305 }; 306 307 dummy-sink { 308 compatible = "arm,coresight-dummy-sink"; 309 310 in-ports { 311 port { 312 eud_in: endpoint { 313 remote-endpoint = <&swao_rep_out1>; 314 }; 315 }; 316 }; 317 }; 318 319 firmware { 320 scm: scm { 321 compatible = "qcom,scm-x1e80100", "qcom,scm"; 322 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 323 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 324 qcom,dload-mode = <&tcsr 0x19000>; 325 }; 326 327 scmi { 328 compatible = "arm,scmi"; 329 mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; 330 mbox-names = "tx", "rx"; 331 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 332 333 #address-cells = <1>; 334 #size-cells = <0>; 335 336 scmi_dvfs: protocol@13 { 337 reg = <0x13>; 338 #power-domain-cells = <1>; 339 }; 340 }; 341 }; 342 343 clk_virt: interconnect-0 { 344 compatible = "qcom,x1e80100-clk-virt"; 345 #interconnect-cells = <2>; 346 qcom,bcm-voters = <&apps_bcm_voter>; 347 }; 348 349 mc_virt: interconnect-1 { 350 compatible = "qcom,x1e80100-mc-virt"; 351 #interconnect-cells = <2>; 352 qcom,bcm-voters = <&apps_bcm_voter>; 353 }; 354 355 memory@80000000 { 356 device_type = "memory"; 357 /* We expect the bootloader to fill in the size */ 358 reg = <0 0x80000000 0 0>; 359 }; 360 361 pmu { 362 compatible = "arm,armv8-pmuv3"; 363 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 364 }; 365 366 psci { 367 compatible = "arm,psci-1.0"; 368 method = "smc"; 369 370 cpu_pd0: power-domain-cpu0 { 371 #power-domain-cells = <0>; 372 power-domains = <&cluster_pd0>; 373 }; 374 375 cpu_pd1: power-domain-cpu1 { 376 #power-domain-cells = <0>; 377 power-domains = <&cluster_pd0>; 378 }; 379 380 cpu_pd2: power-domain-cpu2 { 381 #power-domain-cells = <0>; 382 power-domains = <&cluster_pd0>; 383 }; 384 385 cpu_pd3: power-domain-cpu3 { 386 #power-domain-cells = <0>; 387 power-domains = <&cluster_pd0>; 388 }; 389 390 cpu_pd4: power-domain-cpu4 { 391 #power-domain-cells = <0>; 392 power-domains = <&cluster_pd1>; 393 }; 394 395 cpu_pd5: power-domain-cpu5 { 396 #power-domain-cells = <0>; 397 power-domains = <&cluster_pd1>; 398 }; 399 400 cpu_pd6: power-domain-cpu6 { 401 #power-domain-cells = <0>; 402 power-domains = <&cluster_pd1>; 403 }; 404 405 cpu_pd7: power-domain-cpu7 { 406 #power-domain-cells = <0>; 407 power-domains = <&cluster_pd1>; 408 }; 409 410 cpu_pd8: power-domain-cpu8 { 411 #power-domain-cells = <0>; 412 power-domains = <&cluster_pd2>; 413 }; 414 415 cpu_pd9: power-domain-cpu9 { 416 #power-domain-cells = <0>; 417 power-domains = <&cluster_pd2>; 418 }; 419 420 cpu_pd10: power-domain-cpu10 { 421 #power-domain-cells = <0>; 422 power-domains = <&cluster_pd2>; 423 }; 424 425 cpu_pd11: power-domain-cpu11 { 426 #power-domain-cells = <0>; 427 power-domains = <&cluster_pd2>; 428 }; 429 430 cluster_pd0: power-domain-cpu-cluster0 { 431 #power-domain-cells = <0>; 432 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 433 power-domains = <&system_pd>; 434 }; 435 436 cluster_pd1: power-domain-cpu-cluster1 { 437 #power-domain-cells = <0>; 438 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 439 power-domains = <&system_pd>; 440 }; 441 442 cluster_pd2: power-domain-cpu-cluster2 { 443 #power-domain-cells = <0>; 444 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 445 power-domains = <&system_pd>; 446 }; 447 448 system_pd: power-domain-system { 449 #power-domain-cells = <0>; 450 /* TODO: system-wide idle states */ 451 }; 452 }; 453 454 reserved-memory { 455 #address-cells = <2>; 456 #size-cells = <2>; 457 ranges; 458 459 gunyah_hyp_mem: gunyah-hyp@80000000 { 460 reg = <0x0 0x80000000 0x0 0x800000>; 461 no-map; 462 }; 463 464 hyp_elf_package_mem: hyp-elf-package@80800000 { 465 reg = <0x0 0x80800000 0x0 0x200000>; 466 no-map; 467 }; 468 469 ncc_mem: ncc@80a00000 { 470 reg = <0x0 0x80a00000 0x0 0x400000>; 471 no-map; 472 }; 473 474 cpucp_log_mem: cpucp-log@80e00000 { 475 reg = <0x0 0x80e00000 0x0 0x40000>; 476 no-map; 477 }; 478 479 cpucp_mem: cpucp@80e40000 { 480 reg = <0x0 0x80e40000 0x0 0x540000>; 481 no-map; 482 }; 483 484 reserved-region@81380000 { 485 reg = <0x0 0x81380000 0x0 0x80000>; 486 no-map; 487 }; 488 489 tags_mem: tags-region@81400000 { 490 reg = <0x0 0x81400000 0x0 0x1a0000>; 491 no-map; 492 }; 493 494 xbl_dtlog_mem: xbl-dtlog@81a00000 { 495 reg = <0x0 0x81a00000 0x0 0x40000>; 496 no-map; 497 }; 498 499 xbl_ramdump_mem: xbl-ramdump@81a40000 { 500 reg = <0x0 0x81a40000 0x0 0x1c0000>; 501 no-map; 502 }; 503 504 aop_image_mem: aop-image@81c00000 { 505 reg = <0x0 0x81c00000 0x0 0x60000>; 506 no-map; 507 }; 508 509 aop_cmd_db_mem: aop-cmd-db@81c60000 { 510 compatible = "qcom,cmd-db"; 511 reg = <0x0 0x81c60000 0x0 0x20000>; 512 no-map; 513 }; 514 515 aop_config_mem: aop-config@81c80000 { 516 reg = <0x0 0x81c80000 0x0 0x20000>; 517 no-map; 518 }; 519 520 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 521 reg = <0x0 0x81ca0000 0x0 0x40000>; 522 no-map; 523 }; 524 525 tme_log_mem: tme-log@81ce0000 { 526 reg = <0x0 0x81ce0000 0x0 0x4000>; 527 no-map; 528 }; 529 530 uefi_log_mem: uefi-log@81ce4000 { 531 reg = <0x0 0x81ce4000 0x0 0x10000>; 532 no-map; 533 }; 534 535 secdata_apss_mem: secdata-apss@81cff000 { 536 reg = <0x0 0x81cff000 0x0 0x1000>; 537 no-map; 538 }; 539 540 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 541 reg = <0x0 0x81e00000 0x0 0x100000>; 542 no-map; 543 }; 544 545 gpu_prr_mem: gpu-prr@81f00000 { 546 reg = <0x0 0x81f00000 0x0 0x10000>; 547 no-map; 548 }; 549 550 tpm_control_mem: tpm-control@81f10000 { 551 reg = <0x0 0x81f10000 0x0 0x10000>; 552 no-map; 553 }; 554 555 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 556 reg = <0x0 0x81f20000 0x0 0x10000>; 557 no-map; 558 }; 559 560 pld_pep_mem: pld-pep@81f30000 { 561 reg = <0x0 0x81f30000 0x0 0x6000>; 562 no-map; 563 }; 564 565 pld_gmu_mem: pld-gmu@81f36000 { 566 reg = <0x0 0x81f36000 0x0 0x1000>; 567 no-map; 568 }; 569 570 pld_pdp_mem: pld-pdp@81f37000 { 571 reg = <0x0 0x81f37000 0x0 0x1000>; 572 no-map; 573 }; 574 575 tz_stat_mem: tz-stat@82700000 { 576 reg = <0x0 0x82700000 0x0 0x100000>; 577 no-map; 578 }; 579 580 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 581 reg = <0x0 0x82800000 0x0 0xc00000>; 582 no-map; 583 }; 584 585 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 586 reg = <0x0 0x84b00000 0x0 0x800000>; 587 no-map; 588 }; 589 590 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 591 reg = <0x0 0x85300000 0x0 0x80000>; 592 no-map; 593 }; 594 595 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 596 reg = <0x0 0x866c0000 0x0 0x40000>; 597 no-map; 598 }; 599 600 spss_region_mem: spss-region@86700000 { 601 reg = <0x0 0x86700000 0x0 0x400000>; 602 no-map; 603 }; 604 605 adsp_boot_mem: adsp-boot@86b00000 { 606 reg = <0x0 0x86b00000 0x0 0xc00000>; 607 no-map; 608 }; 609 610 video_mem: video@87700000 { 611 reg = <0x0 0x87700000 0x0 0x700000>; 612 no-map; 613 }; 614 615 adspslpi_mem: adspslpi@87e00000 { 616 reg = <0x0 0x87e00000 0x0 0x3a00000>; 617 no-map; 618 }; 619 620 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 621 reg = <0x0 0x8b800000 0x0 0x80000>; 622 no-map; 623 }; 624 625 cdsp_mem: cdsp@8b900000 { 626 reg = <0x0 0x8b900000 0x0 0x2000000>; 627 no-map; 628 }; 629 630 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 631 reg = <0x0 0x8d900000 0x0 0x80000>; 632 no-map; 633 }; 634 635 gpu_microcode_mem: gpu-microcode@8d9fe000 { 636 reg = <0x0 0x8d9fe000 0x0 0x2000>; 637 no-map; 638 }; 639 640 cvp_mem: cvp@8da00000 { 641 reg = <0x0 0x8da00000 0x0 0x700000>; 642 no-map; 643 }; 644 645 camera_mem: camera@8e100000 { 646 reg = <0x0 0x8e100000 0x0 0x800000>; 647 no-map; 648 }; 649 650 av1_encoder_mem: av1-encoder@8e900000 { 651 reg = <0x0 0x8e900000 0x0 0x700000>; 652 no-map; 653 }; 654 655 reserved-region@8f000000 { 656 reg = <0x0 0x8f000000 0x0 0xa00000>; 657 no-map; 658 }; 659 660 wpss_mem: wpss@8fa00000 { 661 reg = <0x0 0x8fa00000 0x0 0x1900000>; 662 no-map; 663 }; 664 665 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 666 reg = <0x0 0x91300000 0x0 0x80000>; 667 no-map; 668 }; 669 670 xbl_sc_mem: xbl-sc@d8000000 { 671 reg = <0x0 0xd8000000 0x0 0x40000>; 672 no-map; 673 }; 674 675 reserved-region@d8040000 { 676 reg = <0x0 0xd8040000 0x0 0xa0000>; 677 no-map; 678 }; 679 680 qtee_mem: qtee@d80e0000 { 681 reg = <0x0 0xd80e0000 0x0 0x520000>; 682 no-map; 683 }; 684 685 ta_mem: ta@d8600000 { 686 reg = <0x0 0xd8600000 0x0 0x8a00000>; 687 no-map; 688 }; 689 690 tags_mem1: tags@e1000000 { 691 reg = <0x0 0xe1000000 0x0 0x26a0000>; 692 no-map; 693 }; 694 695 llcc_lpi_mem: llcc-lpi@ff800000 { 696 reg = <0x0 0xff800000 0x0 0x600000>; 697 no-map; 698 }; 699 700 smem_mem: smem@ffe00000 { 701 compatible = "qcom,smem"; 702 reg = <0x0 0xffe00000 0x0 0x200000>; 703 hwlocks = <&tcsr_mutex 3>; 704 no-map; 705 }; 706 }; 707 708 qup_opp_table_100mhz: opp-table-qup100mhz { 709 compatible = "operating-points-v2"; 710 711 opp-75000000 { 712 opp-hz = /bits/ 64 <75000000>; 713 required-opps = <&rpmhpd_opp_low_svs>; 714 }; 715 716 opp-100000000 { 717 opp-hz = /bits/ 64 <100000000>; 718 required-opps = <&rpmhpd_opp_svs>; 719 }; 720 }; 721 722 qup_opp_table_120mhz: opp-table-qup120mhz { 723 compatible = "operating-points-v2"; 724 725 opp-75000000 { 726 opp-hz = /bits/ 64 <75000000>; 727 required-opps = <&rpmhpd_opp_low_svs>; 728 }; 729 730 opp-120000000 { 731 opp-hz = /bits/ 64 <120000000>; 732 required-opps = <&rpmhpd_opp_svs>; 733 }; 734 }; 735 736 smp2p-adsp { 737 compatible = "qcom,smp2p"; 738 739 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 740 IPCC_MPROC_SIGNAL_SMP2P 741 IRQ_TYPE_EDGE_RISING>; 742 743 mboxes = <&ipcc IPCC_CLIENT_LPASS 744 IPCC_MPROC_SIGNAL_SMP2P>; 745 746 qcom,smem = <443>, <429>; 747 qcom,local-pid = <0>; 748 qcom,remote-pid = <2>; 749 750 smp2p_adsp_out: master-kernel { 751 qcom,entry-name = "master-kernel"; 752 #qcom,smem-state-cells = <1>; 753 }; 754 755 smp2p_adsp_in: slave-kernel { 756 qcom,entry-name = "slave-kernel"; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 }; 760 }; 761 762 smp2p-cdsp { 763 compatible = "qcom,smp2p"; 764 765 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 766 IPCC_MPROC_SIGNAL_SMP2P 767 IRQ_TYPE_EDGE_RISING>; 768 769 mboxes = <&ipcc IPCC_CLIENT_CDSP 770 IPCC_MPROC_SIGNAL_SMP2P>; 771 772 qcom,smem = <94>, <432>; 773 qcom,local-pid = <0>; 774 qcom,remote-pid = <5>; 775 776 smp2p_cdsp_out: master-kernel { 777 qcom,entry-name = "master-kernel"; 778 #qcom,smem-state-cells = <1>; 779 }; 780 781 smp2p_cdsp_in: slave-kernel { 782 qcom,entry-name = "slave-kernel"; 783 interrupt-controller; 784 #interrupt-cells = <2>; 785 }; 786 }; 787 788 soc: soc@0 { 789 compatible = "simple-bus"; 790 791 #address-cells = <2>; 792 #size-cells = <2>; 793 dma-ranges = <0 0 0 0 0x10 0>; 794 ranges = <0 0 0 0 0x10 0>; 795 796 gcc: clock-controller@100000 { 797 compatible = "qcom,x1e80100-gcc"; 798 reg = <0 0x00100000 0 0x200000>; 799 800 clocks = <&bi_tcxo_div2>, 801 <&sleep_clk>, 802 <&pcie3_phy>, 803 <&pcie4_phy>, 804 <&pcie5_phy>, 805 <&pcie6a_phy>, 806 <0>, 807 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 808 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 809 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 810 811 power-domains = <&rpmhpd RPMHPD_CX>; 812 #clock-cells = <1>; 813 #reset-cells = <1>; 814 #power-domain-cells = <1>; 815 }; 816 817 ipcc: mailbox@408000 { 818 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 819 reg = <0 0x00408000 0 0x1000>; 820 821 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 822 interrupt-controller; 823 #interrupt-cells = <3>; 824 825 #mbox-cells = <2>; 826 }; 827 828 gpi_dma2: dma-controller@800000 { 829 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 830 reg = <0 0x00800000 0 0x60000>; 831 832 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 844 845 dma-channels = <12>; 846 dma-channel-mask = <0x3e>; 847 #dma-cells = <3>; 848 849 iommus = <&apps_smmu 0x436 0x0>; 850 851 status = "disabled"; 852 }; 853 854 qupv3_2: geniqup@8c0000 { 855 compatible = "qcom,geni-se-qup"; 856 reg = <0 0x008c0000 0 0x2000>; 857 858 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 859 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 860 clock-names = "m-ahb", 861 "s-ahb"; 862 863 iommus = <&apps_smmu 0x423 0x0>; 864 865 #address-cells = <2>; 866 #size-cells = <2>; 867 ranges; 868 869 status = "disabled"; 870 871 i2c16: i2c@880000 { 872 compatible = "qcom,geni-i2c"; 873 reg = <0 0x00880000 0 0x4000>; 874 875 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 876 877 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 878 clock-names = "se"; 879 880 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 881 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 882 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 883 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 884 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 885 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 886 interconnect-names = "qup-core", 887 "qup-config", 888 "qup-memory"; 889 890 power-domains = <&rpmhpd RPMHPD_CX>; 891 required-opps = <&rpmhpd_opp_low_svs>; 892 893 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 894 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 895 dma-names = "tx", 896 "rx"; 897 898 pinctrl-0 = <&qup_i2c16_data_clk>; 899 pinctrl-names = "default"; 900 901 #address-cells = <1>; 902 #size-cells = <0>; 903 904 status = "disabled"; 905 }; 906 907 spi16: spi@880000 { 908 compatible = "qcom,geni-spi"; 909 reg = <0 0x00880000 0 0x4000>; 910 911 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 912 913 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 914 clock-names = "se"; 915 916 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 917 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 919 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 920 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 922 interconnect-names = "qup-core", 923 "qup-config", 924 "qup-memory"; 925 926 power-domains = <&rpmhpd RPMHPD_CX>; 927 operating-points-v2 = <&qup_opp_table_120mhz>; 928 929 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 930 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 931 dma-names = "tx", 932 "rx"; 933 934 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 935 pinctrl-names = "default"; 936 937 #address-cells = <1>; 938 #size-cells = <0>; 939 940 status = "disabled"; 941 }; 942 943 i2c17: i2c@884000 { 944 compatible = "qcom,geni-i2c"; 945 reg = <0 0x00884000 0 0x4000>; 946 947 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 948 949 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 950 clock-names = "se"; 951 952 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 953 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 954 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 955 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 956 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 957 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 958 interconnect-names = "qup-core", 959 "qup-config", 960 "qup-memory"; 961 962 power-domains = <&rpmhpd RPMHPD_CX>; 963 required-opps = <&rpmhpd_opp_low_svs>; 964 965 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 966 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 967 dma-names = "tx", 968 "rx"; 969 970 pinctrl-0 = <&qup_i2c17_data_clk>; 971 pinctrl-names = "default"; 972 973 #address-cells = <1>; 974 #size-cells = <0>; 975 976 status = "disabled"; 977 }; 978 979 spi17: spi@884000 { 980 compatible = "qcom,geni-spi"; 981 reg = <0 0x00884000 0 0x4000>; 982 983 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 984 985 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 986 clock-names = "se"; 987 988 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 989 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 990 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 991 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 992 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 993 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 994 interconnect-names = "qup-core", 995 "qup-config", 996 "qup-memory"; 997 998 power-domains = <&rpmhpd RPMHPD_CX>; 999 operating-points-v2 = <&qup_opp_table_120mhz>; 1000 1001 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1002 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1003 dma-names = "tx", 1004 "rx"; 1005 1006 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1007 pinctrl-names = "default"; 1008 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 1012 status = "disabled"; 1013 }; 1014 1015 i2c18: i2c@888000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x00888000 0 0x4000>; 1018 1019 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1020 1021 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1022 clock-names = "se"; 1023 1024 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1025 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1026 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1027 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1028 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1029 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1030 interconnect-names = "qup-core", 1031 "qup-config", 1032 "qup-memory"; 1033 1034 power-domains = <&rpmhpd RPMHPD_CX>; 1035 required-opps = <&rpmhpd_opp_low_svs>; 1036 1037 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1038 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1039 dma-names = "tx", 1040 "rx"; 1041 1042 pinctrl-0 = <&qup_i2c18_data_clk>; 1043 pinctrl-names = "default"; 1044 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 1048 status = "disabled"; 1049 }; 1050 1051 spi18: spi@888000 { 1052 compatible = "qcom,geni-spi"; 1053 reg = <0 0x00888000 0 0x4000>; 1054 1055 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1056 1057 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1058 clock-names = "se"; 1059 1060 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1061 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1062 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1063 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1064 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1065 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1066 interconnect-names = "qup-core", 1067 "qup-config", 1068 "qup-memory"; 1069 1070 power-domains = <&rpmhpd RPMHPD_CX>; 1071 operating-points-v2 = <&qup_opp_table_100mhz>; 1072 1073 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1074 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1075 dma-names = "tx", 1076 "rx"; 1077 1078 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1079 pinctrl-names = "default"; 1080 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 status = "disabled"; 1085 }; 1086 1087 i2c19: i2c@88c000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x0088c000 0 0x4000>; 1090 1091 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1092 1093 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1094 clock-names = "se"; 1095 1096 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1097 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1098 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1099 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1100 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1101 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1102 interconnect-names = "qup-core", 1103 "qup-config", 1104 "qup-memory"; 1105 1106 power-domains = <&rpmhpd RPMHPD_CX>; 1107 required-opps = <&rpmhpd_opp_low_svs>; 1108 1109 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1110 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1111 dma-names = "tx", 1112 "rx"; 1113 1114 pinctrl-0 = <&qup_i2c19_data_clk>; 1115 pinctrl-names = "default"; 1116 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 1120 status = "disabled"; 1121 }; 1122 1123 spi19: spi@88c000 { 1124 compatible = "qcom,geni-spi"; 1125 reg = <0 0x0088c000 0 0x4000>; 1126 1127 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1128 1129 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1130 clock-names = "se"; 1131 1132 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1133 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1134 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1135 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1136 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1137 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1138 interconnect-names = "qup-core", 1139 "qup-config", 1140 "qup-memory"; 1141 1142 power-domains = <&rpmhpd RPMHPD_CX>; 1143 operating-points-v2 = <&qup_opp_table_100mhz>; 1144 1145 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1146 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1147 dma-names = "tx", 1148 "rx"; 1149 1150 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1151 pinctrl-names = "default"; 1152 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 1156 status = "disabled"; 1157 }; 1158 1159 i2c20: i2c@890000 { 1160 compatible = "qcom,geni-i2c"; 1161 reg = <0 0x00890000 0 0x4000>; 1162 1163 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1164 1165 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1166 clock-names = "se"; 1167 1168 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1169 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1170 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1171 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1172 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1174 interconnect-names = "qup-core", 1175 "qup-config", 1176 "qup-memory"; 1177 1178 power-domains = <&rpmhpd RPMHPD_CX>; 1179 required-opps = <&rpmhpd_opp_low_svs>; 1180 1181 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1182 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1183 dma-names = "tx", 1184 "rx"; 1185 1186 pinctrl-0 = <&qup_i2c20_data_clk>; 1187 pinctrl-names = "default"; 1188 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 1192 status = "disabled"; 1193 }; 1194 1195 spi20: spi@890000 { 1196 compatible = "qcom,geni-spi"; 1197 reg = <0 0x00890000 0 0x4000>; 1198 1199 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1200 1201 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1202 clock-names = "se"; 1203 1204 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1205 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1206 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1207 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1208 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1209 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1210 interconnect-names = "qup-core", 1211 "qup-config", 1212 "qup-memory"; 1213 1214 power-domains = <&rpmhpd RPMHPD_CX>; 1215 operating-points-v2 = <&qup_opp_table_100mhz>; 1216 1217 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1218 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1219 dma-names = "tx", 1220 "rx"; 1221 1222 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1223 pinctrl-names = "default"; 1224 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 1228 status = "disabled"; 1229 }; 1230 1231 i2c21: i2c@894000 { 1232 compatible = "qcom,geni-i2c"; 1233 reg = <0 0x00894000 0 0x4000>; 1234 1235 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1236 1237 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1238 clock-names = "se"; 1239 1240 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1241 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1242 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1243 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1244 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1245 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1246 interconnect-names = "qup-core", 1247 "qup-config", 1248 "qup-memory"; 1249 1250 power-domains = <&rpmhpd RPMHPD_CX>; 1251 required-opps = <&rpmhpd_opp_low_svs>; 1252 1253 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1254 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1255 dma-names = "tx", 1256 "rx"; 1257 1258 pinctrl-0 = <&qup_i2c21_data_clk>; 1259 pinctrl-names = "default"; 1260 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 1264 status = "disabled"; 1265 }; 1266 1267 spi21: spi@894000 { 1268 compatible = "qcom,geni-spi"; 1269 reg = <0 0x00894000 0 0x4000>; 1270 1271 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1272 1273 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1274 clock-names = "se"; 1275 1276 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1277 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1278 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1279 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1280 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1281 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1282 interconnect-names = "qup-core", 1283 "qup-config", 1284 "qup-memory"; 1285 1286 power-domains = <&rpmhpd RPMHPD_CX>; 1287 operating-points-v2 = <&qup_opp_table_100mhz>; 1288 1289 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1290 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1291 dma-names = "tx", 1292 "rx"; 1293 1294 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1295 pinctrl-names = "default"; 1296 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 1300 status = "disabled"; 1301 }; 1302 1303 uart21: serial@894000 { 1304 compatible = "qcom,geni-uart"; 1305 reg = <0 0x00894000 0 0x4000>; 1306 1307 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1308 1309 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1310 clock-names = "se"; 1311 1312 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1313 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1314 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1315 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1316 interconnect-names = "qup-core", 1317 "qup-config"; 1318 1319 power-domains = <&rpmhpd RPMHPD_CX>; 1320 operating-points-v2 = <&qup_opp_table_100mhz>; 1321 1322 pinctrl-0 = <&qup_uart21_default>; 1323 pinctrl-names = "default"; 1324 1325 status = "disabled"; 1326 }; 1327 1328 i2c22: i2c@898000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0 0x00898000 0 0x4000>; 1331 1332 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1333 1334 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1335 clock-names = "se"; 1336 1337 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1338 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1339 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1340 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1341 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1342 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1343 interconnect-names = "qup-core", 1344 "qup-config", 1345 "qup-memory"; 1346 1347 power-domains = <&rpmhpd RPMHPD_CX>; 1348 required-opps = <&rpmhpd_opp_low_svs>; 1349 1350 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1351 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1352 dma-names = "tx", 1353 "rx"; 1354 1355 pinctrl-0 = <&qup_i2c22_data_clk>; 1356 pinctrl-names = "default"; 1357 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 1361 status = "disabled"; 1362 }; 1363 1364 spi22: spi@898000 { 1365 compatible = "qcom,geni-spi"; 1366 reg = <0 0x00898000 0 0x4000>; 1367 1368 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1369 1370 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1371 clock-names = "se"; 1372 1373 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1374 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1375 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1376 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1377 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1378 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1379 interconnect-names = "qup-core", 1380 "qup-config", 1381 "qup-memory"; 1382 1383 power-domains = <&rpmhpd RPMHPD_CX>; 1384 operating-points-v2 = <&qup_opp_table_100mhz>; 1385 1386 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1387 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1388 dma-names = "tx", 1389 "rx"; 1390 1391 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1392 pinctrl-names = "default"; 1393 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 1397 status = "disabled"; 1398 }; 1399 1400 i2c23: i2c@89c000 { 1401 compatible = "qcom,geni-i2c"; 1402 reg = <0 0x0089c000 0 0x4000>; 1403 1404 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1405 1406 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1407 clock-names = "se"; 1408 1409 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1410 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1411 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1412 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1413 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1414 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1415 interconnect-names = "qup-core", 1416 "qup-config", 1417 "qup-memory"; 1418 1419 power-domains = <&rpmhpd RPMHPD_CX>; 1420 required-opps = <&rpmhpd_opp_low_svs>; 1421 1422 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1423 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1424 dma-names = "tx", 1425 "rx"; 1426 1427 pinctrl-0 = <&qup_i2c23_data_clk>; 1428 pinctrl-names = "default"; 1429 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 1433 status = "disabled"; 1434 }; 1435 1436 spi23: spi@89c000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x0089c000 0 0x4000>; 1439 1440 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1441 1442 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1443 clock-names = "se"; 1444 1445 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1446 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1448 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1449 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1450 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1451 interconnect-names = "qup-core", 1452 "qup-config", 1453 "qup-memory"; 1454 1455 power-domains = <&rpmhpd RPMHPD_CX>; 1456 operating-points-v2 = <&qup_opp_table_100mhz>; 1457 1458 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1459 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1460 dma-names = "tx", 1461 "rx"; 1462 1463 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1464 pinctrl-names = "default"; 1465 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 1469 status = "disabled"; 1470 }; 1471 }; 1472 1473 gpi_dma1: dma-controller@a00000 { 1474 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1475 reg = <0 0x00a00000 0 0x60000>; 1476 1477 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1489 1490 dma-channels = <12>; 1491 dma-channel-mask = <0x3e>; 1492 #dma-cells = <3>; 1493 1494 iommus = <&apps_smmu 0x136 0x0>; 1495 1496 status = "disabled"; 1497 }; 1498 1499 qupv3_1: geniqup@ac0000 { 1500 compatible = "qcom,geni-se-qup"; 1501 reg = <0 0x00ac0000 0 0x2000>; 1502 1503 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1504 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1505 clock-names = "m-ahb", 1506 "s-ahb"; 1507 1508 iommus = <&apps_smmu 0x123 0x0>; 1509 1510 #address-cells = <2>; 1511 #size-cells = <2>; 1512 ranges; 1513 1514 status = "disabled"; 1515 1516 i2c8: i2c@a80000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00a80000 0 0x4000>; 1519 1520 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1521 1522 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1523 clock-names = "se"; 1524 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1526 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1527 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1528 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1529 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1530 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1531 interconnect-names = "qup-core", 1532 "qup-config", 1533 "qup-memory"; 1534 1535 power-domains = <&rpmhpd RPMHPD_CX>; 1536 required-opps = <&rpmhpd_opp_low_svs>; 1537 1538 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1539 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1540 dma-names = "tx", 1541 "rx"; 1542 1543 pinctrl-0 = <&qup_i2c8_data_clk>; 1544 pinctrl-names = "default"; 1545 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 1549 status = "disabled"; 1550 }; 1551 1552 spi8: spi@a80000 { 1553 compatible = "qcom,geni-spi"; 1554 reg = <0 0x00a80000 0 0x4000>; 1555 1556 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1557 1558 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1559 clock-names = "se"; 1560 1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1562 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1563 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1564 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1565 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1566 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1567 interconnect-names = "qup-core", 1568 "qup-config", 1569 "qup-memory"; 1570 1571 power-domains = <&rpmhpd RPMHPD_CX>; 1572 operating-points-v2 = <&qup_opp_table_120mhz>; 1573 1574 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1575 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1576 dma-names = "tx", 1577 "rx"; 1578 1579 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1580 pinctrl-names = "default"; 1581 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 1585 status = "disabled"; 1586 }; 1587 1588 i2c9: i2c@a84000 { 1589 compatible = "qcom,geni-i2c"; 1590 reg = <0 0x00a84000 0 0x4000>; 1591 1592 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1593 1594 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1595 clock-names = "se"; 1596 1597 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1598 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1599 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1600 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1601 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1602 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1603 interconnect-names = "qup-core", 1604 "qup-config", 1605 "qup-memory"; 1606 1607 power-domains = <&rpmhpd RPMHPD_CX>; 1608 required-opps = <&rpmhpd_opp_low_svs>; 1609 1610 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1611 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1612 dma-names = "tx", 1613 "rx"; 1614 1615 pinctrl-0 = <&qup_i2c9_data_clk>; 1616 pinctrl-names = "default"; 1617 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 1621 status = "disabled"; 1622 }; 1623 1624 spi9: spi@a84000 { 1625 compatible = "qcom,geni-spi"; 1626 reg = <0 0x00a84000 0 0x4000>; 1627 1628 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1629 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1631 clock-names = "se"; 1632 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1634 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1635 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1636 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1637 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1638 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1639 interconnect-names = "qup-core", 1640 "qup-config", 1641 "qup-memory"; 1642 1643 power-domains = <&rpmhpd RPMHPD_CX>; 1644 operating-points-v2 = <&qup_opp_table_120mhz>; 1645 1646 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1647 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1648 dma-names = "tx", 1649 "rx"; 1650 1651 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1652 pinctrl-names = "default"; 1653 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 1657 status = "disabled"; 1658 }; 1659 1660 i2c10: i2c@a88000 { 1661 compatible = "qcom,geni-i2c"; 1662 reg = <0 0x00a88000 0 0x4000>; 1663 1664 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1665 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1667 clock-names = "se"; 1668 1669 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1670 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1671 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1672 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1673 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1674 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1675 interconnect-names = "qup-core", 1676 "qup-config", 1677 "qup-memory"; 1678 1679 power-domains = <&rpmhpd RPMHPD_CX>; 1680 required-opps = <&rpmhpd_opp_low_svs>; 1681 1682 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1683 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1684 dma-names = "tx", 1685 "rx"; 1686 1687 pinctrl-0 = <&qup_i2c10_data_clk>; 1688 pinctrl-names = "default"; 1689 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 1693 status = "disabled"; 1694 }; 1695 1696 spi10: spi@a88000 { 1697 compatible = "qcom,geni-spi"; 1698 reg = <0 0x00a88000 0 0x4000>; 1699 1700 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1701 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1703 clock-names = "se"; 1704 1705 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1706 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1707 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1708 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1709 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1710 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1711 interconnect-names = "qup-core", 1712 "qup-config", 1713 "qup-memory"; 1714 1715 power-domains = <&rpmhpd RPMHPD_CX>; 1716 operating-points-v2 = <&qup_opp_table_100mhz>; 1717 1718 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1719 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1720 dma-names = "tx", 1721 "rx"; 1722 1723 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1724 pinctrl-names = "default"; 1725 1726 #address-cells = <1>; 1727 #size-cells = <0>; 1728 1729 status = "disabled"; 1730 }; 1731 1732 i2c11: i2c@a8c000 { 1733 compatible = "qcom,geni-i2c"; 1734 reg = <0 0x00a8c000 0 0x4000>; 1735 1736 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1737 1738 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1739 clock-names = "se"; 1740 1741 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1742 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1743 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1744 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1745 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1746 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1747 interconnect-names = "qup-core", 1748 "qup-config", 1749 "qup-memory"; 1750 1751 power-domains = <&rpmhpd RPMHPD_CX>; 1752 required-opps = <&rpmhpd_opp_low_svs>; 1753 1754 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1755 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1756 dma-names = "tx", 1757 "rx"; 1758 1759 pinctrl-0 = <&qup_i2c11_data_clk>; 1760 pinctrl-names = "default"; 1761 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 1765 status = "disabled"; 1766 }; 1767 1768 spi11: spi@a8c000 { 1769 compatible = "qcom,geni-spi"; 1770 reg = <0 0x00a8c000 0 0x4000>; 1771 1772 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1773 1774 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1775 clock-names = "se"; 1776 1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1778 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1779 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1780 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1781 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1782 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1783 interconnect-names = "qup-core", 1784 "qup-config", 1785 "qup-memory"; 1786 1787 power-domains = <&rpmhpd RPMHPD_CX>; 1788 operating-points-v2 = <&qup_opp_table_100mhz>; 1789 1790 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1791 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1792 dma-names = "tx", 1793 "rx"; 1794 1795 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1796 pinctrl-names = "default"; 1797 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 1801 status = "disabled"; 1802 }; 1803 1804 i2c12: i2c@a90000 { 1805 compatible = "qcom,geni-i2c"; 1806 reg = <0 0x00a90000 0 0x4000>; 1807 1808 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1809 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1811 clock-names = "se"; 1812 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1814 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1815 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1816 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1817 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1818 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1819 interconnect-names = "qup-core", 1820 "qup-config", 1821 "qup-memory"; 1822 1823 power-domains = <&rpmhpd RPMHPD_CX>; 1824 required-opps = <&rpmhpd_opp_low_svs>; 1825 1826 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1827 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1828 dma-names = "tx", 1829 "rx"; 1830 1831 pinctrl-0 = <&qup_i2c12_data_clk>; 1832 pinctrl-names = "default"; 1833 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 1837 status = "disabled"; 1838 }; 1839 1840 spi12: spi@a90000 { 1841 compatible = "qcom,geni-spi"; 1842 reg = <0 0x00a90000 0 0x4000>; 1843 1844 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1845 1846 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1847 clock-names = "se"; 1848 1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1851 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1852 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1853 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", 1856 "qup-config", 1857 "qup-memory"; 1858 1859 power-domains = <&rpmhpd RPMHPD_CX>; 1860 operating-points-v2 = <&qup_opp_table_100mhz>; 1861 1862 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1863 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1864 dma-names = "tx", 1865 "rx"; 1866 1867 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1868 pinctrl-names = "default"; 1869 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 1873 status = "disabled"; 1874 }; 1875 1876 i2c13: i2c@a94000 { 1877 compatible = "qcom,geni-i2c"; 1878 reg = <0 0x00a94000 0 0x4000>; 1879 1880 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1881 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1883 clock-names = "se"; 1884 1885 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1886 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1887 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1888 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1889 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1890 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1891 interconnect-names = "qup-core", 1892 "qup-config", 1893 "qup-memory"; 1894 1895 power-domains = <&rpmhpd RPMHPD_CX>; 1896 required-opps = <&rpmhpd_opp_low_svs>; 1897 1898 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1899 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1900 dma-names = "tx", 1901 "rx"; 1902 1903 pinctrl-0 = <&qup_i2c13_data_clk>; 1904 pinctrl-names = "default"; 1905 1906 #address-cells = <1>; 1907 #size-cells = <0>; 1908 1909 status = "disabled"; 1910 }; 1911 1912 spi13: spi@a94000 { 1913 compatible = "qcom,geni-spi"; 1914 reg = <0 0x00a94000 0 0x4000>; 1915 1916 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1917 1918 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1919 clock-names = "se"; 1920 1921 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1922 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1923 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1924 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1925 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1926 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1927 interconnect-names = "qup-core", 1928 "qup-config", 1929 "qup-memory"; 1930 1931 power-domains = <&rpmhpd RPMHPD_CX>; 1932 operating-points-v2 = <&qup_opp_table_100mhz>; 1933 1934 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1935 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1936 dma-names = "tx", 1937 "rx"; 1938 1939 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1940 pinctrl-names = "default"; 1941 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 1945 status = "disabled"; 1946 }; 1947 1948 i2c14: i2c@a98000 { 1949 compatible = "qcom,geni-i2c"; 1950 reg = <0 0x00a98000 0 0x4000>; 1951 1952 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1953 1954 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1955 clock-names = "se"; 1956 1957 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1958 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1959 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1960 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1961 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1962 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1963 interconnect-names = "qup-core", 1964 "qup-config", 1965 "qup-memory"; 1966 1967 power-domains = <&rpmhpd RPMHPD_CX>; 1968 required-opps = <&rpmhpd_opp_low_svs>; 1969 1970 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1971 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1972 dma-names = "tx", 1973 "rx"; 1974 1975 pinctrl-0 = <&qup_i2c14_data_clk>; 1976 pinctrl-names = "default"; 1977 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 1981 status = "disabled"; 1982 }; 1983 1984 spi14: spi@a98000 { 1985 compatible = "qcom,geni-spi"; 1986 reg = <0 0x00a98000 0 0x4000>; 1987 1988 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1989 1990 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1991 clock-names = "se"; 1992 1993 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1994 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1995 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1996 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1997 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1998 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1999 interconnect-names = "qup-core", 2000 "qup-config", 2001 "qup-memory"; 2002 2003 power-domains = <&rpmhpd RPMHPD_CX>; 2004 operating-points-v2 = <&qup_opp_table_100mhz>; 2005 2006 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2007 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2008 dma-names = "tx", 2009 "rx"; 2010 2011 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2012 pinctrl-names = "default"; 2013 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 2017 status = "disabled"; 2018 }; 2019 2020 uart14: serial@a98000 { 2021 compatible = "qcom,geni-uart"; 2022 reg = <0 0x00a98000 0 0x4000>; 2023 2024 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2025 2026 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2027 clock-names = "se"; 2028 2029 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2030 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2031 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2032 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2033 interconnect-names = "qup-core", 2034 "qup-config"; 2035 2036 power-domains = <&rpmhpd RPMHPD_CX>; 2037 operating-points-v2 = <&qup_opp_table_100mhz>; 2038 2039 pinctrl-0 = <&qup_uart14_default>; 2040 pinctrl-names = "default"; 2041 2042 status = "disabled"; 2043 }; 2044 2045 i2c15: i2c@a9c000 { 2046 compatible = "qcom,geni-i2c"; 2047 reg = <0 0x00a9c000 0 0x4000>; 2048 2049 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2050 2051 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2052 clock-names = "se"; 2053 2054 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2055 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2057 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2058 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2060 interconnect-names = "qup-core", 2061 "qup-config", 2062 "qup-memory"; 2063 2064 power-domains = <&rpmhpd RPMHPD_CX>; 2065 required-opps = <&rpmhpd_opp_low_svs>; 2066 2067 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2068 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2069 dma-names = "tx", 2070 "rx"; 2071 2072 pinctrl-0 = <&qup_i2c15_data_clk>; 2073 pinctrl-names = "default"; 2074 2075 #address-cells = <1>; 2076 #size-cells = <0>; 2077 2078 status = "disabled"; 2079 }; 2080 2081 spi15: spi@a9c000 { 2082 compatible = "qcom,geni-spi"; 2083 reg = <0 0x00a9c000 0 0x4000>; 2084 2085 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2086 2087 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2088 clock-names = "se"; 2089 2090 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2091 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2092 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2093 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2094 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2095 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2096 interconnect-names = "qup-core", 2097 "qup-config", 2098 "qup-memory"; 2099 2100 power-domains = <&rpmhpd RPMHPD_CX>; 2101 operating-points-v2 = <&qup_opp_table_100mhz>; 2102 2103 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2104 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2105 dma-names = "tx", 2106 "rx"; 2107 2108 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2109 pinctrl-names = "default"; 2110 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 2114 status = "disabled"; 2115 }; 2116 }; 2117 2118 gpi_dma0: dma-controller@b00000 { 2119 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 2120 reg = <0 0x00b00000 0 0x60000>; 2121 2122 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 2134 2135 dma-channels = <12>; 2136 dma-channel-mask = <0x3e>; 2137 #dma-cells = <3>; 2138 2139 iommus = <&apps_smmu 0x456 0x0>; 2140 2141 status = "disabled"; 2142 }; 2143 2144 qupv3_0: geniqup@bc0000 { 2145 compatible = "qcom,geni-se-qup"; 2146 reg = <0 0x00bc0000 0 0x2000>; 2147 2148 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 2149 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 2150 clock-names = "m-ahb", 2151 "s-ahb"; 2152 2153 iommus = <&apps_smmu 0x443 0x0>; 2154 #address-cells = <2>; 2155 #size-cells = <2>; 2156 ranges; 2157 2158 status = "disabled"; 2159 2160 i2c0: i2c@b80000 { 2161 compatible = "qcom,geni-i2c"; 2162 reg = <0 0x00b80000 0 0x4000>; 2163 2164 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2165 2166 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2167 clock-names = "se"; 2168 2169 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2170 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2171 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2172 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2173 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2174 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2175 interconnect-names = "qup-core", 2176 "qup-config", 2177 "qup-memory"; 2178 2179 power-domains = <&rpmhpd RPMHPD_CX>; 2180 required-opps = <&rpmhpd_opp_low_svs>; 2181 2182 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2183 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2184 dma-names = "tx", 2185 "rx"; 2186 2187 pinctrl-0 = <&qup_i2c0_data_clk>; 2188 pinctrl-names = "default"; 2189 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 2193 status = "disabled"; 2194 }; 2195 2196 spi0: spi@b80000 { 2197 compatible = "qcom,geni-spi"; 2198 reg = <0 0x00b80000 0 0x4000>; 2199 2200 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2201 2202 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2203 clock-names = "se"; 2204 2205 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2206 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2207 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2208 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2209 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2210 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2211 interconnect-names = "qup-core", 2212 "qup-config", 2213 "qup-memory"; 2214 2215 power-domains = <&rpmhpd RPMHPD_CX>; 2216 operating-points-v2 = <&qup_opp_table_120mhz>; 2217 2218 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2219 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2220 dma-names = "tx", 2221 "rx"; 2222 2223 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2224 pinctrl-names = "default"; 2225 2226 #address-cells = <1>; 2227 #size-cells = <0>; 2228 2229 status = "disabled"; 2230 }; 2231 2232 i2c1: i2c@b84000 { 2233 compatible = "qcom,geni-i2c"; 2234 reg = <0 0x00b84000 0 0x4000>; 2235 2236 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2237 2238 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2239 clock-names = "se"; 2240 2241 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2242 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2243 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2244 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2245 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2247 interconnect-names = "qup-core", 2248 "qup-config", 2249 "qup-memory"; 2250 2251 power-domains = <&rpmhpd RPMHPD_CX>; 2252 required-opps = <&rpmhpd_opp_low_svs>; 2253 2254 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2255 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2256 dma-names = "tx", 2257 "rx"; 2258 2259 pinctrl-0 = <&qup_i2c1_data_clk>; 2260 pinctrl-names = "default"; 2261 2262 #address-cells = <1>; 2263 #size-cells = <0>; 2264 2265 status = "disabled"; 2266 }; 2267 2268 spi1: spi@b84000 { 2269 compatible = "qcom,geni-spi"; 2270 reg = <0 0x00b84000 0 0x4000>; 2271 2272 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2273 2274 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2275 clock-names = "se"; 2276 2277 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2278 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2280 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2281 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2282 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2283 interconnect-names = "qup-core", 2284 "qup-config", 2285 "qup-memory"; 2286 2287 power-domains = <&rpmhpd RPMHPD_CX>; 2288 operating-points-v2 = <&qup_opp_table_120mhz>; 2289 2290 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2291 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2292 dma-names = "tx", 2293 "rx"; 2294 2295 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2296 pinctrl-names = "default"; 2297 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 2301 status = "disabled"; 2302 }; 2303 2304 i2c2: i2c@b88000 { 2305 compatible = "qcom,geni-i2c"; 2306 reg = <0 0x00b88000 0 0x4000>; 2307 2308 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2309 2310 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2311 clock-names = "se"; 2312 2313 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2314 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2316 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2317 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2318 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2319 interconnect-names = "qup-core", 2320 "qup-config", 2321 "qup-memory"; 2322 2323 power-domains = <&rpmhpd RPMHPD_CX>; 2324 required-opps = <&rpmhpd_opp_low_svs>; 2325 2326 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2327 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2328 dma-names = "tx", 2329 "rx"; 2330 2331 pinctrl-0 = <&qup_i2c2_data_clk>; 2332 pinctrl-names = "default"; 2333 2334 #address-cells = <1>; 2335 #size-cells = <0>; 2336 2337 status = "disabled"; 2338 }; 2339 2340 uart2: serial@b88000 { 2341 compatible = "qcom,geni-uart"; 2342 reg = <0 0x00b88000 0 0x4000>; 2343 2344 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2345 2346 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2347 clock-names = "se"; 2348 2349 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2350 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2351 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2352 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2353 interconnect-names = "qup-core", 2354 "qup-config"; 2355 2356 power-domains = <&rpmhpd RPMHPD_CX>; 2357 operating-points-v2 = <&qup_opp_table_100mhz>; 2358 2359 pinctrl-0 = <&qup_uart2_default>; 2360 pinctrl-names = "default"; 2361 2362 status = "disabled"; 2363 }; 2364 2365 spi2: spi@b88000 { 2366 compatible = "qcom,geni-spi"; 2367 reg = <0 0x00b88000 0 0x4000>; 2368 2369 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2370 2371 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2372 clock-names = "se"; 2373 2374 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2375 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2376 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2377 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2378 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2379 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2380 interconnect-names = "qup-core", 2381 "qup-config", 2382 "qup-memory"; 2383 2384 power-domains = <&rpmhpd RPMHPD_CX>; 2385 operating-points-v2 = <&qup_opp_table_100mhz>; 2386 2387 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2388 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2389 dma-names = "tx", 2390 "rx"; 2391 2392 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2393 pinctrl-names = "default"; 2394 2395 #address-cells = <1>; 2396 #size-cells = <0>; 2397 2398 status = "disabled"; 2399 }; 2400 2401 i2c3: i2c@b8c000 { 2402 compatible = "qcom,geni-i2c"; 2403 reg = <0 0x00b8c000 0 0x4000>; 2404 2405 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2406 2407 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2408 clock-names = "se"; 2409 2410 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2411 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2412 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2413 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2414 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2415 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2416 interconnect-names = "qup-core", 2417 "qup-config", 2418 "qup-memory"; 2419 2420 power-domains = <&rpmhpd RPMHPD_CX>; 2421 required-opps = <&rpmhpd_opp_low_svs>; 2422 2423 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2424 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2425 dma-names = "tx", 2426 "rx"; 2427 2428 pinctrl-0 = <&qup_i2c3_data_clk>; 2429 pinctrl-names = "default"; 2430 2431 #address-cells = <1>; 2432 #size-cells = <0>; 2433 2434 status = "disabled"; 2435 }; 2436 2437 spi3: spi@b8c000 { 2438 compatible = "qcom,geni-spi"; 2439 reg = <0 0x00b8c000 0 0x4000>; 2440 2441 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2442 2443 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2444 clock-names = "se"; 2445 2446 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2447 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2448 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2449 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2450 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2451 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2452 interconnect-names = "qup-core", 2453 "qup-config", 2454 "qup-memory"; 2455 2456 power-domains = <&rpmhpd RPMHPD_CX>; 2457 operating-points-v2 = <&qup_opp_table_100mhz>; 2458 2459 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2460 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2461 dma-names = "tx", 2462 "rx"; 2463 2464 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2465 pinctrl-names = "default"; 2466 2467 #address-cells = <1>; 2468 #size-cells = <0>; 2469 2470 status = "disabled"; 2471 }; 2472 2473 i2c4: i2c@b90000 { 2474 compatible = "qcom,geni-i2c"; 2475 reg = <0 0x00b90000 0 0x4000>; 2476 2477 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2478 2479 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2480 clock-names = "se"; 2481 2482 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2483 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2484 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2485 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2486 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2487 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2488 interconnect-names = "qup-core", 2489 "qup-config", 2490 "qup-memory"; 2491 2492 power-domains = <&rpmhpd RPMHPD_CX>; 2493 required-opps = <&rpmhpd_opp_low_svs>; 2494 2495 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2496 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2497 dma-names = "tx", 2498 "rx"; 2499 2500 pinctrl-0 = <&qup_i2c4_data_clk>; 2501 pinctrl-names = "default"; 2502 2503 #address-cells = <1>; 2504 #size-cells = <0>; 2505 2506 status = "disabled"; 2507 }; 2508 2509 spi4: spi@b90000 { 2510 compatible = "qcom,geni-spi"; 2511 reg = <0 0x00b90000 0 0x4000>; 2512 2513 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2514 2515 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2516 clock-names = "se"; 2517 2518 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2519 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2521 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2522 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2524 interconnect-names = "qup-core", 2525 "qup-config", 2526 "qup-memory"; 2527 2528 power-domains = <&rpmhpd RPMHPD_CX>; 2529 operating-points-v2 = <&qup_opp_table_100mhz>; 2530 2531 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2532 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2533 dma-names = "tx", 2534 "rx"; 2535 2536 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2537 pinctrl-names = "default"; 2538 2539 #address-cells = <1>; 2540 #size-cells = <0>; 2541 2542 status = "disabled"; 2543 }; 2544 2545 i2c5: i2c@b94000 { 2546 compatible = "qcom,geni-i2c"; 2547 reg = <0 0x00b94000 0 0x4000>; 2548 2549 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2550 2551 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2552 clock-names = "se"; 2553 2554 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2555 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2556 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2557 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2558 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2559 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2560 interconnect-names = "qup-core", 2561 "qup-config", 2562 "qup-memory"; 2563 2564 power-domains = <&rpmhpd RPMHPD_CX>; 2565 required-opps = <&rpmhpd_opp_low_svs>; 2566 2567 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2568 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2569 dma-names = "tx", 2570 "rx"; 2571 2572 pinctrl-0 = <&qup_i2c5_data_clk>; 2573 pinctrl-names = "default"; 2574 2575 #address-cells = <1>; 2576 #size-cells = <0>; 2577 2578 status = "disabled"; 2579 }; 2580 2581 spi5: spi@b94000 { 2582 compatible = "qcom,geni-spi"; 2583 reg = <0 0x00b94000 0 0x4000>; 2584 2585 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2586 2587 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2588 clock-names = "se"; 2589 2590 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2591 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2592 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2593 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2594 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2595 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2596 interconnect-names = "qup-core", 2597 "qup-config", 2598 "qup-memory"; 2599 2600 power-domains = <&rpmhpd RPMHPD_CX>; 2601 operating-points-v2 = <&qup_opp_table_100mhz>; 2602 2603 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2604 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2605 dma-names = "tx", 2606 "rx"; 2607 2608 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2609 pinctrl-names = "default"; 2610 2611 #address-cells = <1>; 2612 #size-cells = <0>; 2613 2614 status = "disabled"; 2615 }; 2616 2617 i2c6: i2c@b98000 { 2618 compatible = "qcom,geni-i2c"; 2619 reg = <0 0x00b98000 0 0x4000>; 2620 2621 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2622 2623 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2624 clock-names = "se"; 2625 2626 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2627 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2629 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2630 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2632 interconnect-names = "qup-core", 2633 "qup-config", 2634 "qup-memory"; 2635 2636 power-domains = <&rpmhpd RPMHPD_CX>; 2637 required-opps = <&rpmhpd_opp_low_svs>; 2638 2639 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2640 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2641 dma-names = "tx", 2642 "rx"; 2643 2644 pinctrl-0 = <&qup_i2c6_data_clk>; 2645 pinctrl-names = "default"; 2646 2647 #address-cells = <1>; 2648 #size-cells = <0>; 2649 2650 status = "disabled"; 2651 }; 2652 2653 spi6: spi@b98000 { 2654 compatible = "qcom,geni-spi"; 2655 reg = <0 0x00b98000 0 0x4000>; 2656 2657 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2658 2659 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2660 clock-names = "se"; 2661 2662 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2663 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2664 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2665 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2666 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2667 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2668 interconnect-names = "qup-core", 2669 "qup-config", 2670 "qup-memory"; 2671 2672 power-domains = <&rpmhpd RPMHPD_CX>; 2673 operating-points-v2 = <&qup_opp_table_100mhz>; 2674 2675 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2676 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2677 dma-names = "tx", 2678 "rx"; 2679 2680 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2681 pinctrl-names = "default"; 2682 2683 #address-cells = <1>; 2684 #size-cells = <0>; 2685 2686 status = "disabled"; 2687 }; 2688 2689 i2c7: i2c@b9c000 { 2690 compatible = "qcom,geni-i2c"; 2691 reg = <0 0x00b9c000 0 0x4000>; 2692 2693 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2694 2695 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2696 clock-names = "se"; 2697 2698 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2699 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2701 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2702 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2703 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2704 interconnect-names = "qup-core", 2705 "qup-config", 2706 "qup-memory"; 2707 2708 power-domains = <&rpmhpd RPMHPD_CX>; 2709 required-opps = <&rpmhpd_opp_low_svs>; 2710 2711 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2712 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2713 dma-names = "tx", 2714 "rx"; 2715 2716 pinctrl-0 = <&qup_i2c7_data_clk>; 2717 pinctrl-names = "default"; 2718 2719 #address-cells = <1>; 2720 #size-cells = <0>; 2721 2722 status = "disabled"; 2723 }; 2724 2725 spi7: spi@b9c000 { 2726 compatible = "qcom,geni-spi"; 2727 reg = <0 0x00b9c000 0 0x4000>; 2728 2729 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2730 2731 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2732 clock-names = "se"; 2733 2734 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2735 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2736 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2737 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2738 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2739 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2740 interconnect-names = "qup-core", 2741 "qup-config", 2742 "qup-memory"; 2743 2744 power-domains = <&rpmhpd RPMHPD_CX>; 2745 operating-points-v2 = <&qup_opp_table_100mhz>; 2746 2747 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2748 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2749 dma-names = "tx", 2750 "rx"; 2751 2752 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2753 pinctrl-names = "default"; 2754 2755 #address-cells = <1>; 2756 #size-cells = <0>; 2757 2758 status = "disabled"; 2759 }; 2760 }; 2761 2762 tsens0: thermal-sensor@c271000 { 2763 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2764 reg = <0 0x0c271000 0 0x1000>, 2765 <0 0x0c222000 0 0x1000>; 2766 2767 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2768 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2769 interrupt-names = "uplow", 2770 "critical"; 2771 2772 #qcom,sensors = <16>; 2773 2774 #thermal-sensor-cells = <1>; 2775 }; 2776 2777 tsens1: thermal-sensor@c272000 { 2778 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2779 reg = <0 0x0c272000 0 0x1000>, 2780 <0 0x0c223000 0 0x1000>; 2781 2782 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2783 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2784 interrupt-names = "uplow", 2785 "critical"; 2786 2787 #qcom,sensors = <16>; 2788 2789 #thermal-sensor-cells = <1>; 2790 }; 2791 2792 tsens2: thermal-sensor@c273000 { 2793 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2794 reg = <0 0x0c273000 0 0x1000>, 2795 <0 0x0c224000 0 0x1000>; 2796 2797 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2798 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2799 interrupt-names = "uplow", 2800 "critical"; 2801 2802 #qcom,sensors = <16>; 2803 2804 #thermal-sensor-cells = <1>; 2805 }; 2806 2807 tsens3: thermal-sensor@c274000 { 2808 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2809 reg = <0 0x0c274000 0 0x1000>, 2810 <0 0x0c225000 0 0x1000>; 2811 2812 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2813 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2814 interrupt-names = "uplow", 2815 "critical"; 2816 2817 #qcom,sensors = <16>; 2818 2819 #thermal-sensor-cells = <1>; 2820 }; 2821 2822 usb_1_ss0_hsphy: phy@fd3000 { 2823 compatible = "qcom,x1e80100-snps-eusb2-phy", 2824 "qcom,sm8550-snps-eusb2-phy"; 2825 reg = <0 0x00fd3000 0 0x154>; 2826 #phy-cells = <0>; 2827 2828 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2829 clock-names = "ref"; 2830 2831 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2832 2833 status = "disabled"; 2834 }; 2835 2836 usb_1_ss0_qmpphy: phy@fd5000 { 2837 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2838 reg = <0 0x00fd5000 0 0x4000>; 2839 2840 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2841 <&rpmhcc RPMH_CXO_CLK>, 2842 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2843 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2844 clock-names = "aux", 2845 "ref", 2846 "com_aux", 2847 "usb3_pipe"; 2848 2849 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2850 2851 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2852 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2853 reset-names = "phy", 2854 "common"; 2855 2856 #clock-cells = <1>; 2857 #phy-cells = <1>; 2858 2859 orientation-switch; 2860 2861 status = "disabled"; 2862 2863 ports { 2864 #address-cells = <1>; 2865 #size-cells = <0>; 2866 2867 port@0 { 2868 reg = <0>; 2869 2870 usb_1_ss0_qmpphy_out: endpoint { 2871 }; 2872 }; 2873 2874 port@1 { 2875 reg = <1>; 2876 2877 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2878 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2879 }; 2880 }; 2881 2882 port@2 { 2883 reg = <2>; 2884 2885 usb_1_ss0_qmpphy_dp_in: endpoint { 2886 remote-endpoint = <&mdss_dp0_out>; 2887 }; 2888 }; 2889 }; 2890 }; 2891 2892 usb_1_ss1_hsphy: phy@fd9000 { 2893 compatible = "qcom,x1e80100-snps-eusb2-phy", 2894 "qcom,sm8550-snps-eusb2-phy"; 2895 reg = <0 0x00fd9000 0 0x154>; 2896 #phy-cells = <0>; 2897 2898 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2899 clock-names = "ref"; 2900 2901 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2902 2903 status = "disabled"; 2904 }; 2905 2906 usb_1_ss1_qmpphy: phy@fda000 { 2907 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2908 reg = <0 0x00fda000 0 0x4000>; 2909 2910 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2911 <&rpmhcc RPMH_CXO_CLK>, 2912 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2913 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2914 clock-names = "aux", 2915 "ref", 2916 "com_aux", 2917 "usb3_pipe"; 2918 2919 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2920 2921 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2922 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2923 reset-names = "phy", 2924 "common"; 2925 2926 #clock-cells = <1>; 2927 #phy-cells = <1>; 2928 2929 orientation-switch; 2930 2931 status = "disabled"; 2932 2933 ports { 2934 #address-cells = <1>; 2935 #size-cells = <0>; 2936 2937 port@0 { 2938 reg = <0>; 2939 2940 usb_1_ss1_qmpphy_out: endpoint { 2941 }; 2942 }; 2943 2944 port@1 { 2945 reg = <1>; 2946 2947 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2948 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2949 }; 2950 }; 2951 2952 port@2 { 2953 reg = <2>; 2954 2955 usb_1_ss1_qmpphy_dp_in: endpoint { 2956 remote-endpoint = <&mdss_dp1_out>; 2957 }; 2958 }; 2959 }; 2960 }; 2961 2962 usb_1_ss2_hsphy: phy@fde000 { 2963 compatible = "qcom,x1e80100-snps-eusb2-phy", 2964 "qcom,sm8550-snps-eusb2-phy"; 2965 reg = <0 0x00fde000 0 0x154>; 2966 #phy-cells = <0>; 2967 2968 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2969 clock-names = "ref"; 2970 2971 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2972 2973 status = "disabled"; 2974 }; 2975 2976 usb_1_ss2_qmpphy: phy@fdf000 { 2977 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2978 reg = <0 0x00fdf000 0 0x4000>; 2979 2980 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2981 <&rpmhcc RPMH_CXO_CLK>, 2982 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2983 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2984 clock-names = "aux", 2985 "ref", 2986 "com_aux", 2987 "usb3_pipe"; 2988 2989 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2990 2991 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2992 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2993 reset-names = "phy", 2994 "common"; 2995 2996 #clock-cells = <1>; 2997 #phy-cells = <1>; 2998 2999 orientation-switch; 3000 3001 status = "disabled"; 3002 3003 ports { 3004 #address-cells = <1>; 3005 #size-cells = <0>; 3006 3007 port@0 { 3008 reg = <0>; 3009 3010 usb_1_ss2_qmpphy_out: endpoint { 3011 }; 3012 }; 3013 3014 port@1 { 3015 reg = <1>; 3016 3017 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 3018 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 3019 }; 3020 }; 3021 3022 port@2 { 3023 reg = <2>; 3024 3025 usb_1_ss2_qmpphy_dp_in: endpoint { 3026 remote-endpoint = <&mdss_dp2_out>; 3027 }; 3028 }; 3029 }; 3030 }; 3031 3032 cnoc_main: interconnect@1500000 { 3033 compatible = "qcom,x1e80100-cnoc-main"; 3034 reg = <0 0x01500000 0 0x14400>; 3035 3036 qcom,bcm-voters = <&apps_bcm_voter>; 3037 3038 #interconnect-cells = <2>; 3039 }; 3040 3041 config_noc: interconnect@1600000 { 3042 compatible = "qcom,x1e80100-cnoc-cfg"; 3043 reg = <0 0x01600000 0 0x6600>; 3044 3045 qcom,bcm-voters = <&apps_bcm_voter>; 3046 3047 #interconnect-cells = <2>; 3048 }; 3049 3050 system_noc: interconnect@1680000 { 3051 compatible = "qcom,x1e80100-system-noc"; 3052 reg = <0 0x01680000 0 0x1c080>; 3053 3054 qcom,bcm-voters = <&apps_bcm_voter>; 3055 3056 #interconnect-cells = <2>; 3057 }; 3058 3059 pcie_south_anoc: interconnect@16c0000 { 3060 compatible = "qcom,x1e80100-pcie-south-anoc"; 3061 reg = <0 0x016c0000 0 0xd080>; 3062 3063 qcom,bcm-voters = <&apps_bcm_voter>; 3064 3065 #interconnect-cells = <2>; 3066 }; 3067 3068 pcie_center_anoc: interconnect@16d0000 { 3069 compatible = "qcom,x1e80100-pcie-center-anoc"; 3070 reg = <0 0x016d0000 0 0x7000>; 3071 3072 qcom,bcm-voters = <&apps_bcm_voter>; 3073 3074 #interconnect-cells = <2>; 3075 }; 3076 3077 aggre1_noc: interconnect@16e0000 { 3078 compatible = "qcom,x1e80100-aggre1-noc"; 3079 reg = <0 0x016e0000 0 0x14400>; 3080 3081 qcom,bcm-voters = <&apps_bcm_voter>; 3082 3083 #interconnect-cells = <2>; 3084 }; 3085 3086 aggre2_noc: interconnect@1700000 { 3087 compatible = "qcom,x1e80100-aggre2-noc"; 3088 reg = <0 0x01700000 0 0x1c400>; 3089 3090 qcom,bcm-voters = <&apps_bcm_voter>; 3091 3092 #interconnect-cells = <2>; 3093 }; 3094 3095 pcie_north_anoc: interconnect@1740000 { 3096 compatible = "qcom,x1e80100-pcie-north-anoc"; 3097 reg = <0 0x01740000 0 0x9080>; 3098 3099 qcom,bcm-voters = <&apps_bcm_voter>; 3100 3101 #interconnect-cells = <2>; 3102 }; 3103 3104 usb_center_anoc: interconnect@1750000 { 3105 compatible = "qcom,x1e80100-usb-center-anoc"; 3106 reg = <0 0x01750000 0 0x8800>; 3107 3108 qcom,bcm-voters = <&apps_bcm_voter>; 3109 3110 #interconnect-cells = <2>; 3111 }; 3112 3113 usb_north_anoc: interconnect@1760000 { 3114 compatible = "qcom,x1e80100-usb-north-anoc"; 3115 reg = <0 0x01760000 0 0x7080>; 3116 3117 qcom,bcm-voters = <&apps_bcm_voter>; 3118 3119 #interconnect-cells = <2>; 3120 }; 3121 3122 usb_south_anoc: interconnect@1770000 { 3123 compatible = "qcom,x1e80100-usb-south-anoc"; 3124 reg = <0 0x01770000 0 0xf080>; 3125 3126 qcom,bcm-voters = <&apps_bcm_voter>; 3127 3128 #interconnect-cells = <2>; 3129 }; 3130 3131 mmss_noc: interconnect@1780000 { 3132 compatible = "qcom,x1e80100-mmss-noc"; 3133 reg = <0 0x01780000 0 0x5B800>; 3134 3135 qcom,bcm-voters = <&apps_bcm_voter>; 3136 3137 #interconnect-cells = <2>; 3138 }; 3139 3140 pcie3: pcie@1bd0000 { 3141 device_type = "pci"; 3142 compatible = "qcom,pcie-x1e80100"; 3143 reg = <0x0 0x01bd0000 0x0 0x3000>, 3144 <0x0 0x78000000 0x0 0xf20>, 3145 <0x0 0x78000f40 0x0 0xa8>, 3146 <0x0 0x78001000 0x0 0x1000>, 3147 <0x0 0x78100000 0x0 0x100000>, 3148 <0x0 0x01bd3000 0x0 0x1000>; 3149 reg-names = "parf", 3150 "dbi", 3151 "elbi", 3152 "atu", 3153 "config", 3154 "mhi"; 3155 #address-cells = <3>; 3156 #size-cells = <2>; 3157 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, 3158 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, 3159 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3160 bus-range = <0x00 0xff>; 3161 3162 dma-coherent; 3163 3164 linux,pci-domain = <3>; 3165 num-lanes = <8>; 3166 3167 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3176 interrupt-names = "msi0", 3177 "msi1", 3178 "msi2", 3179 "msi3", 3180 "msi4", 3181 "msi5", 3182 "msi6", 3183 "msi7", 3184 "global"; 3185 3186 #interrupt-cells = <1>; 3187 interrupt-map-mask = <0 0 0 0x7>; 3188 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 3189 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 3190 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3191 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3192 3193 clocks = <&gcc GCC_PCIE_3_AUX_CLK>, 3194 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3195 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 3196 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 3197 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 3198 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3199 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3200 clock-names = "aux", 3201 "cfg", 3202 "bus_master", 3203 "bus_slave", 3204 "slave_q2a", 3205 "noc_aggr", 3206 "cnoc_sf_axi"; 3207 3208 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 3209 assigned-clock-rates = <19200000>; 3210 3211 interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS 3212 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3213 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3214 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 3215 interconnect-names = "pcie-mem", 3216 "cpu-pcie"; 3217 3218 resets = <&gcc GCC_PCIE_3_BCR>, 3219 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; 3220 reset-names = "pci", 3221 "link_down"; 3222 3223 power-domains = <&gcc GCC_PCIE_3_GDSC>; 3224 3225 phys = <&pcie3_phy>; 3226 phy-names = "pciephy"; 3227 3228 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 3229 0x5555 0x5555 0x5555 0x5555>; 3230 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; 3231 3232 operating-points-v2 = <&pcie3_opp_table>; 3233 3234 status = "disabled"; 3235 3236 pcie3_opp_table: opp-table { 3237 compatible = "operating-points-v2"; 3238 3239 /* GEN 1 x1 */ 3240 opp-2500000 { 3241 opp-hz = /bits/ 64 <2500000>; 3242 required-opps = <&rpmhpd_opp_low_svs>; 3243 opp-peak-kBps = <250000 1>; 3244 }; 3245 3246 /* GEN 1 x2 and GEN 2 x1 */ 3247 opp-5000000 { 3248 opp-hz = /bits/ 64 <5000000>; 3249 required-opps = <&rpmhpd_opp_low_svs>; 3250 opp-peak-kBps = <500000 1>; 3251 }; 3252 3253 /* GEN 1 x4 and GEN 2 x2 */ 3254 opp-10000000 { 3255 opp-hz = /bits/ 64 <10000000>; 3256 required-opps = <&rpmhpd_opp_low_svs>; 3257 opp-peak-kBps = <1000000 1>; 3258 }; 3259 3260 /* GEN 1 x8 and GEN 2 x4 */ 3261 opp-20000000 { 3262 opp-hz = /bits/ 64 <20000000>; 3263 required-opps = <&rpmhpd_opp_low_svs>; 3264 opp-peak-kBps = <2000000 1>; 3265 }; 3266 3267 /* GEN 2 x8 */ 3268 opp-40000000 { 3269 opp-hz = /bits/ 64 <40000000>; 3270 required-opps = <&rpmhpd_opp_low_svs>; 3271 opp-peak-kBps = <4000000 1>; 3272 }; 3273 3274 /* GEN 3 x1 */ 3275 opp-8000000 { 3276 opp-hz = /bits/ 64 <8000000>; 3277 required-opps = <&rpmhpd_opp_svs>; 3278 opp-peak-kBps = <984500 1>; 3279 }; 3280 3281 /* GEN 3 x2 and GEN 4 x1 */ 3282 opp-16000000 { 3283 opp-hz = /bits/ 64 <16000000>; 3284 required-opps = <&rpmhpd_opp_svs>; 3285 opp-peak-kBps = <1969000 1>; 3286 }; 3287 3288 /* GEN 3 x4 and GEN 4 x2 */ 3289 opp-32000000 { 3290 opp-hz = /bits/ 64 <32000000>; 3291 required-opps = <&rpmhpd_opp_svs>; 3292 opp-peak-kBps = <3938000 1>; 3293 }; 3294 3295 /* GEN 3 x8 and GEN 4 x4 */ 3296 opp-64000000 { 3297 opp-hz = /bits/ 64 <64000000>; 3298 required-opps = <&rpmhpd_opp_svs>; 3299 opp-peak-kBps = <7876000 1>; 3300 }; 3301 3302 /* GEN 4 x8 */ 3303 opp-128000000 { 3304 opp-hz = /bits/ 64 <128000000>; 3305 required-opps = <&rpmhpd_opp_svs>; 3306 opp-peak-kBps = <15753000 1>; 3307 }; 3308 }; 3309 }; 3310 3311 pcie3_phy: phy@1be0000 { 3312 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; 3313 reg = <0 0x01be0000 0 0x10000>; 3314 3315 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 3316 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3317 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 3318 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 3319 <&gcc GCC_PCIE_3_PIPE_CLK>, 3320 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 3321 clock-names = "aux", 3322 "cfg_ahb", 3323 "ref", 3324 "rchng", 3325 "pipe", 3326 "pipediv2"; 3327 3328 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 3329 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 3330 reset-names = "phy", 3331 "phy_nocsr"; 3332 3333 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 3334 assigned-clock-rates = <100000000>; 3335 3336 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 3337 3338 #clock-cells = <0>; 3339 clock-output-names = "pcie3_pipe_clk"; 3340 3341 #phy-cells = <0>; 3342 3343 status = "disabled"; 3344 }; 3345 3346 pcie6a: pci@1bf8000 { 3347 device_type = "pci"; 3348 compatible = "qcom,pcie-x1e80100"; 3349 reg = <0 0x01bf8000 0 0x3000>, 3350 <0 0x70000000 0 0xf20>, 3351 <0 0x70000f40 0 0xa8>, 3352 <0 0x70001000 0 0x1000>, 3353 <0 0x70100000 0 0x100000>, 3354 <0 0x01bfb000 0 0x1000>; 3355 reg-names = "parf", 3356 "dbi", 3357 "elbi", 3358 "atu", 3359 "config", 3360 "mhi"; 3361 #address-cells = <3>; 3362 #size-cells = <2>; 3363 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3364 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 3365 bus-range = <0x00 0xff>; 3366 3367 dma-coherent; 3368 3369 linux,pci-domain = <6>; 3370 num-lanes = <4>; 3371 3372 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3373 3374 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>; 3383 interrupt-names = "msi0", 3384 "msi1", 3385 "msi2", 3386 "msi3", 3387 "msi4", 3388 "msi5", 3389 "msi6", 3390 "msi7", 3391 "global"; 3392 3393 #interrupt-cells = <1>; 3394 interrupt-map-mask = <0 0 0 0x7>; 3395 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, 3396 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, 3397 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, 3398 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; 3399 3400 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 3401 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3402 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 3403 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 3404 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 3405 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 3406 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 3407 clock-names = "aux", 3408 "cfg", 3409 "bus_master", 3410 "bus_slave", 3411 "slave_q2a", 3412 "noc_aggr", 3413 "cnoc_sf_axi"; 3414 3415 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 3416 assigned-clock-rates = <19200000>; 3417 3418 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 3419 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3421 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>; 3422 interconnect-names = "pcie-mem", 3423 "cpu-pcie"; 3424 3425 resets = <&gcc GCC_PCIE_6A_BCR>, 3426 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 3427 reset-names = "pci", 3428 "link_down"; 3429 3430 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 3431 required-opps = <&rpmhpd_opp_nom>; 3432 3433 phys = <&pcie6a_phy>; 3434 phy-names = "pciephy"; 3435 3436 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3437 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3438 3439 status = "disabled"; 3440 }; 3441 3442 pcie6a_phy: phy@1bfc000 { 3443 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3444 reg = <0 0x01bfc000 0 0x2000>, 3445 <0 0x01bfe000 0 0x2000>; 3446 3447 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3448 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3449 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3450 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3451 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3452 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3453 clock-names = "aux", 3454 "cfg_ahb", 3455 "ref", 3456 "rchng", 3457 "pipe", 3458 "pipediv2"; 3459 3460 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3461 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3462 reset-names = "phy", 3463 "phy_nocsr"; 3464 3465 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3466 assigned-clock-rates = <100000000>; 3467 3468 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3469 3470 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3471 3472 #clock-cells = <0>; 3473 clock-output-names = "pcie6a_pipe_clk"; 3474 3475 #phy-cells = <0>; 3476 3477 status = "disabled"; 3478 }; 3479 3480 pcie5: pci@1c00000 { 3481 device_type = "pci"; 3482 compatible = "qcom,pcie-x1e80100"; 3483 reg = <0 0x01c00000 0 0x3000>, 3484 <0 0x7e000000 0 0xf1d>, 3485 <0 0x7e000f40 0 0xa8>, 3486 <0 0x7e001000 0 0x1000>, 3487 <0 0x7e100000 0 0x100000>, 3488 <0 0x01c03000 0 0x1000>; 3489 reg-names = "parf", 3490 "dbi", 3491 "elbi", 3492 "atu", 3493 "config", 3494 "mhi"; 3495 #address-cells = <3>; 3496 #size-cells = <2>; 3497 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3498 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3499 bus-range = <0x00 0xff>; 3500 3501 dma-coherent; 3502 3503 linux,pci-domain = <5>; 3504 num-lanes = <2>; 3505 3506 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 3515 interrupt-names = "msi0", 3516 "msi1", 3517 "msi2", 3518 "msi3", 3519 "msi4", 3520 "msi5", 3521 "msi6", 3522 "msi7", 3523 "global"; 3524 3525 #interrupt-cells = <1>; 3526 interrupt-map-mask = <0 0 0 0x7>; 3527 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, 3528 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>, 3529 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>, 3530 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>; 3531 3532 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3533 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3534 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3535 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3536 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3537 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3538 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3539 clock-names = "aux", 3540 "cfg", 3541 "bus_master", 3542 "bus_slave", 3543 "slave_q2a", 3544 "noc_aggr", 3545 "cnoc_sf_axi"; 3546 3547 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3548 assigned-clock-rates = <19200000>; 3549 3550 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3551 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3553 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>; 3554 interconnect-names = "pcie-mem", 3555 "cpu-pcie"; 3556 3557 resets = <&gcc GCC_PCIE_5_BCR>, 3558 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3559 reset-names = "pci", 3560 "link_down"; 3561 3562 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3563 required-opps = <&rpmhpd_opp_nom>; 3564 3565 phys = <&pcie5_phy>; 3566 phy-names = "pciephy"; 3567 3568 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3569 3570 status = "disabled"; 3571 }; 3572 3573 pcie5_phy: phy@1c06000 { 3574 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3575 reg = <0 0x01c06000 0 0x2000>; 3576 3577 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3578 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3579 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3580 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3581 <&gcc GCC_PCIE_5_PIPE_CLK>, 3582 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3583 clock-names = "aux", 3584 "cfg_ahb", 3585 "ref", 3586 "rchng", 3587 "pipe", 3588 "pipediv2"; 3589 3590 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3591 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3592 reset-names = "phy", 3593 "phy_nocsr"; 3594 3595 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3596 assigned-clock-rates = <100000000>; 3597 3598 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3599 3600 #clock-cells = <0>; 3601 clock-output-names = "pcie5_pipe_clk"; 3602 3603 #phy-cells = <0>; 3604 3605 status = "disabled"; 3606 }; 3607 3608 pcie4: pci@1c08000 { 3609 device_type = "pci"; 3610 compatible = "qcom,pcie-x1e80100"; 3611 reg = <0 0x01c08000 0 0x3000>, 3612 <0 0x7c000000 0 0xf1d>, 3613 <0 0x7c000f40 0 0xa8>, 3614 <0 0x7c001000 0 0x1000>, 3615 <0 0x7c100000 0 0x100000>, 3616 <0 0x01c0b000 0 0x1000>; 3617 reg-names = "parf", 3618 "dbi", 3619 "elbi", 3620 "atu", 3621 "config", 3622 "mhi"; 3623 #address-cells = <3>; 3624 #size-cells = <2>; 3625 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3626 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3627 bus-range = <0x00 0xff>; 3628 3629 dma-coherent; 3630 3631 linux,pci-domain = <4>; 3632 num-lanes = <2>; 3633 3634 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 3635 3636 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 3645 interrupt-names = "msi0", 3646 "msi1", 3647 "msi2", 3648 "msi3", 3649 "msi4", 3650 "msi5", 3651 "msi6", 3652 "msi7", 3653 "global"; 3654 3655 #interrupt-cells = <1>; 3656 interrupt-map-mask = <0 0 0 0x7>; 3657 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 3658 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 3659 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 3660 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 3661 3662 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3663 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3664 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3665 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3666 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3667 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3668 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3669 clock-names = "aux", 3670 "cfg", 3671 "bus_master", 3672 "bus_slave", 3673 "slave_q2a", 3674 "noc_aggr", 3675 "cnoc_sf_axi"; 3676 3677 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3678 assigned-clock-rates = <19200000>; 3679 3680 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3682 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3683 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 3684 interconnect-names = "pcie-mem", 3685 "cpu-pcie"; 3686 3687 resets = <&gcc GCC_PCIE_4_BCR>, 3688 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3689 reset-names = "pci", 3690 "link_down"; 3691 3692 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3693 required-opps = <&rpmhpd_opp_nom>; 3694 3695 phys = <&pcie4_phy>; 3696 phy-names = "pciephy"; 3697 3698 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3699 3700 status = "disabled"; 3701 3702 pcie4_port0: pcie@0 { 3703 device_type = "pci"; 3704 reg = <0x0 0x0 0x0 0x0 0x0>; 3705 bus-range = <0x01 0xff>; 3706 3707 #address-cells = <3>; 3708 #size-cells = <2>; 3709 ranges; 3710 }; 3711 }; 3712 3713 pcie4_phy: phy@1c0e000 { 3714 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3715 reg = <0 0x01c0e000 0 0x2000>; 3716 3717 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3718 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3719 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3720 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3721 <&gcc GCC_PCIE_4_PIPE_CLK>, 3722 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3723 clock-names = "aux", 3724 "cfg_ahb", 3725 "ref", 3726 "rchng", 3727 "pipe", 3728 "pipediv2"; 3729 3730 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 3731 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 3732 reset-names = "phy", 3733 "phy_nocsr"; 3734 3735 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3736 assigned-clock-rates = <100000000>; 3737 3738 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3739 3740 #clock-cells = <0>; 3741 clock-output-names = "pcie4_pipe_clk"; 3742 3743 #phy-cells = <0>; 3744 3745 status = "disabled"; 3746 }; 3747 3748 tcsr_mutex: hwlock@1f40000 { 3749 compatible = "qcom,tcsr-mutex"; 3750 reg = <0 0x01f40000 0 0x20000>; 3751 #hwlock-cells = <1>; 3752 }; 3753 3754 tcsr: clock-controller@1fc0000 { 3755 compatible = "qcom,x1e80100-tcsr", "syscon"; 3756 reg = <0 0x01fc0000 0 0x30000>; 3757 clocks = <&rpmhcc RPMH_CXO_CLK>; 3758 #clock-cells = <1>; 3759 #reset-cells = <1>; 3760 }; 3761 3762 gpu: gpu@3d00000 { 3763 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3764 reg = <0x0 0x03d00000 0x0 0x40000>, 3765 <0x0 0x03d9e000 0x0 0x1000>, 3766 <0x0 0x03d61000 0x0 0x800>; 3767 3768 reg-names = "kgsl_3d0_reg_memory", 3769 "cx_mem", 3770 "cx_dbgc"; 3771 3772 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3773 3774 iommus = <&adreno_smmu 0 0x0>, 3775 <&adreno_smmu 1 0x0>; 3776 3777 operating-points-v2 = <&gpu_opp_table>; 3778 3779 qcom,gmu = <&gmu>; 3780 #cooling-cells = <2>; 3781 3782 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3783 interconnect-names = "gfx-mem"; 3784 3785 status = "disabled"; 3786 3787 gpu_zap_shader: zap-shader { 3788 memory-region = <&gpu_microcode_mem>; 3789 }; 3790 3791 gpu_opp_table: opp-table { 3792 compatible = "operating-points-v2-adreno", "operating-points-v2"; 3793 3794 opp-1250000000 { 3795 opp-hz = /bits/ 64 <1250000000>; 3796 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3797 opp-peak-kBps = <16500000>; 3798 qcom,opp-acd-level = <0xa82a5ffd>; 3799 }; 3800 3801 opp-1175000000 { 3802 opp-hz = /bits/ 64 <1175000000>; 3803 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 3804 opp-peak-kBps = <14398438>; 3805 qcom,opp-acd-level = <0xa82a5ffd>; 3806 }; 3807 3808 opp-1100000000 { 3809 opp-hz = /bits/ 64 <1100000000>; 3810 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3811 opp-peak-kBps = <14398438>; 3812 qcom,opp-acd-level = <0xa82a5ffd>; 3813 }; 3814 3815 opp-1000000000 { 3816 opp-hz = /bits/ 64 <1000000000>; 3817 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3818 opp-peak-kBps = <14398438>; 3819 qcom,opp-acd-level = <0xa82b5ffd>; 3820 }; 3821 3822 opp-925000000 { 3823 opp-hz = /bits/ 64 <925000000>; 3824 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3825 opp-peak-kBps = <14398438>; 3826 qcom,opp-acd-level = <0xa82b5ffd>; 3827 }; 3828 3829 opp-800000000 { 3830 opp-hz = /bits/ 64 <800000000>; 3831 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3832 opp-peak-kBps = <12449219>; 3833 qcom,opp-acd-level = <0xa82c5ffd>; 3834 }; 3835 3836 opp-744000000 { 3837 opp-hz = /bits/ 64 <744000000>; 3838 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3839 opp-peak-kBps = <10687500>; 3840 qcom,opp-acd-level = <0x882e5ffd>; 3841 }; 3842 3843 opp-687000000 { 3844 opp-hz = /bits/ 64 <687000000>; 3845 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3846 opp-peak-kBps = <8171875>; 3847 qcom,opp-acd-level = <0x882e5ffd>; 3848 }; 3849 3850 opp-550000000 { 3851 opp-hz = /bits/ 64 <550000000>; 3852 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3853 opp-peak-kBps = <6074219>; 3854 qcom,opp-acd-level = <0xc0285ffd>; 3855 }; 3856 3857 opp-390000000 { 3858 opp-hz = /bits/ 64 <390000000>; 3859 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3860 opp-peak-kBps = <3000000>; 3861 qcom,opp-acd-level = <0xc0285ffd>; 3862 }; 3863 3864 opp-300000000 { 3865 opp-hz = /bits/ 64 <300000000>; 3866 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3867 opp-peak-kBps = <2136719>; 3868 qcom,opp-acd-level = <0xc02b5ffd>; 3869 }; 3870 }; 3871 }; 3872 3873 gmu: gmu@3d6a000 { 3874 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 3875 reg = <0x0 0x03d6a000 0x0 0x35000>, 3876 <0x0 0x03d50000 0x0 0x10000>, 3877 <0x0 0x0b280000 0x0 0x10000>; 3878 reg-names = "gmu", "rscc", "gmu_pdc"; 3879 3880 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3882 interrupt-names = "hfi", "gmu"; 3883 3884 clocks = <&gpucc GPU_CC_AHB_CLK>, 3885 <&gpucc GPU_CC_CX_GMU_CLK>, 3886 <&gpucc GPU_CC_CXO_CLK>, 3887 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3888 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3889 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3890 <&gpucc GPU_CC_DEMET_CLK>; 3891 clock-names = "ahb", 3892 "gmu", 3893 "cxo", 3894 "axi", 3895 "memnoc", 3896 "hub", 3897 "demet"; 3898 3899 power-domains = <&gpucc GPU_CX_GDSC>, 3900 <&gpucc GPU_GX_GDSC>; 3901 power-domain-names = "cx", 3902 "gx"; 3903 3904 iommus = <&adreno_smmu 5 0x0>; 3905 3906 qcom,qmp = <&aoss_qmp>; 3907 3908 operating-points-v2 = <&gmu_opp_table>; 3909 3910 gmu_opp_table: opp-table { 3911 compatible = "operating-points-v2"; 3912 3913 opp-550000000 { 3914 opp-hz = /bits/ 64 <550000000>; 3915 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3916 }; 3917 3918 opp-220000000 { 3919 opp-hz = /bits/ 64 <220000000>; 3920 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3921 }; 3922 }; 3923 }; 3924 3925 gpucc: clock-controller@3d90000 { 3926 compatible = "qcom,x1e80100-gpucc"; 3927 reg = <0 0x03d90000 0 0xa000>; 3928 clocks = <&bi_tcxo_div2>, 3929 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 3930 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 3931 #clock-cells = <1>; 3932 #reset-cells = <1>; 3933 #power-domain-cells = <1>; 3934 }; 3935 3936 adreno_smmu: iommu@3da0000 { 3937 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 3938 "qcom,smmu-500", "arm,mmu-500"; 3939 reg = <0x0 0x03da0000 0x0 0x40000>; 3940 #iommu-cells = <2>; 3941 #global-interrupts = <1>; 3942 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3943 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 3968 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3969 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3970 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3971 <&gpucc GPU_CC_AHB_CLK>; 3972 clock-names = "hlos", 3973 "bus", 3974 "iface", 3975 "ahb"; 3976 power-domains = <&gpucc GPU_CX_GDSC>; 3977 dma-coherent; 3978 }; 3979 3980 gem_noc: interconnect@26400000 { 3981 compatible = "qcom,x1e80100-gem-noc"; 3982 reg = <0 0x26400000 0 0x311200>; 3983 3984 qcom,bcm-voters = <&apps_bcm_voter>; 3985 3986 #interconnect-cells = <2>; 3987 }; 3988 3989 nsp_noc: interconnect@320c0000 { 3990 compatible = "qcom,x1e80100-nsp-noc"; 3991 reg = <0 0x320C0000 0 0xe080>; 3992 3993 qcom,bcm-voters = <&apps_bcm_voter>; 3994 3995 #interconnect-cells = <2>; 3996 }; 3997 3998 remoteproc_adsp: remoteproc@6800000 { 3999 compatible = "qcom,x1e80100-adsp-pas"; 4000 reg = <0x0 0x06800000 0x0 0x10000>; 4001 4002 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4003 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4004 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4005 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4006 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4007 interrupt-names = "wdog", 4008 "fatal", 4009 "ready", 4010 "handover", 4011 "stop-ack"; 4012 4013 clocks = <&rpmhcc RPMH_CXO_CLK>; 4014 clock-names = "xo"; 4015 4016 power-domains = <&rpmhpd RPMHPD_LCX>, 4017 <&rpmhpd RPMHPD_LMX>; 4018 power-domain-names = "lcx", 4019 "lmx"; 4020 4021 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4022 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4023 4024 memory-region = <&adspslpi_mem>, 4025 <&q6_adsp_dtb_mem>; 4026 4027 qcom,qmp = <&aoss_qmp>; 4028 4029 qcom,smem-states = <&smp2p_adsp_out 0>; 4030 qcom,smem-state-names = "stop"; 4031 4032 status = "disabled"; 4033 4034 glink-edge { 4035 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4036 IPCC_MPROC_SIGNAL_GLINK_QMP 4037 IRQ_TYPE_EDGE_RISING>; 4038 mboxes = <&ipcc IPCC_CLIENT_LPASS 4039 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4040 4041 label = "lpass"; 4042 qcom,remote-pid = <2>; 4043 4044 fastrpc { 4045 compatible = "qcom,fastrpc"; 4046 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4047 label = "adsp"; 4048 qcom,non-secure-domain; 4049 #address-cells = <1>; 4050 #size-cells = <0>; 4051 4052 compute-cb@3 { 4053 compatible = "qcom,fastrpc-compute-cb"; 4054 reg = <3>; 4055 iommus = <&apps_smmu 0x1003 0x80>, 4056 <&apps_smmu 0x1063 0x0>; 4057 dma-coherent; 4058 }; 4059 4060 compute-cb@4 { 4061 compatible = "qcom,fastrpc-compute-cb"; 4062 reg = <4>; 4063 iommus = <&apps_smmu 0x1004 0x80>, 4064 <&apps_smmu 0x1064 0x0>; 4065 dma-coherent; 4066 }; 4067 4068 compute-cb@5 { 4069 compatible = "qcom,fastrpc-compute-cb"; 4070 reg = <5>; 4071 iommus = <&apps_smmu 0x1005 0x80>, 4072 <&apps_smmu 0x1065 0x0>; 4073 dma-coherent; 4074 }; 4075 4076 compute-cb@6 { 4077 compatible = "qcom,fastrpc-compute-cb"; 4078 reg = <6>; 4079 iommus = <&apps_smmu 0x1006 0x80>, 4080 <&apps_smmu 0x1066 0x0>; 4081 dma-coherent; 4082 }; 4083 4084 compute-cb@7 { 4085 compatible = "qcom,fastrpc-compute-cb"; 4086 reg = <7>; 4087 iommus = <&apps_smmu 0x1007 0x80>, 4088 <&apps_smmu 0x1067 0x0>; 4089 dma-coherent; 4090 }; 4091 }; 4092 4093 gpr { 4094 compatible = "qcom,gpr"; 4095 qcom,glink-channels = "adsp_apps"; 4096 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4097 qcom,intents = <512 20>; 4098 #address-cells = <1>; 4099 #size-cells = <0>; 4100 4101 q6apm: service@1 { 4102 compatible = "qcom,q6apm"; 4103 reg = <GPR_APM_MODULE_IID>; 4104 #sound-dai-cells = <0>; 4105 qcom,protection-domain = "avs/audio", 4106 "msm/adsp/audio_pd"; 4107 4108 q6apmbedai: bedais { 4109 compatible = "qcom,q6apm-lpass-dais"; 4110 #sound-dai-cells = <1>; 4111 }; 4112 4113 q6apmdai: dais { 4114 compatible = "qcom,q6apm-dais"; 4115 iommus = <&apps_smmu 0x1001 0x80>, 4116 <&apps_smmu 0x1061 0x0>; 4117 }; 4118 }; 4119 4120 q6prm: service@2 { 4121 compatible = "qcom,q6prm"; 4122 reg = <GPR_PRM_MODULE_IID>; 4123 qcom,protection-domain = "avs/audio", 4124 "msm/adsp/audio_pd"; 4125 4126 q6prmcc: clock-controller { 4127 compatible = "qcom,q6prm-lpass-clocks"; 4128 #clock-cells = <2>; 4129 }; 4130 }; 4131 }; 4132 }; 4133 }; 4134 4135 lpass_wsa2macro: codec@6aa0000 { 4136 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4137 reg = <0 0x06aa0000 0 0x1000>; 4138 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4139 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4140 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4141 <&lpass_vamacro>; 4142 clock-names = "mclk", 4143 "macro", 4144 "dcodec", 4145 "fsgen"; 4146 4147 #clock-cells = <0>; 4148 clock-output-names = "wsa2-mclk"; 4149 #sound-dai-cells = <1>; 4150 sound-name-prefix = "WSA2"; 4151 }; 4152 4153 swr3: soundwire@6ab0000 { 4154 compatible = "qcom,soundwire-v2.0.0"; 4155 reg = <0 0x06ab0000 0 0x10000>; 4156 clocks = <&lpass_wsa2macro>; 4157 clock-names = "iface"; 4158 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4159 label = "WSA2"; 4160 4161 pinctrl-0 = <&wsa2_swr_active>; 4162 pinctrl-names = "default"; 4163 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 4164 reset-names = "swr_audio_cgcr"; 4165 4166 qcom,din-ports = <4>; 4167 qcom,dout-ports = <9>; 4168 4169 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4170 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4171 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4172 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4173 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4174 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4175 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4176 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4177 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4178 4179 #address-cells = <2>; 4180 #size-cells = <0>; 4181 #sound-dai-cells = <1>; 4182 status = "disabled"; 4183 }; 4184 4185 lpass_rxmacro: codec@6ac0000 { 4186 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4187 reg = <0 0x06ac0000 0 0x1000>; 4188 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4189 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4190 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4191 <&lpass_vamacro>; 4192 clock-names = "mclk", 4193 "macro", 4194 "dcodec", 4195 "fsgen"; 4196 4197 #clock-cells = <0>; 4198 clock-output-names = "mclk"; 4199 #sound-dai-cells = <1>; 4200 }; 4201 4202 swr1: soundwire@6ad0000 { 4203 compatible = "qcom,soundwire-v2.0.0"; 4204 reg = <0 0x06ad0000 0 0x10000>; 4205 clocks = <&lpass_rxmacro>; 4206 clock-names = "iface"; 4207 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4208 label = "RX"; 4209 4210 pinctrl-0 = <&rx_swr_active>; 4211 pinctrl-names = "default"; 4212 4213 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 4214 reset-names = "swr_audio_cgcr"; 4215 qcom,din-ports = <1>; 4216 qcom,dout-ports = <11>; 4217 4218 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4219 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4220 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4221 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4222 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4223 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4224 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4225 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4226 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4227 4228 #address-cells = <2>; 4229 #size-cells = <0>; 4230 #sound-dai-cells = <1>; 4231 status = "disabled"; 4232 }; 4233 4234 lpass_txmacro: codec@6ae0000 { 4235 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4236 reg = <0 0x06ae0000 0 0x1000>; 4237 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4238 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4239 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4240 <&lpass_vamacro>; 4241 clock-names = "mclk", 4242 "macro", 4243 "dcodec", 4244 "fsgen"; 4245 4246 #clock-cells = <0>; 4247 clock-output-names = "mclk"; 4248 #sound-dai-cells = <1>; 4249 }; 4250 4251 lpass_wsamacro: codec@6b00000 { 4252 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4253 reg = <0 0x06b00000 0 0x1000>; 4254 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4255 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4256 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4257 <&lpass_vamacro>; 4258 clock-names = "mclk", 4259 "macro", 4260 "dcodec", 4261 "fsgen"; 4262 4263 #clock-cells = <0>; 4264 clock-output-names = "mclk"; 4265 #sound-dai-cells = <1>; 4266 sound-name-prefix = "WSA"; 4267 }; 4268 4269 swr0: soundwire@6b10000 { 4270 compatible = "qcom,soundwire-v2.0.0"; 4271 reg = <0 0x06b10000 0 0x10000>; 4272 clocks = <&lpass_wsamacro>; 4273 clock-names = "iface"; 4274 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4275 label = "WSA"; 4276 4277 pinctrl-0 = <&wsa_swr_active>; 4278 pinctrl-names = "default"; 4279 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 4280 reset-names = "swr_audio_cgcr"; 4281 4282 qcom,din-ports = <4>; 4283 qcom,dout-ports = <9>; 4284 4285 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4286 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4287 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4288 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4289 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4290 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4291 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4292 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4293 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4294 4295 #address-cells = <2>; 4296 #size-cells = <0>; 4297 #sound-dai-cells = <1>; 4298 status = "disabled"; 4299 }; 4300 4301 lpass_audiocc: clock-controller@6b6c000 { 4302 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 4303 reg = <0 0x06b6c000 0 0x1000>; 4304 #clock-cells = <1>; 4305 #reset-cells = <1>; 4306 }; 4307 4308 swr2: soundwire@6d30000 { 4309 compatible = "qcom,soundwire-v2.0.0"; 4310 reg = <0 0x06d30000 0 0x10000>; 4311 clocks = <&lpass_txmacro>; 4312 clock-names = "iface"; 4313 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 4315 interrupt-names = "core", "wakeup"; 4316 label = "TX"; 4317 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 4318 reset-names = "swr_audio_cgcr"; 4319 4320 pinctrl-0 = <&tx_swr_active>; 4321 pinctrl-names = "default"; 4322 4323 qcom,din-ports = <4>; 4324 qcom,dout-ports = <1>; 4325 4326 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 4327 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 4328 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 4329 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4330 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4331 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4332 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4333 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4334 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 4335 4336 #address-cells = <2>; 4337 #size-cells = <0>; 4338 #sound-dai-cells = <1>; 4339 status = "disabled"; 4340 }; 4341 4342 lpass_vamacro: codec@6d44000 { 4343 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4344 reg = <0 0x06d44000 0 0x1000>; 4345 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4346 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4347 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4348 clock-names = "mclk", 4349 "macro", 4350 "dcodec"; 4351 4352 #clock-cells = <0>; 4353 clock-output-names = "fsgen"; 4354 #sound-dai-cells = <1>; 4355 }; 4356 4357 lpass_tlmm: pinctrl@6e80000 { 4358 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 4359 reg = <0 0x06e80000 0 0x20000>, 4360 <0 0x07250000 0 0x10000>; 4361 4362 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4363 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4364 clock-names = "core", "audio"; 4365 4366 gpio-controller; 4367 #gpio-cells = <2>; 4368 gpio-ranges = <&lpass_tlmm 0 0 23>; 4369 4370 tx_swr_active: tx-swr-active-state { 4371 clk-pins { 4372 pins = "gpio0"; 4373 function = "swr_tx_clk"; 4374 drive-strength = <2>; 4375 slew-rate = <1>; 4376 bias-disable; 4377 }; 4378 4379 data-pins { 4380 pins = "gpio1", "gpio2"; 4381 function = "swr_tx_data"; 4382 drive-strength = <2>; 4383 slew-rate = <1>; 4384 bias-bus-hold; 4385 }; 4386 }; 4387 4388 rx_swr_active: rx-swr-active-state { 4389 clk-pins { 4390 pins = "gpio3"; 4391 function = "swr_rx_clk"; 4392 drive-strength = <2>; 4393 slew-rate = <1>; 4394 bias-disable; 4395 }; 4396 4397 data-pins { 4398 pins = "gpio4", "gpio5"; 4399 function = "swr_rx_data"; 4400 drive-strength = <2>; 4401 slew-rate = <1>; 4402 bias-bus-hold; 4403 }; 4404 }; 4405 4406 dmic01_default: dmic01-default-state { 4407 clk-pins { 4408 pins = "gpio6"; 4409 function = "dmic1_clk"; 4410 drive-strength = <8>; 4411 output-high; 4412 }; 4413 4414 data-pins { 4415 pins = "gpio7"; 4416 function = "dmic1_data"; 4417 drive-strength = <8>; 4418 input-enable; 4419 }; 4420 }; 4421 4422 dmic23_default: dmic23-default-state { 4423 clk-pins { 4424 pins = "gpio8"; 4425 function = "dmic2_clk"; 4426 drive-strength = <8>; 4427 output-high; 4428 }; 4429 4430 data-pins { 4431 pins = "gpio9"; 4432 function = "dmic2_data"; 4433 drive-strength = <8>; 4434 input-enable; 4435 }; 4436 }; 4437 4438 wsa_swr_active: wsa-swr-active-state { 4439 clk-pins { 4440 pins = "gpio10"; 4441 function = "wsa_swr_clk"; 4442 drive-strength = <2>; 4443 slew-rate = <1>; 4444 bias-disable; 4445 }; 4446 4447 data-pins { 4448 pins = "gpio11"; 4449 function = "wsa_swr_data"; 4450 drive-strength = <2>; 4451 slew-rate = <1>; 4452 bias-bus-hold; 4453 }; 4454 }; 4455 4456 wsa2_swr_active: wsa2-swr-active-state { 4457 clk-pins { 4458 pins = "gpio15"; 4459 function = "wsa2_swr_clk"; 4460 drive-strength = <2>; 4461 slew-rate = <1>; 4462 bias-disable; 4463 }; 4464 4465 data-pins { 4466 pins = "gpio16"; 4467 function = "wsa2_swr_data"; 4468 drive-strength = <2>; 4469 slew-rate = <1>; 4470 bias-bus-hold; 4471 }; 4472 }; 4473 }; 4474 4475 lpasscc: clock-controller@6ea0000 { 4476 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 4477 reg = <0 0x06ea0000 0 0x12000>; 4478 #clock-cells = <1>; 4479 #reset-cells = <1>; 4480 }; 4481 4482 lpass_ag_noc: interconnect@7e40000 { 4483 compatible = "qcom,x1e80100-lpass-ag-noc"; 4484 reg = <0 0x07e40000 0 0xe080>; 4485 4486 qcom,bcm-voters = <&apps_bcm_voter>; 4487 4488 #interconnect-cells = <2>; 4489 }; 4490 4491 lpass_lpiaon_noc: interconnect@7400000 { 4492 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4493 reg = <0 0x07400000 0 0x19080>; 4494 4495 qcom,bcm-voters = <&apps_bcm_voter>; 4496 4497 #interconnect-cells = <2>; 4498 }; 4499 4500 lpass_lpicx_noc: interconnect@7430000 { 4501 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4502 reg = <0 0x07430000 0 0x3A200>; 4503 4504 qcom,bcm-voters = <&apps_bcm_voter>; 4505 4506 #interconnect-cells = <2>; 4507 }; 4508 4509 sdhc_2: mmc@8804000 { 4510 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4511 reg = <0 0x08804000 0 0x1000>; 4512 4513 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4514 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4515 interrupt-names = "hc_irq", "pwr_irq"; 4516 4517 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4518 <&gcc GCC_SDCC2_APPS_CLK>, 4519 <&rpmhcc RPMH_CXO_CLK>; 4520 clock-names = "iface", "core", "xo"; 4521 iommus = <&apps_smmu 0x520 0>; 4522 qcom,dll-config = <0x0007642c>; 4523 qcom,ddr-config = <0x80040868>; 4524 power-domains = <&rpmhpd RPMHPD_CX>; 4525 operating-points-v2 = <&sdhc2_opp_table>; 4526 4527 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4528 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4529 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4530 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4531 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4532 bus-width = <4>; 4533 dma-coherent; 4534 4535 status = "disabled"; 4536 4537 sdhc2_opp_table: opp-table { 4538 compatible = "operating-points-v2"; 4539 4540 opp-19200000 { 4541 opp-hz = /bits/ 64 <19200000>; 4542 required-opps = <&rpmhpd_opp_min_svs>; 4543 }; 4544 4545 opp-50000000 { 4546 opp-hz = /bits/ 64 <50000000>; 4547 required-opps = <&rpmhpd_opp_low_svs>; 4548 }; 4549 4550 opp-100000000 { 4551 opp-hz = /bits/ 64 <100000000>; 4552 required-opps = <&rpmhpd_opp_svs>; 4553 }; 4554 4555 opp-202000000 { 4556 opp-hz = /bits/ 64 <202000000>; 4557 required-opps = <&rpmhpd_opp_svs_l1>; 4558 }; 4559 }; 4560 }; 4561 4562 sdhc_4: mmc@8844000 { 4563 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4564 reg = <0 0x08844000 0 0x1000>; 4565 4566 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4567 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 4568 interrupt-names = "hc_irq", "pwr_irq"; 4569 4570 clocks = <&gcc GCC_SDCC4_AHB_CLK>, 4571 <&gcc GCC_SDCC4_APPS_CLK>, 4572 <&rpmhcc RPMH_CXO_CLK>; 4573 clock-names = "iface", "core", "xo"; 4574 iommus = <&apps_smmu 0x160 0>; 4575 qcom,dll-config = <0x0007642c>; 4576 qcom,ddr-config = <0x80040868>; 4577 power-domains = <&rpmhpd RPMHPD_CX>; 4578 operating-points-v2 = <&sdhc4_opp_table>; 4579 4580 interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS 4581 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4582 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4583 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 4584 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4585 bus-width = <4>; 4586 dma-coherent; 4587 4588 status = "disabled"; 4589 4590 sdhc4_opp_table: opp-table { 4591 compatible = "operating-points-v2"; 4592 4593 opp-19200000 { 4594 opp-hz = /bits/ 64 <19200000>; 4595 required-opps = <&rpmhpd_opp_min_svs>; 4596 }; 4597 4598 opp-50000000 { 4599 opp-hz = /bits/ 64 <50000000>; 4600 required-opps = <&rpmhpd_opp_low_svs>; 4601 }; 4602 4603 opp-100000000 { 4604 opp-hz = /bits/ 64 <100000000>; 4605 required-opps = <&rpmhpd_opp_svs>; 4606 }; 4607 4608 opp-202000000 { 4609 opp-hz = /bits/ 64 <202000000>; 4610 required-opps = <&rpmhpd_opp_svs_l1>; 4611 }; 4612 }; 4613 }; 4614 4615 usb_2_hsphy: phy@88e0000 { 4616 compatible = "qcom,x1e80100-snps-eusb2-phy", 4617 "qcom,sm8550-snps-eusb2-phy"; 4618 reg = <0 0x088e0000 0 0x154>; 4619 #phy-cells = <0>; 4620 4621 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4622 clock-names = "ref"; 4623 4624 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4625 4626 status = "disabled"; 4627 }; 4628 4629 usb_mp_hsphy0: phy@88e1000 { 4630 compatible = "qcom,x1e80100-snps-eusb2-phy", 4631 "qcom,sm8550-snps-eusb2-phy"; 4632 reg = <0 0x088e1000 0 0x154>; 4633 #phy-cells = <0>; 4634 4635 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4636 clock-names = "ref"; 4637 4638 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4639 4640 status = "disabled"; 4641 }; 4642 4643 usb_mp_hsphy1: phy@88e2000 { 4644 compatible = "qcom,x1e80100-snps-eusb2-phy", 4645 "qcom,sm8550-snps-eusb2-phy"; 4646 reg = <0 0x088e2000 0 0x154>; 4647 #phy-cells = <0>; 4648 4649 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4650 clock-names = "ref"; 4651 4652 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4653 4654 status = "disabled"; 4655 }; 4656 4657 usb_mp_qmpphy0: phy@88e3000 { 4658 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4659 reg = <0 0x088e3000 0 0x2000>; 4660 4661 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4662 <&rpmhcc RPMH_CXO_CLK>, 4663 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4664 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4665 clock-names = "aux", 4666 "ref", 4667 "com_aux", 4668 "pipe"; 4669 4670 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4671 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4672 reset-names = "phy", 4673 "phy_phy"; 4674 4675 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 4676 4677 #clock-cells = <0>; 4678 clock-output-names = "usb_mp_phy0_pipe_clk"; 4679 4680 #phy-cells = <0>; 4681 4682 status = "disabled"; 4683 }; 4684 4685 usb_mp_qmpphy1: phy@88e5000 { 4686 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4687 reg = <0 0x088e5000 0 0x2000>; 4688 4689 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4690 <&rpmhcc RPMH_CXO_CLK>, 4691 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4692 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 4693 clock-names = "aux", 4694 "ref", 4695 "com_aux", 4696 "pipe"; 4697 4698 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 4699 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 4700 reset-names = "phy", 4701 "phy_phy"; 4702 4703 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 4704 4705 #clock-cells = <0>; 4706 clock-output-names = "usb_mp_phy1_pipe_clk"; 4707 4708 #phy-cells = <0>; 4709 4710 status = "disabled"; 4711 }; 4712 4713 usb_1_ss2: usb@a0f8800 { 4714 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4715 reg = <0 0x0a0f8800 0 0x400>; 4716 4717 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4718 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4719 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4720 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4721 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4722 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4723 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4724 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4725 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4726 clock-names = "cfg_noc", 4727 "core", 4728 "iface", 4729 "sleep", 4730 "mock_utmi", 4731 "noc_aggr", 4732 "noc_aggr_north", 4733 "noc_aggr_south", 4734 "noc_sys"; 4735 4736 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4737 <&gcc GCC_USB30_TERT_MASTER_CLK>; 4738 assigned-clock-rates = <19200000>, 4739 <200000000>; 4740 4741 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4742 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 4743 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4744 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 4745 interrupt-names = "pwr_event", 4746 "dp_hs_phy_irq", 4747 "dm_hs_phy_irq", 4748 "ss_phy_irq"; 4749 4750 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4751 required-opps = <&rpmhpd_opp_nom>; 4752 4753 resets = <&gcc GCC_USB30_TERT_BCR>; 4754 4755 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 4756 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4757 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4758 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4759 interconnect-names = "usb-ddr", 4760 "apps-usb"; 4761 4762 wakeup-source; 4763 4764 #address-cells = <2>; 4765 #size-cells = <2>; 4766 ranges; 4767 4768 status = "disabled"; 4769 4770 usb_1_ss2_dwc3: usb@a000000 { 4771 compatible = "snps,dwc3"; 4772 reg = <0 0x0a000000 0 0xcd00>; 4773 4774 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 4775 4776 iommus = <&apps_smmu 0x14a0 0x0>; 4777 4778 phys = <&usb_1_ss2_hsphy>, 4779 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 4780 phy-names = "usb2-phy", 4781 "usb3-phy"; 4782 4783 snps,dis_u2_susphy_quirk; 4784 snps,dis_enblslpm_quirk; 4785 snps,usb3_lpm_capable; 4786 snps,dis-u1-entry-quirk; 4787 snps,dis-u2-entry-quirk; 4788 4789 dma-coherent; 4790 4791 ports { 4792 #address-cells = <1>; 4793 #size-cells = <0>; 4794 4795 port@0 { 4796 reg = <0>; 4797 4798 usb_1_ss2_dwc3_hs: endpoint { 4799 }; 4800 }; 4801 4802 port@1 { 4803 reg = <1>; 4804 4805 usb_1_ss2_dwc3_ss: endpoint { 4806 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 4807 }; 4808 }; 4809 }; 4810 }; 4811 }; 4812 4813 usb_2: usb@a2f8800 { 4814 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4815 reg = <0 0x0a2f8800 0 0x400>; 4816 #address-cells = <2>; 4817 #size-cells = <2>; 4818 ranges; 4819 4820 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4821 <&gcc GCC_USB20_MASTER_CLK>, 4822 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4823 <&gcc GCC_USB20_SLEEP_CLK>, 4824 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4825 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4826 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4827 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4828 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4829 clock-names = "cfg_noc", 4830 "core", 4831 "iface", 4832 "sleep", 4833 "mock_utmi", 4834 "noc_aggr", 4835 "noc_aggr_north", 4836 "noc_aggr_south", 4837 "noc_sys"; 4838 4839 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4840 <&gcc GCC_USB20_MASTER_CLK>; 4841 assigned-clock-rates = <19200000>, <200000000>; 4842 4843 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 4844 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 4845 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 4846 interrupt-names = "pwr_event", 4847 "dp_hs_phy_irq", 4848 "dm_hs_phy_irq"; 4849 4850 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4851 required-opps = <&rpmhpd_opp_nom>; 4852 4853 resets = <&gcc GCC_USB20_PRIM_BCR>; 4854 4855 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4856 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4857 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4858 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4859 interconnect-names = "usb-ddr", 4860 "apps-usb"; 4861 4862 wakeup-source; 4863 4864 status = "disabled"; 4865 4866 usb_2_dwc3: usb@a200000 { 4867 compatible = "snps,dwc3"; 4868 reg = <0 0x0a200000 0 0xcd00>; 4869 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 4870 iommus = <&apps_smmu 0x14e0 0x0>; 4871 phys = <&usb_2_hsphy>; 4872 phy-names = "usb2-phy"; 4873 maximum-speed = "high-speed"; 4874 snps,dis-u1-entry-quirk; 4875 snps,dis-u2-entry-quirk; 4876 4877 dma-coherent; 4878 4879 ports { 4880 #address-cells = <1>; 4881 #size-cells = <0>; 4882 4883 port@0 { 4884 reg = <0>; 4885 4886 usb_2_dwc3_hs: endpoint { 4887 }; 4888 }; 4889 }; 4890 }; 4891 }; 4892 4893 usb_mp: usb@a4f8800 { 4894 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; 4895 reg = <0 0x0a4f8800 0 0x400>; 4896 4897 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4898 <&gcc GCC_USB30_MP_MASTER_CLK>, 4899 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4900 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4901 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4902 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4903 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4904 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4905 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4906 clock-names = "cfg_noc", 4907 "core", 4908 "iface", 4909 "sleep", 4910 "mock_utmi", 4911 "noc_aggr", 4912 "noc_aggr_north", 4913 "noc_aggr_south", 4914 "noc_sys"; 4915 4916 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4917 <&gcc GCC_USB30_MP_MASTER_CLK>; 4918 assigned-clock-rates = <19200000>, 4919 <200000000>; 4920 4921 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 4922 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 4923 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 4924 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 4925 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 4926 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 4927 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 4928 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 4929 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 4930 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 4931 interrupt-names = "pwr_event_1", "pwr_event_2", 4932 "hs_phy_1", "hs_phy_2", 4933 "dp_hs_phy_1", "dm_hs_phy_1", 4934 "dp_hs_phy_2", "dm_hs_phy_2", 4935 "ss_phy_1", "ss_phy_2"; 4936 4937 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4938 required-opps = <&rpmhpd_opp_nom>; 4939 4940 resets = <&gcc GCC_USB30_MP_BCR>; 4941 4942 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 4943 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4944 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4945 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; 4946 interconnect-names = "usb-ddr", 4947 "apps-usb"; 4948 4949 wakeup-source; 4950 4951 #address-cells = <2>; 4952 #size-cells = <2>; 4953 ranges; 4954 4955 status = "disabled"; 4956 4957 usb_mp_dwc3: usb@a400000 { 4958 compatible = "snps,dwc3"; 4959 reg = <0 0x0a400000 0 0xcd00>; 4960 4961 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 4962 4963 iommus = <&apps_smmu 0x1400 0x0>; 4964 4965 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 4966 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 4967 phy-names = "usb2-0", "usb3-0", 4968 "usb2-1", "usb3-1"; 4969 dr_mode = "host"; 4970 4971 snps,dis_u2_susphy_quirk; 4972 snps,dis_enblslpm_quirk; 4973 snps,usb3_lpm_capable; 4974 snps,dis-u1-entry-quirk; 4975 snps,dis-u2-entry-quirk; 4976 4977 dma-coherent; 4978 }; 4979 }; 4980 4981 usb_1_ss0: usb@a6f8800 { 4982 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4983 reg = <0 0x0a6f8800 0 0x400>; 4984 4985 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4986 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4987 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4988 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4989 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4990 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4991 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 4992 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 4993 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4994 clock-names = "cfg_noc", 4995 "core", 4996 "iface", 4997 "sleep", 4998 "mock_utmi", 4999 "noc_aggr", 5000 "noc_aggr_north", 5001 "noc_aggr_south", 5002 "noc_sys"; 5003 5004 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5005 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5006 assigned-clock-rates = <19200000>, 5007 <200000000>; 5008 5009 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 5010 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 5011 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5012 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5013 interrupt-names = "pwr_event", 5014 "dp_hs_phy_irq", 5015 "dm_hs_phy_irq", 5016 "ss_phy_irq"; 5017 5018 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5019 required-opps = <&rpmhpd_opp_nom>; 5020 5021 resets = <&gcc GCC_USB30_PRIM_BCR>; 5022 5023 wakeup-source; 5024 5025 #address-cells = <2>; 5026 #size-cells = <2>; 5027 ranges; 5028 5029 status = "disabled"; 5030 5031 usb_1_ss0_dwc3: usb@a600000 { 5032 compatible = "snps,dwc3"; 5033 reg = <0 0x0a600000 0 0xcd00>; 5034 5035 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 5036 5037 iommus = <&apps_smmu 0x1420 0x0>; 5038 5039 phys = <&usb_1_ss0_hsphy>, 5040 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 5041 phy-names = "usb2-phy", 5042 "usb3-phy"; 5043 5044 snps,dis_u2_susphy_quirk; 5045 snps,dis_enblslpm_quirk; 5046 snps,usb3_lpm_capable; 5047 snps,dis-u1-entry-quirk; 5048 snps,dis-u2-entry-quirk; 5049 5050 dma-coherent; 5051 5052 ports { 5053 #address-cells = <1>; 5054 #size-cells = <0>; 5055 5056 port@0 { 5057 reg = <0>; 5058 5059 usb_1_ss0_dwc3_hs: endpoint { 5060 }; 5061 }; 5062 5063 port@1 { 5064 reg = <1>; 5065 5066 usb_1_ss0_dwc3_ss: endpoint { 5067 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 5068 }; 5069 }; 5070 }; 5071 }; 5072 }; 5073 5074 usb_1_ss1: usb@a8f8800 { 5075 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5076 reg = <0 0x0a8f8800 0 0x400>; 5077 5078 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5079 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5080 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5081 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5082 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5083 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5084 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5085 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5086 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5087 clock-names = "cfg_noc", 5088 "core", 5089 "iface", 5090 "sleep", 5091 "mock_utmi", 5092 "noc_aggr", 5093 "noc_aggr_north", 5094 "noc_aggr_south", 5095 "noc_sys"; 5096 5097 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5098 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5099 assigned-clock-rates = <19200000>, 5100 <200000000>; 5101 5102 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 5103 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 5104 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5105 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 5106 interrupt-names = "pwr_event", 5107 "dp_hs_phy_irq", 5108 "dm_hs_phy_irq", 5109 "ss_phy_irq"; 5110 5111 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5112 required-opps = <&rpmhpd_opp_nom>; 5113 5114 resets = <&gcc GCC_USB30_SEC_BCR>; 5115 5116 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5118 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5119 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5120 interconnect-names = "usb-ddr", 5121 "apps-usb"; 5122 5123 wakeup-source; 5124 5125 #address-cells = <2>; 5126 #size-cells = <2>; 5127 ranges; 5128 5129 status = "disabled"; 5130 5131 usb_1_ss1_dwc3: usb@a800000 { 5132 compatible = "snps,dwc3"; 5133 reg = <0 0x0a800000 0 0xcd00>; 5134 5135 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 5136 5137 iommus = <&apps_smmu 0x1460 0x0>; 5138 5139 phys = <&usb_1_ss1_hsphy>, 5140 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 5141 phy-names = "usb2-phy", 5142 "usb3-phy"; 5143 5144 snps,dis_u2_susphy_quirk; 5145 snps,dis_enblslpm_quirk; 5146 snps,usb3_lpm_capable; 5147 snps,dis-u1-entry-quirk; 5148 snps,dis-u2-entry-quirk; 5149 5150 dma-coherent; 5151 5152 ports { 5153 #address-cells = <1>; 5154 #size-cells = <0>; 5155 5156 port@0 { 5157 reg = <0>; 5158 5159 usb_1_ss1_dwc3_hs: endpoint { 5160 }; 5161 }; 5162 5163 port@1 { 5164 reg = <1>; 5165 5166 usb_1_ss1_dwc3_ss: endpoint { 5167 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 5168 }; 5169 }; 5170 }; 5171 }; 5172 }; 5173 5174 mdss: display-subsystem@ae00000 { 5175 compatible = "qcom,x1e80100-mdss"; 5176 reg = <0 0x0ae00000 0 0x1000>; 5177 reg-names = "mdss"; 5178 5179 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5180 5181 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5182 <&gcc GCC_DISP_HF_AXI_CLK>, 5183 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5184 5185 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5186 5187 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5188 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 5189 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 5190 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5191 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5192 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5193 interconnect-names = "mdp0-mem", 5194 "mdp1-mem", 5195 "cpu-cfg"; 5196 5197 power-domains = <&dispcc MDSS_GDSC>; 5198 5199 iommus = <&apps_smmu 0x1c00 0x2>; 5200 5201 interrupt-controller; 5202 #interrupt-cells = <1>; 5203 5204 #address-cells = <2>; 5205 #size-cells = <2>; 5206 ranges; 5207 5208 status = "disabled"; 5209 5210 mdss_mdp: display-controller@ae01000 { 5211 compatible = "qcom,x1e80100-dpu"; 5212 reg = <0 0x0ae01000 0 0x8f000>, 5213 <0 0x0aeb0000 0 0x2008>; 5214 reg-names = "mdp", 5215 "vbif"; 5216 5217 interrupts-extended = <&mdss 0>; 5218 5219 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5220 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5221 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5222 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5223 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5224 clock-names = "nrt_bus", 5225 "iface", 5226 "lut", 5227 "core", 5228 "vsync"; 5229 5230 operating-points-v2 = <&mdp_opp_table>; 5231 5232 power-domains = <&rpmhpd RPMHPD_MMCX>; 5233 5234 ports { 5235 #address-cells = <1>; 5236 #size-cells = <0>; 5237 5238 port@0 { 5239 reg = <0>; 5240 5241 mdss_intf0_out: endpoint { 5242 remote-endpoint = <&mdss_dp0_in>; 5243 }; 5244 }; 5245 5246 port@4 { 5247 reg = <4>; 5248 5249 mdss_intf4_out: endpoint { 5250 remote-endpoint = <&mdss_dp1_in>; 5251 }; 5252 }; 5253 5254 port@5 { 5255 reg = <5>; 5256 5257 mdss_intf5_out: endpoint { 5258 remote-endpoint = <&mdss_dp3_in>; 5259 }; 5260 }; 5261 5262 port@6 { 5263 reg = <6>; 5264 5265 mdss_intf6_out: endpoint { 5266 remote-endpoint = <&mdss_dp2_in>; 5267 }; 5268 }; 5269 }; 5270 5271 mdp_opp_table: opp-table { 5272 compatible = "operating-points-v2"; 5273 5274 opp-200000000 { 5275 opp-hz = /bits/ 64 <200000000>; 5276 required-opps = <&rpmhpd_opp_low_svs>; 5277 }; 5278 5279 opp-325000000 { 5280 opp-hz = /bits/ 64 <325000000>; 5281 required-opps = <&rpmhpd_opp_svs>; 5282 }; 5283 5284 opp-375000000 { 5285 opp-hz = /bits/ 64 <375000000>; 5286 required-opps = <&rpmhpd_opp_svs_l1>; 5287 }; 5288 5289 opp-514000000 { 5290 opp-hz = /bits/ 64 <514000000>; 5291 required-opps = <&rpmhpd_opp_nom>; 5292 }; 5293 5294 opp-575000000 { 5295 opp-hz = /bits/ 64 <575000000>; 5296 required-opps = <&rpmhpd_opp_nom_l1>; 5297 }; 5298 }; 5299 }; 5300 5301 mdss_dp0: displayport-controller@ae90000 { 5302 compatible = "qcom,x1e80100-dp"; 5303 reg = <0 0x0ae90000 0 0x200>, 5304 <0 0x0ae90200 0 0x200>, 5305 <0 0x0ae90400 0 0x600>, 5306 <0 0x0ae91000 0 0x400>, 5307 <0 0x0ae91400 0 0x400>; 5308 5309 interrupts-extended = <&mdss 12>; 5310 5311 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5312 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5313 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5314 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5315 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 5316 clock-names = "core_iface", 5317 "core_aux", 5318 "ctrl_link", 5319 "ctrl_link_iface", 5320 "stream_pixel"; 5321 5322 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5323 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 5324 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5325 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5326 5327 operating-points-v2 = <&mdss_dp0_opp_table>; 5328 5329 power-domains = <&rpmhpd RPMHPD_MMCX>; 5330 5331 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 5332 phy-names = "dp"; 5333 5334 #sound-dai-cells = <0>; 5335 5336 status = "disabled"; 5337 5338 ports { 5339 #address-cells = <1>; 5340 #size-cells = <0>; 5341 5342 port@0 { 5343 reg = <0>; 5344 5345 mdss_dp0_in: endpoint { 5346 remote-endpoint = <&mdss_intf0_out>; 5347 }; 5348 }; 5349 5350 port@1 { 5351 reg = <1>; 5352 5353 mdss_dp0_out: endpoint { 5354 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 5355 }; 5356 }; 5357 }; 5358 5359 mdss_dp0_opp_table: opp-table { 5360 compatible = "operating-points-v2"; 5361 5362 opp-160000000 { 5363 opp-hz = /bits/ 64 <160000000>; 5364 required-opps = <&rpmhpd_opp_low_svs>; 5365 }; 5366 5367 opp-270000000 { 5368 opp-hz = /bits/ 64 <270000000>; 5369 required-opps = <&rpmhpd_opp_svs>; 5370 }; 5371 5372 opp-540000000 { 5373 opp-hz = /bits/ 64 <540000000>; 5374 required-opps = <&rpmhpd_opp_svs_l1>; 5375 }; 5376 5377 opp-810000000 { 5378 opp-hz = /bits/ 64 <810000000>; 5379 required-opps = <&rpmhpd_opp_nom>; 5380 }; 5381 }; 5382 }; 5383 5384 mdss_dp1: displayport-controller@ae98000 { 5385 compatible = "qcom,x1e80100-dp"; 5386 reg = <0 0x0ae98000 0 0x200>, 5387 <0 0x0ae98200 0 0x200>, 5388 <0 0x0ae98400 0 0x600>, 5389 <0 0x0ae99000 0 0x400>, 5390 <0 0x0ae99400 0 0x400>; 5391 5392 interrupts-extended = <&mdss 13>; 5393 5394 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5395 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5396 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5397 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5398 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 5399 clock-names = "core_iface", 5400 "core_aux", 5401 "ctrl_link", 5402 "ctrl_link_iface", 5403 "stream_pixel"; 5404 5405 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5406 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 5407 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5408 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5409 5410 operating-points-v2 = <&mdss_dp1_opp_table>; 5411 5412 power-domains = <&rpmhpd RPMHPD_MMCX>; 5413 5414 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 5415 phy-names = "dp"; 5416 5417 #sound-dai-cells = <0>; 5418 5419 status = "disabled"; 5420 5421 ports { 5422 #address-cells = <1>; 5423 #size-cells = <0>; 5424 5425 port@0 { 5426 reg = <0>; 5427 5428 mdss_dp1_in: endpoint { 5429 remote-endpoint = <&mdss_intf4_out>; 5430 }; 5431 }; 5432 5433 port@1 { 5434 reg = <1>; 5435 5436 mdss_dp1_out: endpoint { 5437 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 5438 }; 5439 }; 5440 }; 5441 5442 mdss_dp1_opp_table: opp-table { 5443 compatible = "operating-points-v2"; 5444 5445 opp-160000000 { 5446 opp-hz = /bits/ 64 <160000000>; 5447 required-opps = <&rpmhpd_opp_low_svs>; 5448 }; 5449 5450 opp-270000000 { 5451 opp-hz = /bits/ 64 <270000000>; 5452 required-opps = <&rpmhpd_opp_svs>; 5453 }; 5454 5455 opp-540000000 { 5456 opp-hz = /bits/ 64 <540000000>; 5457 required-opps = <&rpmhpd_opp_svs_l1>; 5458 }; 5459 5460 opp-810000000 { 5461 opp-hz = /bits/ 64 <810000000>; 5462 required-opps = <&rpmhpd_opp_nom>; 5463 }; 5464 }; 5465 }; 5466 5467 mdss_dp2: displayport-controller@ae9a000 { 5468 compatible = "qcom,x1e80100-dp"; 5469 reg = <0 0x0ae9a000 0 0x200>, 5470 <0 0x0ae9a200 0 0x200>, 5471 <0 0x0ae9a400 0 0x600>, 5472 <0 0x0ae9b000 0 0x400>, 5473 <0 0x0ae9b400 0 0x400>; 5474 5475 interrupts-extended = <&mdss 14>; 5476 5477 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5478 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5479 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5480 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5481 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 5482 clock-names = "core_iface", 5483 "core_aux", 5484 "ctrl_link", 5485 "ctrl_link_iface", 5486 "stream_pixel"; 5487 5488 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5489 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 5490 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5491 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5492 5493 operating-points-v2 = <&mdss_dp2_opp_table>; 5494 5495 power-domains = <&rpmhpd RPMHPD_MMCX>; 5496 5497 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 5498 phy-names = "dp"; 5499 5500 #sound-dai-cells = <0>; 5501 5502 status = "disabled"; 5503 5504 ports { 5505 #address-cells = <1>; 5506 #size-cells = <0>; 5507 5508 port@0 { 5509 reg = <0>; 5510 mdss_dp2_in: endpoint { 5511 remote-endpoint = <&mdss_intf6_out>; 5512 }; 5513 }; 5514 5515 port@1 { 5516 reg = <1>; 5517 5518 mdss_dp2_out: endpoint { 5519 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 5520 }; 5521 }; 5522 }; 5523 5524 mdss_dp2_opp_table: opp-table { 5525 compatible = "operating-points-v2"; 5526 5527 opp-160000000 { 5528 opp-hz = /bits/ 64 <160000000>; 5529 required-opps = <&rpmhpd_opp_low_svs>; 5530 }; 5531 5532 opp-270000000 { 5533 opp-hz = /bits/ 64 <270000000>; 5534 required-opps = <&rpmhpd_opp_svs>; 5535 }; 5536 5537 opp-540000000 { 5538 opp-hz = /bits/ 64 <540000000>; 5539 required-opps = <&rpmhpd_opp_svs_l1>; 5540 }; 5541 5542 opp-810000000 { 5543 opp-hz = /bits/ 64 <810000000>; 5544 required-opps = <&rpmhpd_opp_nom>; 5545 }; 5546 }; 5547 }; 5548 5549 mdss_dp3: displayport-controller@aea0000 { 5550 compatible = "qcom,x1e80100-dp"; 5551 reg = <0 0x0aea0000 0 0x200>, 5552 <0 0x0aea0200 0 0x200>, 5553 <0 0x0aea0400 0 0x600>, 5554 <0 0x0aea1000 0 0x400>, 5555 <0 0x0aea1400 0 0x400>; 5556 5557 interrupts-extended = <&mdss 15>; 5558 5559 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5560 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5561 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5562 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5563 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5564 clock-names = "core_iface", 5565 "core_aux", 5566 "ctrl_link", 5567 "ctrl_link_iface", 5568 "stream_pixel"; 5569 5570 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5571 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5572 assigned-clock-parents = <&mdss_dp3_phy 0>, 5573 <&mdss_dp3_phy 1>; 5574 5575 operating-points-v2 = <&mdss_dp3_opp_table>; 5576 5577 power-domains = <&rpmhpd RPMHPD_MMCX>; 5578 5579 phys = <&mdss_dp3_phy>; 5580 phy-names = "dp"; 5581 5582 #sound-dai-cells = <0>; 5583 5584 status = "disabled"; 5585 5586 ports { 5587 #address-cells = <1>; 5588 #size-cells = <0>; 5589 5590 port@0 { 5591 reg = <0>; 5592 5593 mdss_dp3_in: endpoint { 5594 remote-endpoint = <&mdss_intf5_out>; 5595 }; 5596 }; 5597 5598 port@1 { 5599 reg = <1>; 5600 }; 5601 }; 5602 5603 mdss_dp3_opp_table: opp-table { 5604 compatible = "operating-points-v2"; 5605 5606 opp-160000000 { 5607 opp-hz = /bits/ 64 <160000000>; 5608 required-opps = <&rpmhpd_opp_low_svs>; 5609 }; 5610 5611 opp-270000000 { 5612 opp-hz = /bits/ 64 <270000000>; 5613 required-opps = <&rpmhpd_opp_svs>; 5614 }; 5615 5616 opp-540000000 { 5617 opp-hz = /bits/ 64 <540000000>; 5618 required-opps = <&rpmhpd_opp_svs_l1>; 5619 }; 5620 5621 opp-810000000 { 5622 opp-hz = /bits/ 64 <810000000>; 5623 required-opps = <&rpmhpd_opp_nom>; 5624 }; 5625 }; 5626 }; 5627 5628 }; 5629 5630 mdss_dp2_phy: phy@aec2a00 { 5631 compatible = "qcom,x1e80100-dp-phy"; 5632 reg = <0 0x0aec2a00 0 0x19c>, 5633 <0 0x0aec2200 0 0xec>, 5634 <0 0x0aec2600 0 0xec>, 5635 <0 0x0aec2000 0 0x1c8>; 5636 5637 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5638 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5639 clock-names = "aux", 5640 "cfg_ahb"; 5641 5642 power-domains = <&rpmhpd RPMHPD_MX>; 5643 5644 #clock-cells = <1>; 5645 #phy-cells = <0>; 5646 5647 status = "disabled"; 5648 }; 5649 5650 mdss_dp3_phy: phy@aec5a00 { 5651 compatible = "qcom,x1e80100-dp-phy"; 5652 reg = <0 0x0aec5a00 0 0x19c>, 5653 <0 0x0aec5200 0 0xec>, 5654 <0 0x0aec5600 0 0xec>, 5655 <0 0x0aec5000 0 0x1c8>; 5656 5657 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5658 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5659 clock-names = "aux", 5660 "cfg_ahb"; 5661 5662 power-domains = <&rpmhpd RPMHPD_MX>; 5663 5664 #clock-cells = <1>; 5665 #phy-cells = <0>; 5666 5667 status = "disabled"; 5668 }; 5669 5670 dispcc: clock-controller@af00000 { 5671 compatible = "qcom,x1e80100-dispcc"; 5672 reg = <0 0x0af00000 0 0x20000>; 5673 clocks = <&bi_tcxo_div2>, 5674 <&bi_tcxo_ao_div2>, 5675 <&gcc GCC_DISP_AHB_CLK>, 5676 <&sleep_clk>, 5677 <0>, /* dsi0 */ 5678 <0>, 5679 <0>, /* dsi1 */ 5680 <0>, 5681 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 5682 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5683 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 5684 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5685 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 5686 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5687 <&mdss_dp3_phy 0>, /* dp3 */ 5688 <&mdss_dp3_phy 1>; 5689 power-domains = <&rpmhpd RPMHPD_MMCX>; 5690 required-opps = <&rpmhpd_opp_low_svs>; 5691 #clock-cells = <1>; 5692 #reset-cells = <1>; 5693 #power-domain-cells = <1>; 5694 }; 5695 5696 pdc: interrupt-controller@b220000 { 5697 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 5698 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5699 5700 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 5701 <47 522 52>, <99 609 32>, 5702 <131 717 12>, <143 816 19>; 5703 #interrupt-cells = <2>; 5704 interrupt-parent = <&intc>; 5705 interrupt-controller; 5706 }; 5707 5708 aoss_qmp: power-management@c300000 { 5709 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 5710 reg = <0 0x0c300000 0 0x400>; 5711 interrupt-parent = <&ipcc>; 5712 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5713 IRQ_TYPE_EDGE_RISING>; 5714 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5715 5716 #clock-cells = <0>; 5717 }; 5718 5719 sram@c3f0000 { 5720 compatible = "qcom,rpmh-stats"; 5721 reg = <0 0x0c3f0000 0 0x400>; 5722 }; 5723 5724 spmi: arbiter@c400000 { 5725 compatible = "qcom,x1e80100-spmi-pmic-arb"; 5726 reg = <0 0x0c400000 0 0x3000>, 5727 <0 0x0c500000 0 0x400000>, 5728 <0 0x0c440000 0 0x80000>; 5729 reg-names = "core", "chnls", "obsrvr"; 5730 5731 qcom,ee = <0>; 5732 qcom,channel = <0>; 5733 5734 #address-cells = <2>; 5735 #size-cells = <2>; 5736 ranges; 5737 5738 spmi_bus0: spmi@c42d000 { 5739 reg = <0 0x0c42d000 0 0x4000>, 5740 <0 0x0c4c0000 0 0x10000>; 5741 reg-names = "cnfg", "intr"; 5742 5743 interrupt-names = "periph_irq"; 5744 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5745 interrupt-controller; 5746 #interrupt-cells = <4>; 5747 5748 #address-cells = <2>; 5749 #size-cells = <0>; 5750 }; 5751 5752 spmi_bus1: spmi@c432000 { 5753 reg = <0 0x0c432000 0 0x4000>, 5754 <0 0x0c4d0000 0 0x10000>; 5755 reg-names = "cnfg", "intr"; 5756 5757 interrupt-names = "periph_irq"; 5758 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5759 interrupt-controller; 5760 #interrupt-cells = <4>; 5761 5762 #address-cells = <2>; 5763 #size-cells = <0>; 5764 }; 5765 }; 5766 5767 tlmm: pinctrl@f100000 { 5768 compatible = "qcom,x1e80100-tlmm"; 5769 reg = <0 0x0f100000 0 0xf00000>; 5770 5771 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5772 5773 gpio-controller; 5774 #gpio-cells = <2>; 5775 5776 interrupt-controller; 5777 #interrupt-cells = <2>; 5778 5779 gpio-ranges = <&tlmm 0 0 239>; 5780 wakeup-parent = <&pdc>; 5781 5782 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5783 /* SDA, SCL */ 5784 pins = "gpio0", "gpio1"; 5785 function = "qup0_se0"; 5786 drive-strength = <2>; 5787 bias-pull-up = <2200>; 5788 }; 5789 5790 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5791 /* SDA, SCL */ 5792 pins = "gpio4", "gpio5"; 5793 function = "qup0_se1"; 5794 drive-strength = <2>; 5795 bias-pull-up = <2200>; 5796 }; 5797 5798 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5799 /* SDA, SCL */ 5800 pins = "gpio8", "gpio9"; 5801 function = "qup0_se2"; 5802 drive-strength = <2>; 5803 bias-pull-up = <2200>; 5804 }; 5805 5806 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5807 /* SDA, SCL */ 5808 pins = "gpio12", "gpio13"; 5809 function = "qup0_se3"; 5810 drive-strength = <2>; 5811 bias-pull-up = <2200>; 5812 }; 5813 5814 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5815 /* SDA, SCL */ 5816 pins = "gpio16", "gpio17"; 5817 function = "qup0_se4"; 5818 drive-strength = <2>; 5819 bias-pull-up = <2200>; 5820 }; 5821 5822 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5823 /* SDA, SCL */ 5824 pins = "gpio20", "gpio21"; 5825 function = "qup0_se5"; 5826 drive-strength = <2>; 5827 bias-pull-up = <2200>; 5828 }; 5829 5830 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5831 /* SDA, SCL */ 5832 pins = "gpio24", "gpio25"; 5833 function = "qup0_se6"; 5834 drive-strength = <2>; 5835 bias-pull-up = <2200>; 5836 }; 5837 5838 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5839 /* SDA, SCL */ 5840 pins = "gpio14", "gpio15"; 5841 function = "qup0_se7"; 5842 drive-strength = <2>; 5843 bias-pull-up = <2200>; 5844 }; 5845 5846 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5847 /* SDA, SCL */ 5848 pins = "gpio32", "gpio33"; 5849 function = "qup1_se0"; 5850 drive-strength = <2>; 5851 bias-pull-up = <2200>; 5852 }; 5853 5854 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5855 /* SDA, SCL */ 5856 pins = "gpio36", "gpio37"; 5857 function = "qup1_se1"; 5858 drive-strength = <2>; 5859 bias-pull-up = <2200>; 5860 }; 5861 5862 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5863 /* SDA, SCL */ 5864 pins = "gpio40", "gpio41"; 5865 function = "qup1_se2"; 5866 drive-strength = <2>; 5867 bias-pull-up = <2200>; 5868 }; 5869 5870 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5871 /* SDA, SCL */ 5872 pins = "gpio44", "gpio45"; 5873 function = "qup1_se3"; 5874 drive-strength = <2>; 5875 bias-pull-up = <2200>; 5876 }; 5877 5878 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5879 /* SDA, SCL */ 5880 pins = "gpio48", "gpio49"; 5881 function = "qup1_se4"; 5882 drive-strength = <2>; 5883 bias-pull-up = <2200>; 5884 }; 5885 5886 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5887 /* SDA, SCL */ 5888 pins = "gpio52", "gpio53"; 5889 function = "qup1_se5"; 5890 drive-strength = <2>; 5891 bias-pull-up = <2200>; 5892 }; 5893 5894 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5895 /* SDA, SCL */ 5896 pins = "gpio56", "gpio57"; 5897 function = "qup1_se6"; 5898 drive-strength = <2>; 5899 bias-pull-up = <2200>; 5900 }; 5901 5902 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5903 /* SDA, SCL */ 5904 pins = "gpio54", "gpio55"; 5905 function = "qup1_se7"; 5906 drive-strength = <2>; 5907 bias-pull-up = <2200>; 5908 }; 5909 5910 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5911 /* SDA, SCL */ 5912 pins = "gpio64", "gpio65"; 5913 function = "qup2_se0"; 5914 drive-strength = <2>; 5915 bias-pull-up = <2200>; 5916 }; 5917 5918 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5919 /* SDA, SCL */ 5920 pins = "gpio68", "gpio69"; 5921 function = "qup2_se1"; 5922 drive-strength = <2>; 5923 bias-pull-up = <2200>; 5924 }; 5925 5926 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5927 /* SDA, SCL */ 5928 pins = "gpio72", "gpio73"; 5929 function = "qup2_se2"; 5930 drive-strength = <2>; 5931 bias-pull-up = <2200>; 5932 }; 5933 5934 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5935 /* SDA, SCL */ 5936 pins = "gpio76", "gpio77"; 5937 function = "qup2_se3"; 5938 drive-strength = <2>; 5939 bias-pull-up = <2200>; 5940 }; 5941 5942 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5943 /* SDA, SCL */ 5944 pins = "gpio80", "gpio81"; 5945 function = "qup2_se4"; 5946 drive-strength = <2>; 5947 bias-pull-up = <2200>; 5948 }; 5949 5950 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5951 /* SDA, SCL */ 5952 pins = "gpio84", "gpio85"; 5953 function = "qup2_se5"; 5954 drive-strength = <2>; 5955 bias-pull-up = <2200>; 5956 }; 5957 5958 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5959 /* SDA, SCL */ 5960 pins = "gpio88", "gpio89"; 5961 function = "qup2_se6"; 5962 drive-strength = <2>; 5963 bias-pull-up = <2200>; 5964 }; 5965 5966 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5967 /* SDA, SCL */ 5968 pins = "gpio86", "gpio87"; 5969 function = "qup2_se7"; 5970 drive-strength = <2>; 5971 bias-pull-up = <2200>; 5972 }; 5973 5974 qup_spi0_cs: qup-spi0-cs-state { 5975 pins = "gpio3"; 5976 function = "qup0_se0"; 5977 drive-strength = <6>; 5978 bias-disable; 5979 }; 5980 5981 qup_spi0_data_clk: qup-spi0-data-clk-state { 5982 /* MISO, MOSI, CLK */ 5983 pins = "gpio0", "gpio1", "gpio2"; 5984 function = "qup0_se0"; 5985 drive-strength = <6>; 5986 bias-disable; 5987 }; 5988 5989 qup_spi1_cs: qup-spi1-cs-state { 5990 pins = "gpio7"; 5991 function = "qup0_se1"; 5992 drive-strength = <6>; 5993 bias-disable; 5994 }; 5995 5996 qup_spi1_data_clk: qup-spi1-data-clk-state { 5997 /* MISO, MOSI, CLK */ 5998 pins = "gpio4", "gpio5", "gpio6"; 5999 function = "qup0_se1"; 6000 drive-strength = <6>; 6001 bias-disable; 6002 }; 6003 6004 qup_spi2_cs: qup-spi2-cs-state { 6005 pins = "gpio11"; 6006 function = "qup0_se2"; 6007 drive-strength = <6>; 6008 bias-disable; 6009 }; 6010 6011 qup_spi2_data_clk: qup-spi2-data-clk-state { 6012 /* MISO, MOSI, CLK */ 6013 pins = "gpio8", "gpio9", "gpio10"; 6014 function = "qup0_se2"; 6015 drive-strength = <6>; 6016 bias-disable; 6017 }; 6018 6019 qup_spi3_cs: qup-spi3-cs-state { 6020 pins = "gpio15"; 6021 function = "qup0_se3"; 6022 drive-strength = <6>; 6023 bias-disable; 6024 }; 6025 6026 qup_spi3_data_clk: qup-spi3-data-clk-state { 6027 /* MISO, MOSI, CLK */ 6028 pins = "gpio12", "gpio13", "gpio14"; 6029 function = "qup0_se3"; 6030 drive-strength = <6>; 6031 bias-disable; 6032 }; 6033 6034 qup_spi4_cs: qup-spi4-cs-state { 6035 pins = "gpio19"; 6036 function = "qup0_se4"; 6037 drive-strength = <6>; 6038 bias-disable; 6039 }; 6040 6041 qup_spi4_data_clk: qup-spi4-data-clk-state { 6042 /* MISO, MOSI, CLK */ 6043 pins = "gpio16", "gpio17", "gpio18"; 6044 function = "qup0_se4"; 6045 drive-strength = <6>; 6046 bias-disable; 6047 }; 6048 6049 qup_spi5_cs: qup-spi5-cs-state { 6050 pins = "gpio23"; 6051 function = "qup0_se5"; 6052 drive-strength = <6>; 6053 bias-disable; 6054 }; 6055 6056 qup_spi5_data_clk: qup-spi5-data-clk-state { 6057 /* MISO, MOSI, CLK */ 6058 pins = "gpio20", "gpio21", "gpio22"; 6059 function = "qup0_se5"; 6060 drive-strength = <6>; 6061 bias-disable; 6062 }; 6063 6064 qup_spi6_cs: qup-spi6-cs-state { 6065 pins = "gpio27"; 6066 function = "qup0_se6"; 6067 drive-strength = <6>; 6068 bias-disable; 6069 }; 6070 6071 qup_spi6_data_clk: qup-spi6-data-clk-state { 6072 /* MISO, MOSI, CLK */ 6073 pins = "gpio24", "gpio25", "gpio26"; 6074 function = "qup0_se6"; 6075 drive-strength = <6>; 6076 bias-disable; 6077 }; 6078 6079 qup_spi7_cs: qup-spi7-cs-state { 6080 pins = "gpio13"; 6081 function = "qup0_se7"; 6082 drive-strength = <6>; 6083 bias-disable; 6084 }; 6085 6086 qup_spi7_data_clk: qup-spi7-data-clk-state { 6087 /* MISO, MOSI, CLK */ 6088 pins = "gpio14", "gpio15", "gpio12"; 6089 function = "qup0_se7"; 6090 drive-strength = <6>; 6091 bias-disable; 6092 }; 6093 6094 qup_spi8_cs: qup-spi8-cs-state { 6095 pins = "gpio35"; 6096 function = "qup1_se0"; 6097 drive-strength = <6>; 6098 bias-disable; 6099 }; 6100 6101 qup_spi8_data_clk: qup-spi8-data-clk-state { 6102 /* MISO, MOSI, CLK */ 6103 pins = "gpio32", "gpio33", "gpio34"; 6104 function = "qup1_se0"; 6105 drive-strength = <6>; 6106 bias-disable; 6107 }; 6108 6109 qup_spi9_cs: qup-spi9-cs-state { 6110 pins = "gpio39"; 6111 function = "qup1_se1"; 6112 drive-strength = <6>; 6113 bias-disable; 6114 }; 6115 6116 qup_spi9_data_clk: qup-spi9-data-clk-state { 6117 /* MISO, MOSI, CLK */ 6118 pins = "gpio36", "gpio37", "gpio38"; 6119 function = "qup1_se1"; 6120 drive-strength = <6>; 6121 bias-disable; 6122 }; 6123 6124 qup_spi10_cs: qup-spi10-cs-state { 6125 pins = "gpio43"; 6126 function = "qup1_se2"; 6127 drive-strength = <6>; 6128 bias-disable; 6129 }; 6130 6131 qup_spi10_data_clk: qup-spi10-data-clk-state { 6132 /* MISO, MOSI, CLK */ 6133 pins = "gpio40", "gpio41", "gpio42"; 6134 function = "qup1_se2"; 6135 drive-strength = <6>; 6136 bias-disable; 6137 }; 6138 6139 qup_spi11_cs: qup-spi11-cs-state { 6140 pins = "gpio47"; 6141 function = "qup1_se3"; 6142 drive-strength = <6>; 6143 bias-disable; 6144 }; 6145 6146 qup_spi11_data_clk: qup-spi11-data-clk-state { 6147 /* MISO, MOSI, CLK */ 6148 pins = "gpio44", "gpio45", "gpio46"; 6149 function = "qup1_se3"; 6150 drive-strength = <6>; 6151 bias-disable; 6152 }; 6153 6154 qup_spi12_cs: qup-spi12-cs-state { 6155 pins = "gpio51"; 6156 function = "qup1_se4"; 6157 drive-strength = <6>; 6158 bias-disable; 6159 }; 6160 6161 qup_spi12_data_clk: qup-spi12-data-clk-state { 6162 /* MISO, MOSI, CLK */ 6163 pins = "gpio48", "gpio49", "gpio50"; 6164 function = "qup1_se4"; 6165 drive-strength = <6>; 6166 bias-disable; 6167 }; 6168 6169 qup_spi13_cs: qup-spi13-cs-state { 6170 pins = "gpio55"; 6171 function = "qup1_se5"; 6172 drive-strength = <6>; 6173 bias-disable; 6174 }; 6175 6176 qup_spi13_data_clk: qup-spi13-data-clk-state { 6177 /* MISO, MOSI, CLK */ 6178 pins = "gpio52", "gpio53", "gpio54"; 6179 function = "qup1_se5"; 6180 drive-strength = <6>; 6181 bias-disable; 6182 }; 6183 6184 qup_spi14_cs: qup-spi14-cs-state { 6185 pins = "gpio59"; 6186 function = "qup1_se6"; 6187 drive-strength = <6>; 6188 bias-disable; 6189 }; 6190 6191 qup_spi14_data_clk: qup-spi14-data-clk-state { 6192 /* MISO, MOSI, CLK */ 6193 pins = "gpio56", "gpio57", "gpio58"; 6194 function = "qup1_se6"; 6195 drive-strength = <6>; 6196 bias-disable; 6197 }; 6198 6199 qup_spi15_cs: qup-spi15-cs-state { 6200 pins = "gpio53"; 6201 function = "qup1_se7"; 6202 drive-strength = <6>; 6203 bias-disable; 6204 }; 6205 6206 qup_spi15_data_clk: qup-spi15-data-clk-state { 6207 /* MISO, MOSI, CLK */ 6208 pins = "gpio54", "gpio55", "gpio52"; 6209 function = "qup1_se7"; 6210 drive-strength = <6>; 6211 bias-disable; 6212 }; 6213 6214 qup_spi16_cs: qup-spi16-cs-state { 6215 pins = "gpio67"; 6216 function = "qup2_se0"; 6217 drive-strength = <6>; 6218 bias-disable; 6219 }; 6220 6221 qup_spi16_data_clk: qup-spi16-data-clk-state { 6222 /* MISO, MOSI, CLK */ 6223 pins = "gpio64", "gpio65", "gpio66"; 6224 function = "qup2_se0"; 6225 drive-strength = <6>; 6226 bias-disable; 6227 }; 6228 6229 qup_spi17_cs: qup-spi17-cs-state { 6230 pins = "gpio71"; 6231 function = "qup2_se1"; 6232 drive-strength = <6>; 6233 bias-disable; 6234 }; 6235 6236 qup_spi17_data_clk: qup-spi17-data-clk-state { 6237 /* MISO, MOSI, CLK */ 6238 pins = "gpio68", "gpio69", "gpio70"; 6239 function = "qup2_se1"; 6240 drive-strength = <6>; 6241 bias-disable; 6242 }; 6243 6244 qup_spi18_cs: qup-spi18-cs-state { 6245 pins = "gpio75"; 6246 function = "qup2_se2"; 6247 drive-strength = <6>; 6248 bias-disable; 6249 }; 6250 6251 qup_spi18_data_clk: qup-spi18-data-clk-state { 6252 /* MISO, MOSI, CLK */ 6253 pins = "gpio72", "gpio73", "gpio74"; 6254 function = "qup2_se2"; 6255 drive-strength = <6>; 6256 bias-disable; 6257 }; 6258 6259 qup_spi19_cs: qup-spi19-cs-state { 6260 pins = "gpio79"; 6261 function = "qup2_se3"; 6262 drive-strength = <6>; 6263 bias-disable; 6264 }; 6265 6266 qup_spi19_data_clk: qup-spi19-data-clk-state { 6267 /* MISO, MOSI, CLK */ 6268 pins = "gpio76", "gpio77", "gpio78"; 6269 function = "qup2_se3"; 6270 drive-strength = <6>; 6271 bias-disable; 6272 }; 6273 6274 qup_spi20_cs: qup-spi20-cs-state { 6275 pins = "gpio83"; 6276 function = "qup2_se4"; 6277 drive-strength = <6>; 6278 bias-disable; 6279 }; 6280 6281 qup_spi20_data_clk: qup-spi20-data-clk-state { 6282 /* MISO, MOSI, CLK */ 6283 pins = "gpio80", "gpio81", "gpio82"; 6284 function = "qup2_se4"; 6285 drive-strength = <6>; 6286 bias-disable; 6287 }; 6288 6289 qup_spi21_cs: qup-spi21-cs-state { 6290 pins = "gpio87"; 6291 function = "qup2_se5"; 6292 drive-strength = <6>; 6293 bias-disable; 6294 }; 6295 6296 qup_spi21_data_clk: qup-spi21-data-clk-state { 6297 /* MISO, MOSI, CLK */ 6298 pins = "gpio84", "gpio85", "gpio86"; 6299 function = "qup2_se5"; 6300 drive-strength = <6>; 6301 bias-disable; 6302 }; 6303 6304 qup_spi22_cs: qup-spi22-cs-state { 6305 pins = "gpio91"; 6306 function = "qup2_se6"; 6307 drive-strength = <6>; 6308 bias-disable; 6309 }; 6310 6311 qup_spi22_data_clk: qup-spi22-data-clk-state { 6312 /* MISO, MOSI, CLK */ 6313 pins = "gpio88", "gpio89", "gpio90"; 6314 function = "qup2_se6"; 6315 drive-strength = <6>; 6316 bias-disable; 6317 }; 6318 6319 qup_spi23_cs: qup-spi23-cs-state { 6320 pins = "gpio85"; 6321 function = "qup2_se7"; 6322 drive-strength = <6>; 6323 bias-disable; 6324 }; 6325 6326 qup_spi23_data_clk: qup-spi23-data-clk-state { 6327 /* MISO, MOSI, CLK */ 6328 pins = "gpio86", "gpio87", "gpio84"; 6329 function = "qup2_se7"; 6330 drive-strength = <6>; 6331 bias-disable; 6332 }; 6333 6334 qup_uart2_default: qup-uart2-default-state { 6335 cts-pins { 6336 pins = "gpio8"; 6337 function = "qup0_se2"; 6338 drive-strength = <2>; 6339 bias-disable; 6340 }; 6341 6342 rts-pins { 6343 pins = "gpio9"; 6344 function = "qup0_se2"; 6345 drive-strength = <2>; 6346 bias-disable; 6347 }; 6348 6349 tx-pins { 6350 pins = "gpio10"; 6351 function = "qup0_se2"; 6352 drive-strength = <2>; 6353 bias-disable; 6354 }; 6355 6356 rx-pins { 6357 pins = "gpio11"; 6358 function = "qup0_se2"; 6359 drive-strength = <2>; 6360 bias-disable; 6361 }; 6362 }; 6363 6364 qup_uart14_default: qup-uart14-default-state { 6365 cts-pins { 6366 pins = "gpio56"; 6367 function = "qup1_se6"; 6368 bias-bus-hold; 6369 }; 6370 6371 rts-pins { 6372 pins = "gpio57"; 6373 function = "qup1_se6"; 6374 drive-strength = <2>; 6375 bias-disable; 6376 }; 6377 6378 tx-pins { 6379 pins = "gpio58"; 6380 function = "qup1_se6"; 6381 drive-strength = <2>; 6382 bias-disable; 6383 }; 6384 6385 rx-pins { 6386 pins = "gpio59"; 6387 function = "qup1_se6"; 6388 bias-pull-up; 6389 }; 6390 }; 6391 6392 qup_uart21_default: qup-uart21-default-state { 6393 tx-pins { 6394 pins = "gpio86"; 6395 function = "qup2_se5"; 6396 drive-strength = <2>; 6397 bias-disable; 6398 }; 6399 6400 rx-pins { 6401 pins = "gpio87"; 6402 function = "qup2_se5"; 6403 drive-strength = <2>; 6404 bias-disable; 6405 }; 6406 }; 6407 6408 sdc2_default: sdc2-default-state { 6409 clk-pins { 6410 pins = "sdc2_clk"; 6411 drive-strength = <16>; 6412 bias-disable; 6413 }; 6414 6415 cmd-pins { 6416 pins = "sdc2_cmd"; 6417 drive-strength = <10>; 6418 bias-pull-up; 6419 }; 6420 6421 data-pins { 6422 pins = "sdc2_data"; 6423 drive-strength = <10>; 6424 bias-pull-up; 6425 }; 6426 }; 6427 6428 sdc2_sleep: sdc2-sleep-state { 6429 clk-pins { 6430 pins = "sdc2_clk"; 6431 drive-strength = <2>; 6432 bias-disable; 6433 }; 6434 6435 cmd-pins { 6436 pins = "sdc2_cmd"; 6437 drive-strength = <2>; 6438 bias-pull-up; 6439 }; 6440 6441 data-pins { 6442 pins = "sdc2_data"; 6443 drive-strength = <2>; 6444 bias-pull-up; 6445 }; 6446 }; 6447 }; 6448 6449 stm@10002000 { 6450 compatible = "arm,coresight-stm", "arm,primecell"; 6451 reg = <0x0 0x10002000 0x0 0x1000>, 6452 <0x0 0x16280000 0x0 0x180000>; 6453 reg-names = "stm-base", 6454 "stm-stimulus-base"; 6455 6456 clocks = <&aoss_qmp>; 6457 clock-names = "apb_pclk"; 6458 6459 out-ports { 6460 port { 6461 stm_out: endpoint { 6462 remote-endpoint = <&funnel0_in7>; 6463 }; 6464 }; 6465 }; 6466 }; 6467 6468 tpdm@10003000 { 6469 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6470 reg = <0x0 0x10003000 0x0 0x1000>; 6471 6472 clocks = <&aoss_qmp>; 6473 clock-names = "apb_pclk"; 6474 6475 qcom,cmb-element-bits = <32>; 6476 qcom,cmb-msrs-num = <32>; 6477 status = "disabled"; 6478 6479 out-ports { 6480 port { 6481 dcc_tpdm_out: endpoint { 6482 remote-endpoint = <&qdss_tpda_in0>; 6483 }; 6484 }; 6485 }; 6486 }; 6487 6488 tpda@10004000 { 6489 compatible = "qcom,coresight-tpda", "arm,primecell"; 6490 reg = <0x0 0x10004000 0x0 0x1000>; 6491 6492 clocks = <&aoss_qmp>; 6493 clock-names = "apb_pclk"; 6494 6495 in-ports { 6496 #address-cells = <1>; 6497 #size-cells = <0>; 6498 6499 port@0 { 6500 reg = <0>; 6501 6502 qdss_tpda_in0: endpoint { 6503 remote-endpoint = <&dcc_tpdm_out>; 6504 }; 6505 }; 6506 6507 port@1 { 6508 reg = <1>; 6509 6510 qdss_tpda_in1: endpoint { 6511 remote-endpoint = <&qdss_tpdm_out>; 6512 }; 6513 }; 6514 }; 6515 6516 out-ports { 6517 port { 6518 qdss_tpda_out: endpoint { 6519 remote-endpoint = <&funnel0_in6>; 6520 }; 6521 }; 6522 }; 6523 }; 6524 6525 tpdm@1000f000 { 6526 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6527 reg = <0x0 0x1000f000 0x0 0x1000>; 6528 6529 clocks = <&aoss_qmp>; 6530 clock-names = "apb_pclk"; 6531 6532 qcom,cmb-element-bits = <32>; 6533 qcom,cmb-msrs-num = <32>; 6534 6535 out-ports { 6536 port { 6537 qdss_tpdm_out: endpoint { 6538 remote-endpoint = <&qdss_tpda_in1>; 6539 }; 6540 }; 6541 }; 6542 }; 6543 6544 funnel@10041000 { 6545 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6546 reg = <0x0 0x10041000 0x0 0x1000>; 6547 6548 clocks = <&aoss_qmp>; 6549 clock-names = "apb_pclk"; 6550 6551 in-ports { 6552 #address-cells = <1>; 6553 #size-cells = <0>; 6554 6555 port@6 { 6556 reg = <6>; 6557 6558 funnel0_in6: endpoint { 6559 remote-endpoint = <&qdss_tpda_out>; 6560 }; 6561 }; 6562 6563 port@7 { 6564 reg = <7>; 6565 6566 funnel0_in7: endpoint { 6567 remote-endpoint = <&stm_out>; 6568 }; 6569 }; 6570 }; 6571 6572 out-ports { 6573 port { 6574 funnel0_out: endpoint { 6575 remote-endpoint = <&qdss_funnel_in0>; 6576 }; 6577 }; 6578 }; 6579 }; 6580 6581 funnel@10042000 { 6582 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6583 reg = <0x0 0x10042000 0x0 0x1000>; 6584 6585 clocks = <&aoss_qmp>; 6586 clock-names = "apb_pclk"; 6587 6588 in-ports { 6589 #address-cells = <1>; 6590 #size-cells = <0>; 6591 6592 port@2 { 6593 reg = <2>; 6594 6595 funnel1_in2: endpoint { 6596 remote-endpoint = <&tmess_funnel_out>; 6597 }; 6598 }; 6599 6600 port@5 { 6601 reg = <5>; 6602 6603 funnel1_in5: endpoint { 6604 remote-endpoint = <&dlst_funnel_out>; 6605 }; 6606 }; 6607 6608 port@6 { 6609 reg = <6>; 6610 6611 funnel1_in6: endpoint { 6612 remote-endpoint = <&dlct1_funnel_out>; 6613 }; 6614 }; 6615 }; 6616 6617 out-ports { 6618 port { 6619 funnel1_out: endpoint { 6620 remote-endpoint = <&qdss_funnel_in1>; 6621 }; 6622 }; 6623 }; 6624 }; 6625 6626 funnel@10045000 { 6627 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6628 reg = <0x0 0x10045000 0x0 0x1000>; 6629 6630 clocks = <&aoss_qmp>; 6631 clock-names = "apb_pclk"; 6632 6633 in-ports { 6634 #address-cells = <1>; 6635 #size-cells = <0>; 6636 6637 port@0 { 6638 reg = <0>; 6639 6640 qdss_funnel_in0: endpoint { 6641 remote-endpoint = <&funnel0_out>; 6642 }; 6643 }; 6644 6645 port@1 { 6646 reg = <1>; 6647 6648 qdss_funnel_in1: endpoint { 6649 remote-endpoint = <&funnel1_out>; 6650 }; 6651 }; 6652 }; 6653 6654 out-ports { 6655 port { 6656 qdss_funnel_out: endpoint { 6657 remote-endpoint = <&aoss_funnel_in7>; 6658 }; 6659 }; 6660 }; 6661 }; 6662 6663 tpdm@10800000 { 6664 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6665 reg = <0x0 0x10800000 0x0 0x1000>; 6666 6667 clocks = <&aoss_qmp>; 6668 clock-names = "apb_pclk"; 6669 6670 qcom,cmb-element-bits = <64>; 6671 qcom,cmb-msrs-num = <32>; 6672 6673 out-ports { 6674 port { 6675 mxa_tpdm_out: endpoint { 6676 remote-endpoint = <&dlct2_tpda_in15>; 6677 }; 6678 }; 6679 }; 6680 }; 6681 6682 tpdm@1082c000 { 6683 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6684 reg = <0x0 0x1082c000 0x0 0x1000>; 6685 6686 clocks = <&aoss_qmp>; 6687 clock-names = "apb_pclk"; 6688 6689 qcom,dsb-element-bits = <32>; 6690 qcom,dsb-msrs-num = <32>; 6691 6692 out-ports { 6693 port { 6694 gcc_tpdm_out: endpoint { 6695 remote-endpoint = <&dlct1_tpda_in21>; 6696 }; 6697 }; 6698 }; 6699 }; 6700 6701 tpdm@10841000 { 6702 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6703 reg = <0x0 0x10841000 0x0 0x1000>; 6704 6705 clocks = <&aoss_qmp>; 6706 clock-names = "apb_pclk"; 6707 6708 qcom,cmb-element-bits = <32>; 6709 qcom,cmb-msrs-num = <32>; 6710 6711 out-ports { 6712 port { 6713 prng_tpdm_out: endpoint { 6714 remote-endpoint = <&dlct1_tpda_in19>; 6715 }; 6716 }; 6717 }; 6718 }; 6719 6720 tpdm@10844000 { 6721 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6722 reg = <0x0 0x10844000 0x0 0x1000>; 6723 6724 clocks = <&aoss_qmp>; 6725 clock-names = "apb_pclk"; 6726 6727 qcom,dsb-element-bits = <32>; 6728 qcom,dsb-msrs-num = <32>; 6729 6730 out-ports { 6731 port { 6732 lpass_cx_tpdm_out: endpoint { 6733 remote-endpoint = <&lpass_cx_funnel_in0>; 6734 }; 6735 }; 6736 }; 6737 }; 6738 6739 funnel@10846000 { 6740 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6741 reg = <0x0 0x10846000 0x0 0x1000>; 6742 6743 clocks = <&aoss_qmp>; 6744 clock-names = "apb_pclk"; 6745 6746 in-ports { 6747 port { 6748 lpass_cx_funnel_in0: endpoint { 6749 remote-endpoint = <&lpass_cx_tpdm_out>; 6750 }; 6751 }; 6752 }; 6753 6754 out-ports { 6755 port { 6756 lpass_cx_funnel_out: endpoint { 6757 remote-endpoint = <&dlct1_tpda_in4>; 6758 }; 6759 }; 6760 }; 6761 }; 6762 6763 cti@1098b000 { 6764 compatible = "arm,coresight-cti", "arm,primecell"; 6765 reg = <0x0 0x1098b000 0x0 0x1000>; 6766 6767 clocks = <&aoss_qmp>; 6768 clock-names = "apb_pclk"; 6769 }; 6770 6771 tpdm@109d0000 { 6772 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6773 reg = <0x0 0x109d0000 0x0 0x1000>; 6774 6775 clocks = <&aoss_qmp>; 6776 clock-names = "apb_pclk"; 6777 6778 qcom,dsb-element-bits = <32>; 6779 qcom,dsb-msrs-num = <32>; 6780 status = "disabled"; 6781 6782 out-ports { 6783 port { 6784 qm_tpdm_out: endpoint { 6785 remote-endpoint = <&dlct1_tpda_in20>; 6786 }; 6787 }; 6788 }; 6789 }; 6790 6791 tpdm@10ac0000 { 6792 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6793 reg = <0x0 0x10ac0000 0x0 0x1000>; 6794 6795 clocks = <&aoss_qmp>; 6796 clock-names = "apb_pclk"; 6797 6798 qcom,dsb-element-bits = <32>; 6799 qcom,dsb-msrs-num = <32>; 6800 status = "disabled"; 6801 6802 out-ports { 6803 port { 6804 dlst_tpdm0_out: endpoint { 6805 remote-endpoint = <&dlst_tpda_in8>; 6806 }; 6807 }; 6808 }; 6809 }; 6810 6811 tpdm@10ac1000 { 6812 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6813 reg = <0x0 0x10ac1000 0x0 0x1000>; 6814 6815 clocks = <&aoss_qmp>; 6816 clock-names = "apb_pclk"; 6817 6818 qcom,cmb-element-bits = <64>; 6819 qcom,cmb-msrs-num = <32>; 6820 6821 out-ports { 6822 port { 6823 dlst_tpdm1_out: endpoint { 6824 remote-endpoint = <&dlst_tpda_in9>; 6825 }; 6826 }; 6827 }; 6828 }; 6829 6830 tpda@10ac4000 { 6831 compatible = "qcom,coresight-tpda", "arm,primecell"; 6832 reg = <0x0 0x10ac4000 0x0 0x1000>; 6833 6834 clocks = <&aoss_qmp>; 6835 clock-names = "apb_pclk"; 6836 6837 in-ports { 6838 #address-cells = <1>; 6839 #size-cells = <0>; 6840 6841 port@8 { 6842 reg = <8>; 6843 6844 dlst_tpda_in8: endpoint { 6845 remote-endpoint = <&dlst_tpdm0_out>; 6846 }; 6847 }; 6848 6849 port@9 { 6850 reg = <9>; 6851 6852 dlst_tpda_in9: endpoint { 6853 remote-endpoint = <&dlst_tpdm1_out>; 6854 }; 6855 }; 6856 }; 6857 6858 out-ports { 6859 port { 6860 dlst_tpda_out: endpoint { 6861 remote-endpoint = <&dlst_funnel_in0>; 6862 }; 6863 }; 6864 }; 6865 }; 6866 6867 funnel@10ac5000 { 6868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6869 reg = <0x0 0x10ac5000 0x0 0x1000>; 6870 6871 clocks = <&aoss_qmp>; 6872 clock-names = "apb_pclk"; 6873 6874 in-ports { 6875 port { 6876 dlst_funnel_in0: endpoint { 6877 remote-endpoint = <&dlst_tpda_out>; 6878 }; 6879 }; 6880 }; 6881 6882 out-ports { 6883 port { 6884 dlst_funnel_out: endpoint { 6885 remote-endpoint = <&funnel1_in5>; 6886 }; 6887 }; 6888 }; 6889 }; 6890 6891 funnel@10b04000 { 6892 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6893 reg = <0x0 0x10b04000 0x0 0x1000>; 6894 6895 clocks = <&aoss_qmp>; 6896 clock-names = "apb_pclk"; 6897 6898 in-ports { 6899 #address-cells = <1>; 6900 #size-cells = <0>; 6901 6902 port@3 { 6903 reg = <3>; 6904 6905 aoss_funnel_in3: endpoint { 6906 remote-endpoint = <&ddr_lpi_funnel_out>; 6907 }; 6908 }; 6909 6910 port@6 { 6911 reg = <6>; 6912 6913 aoss_funnel_in6: endpoint { 6914 remote-endpoint = <&aoss_tpda_out>; 6915 }; 6916 }; 6917 6918 port@7 { 6919 reg = <7>; 6920 6921 aoss_funnel_in7: endpoint { 6922 remote-endpoint = <&qdss_funnel_out>; 6923 }; 6924 }; 6925 }; 6926 6927 out-ports { 6928 port { 6929 aoss_funnel_out: endpoint { 6930 remote-endpoint = <&etf0_in>; 6931 }; 6932 }; 6933 }; 6934 }; 6935 6936 etf0: tmc@10b05000 { 6937 compatible = "arm,coresight-tmc", "arm,primecell"; 6938 reg = <0x0 0x10b05000 0x0 0x1000>; 6939 6940 clocks = <&aoss_qmp>; 6941 clock-names = "apb_pclk"; 6942 6943 in-ports { 6944 port { 6945 etf0_in: endpoint { 6946 remote-endpoint = <&aoss_funnel_out>; 6947 }; 6948 }; 6949 }; 6950 6951 out-ports { 6952 port { 6953 etf0_out: endpoint { 6954 remote-endpoint = <&swao_rep_in>; 6955 }; 6956 }; 6957 }; 6958 }; 6959 6960 replicator@10b06000 { 6961 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6962 reg = <0x0 0x10b06000 0x0 0x1000>; 6963 6964 clocks = <&aoss_qmp>; 6965 clock-names = "apb_pclk"; 6966 6967 in-ports { 6968 port { 6969 swao_rep_in: endpoint { 6970 remote-endpoint = <&etf0_out>; 6971 }; 6972 }; 6973 }; 6974 6975 out-ports { 6976 port { 6977 swao_rep_out1: endpoint { 6978 remote-endpoint = <&eud_in>; 6979 }; 6980 }; 6981 }; 6982 }; 6983 6984 tpda@10b08000 { 6985 compatible = "qcom,coresight-tpda", "arm,primecell"; 6986 reg = <0x0 0x10b08000 0x0 0x1000>; 6987 6988 clocks = <&aoss_qmp>; 6989 clock-names = "apb_pclk"; 6990 6991 in-ports { 6992 #address-cells = <1>; 6993 #size-cells = <0>; 6994 6995 port@0 { 6996 reg = <0>; 6997 6998 aoss_tpda_in0: endpoint { 6999 remote-endpoint = <&aoss_tpdm0_out>; 7000 }; 7001 }; 7002 7003 port@1 { 7004 reg = <1>; 7005 7006 aoss_tpda_in1: endpoint { 7007 remote-endpoint = <&aoss_tpdm1_out>; 7008 }; 7009 }; 7010 7011 port@2 { 7012 reg = <2>; 7013 7014 aoss_tpda_in2: endpoint { 7015 remote-endpoint = <&aoss_tpdm2_out>; 7016 }; 7017 }; 7018 7019 port@3 { 7020 reg = <3>; 7021 7022 aoss_tpda_in3: endpoint { 7023 remote-endpoint = <&aoss_tpdm3_out>; 7024 }; 7025 }; 7026 7027 port@4 { 7028 reg = <4>; 7029 7030 aoss_tpda_in4: endpoint { 7031 remote-endpoint = <&aoss_tpdm4_out>; 7032 }; 7033 }; 7034 }; 7035 7036 out-ports { 7037 port { 7038 aoss_tpda_out: endpoint { 7039 remote-endpoint = <&aoss_funnel_in6>; 7040 }; 7041 }; 7042 }; 7043 }; 7044 7045 tpdm@10b09000 { 7046 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7047 reg = <0x0 0x10b09000 0x0 0x1000>; 7048 7049 clocks = <&aoss_qmp>; 7050 clock-names = "apb_pclk"; 7051 7052 qcom,cmb-element-bits = <64>; 7053 qcom,cmb-msrs-num = <32>; 7054 7055 out-ports { 7056 port { 7057 aoss_tpdm0_out: endpoint { 7058 remote-endpoint = <&aoss_tpda_in0>; 7059 }; 7060 }; 7061 }; 7062 }; 7063 7064 tpdm@10b0a000 { 7065 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7066 reg = <0x0 0x10b0a000 0x0 0x1000>; 7067 7068 clocks = <&aoss_qmp>; 7069 clock-names = "apb_pclk"; 7070 7071 qcom,cmb-element-bits = <64>; 7072 qcom,cmb-msrs-num = <32>; 7073 7074 out-ports { 7075 port { 7076 aoss_tpdm1_out: endpoint { 7077 remote-endpoint = <&aoss_tpda_in1>; 7078 }; 7079 }; 7080 }; 7081 }; 7082 7083 tpdm@10b0b000 { 7084 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7085 reg = <0x0 0x10b0b000 0x0 0x1000>; 7086 7087 clocks = <&aoss_qmp>; 7088 clock-names = "apb_pclk"; 7089 7090 qcom,cmb-element-bits = <64>; 7091 qcom,cmb-msrs-num = <32>; 7092 7093 out-ports { 7094 port { 7095 aoss_tpdm2_out: endpoint { 7096 remote-endpoint = <&aoss_tpda_in2>; 7097 }; 7098 }; 7099 }; 7100 }; 7101 7102 tpdm@10b0c000 { 7103 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7104 reg = <0x0 0x10b0c000 0x0 0x1000>; 7105 7106 clocks = <&aoss_qmp>; 7107 clock-names = "apb_pclk"; 7108 7109 qcom,cmb-element-bits = <64>; 7110 qcom,cmb-msrs-num = <32>; 7111 7112 out-ports { 7113 port { 7114 aoss_tpdm3_out: endpoint { 7115 remote-endpoint = <&aoss_tpda_in3>; 7116 }; 7117 }; 7118 }; 7119 }; 7120 7121 tpdm@10b0d000 { 7122 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7123 reg = <0x0 0x10b0d000 0x0 0x1000>; 7124 7125 clocks = <&aoss_qmp>; 7126 clock-names = "apb_pclk"; 7127 7128 qcom,dsb-element-bits = <32>; 7129 qcom,dsb-msrs-num = <32>; 7130 7131 out-ports { 7132 port { 7133 aoss_tpdm4_out: endpoint { 7134 remote-endpoint = <&aoss_tpda_in4>; 7135 }; 7136 }; 7137 }; 7138 }; 7139 7140 tpdm@10b20000 { 7141 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7142 reg = <0x0 0x10b20000 0x0 0x1000>; 7143 7144 clocks = <&aoss_qmp>; 7145 clock-names = "apb_pclk"; 7146 7147 qcom,dsb-element-bits = <32>; 7148 qcom,dsb-msrs-num = <32>; 7149 status = "disabled"; 7150 7151 out-ports { 7152 port { 7153 lpicc_tpdm_out: endpoint { 7154 remote-endpoint = <&ddr_lpi_tpda_in>; 7155 }; 7156 }; 7157 }; 7158 }; 7159 7160 tpda@10b23000 { 7161 compatible = "qcom,coresight-tpda", "arm,primecell"; 7162 reg = <0x0 0x10b23000 0x0 0x1000>; 7163 7164 clocks = <&aoss_qmp>; 7165 clock-names = "apb_pclk"; 7166 status = "disabled"; 7167 7168 in-ports { 7169 port { 7170 ddr_lpi_tpda_in: endpoint { 7171 remote-endpoint = <&lpicc_tpdm_out>; 7172 }; 7173 }; 7174 }; 7175 7176 out-ports { 7177 port { 7178 ddr_lpi_tpda_out: endpoint { 7179 remote-endpoint = <&ddr_lpi_funnel_in0>; 7180 }; 7181 }; 7182 }; 7183 }; 7184 7185 funnel@10b24000 { 7186 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7187 reg = <0x0 0x10b24000 0x0 0x1000>; 7188 7189 clocks = <&aoss_qmp>; 7190 clock-names = "apb_pclk"; 7191 status = "disabled"; 7192 7193 in-ports { 7194 port { 7195 ddr_lpi_funnel_in0: endpoint { 7196 remote-endpoint = <&ddr_lpi_tpda_out>; 7197 }; 7198 }; 7199 }; 7200 7201 out-ports { 7202 port { 7203 ddr_lpi_funnel_out: endpoint { 7204 remote-endpoint = <&aoss_funnel_in3>; 7205 }; 7206 }; 7207 }; 7208 }; 7209 7210 tpdm@10c08000 { 7211 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7212 reg = <0x0 0x10c08000 0x0 0x1000>; 7213 7214 clocks = <&aoss_qmp>; 7215 clock-names = "apb_pclk"; 7216 7217 qcom,dsb-element-bits = <32>; 7218 qcom,dsb-msrs-num = <32>; 7219 7220 out-ports { 7221 port { 7222 mm_tpdm_out: endpoint { 7223 remote-endpoint = <&mm_funnel_in4>; 7224 }; 7225 }; 7226 }; 7227 }; 7228 7229 funnel@10c0b000 { 7230 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7231 reg = <0x0 0x10c0b000 0x0 0x1000>; 7232 7233 clocks = <&aoss_qmp>; 7234 clock-names = "apb_pclk"; 7235 7236 in-ports { 7237 #address-cells = <1>; 7238 #size-cells = <0>; 7239 7240 port@4 { 7241 reg = <4>; 7242 7243 mm_funnel_in4: endpoint { 7244 remote-endpoint = <&mm_tpdm_out>; 7245 }; 7246 }; 7247 }; 7248 7249 out-ports { 7250 port { 7251 mm_funnel_out: endpoint { 7252 remote-endpoint = <&dlct2_tpda_in4>; 7253 }; 7254 }; 7255 }; 7256 }; 7257 7258 tpdm@10c28000 { 7259 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7260 reg = <0x0 0x10c28000 0x0 0x1000>; 7261 7262 clocks = <&aoss_qmp>; 7263 clock-names = "apb_pclk"; 7264 7265 qcom,dsb-element-bits = <32>; 7266 qcom,dsb-msrs-num = <32>; 7267 7268 out-ports { 7269 port { 7270 dlct1_tpdm_out: endpoint { 7271 remote-endpoint = <&dlct1_tpda_in26>; 7272 }; 7273 }; 7274 }; 7275 }; 7276 7277 tpdm@10c29000 { 7278 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7279 reg = <0x0 0x10c29000 0x0 0x1000>; 7280 7281 clocks = <&aoss_qmp>; 7282 clock-names = "apb_pclk"; 7283 7284 qcom,cmb-element-bits = <64>; 7285 qcom,cmb-msrs-num = <32>; 7286 7287 out-ports { 7288 port { 7289 ipcc_tpdm_out: endpoint { 7290 remote-endpoint = <&dlct1_tpda_in27>; 7291 }; 7292 }; 7293 }; 7294 }; 7295 7296 tpda@10c2b000 { 7297 compatible = "qcom,coresight-tpda", "arm,primecell"; 7298 reg = <0x0 0x10c2b000 0x0 0x1000>; 7299 7300 clocks = <&aoss_qmp>; 7301 clock-names = "apb_pclk"; 7302 7303 in-ports { 7304 #address-cells = <1>; 7305 #size-cells = <0>; 7306 7307 port@4 { 7308 reg = <4>; 7309 7310 dlct1_tpda_in4: endpoint { 7311 remote-endpoint = <&lpass_cx_funnel_out>; 7312 }; 7313 }; 7314 7315 port@13 { 7316 reg = <19>; 7317 7318 dlct1_tpda_in19: endpoint { 7319 remote-endpoint = <&prng_tpdm_out>; 7320 }; 7321 }; 7322 7323 port@14 { 7324 reg = <20>; 7325 7326 dlct1_tpda_in20: endpoint { 7327 remote-endpoint = <&qm_tpdm_out>; 7328 }; 7329 }; 7330 7331 port@15 { 7332 reg = <21>; 7333 7334 dlct1_tpda_in21: endpoint { 7335 remote-endpoint = <&gcc_tpdm_out>; 7336 }; 7337 }; 7338 7339 port@1a { 7340 reg = <26>; 7341 7342 dlct1_tpda_in26: endpoint { 7343 remote-endpoint = <&dlct1_tpdm_out>; 7344 }; 7345 }; 7346 7347 port@1b { 7348 reg = <27>; 7349 7350 dlct1_tpda_in27: endpoint { 7351 remote-endpoint = <&ipcc_tpdm_out>; 7352 }; 7353 }; 7354 }; 7355 7356 out-ports { 7357 port { 7358 dlct1_tpda_out: endpoint { 7359 remote-endpoint = <&dlct1_funnel_in0>; 7360 }; 7361 }; 7362 }; 7363 }; 7364 7365 funnel@10c2c000 { 7366 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7367 reg = <0x0 0x10c2c000 0x0 0x1000>; 7368 7369 clocks = <&aoss_qmp>; 7370 clock-names = "apb_pclk"; 7371 7372 in-ports { 7373 #address-cells = <1>; 7374 #size-cells = <0>; 7375 7376 port@0 { 7377 reg = <0>; 7378 7379 dlct1_funnel_in0: endpoint { 7380 remote-endpoint = <&dlct1_tpda_out>; 7381 }; 7382 }; 7383 7384 port@4 { 7385 reg = <4>; 7386 7387 dlct1_funnel_in4: endpoint { 7388 remote-endpoint = <&dlct2_funnel_out>; 7389 }; 7390 }; 7391 7392 port@5 { 7393 reg = <5>; 7394 7395 dlct1_funnel_in5: endpoint { 7396 remote-endpoint = <&ddr_funnel0_out>; 7397 }; 7398 }; 7399 }; 7400 7401 out-ports { 7402 port { 7403 dlct1_funnel_out: endpoint { 7404 remote-endpoint = <&funnel1_in6>; 7405 }; 7406 }; 7407 }; 7408 }; 7409 7410 tpdm@10c38000 { 7411 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7412 reg = <0x0 0x10c38000 0x0 0x1000>; 7413 7414 clocks = <&aoss_qmp>; 7415 clock-names = "apb_pclk"; 7416 7417 qcom,cmb-element-bits = <64>; 7418 qcom,cmb-msrs-num = <32>; 7419 7420 out-ports { 7421 port { 7422 dlct2_tpdm0_out: endpoint { 7423 remote-endpoint = <&dlct2_tpda_in16>; 7424 }; 7425 }; 7426 }; 7427 }; 7428 7429 tpdm@10c39000 { 7430 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7431 reg = <0x0 0x10c39000 0x0 0x1000>; 7432 7433 clocks = <&aoss_qmp>; 7434 clock-names = "apb_pclk"; 7435 7436 qcom,cmb-element-bits = <64>; 7437 qcom,cmb-msrs-num = <32>; 7438 7439 out-ports { 7440 port { 7441 dlct2_tpdm1_out: endpoint { 7442 remote-endpoint = <&dlct2_tpda_in17>; 7443 }; 7444 }; 7445 }; 7446 }; 7447 7448 tpda@10c3c000 { 7449 compatible = "qcom,coresight-tpda", "arm,primecell"; 7450 reg = <0x0 0x10c3c000 0x0 0x1000>; 7451 7452 clocks = <&aoss_qmp>; 7453 clock-names = "apb_pclk"; 7454 7455 in-ports { 7456 #address-cells = <1>; 7457 #size-cells = <0>; 7458 7459 port@4 { 7460 reg = <4>; 7461 7462 dlct2_tpda_in4: endpoint { 7463 remote-endpoint = <&mm_funnel_out>; 7464 }; 7465 }; 7466 7467 port@f { 7468 reg = <15>; 7469 7470 dlct2_tpda_in15: endpoint { 7471 remote-endpoint = <&mxa_tpdm_out>; 7472 }; 7473 }; 7474 7475 port@10 { 7476 reg = <16>; 7477 7478 dlct2_tpda_in16: endpoint { 7479 remote-endpoint = <&dlct2_tpdm0_out>; 7480 }; 7481 }; 7482 7483 port@11 { 7484 reg = <17>; 7485 7486 dlct2_tpda_in17: endpoint { 7487 remote-endpoint = <&dlct2_tpdm1_out>; 7488 }; 7489 }; 7490 }; 7491 7492 out-ports { 7493 port { 7494 dlct2_tpda_out: endpoint { 7495 remote-endpoint = <&dlct2_funnel_in0>; 7496 }; 7497 }; 7498 }; 7499 }; 7500 7501 funnel@10c3d000 { 7502 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7503 reg = <0x0 0x10c3d000 0x0 0x1000>; 7504 7505 clocks = <&aoss_qmp>; 7506 clock-names = "apb_pclk"; 7507 7508 in-ports { 7509 port { 7510 dlct2_funnel_in0: endpoint { 7511 remote-endpoint = <&dlct2_tpda_out>; 7512 }; 7513 }; 7514 }; 7515 7516 out-ports { 7517 port { 7518 dlct2_funnel_out: endpoint { 7519 remote-endpoint = <&dlct1_funnel_in4>; 7520 }; 7521 }; 7522 }; 7523 }; 7524 7525 tpdm@10cc1000 { 7526 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7527 reg = <0x0 0x10cc1000 0x0 0x1000>; 7528 7529 clocks = <&aoss_qmp>; 7530 clock-names = "apb_pclk"; 7531 7532 qcom,cmb-element-bits = <64>; 7533 qcom,cmb-msrs-num = <32>; 7534 qcom,dsb-element-bits = <32>; 7535 qcom,dsb-msrs-num = <32>; 7536 status = "disabled"; 7537 7538 out-ports { 7539 port { 7540 tmess_tpdm1_out: endpoint { 7541 remote-endpoint = <&tmess_tpda_in2>; 7542 }; 7543 }; 7544 }; 7545 }; 7546 7547 tpda@10cc4000 { 7548 compatible = "qcom,coresight-tpda", "arm,primecell"; 7549 reg = <0x0 0x10cc4000 0x0 0x1000>; 7550 7551 clocks = <&aoss_qmp>; 7552 clock-names = "apb_pclk"; 7553 7554 in-ports { 7555 #address-cells = <1>; 7556 #size-cells = <0>; 7557 7558 port@2 { 7559 reg = <2>; 7560 7561 tmess_tpda_in2: endpoint { 7562 remote-endpoint = <&tmess_tpdm1_out>; 7563 }; 7564 }; 7565 }; 7566 7567 out-ports { 7568 port { 7569 tmess_tpda_out: endpoint { 7570 remote-endpoint = <&tmess_funnel_in0>; 7571 }; 7572 }; 7573 }; 7574 }; 7575 7576 funnel@10cc5000 { 7577 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7578 reg = <0x0 0x10cc5000 0x0 0x1000>; 7579 7580 clocks = <&aoss_qmp>; 7581 clock-names = "apb_pclk"; 7582 7583 in-ports { 7584 port { 7585 tmess_funnel_in0: endpoint { 7586 remote-endpoint = <&tmess_tpda_out>; 7587 }; 7588 }; 7589 }; 7590 7591 out-ports { 7592 port { 7593 tmess_funnel_out: endpoint { 7594 remote-endpoint = <&funnel1_in2>; 7595 }; 7596 }; 7597 }; 7598 }; 7599 7600 funnel@10d04000 { 7601 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7602 reg = <0x0 0x10d04000 0x0 0x1000>; 7603 7604 clocks = <&aoss_qmp>; 7605 clock-names = "apb_pclk"; 7606 7607 in-ports { 7608 #address-cells = <1>; 7609 #size-cells = <0>; 7610 7611 port@6 { 7612 reg = <6>; 7613 7614 ddr_funnel0_in6: endpoint { 7615 remote-endpoint = <&ddr_funnel1_out>; 7616 }; 7617 }; 7618 }; 7619 7620 out-ports { 7621 port { 7622 ddr_funnel0_out: endpoint { 7623 remote-endpoint = <&dlct1_funnel_in5>; 7624 }; 7625 }; 7626 }; 7627 }; 7628 7629 tpdm@10d08000 { 7630 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7631 reg = <0x0 0x10d08000 0x0 0x1000>; 7632 7633 clocks = <&aoss_qmp>; 7634 clock-names = "apb_pclk"; 7635 7636 qcom,cmb-element-bits = <32>; 7637 qcom,cmb-msrs-num = <32>; 7638 7639 out-ports { 7640 port { 7641 llcc0_tpdm_out: endpoint { 7642 remote-endpoint = <&llcc_tpda_in0>; 7643 }; 7644 }; 7645 }; 7646 }; 7647 7648 tpdm@10d09000 { 7649 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7650 reg = <0x0 0x10d09000 0x0 0x1000>; 7651 7652 clocks = <&aoss_qmp>; 7653 clock-names = "apb_pclk"; 7654 7655 qcom,cmb-element-bits = <32>; 7656 qcom,cmb-msrs-num = <32>; 7657 7658 out-ports { 7659 port { 7660 llcc1_tpdm_out: endpoint { 7661 remote-endpoint = <&llcc_tpda_in1>; 7662 }; 7663 }; 7664 }; 7665 }; 7666 7667 tpdm@10d0a000 { 7668 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7669 reg = <0x0 0x10d0a000 0x0 0x1000>; 7670 7671 clocks = <&aoss_qmp>; 7672 clock-names = "apb_pclk"; 7673 7674 qcom,cmb-element-bits = <32>; 7675 qcom,cmb-msrs-num = <32>; 7676 7677 out-ports { 7678 port { 7679 llcc2_tpdm_out: endpoint { 7680 remote-endpoint = <&llcc_tpda_in2>; 7681 }; 7682 }; 7683 }; 7684 }; 7685 7686 tpdm@10d0b000 { 7687 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7688 reg = <0x0 0x10d0b000 0x0 0x1000>; 7689 7690 clocks = <&aoss_qmp>; 7691 clock-names = "apb_pclk"; 7692 7693 qcom,cmb-element-bits = <32>; 7694 qcom,cmb-msrs-num = <32>; 7695 7696 out-ports { 7697 port { 7698 llcc3_tpdm_out: endpoint { 7699 remote-endpoint = <&llcc_tpda_in3>; 7700 }; 7701 }; 7702 }; 7703 }; 7704 7705 tpdm@10d0c000 { 7706 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7707 reg = <0x0 0x10d0c000 0x0 0x1000>; 7708 7709 clocks = <&aoss_qmp>; 7710 clock-names = "apb_pclk"; 7711 7712 qcom,cmb-element-bits = <32>; 7713 qcom,cmb-msrs-num = <32>; 7714 7715 out-ports { 7716 port { 7717 llcc4_tpdm_out: endpoint { 7718 remote-endpoint = <&llcc_tpda_in4>; 7719 }; 7720 }; 7721 }; 7722 }; 7723 7724 tpdm@10d0d000 { 7725 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7726 reg = <0x0 0x10d0d000 0x0 0x1000>; 7727 7728 clocks = <&aoss_qmp>; 7729 clock-names = "apb_pclk"; 7730 7731 qcom,cmb-element-bits = <32>; 7732 qcom,cmb-msrs-num = <32>; 7733 7734 out-ports { 7735 port { 7736 llcc5_tpdm_out: endpoint { 7737 remote-endpoint = <&llcc_tpda_in5>; 7738 }; 7739 }; 7740 }; 7741 }; 7742 7743 tpdm@10d0e000 { 7744 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7745 reg = <0x0 0x10d0e000 0x0 0x1000>; 7746 7747 clocks = <&aoss_qmp>; 7748 clock-names = "apb_pclk"; 7749 7750 qcom,cmb-element-bits = <32>; 7751 qcom,cmb-msrs-num = <32>; 7752 7753 out-ports { 7754 port { 7755 llcc6_tpdm_out: endpoint { 7756 remote-endpoint = <&llcc_tpda_in6>; 7757 }; 7758 }; 7759 }; 7760 }; 7761 7762 tpdm@10d0f000 { 7763 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7764 reg = <0x0 0x10d0f000 0x0 0x1000>; 7765 7766 clocks = <&aoss_qmp>; 7767 clock-names = "apb_pclk"; 7768 7769 qcom,cmb-element-bits = <32>; 7770 qcom,cmb-msrs-num = <32>; 7771 7772 out-ports { 7773 port { 7774 llcc7_tpdm_out: endpoint { 7775 remote-endpoint = <&llcc_tpda_in7>; 7776 }; 7777 }; 7778 }; 7779 }; 7780 7781 tpda@10d12000 { 7782 compatible = "qcom,coresight-tpda", "arm,primecell"; 7783 reg = <0x0 0x10d12000 0x0 0x1000>; 7784 7785 clocks = <&aoss_qmp>; 7786 clock-names = "apb_pclk"; 7787 7788 in-ports { 7789 #address-cells = <1>; 7790 #size-cells = <0>; 7791 7792 port@0 { 7793 reg = <0>; 7794 7795 llcc_tpda_in0: endpoint { 7796 remote-endpoint = <&llcc0_tpdm_out>; 7797 }; 7798 }; 7799 7800 port@1 { 7801 reg = <1>; 7802 7803 llcc_tpda_in1: endpoint { 7804 remote-endpoint = <&llcc1_tpdm_out>; 7805 }; 7806 }; 7807 7808 port@2 { 7809 reg = <2>; 7810 7811 llcc_tpda_in2: endpoint { 7812 remote-endpoint = <&llcc2_tpdm_out>; 7813 }; 7814 }; 7815 7816 port@3 { 7817 reg = <3>; 7818 7819 llcc_tpda_in3: endpoint { 7820 remote-endpoint = <&llcc3_tpdm_out>; 7821 }; 7822 }; 7823 7824 port@4 { 7825 reg = <4>; 7826 7827 llcc_tpda_in4: endpoint { 7828 remote-endpoint = <&llcc4_tpdm_out>; 7829 }; 7830 }; 7831 7832 port@5 { 7833 reg = <5>; 7834 7835 llcc_tpda_in5: endpoint { 7836 remote-endpoint = <&llcc5_tpdm_out>; 7837 }; 7838 }; 7839 7840 port@6 { 7841 reg = <6>; 7842 7843 llcc_tpda_in6: endpoint { 7844 remote-endpoint = <&llcc6_tpdm_out>; 7845 }; 7846 }; 7847 7848 port@7 { 7849 reg = <7>; 7850 7851 llcc_tpda_in7: endpoint { 7852 remote-endpoint = <&llcc7_tpdm_out>; 7853 }; 7854 }; 7855 }; 7856 7857 out-ports { 7858 port { 7859 llcc_tpda_out: endpoint { 7860 remote-endpoint = <&ddr_funnel1_in0>; 7861 }; 7862 }; 7863 }; 7864 }; 7865 7866 funnel@10d13000 { 7867 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7868 reg = <0x0 0x10d13000 0x0 0x1000>; 7869 7870 clocks = <&aoss_qmp>; 7871 clock-names = "apb_pclk"; 7872 7873 in-ports { 7874 port { 7875 ddr_funnel1_in0: endpoint { 7876 remote-endpoint = <&llcc_tpda_out>; 7877 }; 7878 }; 7879 }; 7880 7881 out-ports { 7882 port { 7883 ddr_funnel1_out: endpoint { 7884 remote-endpoint = <&ddr_funnel0_in6>; 7885 }; 7886 }; 7887 }; 7888 }; 7889 7890 apps_smmu: iommu@15000000 { 7891 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7892 reg = <0 0x15000000 0 0x100000>; 7893 7894 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 7895 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 7896 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 7897 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 7898 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 7899 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 7900 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 7901 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 7902 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 7903 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 7904 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 7905 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 7906 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 7907 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 7908 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 7909 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 7910 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 7911 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 7912 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 7913 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 7914 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 7915 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 7916 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 7917 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7918 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 7919 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7920 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 7921 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7922 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 7923 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7924 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 7925 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7926 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 7927 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7928 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 7929 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 7930 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 7931 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 7932 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 7933 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 7934 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 7935 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 7936 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 7937 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 7938 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 7939 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 7940 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 7941 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 7942 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 7943 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 7944 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 7945 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 7946 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 7947 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 7948 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 7949 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 7950 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 7951 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 7952 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 7953 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 7954 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 7955 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 7956 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 7957 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 7958 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 7959 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 7960 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 7961 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 7962 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 7963 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 7964 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 7965 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 7966 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 7967 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 7968 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 7969 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 7970 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 7971 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 7972 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 7973 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 7974 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 7975 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 7976 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 7977 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7978 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 7979 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 7980 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 7981 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 7982 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 7983 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 7984 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 7985 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 7986 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 7987 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 7988 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 7989 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 7990 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 7991 7992 #iommu-cells = <2>; 7993 #global-interrupts = <1>; 7994 7995 dma-coherent; 7996 }; 7997 7998 pcie_smmu: iommu@15400000 { 7999 compatible = "arm,smmu-v3"; 8000 reg = <0 0x15400000 0 0x80000>; 8001 #iommu-cells = <1>; 8002 interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 8003 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 8004 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; 8005 interrupt-names = "eventq", 8006 "gerror", 8007 "cmdq-sync"; 8008 dma-coherent; 8009 status = "reserved"; /* Controlled by Gunyah. */ 8010 }; 8011 8012 intc: interrupt-controller@17000000 { 8013 compatible = "arm,gic-v3"; 8014 reg = <0 0x17000000 0 0x10000>, /* GICD */ 8015 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 8016 8017 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 8018 8019 #interrupt-cells = <3>; 8020 interrupt-controller; 8021 8022 #redistributor-regions = <1>; 8023 redistributor-stride = <0x0 0x40000>; 8024 8025 #address-cells = <2>; 8026 #size-cells = <2>; 8027 ranges; 8028 8029 gic_its: msi-controller@17040000 { 8030 compatible = "arm,gic-v3-its"; 8031 reg = <0 0x17040000 0 0x40000>; 8032 8033 msi-controller; 8034 #msi-cells = <1>; 8035 }; 8036 }; 8037 8038 cpucp_mbox: mailbox@17430000 { 8039 compatible = "qcom,x1e80100-cpucp-mbox"; 8040 reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; 8041 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8042 #mbox-cells = <1>; 8043 }; 8044 8045 apps_rsc: rsc@17500000 { 8046 compatible = "qcom,rpmh-rsc"; 8047 reg = <0 0x17500000 0 0x10000>, 8048 <0 0x17510000 0 0x10000>, 8049 <0 0x17520000 0 0x10000>; 8050 reg-names = "drv-0", "drv-1", "drv-2"; 8051 8052 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 8053 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 8054 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 8055 qcom,tcs-offset = <0xd00>; 8056 qcom,drv-id = <2>; 8057 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 8058 <WAKE_TCS 2>, <CONTROL_TCS 0>; 8059 8060 label = "apps_rsc"; 8061 power-domains = <&system_pd>; 8062 8063 apps_bcm_voter: bcm-voter { 8064 compatible = "qcom,bcm-voter"; 8065 }; 8066 8067 rpmhcc: clock-controller { 8068 compatible = "qcom,x1e80100-rpmh-clk"; 8069 8070 clocks = <&xo_board>; 8071 clock-names = "xo"; 8072 8073 #clock-cells = <1>; 8074 }; 8075 8076 rpmhpd: power-controller { 8077 compatible = "qcom,x1e80100-rpmhpd"; 8078 8079 operating-points-v2 = <&rpmhpd_opp_table>; 8080 8081 #power-domain-cells = <1>; 8082 8083 rpmhpd_opp_table: opp-table { 8084 compatible = "operating-points-v2"; 8085 8086 rpmhpd_opp_ret: opp-16 { 8087 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8088 }; 8089 8090 rpmhpd_opp_min_svs: opp-48 { 8091 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8092 }; 8093 8094 rpmhpd_opp_low_svs_d2: opp-52 { 8095 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8096 }; 8097 8098 rpmhpd_opp_low_svs_d1: opp-56 { 8099 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8100 }; 8101 8102 rpmhpd_opp_low_svs_d0: opp-60 { 8103 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8104 }; 8105 8106 rpmhpd_opp_low_svs: opp-64 { 8107 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8108 }; 8109 8110 rpmhpd_opp_low_svs_l1: opp-80 { 8111 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8112 }; 8113 8114 rpmhpd_opp_svs: opp-128 { 8115 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8116 }; 8117 8118 rpmhpd_opp_svs_l0: opp-144 { 8119 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8120 }; 8121 8122 rpmhpd_opp_svs_l1: opp-192 { 8123 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8124 }; 8125 8126 rpmhpd_opp_nom: opp-256 { 8127 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8128 }; 8129 8130 rpmhpd_opp_nom_l1: opp-320 { 8131 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8132 }; 8133 8134 rpmhpd_opp_nom_l2: opp-336 { 8135 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8136 }; 8137 8138 rpmhpd_opp_turbo: opp-384 { 8139 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8140 }; 8141 8142 rpmhpd_opp_turbo_l1: opp-416 { 8143 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8144 }; 8145 }; 8146 }; 8147 }; 8148 8149 timer@17800000 { 8150 compatible = "arm,armv7-timer-mem"; 8151 reg = <0 0x17800000 0 0x1000>; 8152 8153 #address-cells = <2>; 8154 #size-cells = <1>; 8155 ranges = <0 0 0 0 0x20000000>; 8156 8157 frame@17801000 { 8158 reg = <0 0x17801000 0x1000>, 8159 <0 0x17802000 0x1000>; 8160 8161 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8162 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8163 8164 frame-number = <0>; 8165 }; 8166 8167 frame@17803000 { 8168 reg = <0 0x17803000 0x1000>; 8169 8170 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8171 8172 frame-number = <1>; 8173 8174 status = "disabled"; 8175 }; 8176 8177 frame@17805000 { 8178 reg = <0 0x17805000 0x1000>; 8179 8180 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8181 8182 frame-number = <2>; 8183 8184 status = "disabled"; 8185 }; 8186 8187 frame@17807000 { 8188 reg = <0 0x17807000 0x1000>; 8189 8190 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8191 8192 frame-number = <3>; 8193 8194 status = "disabled"; 8195 }; 8196 8197 frame@17809000 { 8198 reg = <0 0x17809000 0x1000>; 8199 8200 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8201 8202 frame-number = <4>; 8203 8204 status = "disabled"; 8205 }; 8206 8207 frame@1780b000 { 8208 reg = <0 0x1780b000 0x1000>; 8209 8210 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8211 8212 frame-number = <5>; 8213 8214 status = "disabled"; 8215 }; 8216 8217 frame@1780d000 { 8218 reg = <0 0x1780d000 0x1000>; 8219 8220 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8221 8222 frame-number = <6>; 8223 8224 status = "disabled"; 8225 }; 8226 }; 8227 8228 sram: sram@18b4e000 { 8229 compatible = "mmio-sram"; 8230 reg = <0x0 0x18b4e000 0x0 0x400>; 8231 8232 #address-cells = <1>; 8233 #size-cells = <1>; 8234 ranges = <0x0 0x0 0x18b4e000 0x400>; 8235 8236 cpu_scp_lpri0: scp-sram-section@0 { 8237 compatible = "arm,scmi-shmem"; 8238 reg = <0x0 0x200>; 8239 }; 8240 8241 cpu_scp_lpri1: scp-sram-section@200 { 8242 compatible = "arm,scmi-shmem"; 8243 reg = <0x200 0x200>; 8244 }; 8245 }; 8246 8247 sbsa_watchdog: watchdog@1c840000 { 8248 compatible = "arm,sbsa-gwdt"; 8249 reg = <0 0x1c840000 0 0x1000>, 8250 <0 0x1c850000 0 0x1000>; 8251 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8252 }; 8253 8254 pmu@24091000 { 8255 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 8256 reg = <0 0x24091000 0 0x1000>; 8257 8258 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 8259 8260 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 8261 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 8262 8263 operating-points-v2 = <&llcc_bwmon_opp_table>; 8264 8265 llcc_bwmon_opp_table: opp-table { 8266 compatible = "operating-points-v2"; 8267 8268 opp-0 { 8269 opp-peak-kBps = <800000>; 8270 }; 8271 8272 opp-1 { 8273 opp-peak-kBps = <2188000>; 8274 }; 8275 8276 opp-2 { 8277 opp-peak-kBps = <3072000>; 8278 }; 8279 8280 opp-3 { 8281 opp-peak-kBps = <6220800>; 8282 }; 8283 8284 opp-4 { 8285 opp-peak-kBps = <6835200>; 8286 }; 8287 8288 opp-5 { 8289 opp-peak-kBps = <8371200>; 8290 }; 8291 8292 opp-6 { 8293 opp-peak-kBps = <10944000>; 8294 }; 8295 8296 opp-7 { 8297 opp-peak-kBps = <12748800>; 8298 }; 8299 8300 opp-8 { 8301 opp-peak-kBps = <14745600>; 8302 }; 8303 8304 opp-9 { 8305 opp-peak-kBps = <16896000>; 8306 }; 8307 }; 8308 }; 8309 8310 /* cluster0 */ 8311 bwmon_cluster0: pmu@240b3400 { 8312 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8313 reg = <0 0x240b3400 0 0x600>; 8314 8315 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8316 8317 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8318 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8319 8320 operating-points-v2 = <&cpu_bwmon_opp_table>; 8321 }; 8322 8323 /* cluster2 */ 8324 bwmon_cluster2: pmu@240b5400 { 8325 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8326 reg = <0 0x240b5400 0 0x600>; 8327 8328 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8329 8330 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8331 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8332 8333 operating-points-v2 = <&cpu_bwmon_opp_table>; 8334 8335 cpu_bwmon_opp_table: opp-table { 8336 compatible = "operating-points-v2"; 8337 8338 opp-0 { 8339 opp-peak-kBps = <4800000>; 8340 }; 8341 8342 opp-1 { 8343 opp-peak-kBps = <7464000>; 8344 }; 8345 8346 opp-2 { 8347 opp-peak-kBps = <9600000>; 8348 }; 8349 8350 opp-3 { 8351 opp-peak-kBps = <12896000>; 8352 }; 8353 8354 opp-4 { 8355 opp-peak-kBps = <14928000>; 8356 }; 8357 8358 opp-5 { 8359 opp-peak-kBps = <17064000>; 8360 }; 8361 }; 8362 }; 8363 8364 /* cluster1 */ 8365 pmu@240b6400 { 8366 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8367 reg = <0 0x240b6400 0 0x600>; 8368 8369 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8370 8371 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8372 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8373 8374 operating-points-v2 = <&cpu_bwmon_opp_table>; 8375 }; 8376 8377 system-cache-controller@25000000 { 8378 compatible = "qcom,x1e80100-llcc"; 8379 reg = <0 0x25000000 0 0x200000>, 8380 <0 0x25200000 0 0x200000>, 8381 <0 0x25400000 0 0x200000>, 8382 <0 0x25600000 0 0x200000>, 8383 <0 0x25800000 0 0x200000>, 8384 <0 0x25a00000 0 0x200000>, 8385 <0 0x25c00000 0 0x200000>, 8386 <0 0x25e00000 0 0x200000>, 8387 <0 0x26000000 0 0x200000>, 8388 <0 0x26200000 0 0x200000>; 8389 reg-names = "llcc0_base", 8390 "llcc1_base", 8391 "llcc2_base", 8392 "llcc3_base", 8393 "llcc4_base", 8394 "llcc5_base", 8395 "llcc6_base", 8396 "llcc7_base", 8397 "llcc_broadcast_base", 8398 "llcc_broadcast_and_base"; 8399 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8400 }; 8401 8402 remoteproc_cdsp: remoteproc@32300000 { 8403 compatible = "qcom,x1e80100-cdsp-pas"; 8404 reg = <0x0 0x32300000 0x0 0x10000>; 8405 8406 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8407 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8408 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8409 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8410 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 8411 interrupt-names = "wdog", 8412 "fatal", 8413 "ready", 8414 "handover", 8415 "stop-ack"; 8416 8417 clocks = <&rpmhcc RPMH_CXO_CLK>; 8418 clock-names = "xo"; 8419 8420 power-domains = <&rpmhpd RPMHPD_CX>, 8421 <&rpmhpd RPMHPD_MXC>, 8422 <&rpmhpd RPMHPD_NSP>; 8423 power-domain-names = "cx", 8424 "mxc", 8425 "nsp"; 8426 8427 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8428 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8429 8430 memory-region = <&cdsp_mem>, 8431 <&q6_cdsp_dtb_mem>; 8432 8433 qcom,qmp = <&aoss_qmp>; 8434 8435 qcom,smem-states = <&smp2p_cdsp_out 0>; 8436 qcom,smem-state-names = "stop"; 8437 8438 status = "disabled"; 8439 8440 glink-edge { 8441 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8442 IPCC_MPROC_SIGNAL_GLINK_QMP 8443 IRQ_TYPE_EDGE_RISING>; 8444 mboxes = <&ipcc IPCC_CLIENT_CDSP 8445 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8446 8447 label = "cdsp"; 8448 qcom,remote-pid = <5>; 8449 8450 fastrpc { 8451 compatible = "qcom,fastrpc"; 8452 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8453 label = "cdsp"; 8454 qcom,non-secure-domain; 8455 #address-cells = <1>; 8456 #size-cells = <0>; 8457 8458 compute-cb@1 { 8459 compatible = "qcom,fastrpc-compute-cb"; 8460 reg = <1>; 8461 iommus = <&apps_smmu 0x0c01 0x20>; 8462 dma-coherent; 8463 }; 8464 8465 compute-cb@2 { 8466 compatible = "qcom,fastrpc-compute-cb"; 8467 reg = <2>; 8468 iommus = <&apps_smmu 0x0c02 0x20>; 8469 dma-coherent; 8470 }; 8471 8472 compute-cb@3 { 8473 compatible = "qcom,fastrpc-compute-cb"; 8474 reg = <3>; 8475 iommus = <&apps_smmu 0x0c03 0x20>; 8476 dma-coherent; 8477 }; 8478 8479 compute-cb@4 { 8480 compatible = "qcom,fastrpc-compute-cb"; 8481 reg = <4>; 8482 iommus = <&apps_smmu 0x0c04 0x20>; 8483 dma-coherent; 8484 }; 8485 8486 compute-cb@5 { 8487 compatible = "qcom,fastrpc-compute-cb"; 8488 reg = <5>; 8489 iommus = <&apps_smmu 0x0c05 0x20>; 8490 dma-coherent; 8491 }; 8492 8493 compute-cb@6 { 8494 compatible = "qcom,fastrpc-compute-cb"; 8495 reg = <6>; 8496 iommus = <&apps_smmu 0x0c06 0x20>; 8497 dma-coherent; 8498 }; 8499 8500 compute-cb@7 { 8501 compatible = "qcom,fastrpc-compute-cb"; 8502 reg = <7>; 8503 iommus = <&apps_smmu 0x0c07 0x20>; 8504 dma-coherent; 8505 }; 8506 8507 compute-cb@8 { 8508 compatible = "qcom,fastrpc-compute-cb"; 8509 reg = <8>; 8510 iommus = <&apps_smmu 0x0c08 0x20>; 8511 dma-coherent; 8512 }; 8513 8514 /* note: compute-cb@9 is secure */ 8515 8516 compute-cb@10 { 8517 compatible = "qcom,fastrpc-compute-cb"; 8518 reg = <10>; 8519 iommus = <&apps_smmu 0x0c0c 0x20>; 8520 dma-coherent; 8521 }; 8522 8523 compute-cb@11 { 8524 compatible = "qcom,fastrpc-compute-cb"; 8525 reg = <11>; 8526 iommus = <&apps_smmu 0x0c0d 0x20>; 8527 dma-coherent; 8528 }; 8529 8530 compute-cb@12 { 8531 compatible = "qcom,fastrpc-compute-cb"; 8532 reg = <12>; 8533 iommus = <&apps_smmu 0x0c0e 0x20>; 8534 dma-coherent; 8535 }; 8536 8537 compute-cb@13 { 8538 compatible = "qcom,fastrpc-compute-cb"; 8539 reg = <13>; 8540 iommus = <&apps_smmu 0x0c0f 0x20>; 8541 dma-coherent; 8542 }; 8543 }; 8544 }; 8545 }; 8546 }; 8547 8548 timer { 8549 compatible = "arm,armv8-timer"; 8550 8551 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8552 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8553 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8554 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8555 }; 8556 8557 thermal_zones: thermal-zones { 8558 aoss0-thermal { 8559 thermal-sensors = <&tsens0 0>; 8560 8561 trips { 8562 trip-point0 { 8563 temperature = <90000>; 8564 hysteresis = <2000>; 8565 type = "hot"; 8566 }; 8567 8568 aoss0-critical { 8569 temperature = <115000>; 8570 hysteresis = <1000>; 8571 type = "critical"; 8572 }; 8573 }; 8574 }; 8575 8576 cpu0-0-top-thermal { 8577 thermal-sensors = <&tsens0 1>; 8578 8579 trips { 8580 cpu-critical { 8581 temperature = <115000>; 8582 hysteresis = <1000>; 8583 type = "critical"; 8584 }; 8585 }; 8586 }; 8587 8588 cpu0-0-btm-thermal { 8589 thermal-sensors = <&tsens0 2>; 8590 8591 trips { 8592 cpu-critical { 8593 temperature = <115000>; 8594 hysteresis = <1000>; 8595 type = "critical"; 8596 }; 8597 }; 8598 }; 8599 8600 cpu0-1-top-thermal { 8601 thermal-sensors = <&tsens0 3>; 8602 8603 trips { 8604 cpu-critical { 8605 temperature = <115000>; 8606 hysteresis = <1000>; 8607 type = "critical"; 8608 }; 8609 }; 8610 }; 8611 8612 cpu0-1-btm-thermal { 8613 thermal-sensors = <&tsens0 4>; 8614 8615 trips { 8616 cpu-critical { 8617 temperature = <115000>; 8618 hysteresis = <1000>; 8619 type = "critical"; 8620 }; 8621 }; 8622 }; 8623 8624 cpu0-2-top-thermal { 8625 thermal-sensors = <&tsens0 5>; 8626 8627 trips { 8628 cpu-critical { 8629 temperature = <115000>; 8630 hysteresis = <1000>; 8631 type = "critical"; 8632 }; 8633 }; 8634 }; 8635 8636 cpu0-2-btm-thermal { 8637 thermal-sensors = <&tsens0 6>; 8638 8639 trips { 8640 cpu-critical { 8641 temperature = <115000>; 8642 hysteresis = <1000>; 8643 type = "critical"; 8644 }; 8645 }; 8646 }; 8647 8648 cpu0-3-top-thermal { 8649 thermal-sensors = <&tsens0 7>; 8650 8651 trips { 8652 cpu-critical { 8653 temperature = <115000>; 8654 hysteresis = <1000>; 8655 type = "critical"; 8656 }; 8657 }; 8658 }; 8659 8660 cpu0-3-btm-thermal { 8661 thermal-sensors = <&tsens0 8>; 8662 8663 trips { 8664 cpu-critical { 8665 temperature = <115000>; 8666 hysteresis = <1000>; 8667 type = "critical"; 8668 }; 8669 }; 8670 }; 8671 8672 cpuss0-top-thermal { 8673 thermal-sensors = <&tsens0 9>; 8674 8675 trips { 8676 cpuss2-critical { 8677 temperature = <115000>; 8678 hysteresis = <1000>; 8679 type = "critical"; 8680 }; 8681 }; 8682 }; 8683 8684 cpuss0-btm-thermal { 8685 thermal-sensors = <&tsens0 10>; 8686 8687 trips { 8688 cpuss2-critical { 8689 temperature = <115000>; 8690 hysteresis = <1000>; 8691 type = "critical"; 8692 }; 8693 }; 8694 }; 8695 8696 mem-thermal { 8697 thermal-sensors = <&tsens0 11>; 8698 8699 trips { 8700 trip-point0 { 8701 temperature = <90000>; 8702 hysteresis = <2000>; 8703 type = "hot"; 8704 }; 8705 8706 mem-critical { 8707 temperature = <115000>; 8708 hysteresis = <0>; 8709 type = "critical"; 8710 }; 8711 }; 8712 }; 8713 8714 video-thermal { 8715 thermal-sensors = <&tsens0 12>; 8716 8717 trips { 8718 trip-point0 { 8719 temperature = <90000>; 8720 hysteresis = <2000>; 8721 type = "hot"; 8722 }; 8723 8724 video-critical { 8725 temperature = <115000>; 8726 hysteresis = <1000>; 8727 type = "critical"; 8728 }; 8729 }; 8730 }; 8731 8732 aoss1-thermal { 8733 thermal-sensors = <&tsens1 0>; 8734 8735 trips { 8736 trip-point0 { 8737 temperature = <90000>; 8738 hysteresis = <2000>; 8739 type = "hot"; 8740 }; 8741 8742 aoss0-critical { 8743 temperature = <115000>; 8744 hysteresis = <1000>; 8745 type = "critical"; 8746 }; 8747 }; 8748 }; 8749 8750 cpu1-0-top-thermal { 8751 thermal-sensors = <&tsens1 1>; 8752 8753 trips { 8754 cpu-critical { 8755 temperature = <115000>; 8756 hysteresis = <1000>; 8757 type = "critical"; 8758 }; 8759 }; 8760 }; 8761 8762 cpu1-0-btm-thermal { 8763 thermal-sensors = <&tsens1 2>; 8764 8765 trips { 8766 cpu-critical { 8767 temperature = <115000>; 8768 hysteresis = <1000>; 8769 type = "critical"; 8770 }; 8771 }; 8772 }; 8773 8774 cpu1-1-top-thermal { 8775 thermal-sensors = <&tsens1 3>; 8776 8777 trips { 8778 cpu-critical { 8779 temperature = <115000>; 8780 hysteresis = <1000>; 8781 type = "critical"; 8782 }; 8783 }; 8784 }; 8785 8786 cpu1-1-btm-thermal { 8787 thermal-sensors = <&tsens1 4>; 8788 8789 trips { 8790 cpu-critical { 8791 temperature = <115000>; 8792 hysteresis = <1000>; 8793 type = "critical"; 8794 }; 8795 }; 8796 }; 8797 8798 cpu1-2-top-thermal { 8799 thermal-sensors = <&tsens1 5>; 8800 8801 trips { 8802 cpu-critical { 8803 temperature = <115000>; 8804 hysteresis = <1000>; 8805 type = "critical"; 8806 }; 8807 }; 8808 }; 8809 8810 cpu1-2-btm-thermal { 8811 thermal-sensors = <&tsens1 6>; 8812 8813 trips { 8814 cpu-critical { 8815 temperature = <115000>; 8816 hysteresis = <1000>; 8817 type = "critical"; 8818 }; 8819 }; 8820 }; 8821 8822 cpu1-3-top-thermal { 8823 thermal-sensors = <&tsens1 7>; 8824 8825 trips { 8826 cpu-critical { 8827 temperature = <115000>; 8828 hysteresis = <1000>; 8829 type = "critical"; 8830 }; 8831 }; 8832 }; 8833 8834 cpu1-3-btm-thermal { 8835 thermal-sensors = <&tsens1 8>; 8836 8837 trips { 8838 cpu-critical { 8839 temperature = <115000>; 8840 hysteresis = <1000>; 8841 type = "critical"; 8842 }; 8843 }; 8844 }; 8845 8846 cpuss1-top-thermal { 8847 thermal-sensors = <&tsens1 9>; 8848 8849 trips { 8850 cpuss2-critical { 8851 temperature = <115000>; 8852 hysteresis = <1000>; 8853 type = "critical"; 8854 }; 8855 }; 8856 }; 8857 8858 cpuss1-btm-thermal { 8859 thermal-sensors = <&tsens1 10>; 8860 8861 trips { 8862 cpuss2-critical { 8863 temperature = <115000>; 8864 hysteresis = <1000>; 8865 type = "critical"; 8866 }; 8867 }; 8868 }; 8869 8870 aoss2-thermal { 8871 thermal-sensors = <&tsens2 0>; 8872 8873 trips { 8874 trip-point0 { 8875 temperature = <90000>; 8876 hysteresis = <2000>; 8877 type = "hot"; 8878 }; 8879 8880 aoss0-critical { 8881 temperature = <115000>; 8882 hysteresis = <1000>; 8883 type = "critical"; 8884 }; 8885 }; 8886 }; 8887 8888 cpu2-0-top-thermal { 8889 thermal-sensors = <&tsens2 1>; 8890 8891 trips { 8892 cpu-critical { 8893 temperature = <115000>; 8894 hysteresis = <1000>; 8895 type = "critical"; 8896 }; 8897 }; 8898 }; 8899 8900 cpu2-0-btm-thermal { 8901 thermal-sensors = <&tsens2 2>; 8902 8903 trips { 8904 cpu-critical { 8905 temperature = <115000>; 8906 hysteresis = <1000>; 8907 type = "critical"; 8908 }; 8909 }; 8910 }; 8911 8912 cpu2-1-top-thermal { 8913 thermal-sensors = <&tsens2 3>; 8914 8915 trips { 8916 cpu-critical { 8917 temperature = <115000>; 8918 hysteresis = <1000>; 8919 type = "critical"; 8920 }; 8921 }; 8922 }; 8923 8924 cpu2-1-btm-thermal { 8925 thermal-sensors = <&tsens2 4>; 8926 8927 trips { 8928 cpu-critical { 8929 temperature = <115000>; 8930 hysteresis = <1000>; 8931 type = "critical"; 8932 }; 8933 }; 8934 }; 8935 8936 cpu2-2-top-thermal { 8937 thermal-sensors = <&tsens2 5>; 8938 8939 trips { 8940 cpu-critical { 8941 temperature = <115000>; 8942 hysteresis = <1000>; 8943 type = "critical"; 8944 }; 8945 }; 8946 }; 8947 8948 cpu2-2-btm-thermal { 8949 thermal-sensors = <&tsens2 6>; 8950 8951 trips { 8952 cpu-critical { 8953 temperature = <115000>; 8954 hysteresis = <1000>; 8955 type = "critical"; 8956 }; 8957 }; 8958 }; 8959 8960 cpu2-3-top-thermal { 8961 thermal-sensors = <&tsens2 7>; 8962 8963 trips { 8964 cpu-critical { 8965 temperature = <115000>; 8966 hysteresis = <1000>; 8967 type = "critical"; 8968 }; 8969 }; 8970 }; 8971 8972 cpu2-3-btm-thermal { 8973 thermal-sensors = <&tsens2 8>; 8974 8975 trips { 8976 cpu-critical { 8977 temperature = <115000>; 8978 hysteresis = <1000>; 8979 type = "critical"; 8980 }; 8981 }; 8982 }; 8983 8984 cpuss2-top-thermal { 8985 thermal-sensors = <&tsens2 9>; 8986 8987 trips { 8988 cpuss2-critical { 8989 temperature = <115000>; 8990 hysteresis = <1000>; 8991 type = "critical"; 8992 }; 8993 }; 8994 }; 8995 8996 cpuss2-btm-thermal { 8997 thermal-sensors = <&tsens2 10>; 8998 8999 trips { 9000 cpuss2-critical { 9001 temperature = <115000>; 9002 hysteresis = <1000>; 9003 type = "critical"; 9004 }; 9005 }; 9006 }; 9007 9008 aoss3-thermal { 9009 thermal-sensors = <&tsens3 0>; 9010 9011 trips { 9012 trip-point0 { 9013 temperature = <90000>; 9014 hysteresis = <2000>; 9015 type = "hot"; 9016 }; 9017 9018 aoss0-critical { 9019 temperature = <115000>; 9020 hysteresis = <1000>; 9021 type = "critical"; 9022 }; 9023 }; 9024 }; 9025 9026 nsp0-thermal { 9027 thermal-sensors = <&tsens3 1>; 9028 9029 trips { 9030 trip-point0 { 9031 temperature = <90000>; 9032 hysteresis = <2000>; 9033 type = "hot"; 9034 }; 9035 9036 nsp0-critical { 9037 temperature = <115000>; 9038 hysteresis = <1000>; 9039 type = "critical"; 9040 }; 9041 }; 9042 }; 9043 9044 nsp1-thermal { 9045 thermal-sensors = <&tsens3 2>; 9046 9047 trips { 9048 trip-point0 { 9049 temperature = <90000>; 9050 hysteresis = <2000>; 9051 type = "hot"; 9052 }; 9053 9054 nsp1-critical { 9055 temperature = <115000>; 9056 hysteresis = <1000>; 9057 type = "critical"; 9058 }; 9059 }; 9060 }; 9061 9062 nsp2-thermal { 9063 thermal-sensors = <&tsens3 3>; 9064 9065 trips { 9066 trip-point0 { 9067 temperature = <90000>; 9068 hysteresis = <2000>; 9069 type = "hot"; 9070 }; 9071 9072 nsp2-critical { 9073 temperature = <115000>; 9074 hysteresis = <1000>; 9075 type = "critical"; 9076 }; 9077 }; 9078 }; 9079 9080 nsp3-thermal { 9081 thermal-sensors = <&tsens3 4>; 9082 9083 trips { 9084 trip-point0 { 9085 temperature = <90000>; 9086 hysteresis = <2000>; 9087 type = "hot"; 9088 }; 9089 9090 nsp3-critical { 9091 temperature = <115000>; 9092 hysteresis = <1000>; 9093 type = "critical"; 9094 }; 9095 }; 9096 }; 9097 9098 gpuss-0-thermal { 9099 polling-delay-passive = <200>; 9100 9101 thermal-sensors = <&tsens3 5>; 9102 9103 cooling-maps { 9104 map0 { 9105 trip = <&gpuss0_alert0>; 9106 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9107 }; 9108 }; 9109 9110 trips { 9111 gpuss0_alert0: trip-point0 { 9112 temperature = <95000>; 9113 hysteresis = <1000>; 9114 type = "passive"; 9115 }; 9116 9117 gpu-critical { 9118 temperature = <115000>; 9119 hysteresis = <1000>; 9120 type = "critical"; 9121 }; 9122 }; 9123 }; 9124 9125 gpuss-1-thermal { 9126 polling-delay-passive = <200>; 9127 9128 thermal-sensors = <&tsens3 6>; 9129 9130 cooling-maps { 9131 map0 { 9132 trip = <&gpuss1_alert0>; 9133 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9134 }; 9135 }; 9136 9137 trips { 9138 gpuss1_alert0: trip-point0 { 9139 temperature = <95000>; 9140 hysteresis = <1000>; 9141 type = "passive"; 9142 }; 9143 9144 gpu-critical { 9145 temperature = <115000>; 9146 hysteresis = <1000>; 9147 type = "critical"; 9148 }; 9149 }; 9150 }; 9151 9152 gpuss-2-thermal { 9153 polling-delay-passive = <200>; 9154 9155 thermal-sensors = <&tsens3 7>; 9156 9157 cooling-maps { 9158 map0 { 9159 trip = <&gpuss2_alert0>; 9160 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9161 }; 9162 }; 9163 9164 trips { 9165 gpuss2_alert0: trip-point0 { 9166 temperature = <95000>; 9167 hysteresis = <1000>; 9168 type = "passive"; 9169 }; 9170 9171 gpu-critical { 9172 temperature = <115000>; 9173 hysteresis = <1000>; 9174 type = "critical"; 9175 }; 9176 }; 9177 }; 9178 9179 gpuss-3-thermal { 9180 polling-delay-passive = <200>; 9181 9182 thermal-sensors = <&tsens3 8>; 9183 9184 cooling-maps { 9185 map0 { 9186 trip = <&gpuss3_alert0>; 9187 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9188 }; 9189 }; 9190 9191 trips { 9192 gpuss3_alert0: trip-point0 { 9193 temperature = <95000>; 9194 hysteresis = <1000>; 9195 type = "passive"; 9196 }; 9197 9198 gpu-critical { 9199 temperature = <115000>; 9200 hysteresis = <1000>; 9201 type = "critical"; 9202 }; 9203 }; 9204 }; 9205 9206 gpuss-4-thermal { 9207 polling-delay-passive = <200>; 9208 9209 thermal-sensors = <&tsens3 9>; 9210 9211 cooling-maps { 9212 map0 { 9213 trip = <&gpuss4_alert0>; 9214 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9215 }; 9216 }; 9217 9218 trips { 9219 gpuss4_alert0: trip-point0 { 9220 temperature = <95000>; 9221 hysteresis = <1000>; 9222 type = "passive"; 9223 }; 9224 9225 gpu-critical { 9226 temperature = <115000>; 9227 hysteresis = <1000>; 9228 type = "critical"; 9229 }; 9230 }; 9231 }; 9232 9233 gpuss-5-thermal { 9234 polling-delay-passive = <200>; 9235 9236 thermal-sensors = <&tsens3 10>; 9237 9238 cooling-maps { 9239 map0 { 9240 trip = <&gpuss5_alert0>; 9241 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9242 }; 9243 }; 9244 9245 trips { 9246 gpuss5_alert0: trip-point0 { 9247 temperature = <95000>; 9248 hysteresis = <1000>; 9249 type = "passive"; 9250 }; 9251 9252 gpu-critical { 9253 temperature = <115000>; 9254 hysteresis = <1000>; 9255 type = "critical"; 9256 }; 9257 }; 9258 }; 9259 9260 gpuss-6-thermal { 9261 polling-delay-passive = <200>; 9262 9263 thermal-sensors = <&tsens3 11>; 9264 9265 cooling-maps { 9266 map0 { 9267 trip = <&gpuss6_alert0>; 9268 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9269 }; 9270 }; 9271 9272 trips { 9273 gpuss6_alert0: trip-point0 { 9274 temperature = <95000>; 9275 hysteresis = <1000>; 9276 type = "passive"; 9277 }; 9278 9279 gpu-critical { 9280 temperature = <115000>; 9281 hysteresis = <1000>; 9282 type = "critical"; 9283 }; 9284 }; 9285 }; 9286 9287 gpuss-7-thermal { 9288 polling-delay-passive = <200>; 9289 9290 thermal-sensors = <&tsens3 12>; 9291 9292 cooling-maps { 9293 map0 { 9294 trip = <&gpuss7_alert0>; 9295 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9296 }; 9297 }; 9298 9299 trips { 9300 gpuss7_alert0: trip-point0 { 9301 temperature = <95000>; 9302 hysteresis = <1000>; 9303 type = "passive"; 9304 }; 9305 9306 gpu-critical { 9307 temperature = <115000>; 9308 hysteresis = <1000>; 9309 type = "critical"; 9310 }; 9311 }; 9312 }; 9313 9314 camera0-thermal { 9315 thermal-sensors = <&tsens3 13>; 9316 9317 trips { 9318 trip-point0 { 9319 temperature = <90000>; 9320 hysteresis = <2000>; 9321 type = "hot"; 9322 }; 9323 9324 camera0-critical { 9325 temperature = <115000>; 9326 hysteresis = <1000>; 9327 type = "critical"; 9328 }; 9329 }; 9330 }; 9331 9332 camera1-thermal { 9333 thermal-sensors = <&tsens3 14>; 9334 9335 trips { 9336 trip-point0 { 9337 temperature = <90000>; 9338 hysteresis = <2000>; 9339 type = "hot"; 9340 }; 9341 9342 camera0-critical { 9343 temperature = <115000>; 9344 hysteresis = <1000>; 9345 type = "critical"; 9346 }; 9347 }; 9348 }; 9349 }; 9350}; 9351