1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8750-gcc.h> 8#include <dt-bindings/clock/qcom,sm8750-tcsr.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/power/qcom,rpmhpd.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,gpr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "qcom,oryon"; 34 reg = <0x0 0x0>; 35 enable-method = "psci"; 36 next-level-cache = <&l2_0>; 37 power-domains = <&cpu_pd0>; 38 power-domain-names = "psci"; 39 40 l2_0: l2-cache { 41 compatible = "cache"; 42 cache-level = <2>; 43 cache-unified; 44 }; 45 }; 46 47 cpu1: cpu@100 { 48 device_type = "cpu"; 49 compatible = "qcom,oryon"; 50 reg = <0x0 0x100>; 51 enable-method = "psci"; 52 next-level-cache = <&l2_0>; 53 power-domains = <&cpu_pd1>; 54 power-domain-names = "psci"; 55 }; 56 57 cpu2: cpu@200 { 58 device_type = "cpu"; 59 compatible = "qcom,oryon"; 60 reg = <0x0 0x200>; 61 enable-method = "psci"; 62 next-level-cache = <&l2_0>; 63 power-domains = <&cpu_pd2>; 64 power-domain-names = "psci"; 65 }; 66 67 cpu3: cpu@300 { 68 device_type = "cpu"; 69 compatible = "qcom,oryon"; 70 reg = <0x0 0x300>; 71 enable-method = "psci"; 72 next-level-cache = <&l2_0>; 73 power-domains = <&cpu_pd3>; 74 power-domain-names = "psci"; 75 }; 76 77 cpu4: cpu@400 { 78 device_type = "cpu"; 79 compatible = "qcom,oryon"; 80 reg = <0x0 0x400>; 81 enable-method = "psci"; 82 next-level-cache = <&l2_0>; 83 power-domains = <&cpu_pd4>; 84 power-domain-names = "psci"; 85 }; 86 87 cpu5: cpu@500 { 88 device_type = "cpu"; 89 compatible = "qcom,oryon"; 90 reg = <0x0 0x500>; 91 enable-method = "psci"; 92 next-level-cache = <&l2_0>; 93 power-domains = <&cpu_pd5>; 94 power-domain-names = "psci"; 95 }; 96 97 cpu6: cpu@10000 { 98 device_type = "cpu"; 99 compatible = "qcom,oryon"; 100 reg = <0x0 0x10000>; 101 enable-method = "psci"; 102 next-level-cache = <&l2_1>; 103 power-domains = <&cpu_pd6>; 104 power-domain-names = "psci"; 105 106 l2_1: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 cache-unified; 110 }; 111 }; 112 113 cpu7: cpu@10100 { 114 device_type = "cpu"; 115 compatible = "qcom,oryon"; 116 reg = <0x0 0x10100>; 117 enable-method = "psci"; 118 next-level-cache = <&l2_1>; 119 power-domains = <&cpu_pd7>; 120 power-domain-names = "psci"; 121 }; 122 123 cpu-map { 124 cluster0 { 125 core0 { 126 cpu = <&cpu0>; 127 }; 128 129 core1 { 130 cpu = <&cpu1>; 131 }; 132 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 137 core3 { 138 cpu = <&cpu3>; 139 }; 140 141 core4 { 142 cpu = <&cpu4>; 143 }; 144 145 core5 { 146 cpu = <&cpu5>; 147 }; 148 }; 149 150 cluster1 { 151 core0 { 152 cpu = <&cpu6>; 153 }; 154 155 core1 { 156 cpu = <&cpu7>; 157 }; 158 }; 159 }; 160 161 idle-states { 162 entry-method = "psci"; 163 164 cluster0_c4: cpu-sleep-0 { 165 compatible = "arm,idle-state"; 166 idle-state-name = "ret"; 167 arm,psci-suspend-param = <0x00000004>; 168 entry-latency-us = <93>; 169 exit-latency-us = <129>; 170 min-residency-us = <560>; 171 }; 172 173 cluster1_c4: cpu-sleep-1 { 174 compatible = "arm,idle-state"; 175 idle-state-name = "ret"; 176 arm,psci-suspend-param = <0x00000004>; 177 entry-latency-us = <172>; 178 exit-latency-us = <130>; 179 min-residency-us = <686>; 180 }; 181 }; 182 183 domain-idle-states { 184 cluster_cl5: cluster-sleep-0 { 185 compatible = "domain-idle-state"; 186 arm,psci-suspend-param = <0x01000054>; 187 entry-latency-us = <2150>; 188 exit-latency-us = <1983>; 189 min-residency-us = <9144>; 190 }; 191 192 domain_ss3: domain-sleep-0 { 193 compatible = "domain-idle-state"; 194 arm,psci-suspend-param = <0x0200c354>; 195 entry-latency-us = <2800>; 196 exit-latency-us = <4400>; 197 min-residency-us = <10150>; 198 }; 199 }; 200 }; 201 202 firmware { 203 scm: scm { 204 compatible = "qcom,scm-sm8750", "qcom,scm"; 205 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 206 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 207 }; 208 }; 209 210 clk_virt: interconnect-0 { 211 compatible = "qcom,sm8750-clk-virt"; 212 #interconnect-cells = <2>; 213 qcom,bcm-voters = <&apps_bcm_voter>; 214 }; 215 216 mc_virt: interconnect-1 { 217 compatible = "qcom,sm8750-mc-virt"; 218 #interconnect-cells = <2>; 219 qcom,bcm-voters = <&apps_bcm_voter>; 220 }; 221 222 memory@a0000000 { 223 device_type = "memory"; 224 /* We expect the bootloader to fill in the size */ 225 reg = <0x0 0xa0000000 0x0 0x0>; 226 }; 227 228 pmu { 229 compatible = "arm,armv8-pmuv3"; 230 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 231 }; 232 233 psci { 234 compatible = "arm,psci-1.0"; 235 method = "smc"; 236 237 cpu_pd0: power-domain-cpu0 { 238 #power-domain-cells = <0>; 239 power-domains = <&cluster0_pd>; 240 domain-idle-states = <&cluster0_c4>; 241 }; 242 243 cpu_pd1: power-domain-cpu1 { 244 #power-domain-cells = <0>; 245 power-domains = <&cluster0_pd>; 246 domain-idle-states = <&cluster0_c4>; 247 }; 248 249 cpu_pd2: power-domain-cpu2 { 250 #power-domain-cells = <0>; 251 power-domains = <&cluster0_pd>; 252 domain-idle-states = <&cluster0_c4>; 253 }; 254 255 cpu_pd3: power-domain-cpu3 { 256 #power-domain-cells = <0>; 257 power-domains = <&cluster0_pd>; 258 domain-idle-states = <&cluster0_c4>; 259 }; 260 261 cpu_pd4: power-domain-cpu4 { 262 #power-domain-cells = <0>; 263 power-domains = <&cluster0_pd>; 264 domain-idle-states = <&cluster0_c4>; 265 }; 266 267 cpu_pd5: power-domain-cpu5 { 268 #power-domain-cells = <0>; 269 power-domains = <&cluster0_pd>; 270 domain-idle-states = <&cluster0_c4>; 271 }; 272 273 cpu_pd6: power-domain-cpu6 { 274 #power-domain-cells = <0>; 275 power-domains = <&cluster1_pd>; 276 domain-idle-states = <&cluster1_c4>; 277 }; 278 279 cpu_pd7: power-domain-cpu7 { 280 #power-domain-cells = <0>; 281 power-domains = <&cluster1_pd>; 282 domain-idle-states = <&cluster1_c4>; 283 }; 284 285 cluster0_pd: power-domain-cluster0 { 286 #power-domain-cells = <0>; 287 domain-idle-states = <&cluster_cl5>; 288 power-domains = <&system_pd>; 289 }; 290 291 cluster1_pd: power-domain-cluster1 { 292 #power-domain-cells = <0>; 293 domain-idle-states = <&cluster_cl5>; 294 power-domains = <&system_pd>; 295 }; 296 297 system_pd: power-domain-system { 298 #power-domain-cells = <0>; 299 domain-idle-states = <&domain_ss3>; 300 }; 301 }; 302 303 reserved-memory { 304 #address-cells = <2>; 305 #size-cells = <2>; 306 ranges; 307 308 gunyah_hyp_mem: gunyah-hyp@80000000 { 309 reg = <0x0 0x80000000 0x0 0xe00000>; 310 no-map; 311 }; 312 313 cpusys_vm_mem: cpusys-vm-mem@80e00000 { 314 reg = <0x0 0x80e00000 0x0 0x40000>; 315 no-map; 316 }; 317 318 cpucp_mem: cpucp@81200000 { 319 reg = <0x0 0x81200000 0x0 0x200000>; 320 no-map; 321 }; 322 323 xbl_dtlog_mem: xbl-dtlog@81a00000 { 324 reg = <0x0 0x81a00000 0x0 0x40000>; 325 no-map; 326 }; 327 328 aop_image_mem: aop-image@81c00000 { 329 reg = <0x0 0x81c00000 0x0 0x60000>; 330 no-map; 331 }; 332 333 aop_cmd_db_mem: aop-cmd-db@81c60000 { 334 compatible = "qcom,cmd-db"; 335 reg = <0x0 0x81c60000 0x0 0x20000>; 336 no-map; 337 }; 338 339 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 340 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 341 reg = <0x0 0x81c80000 0x0 0x74000>; 342 no-map; 343 }; 344 345 /* Secdata region can be reused by apps */ 346 347 smem_mem: smem@81d00000 { 348 compatible = "qcom,smem"; 349 reg = <0x0 0x81d00000 0x0 0x200000>; 350 hwlocks = <&tcsr_mutex 3>; 351 no-map; 352 }; 353 354 pdp_ns_shared_mem: pdp-ns-shared@81f00000 { 355 reg = <0x0 0x81f00000 0x0 0x100000>; 356 no-map; 357 }; 358 359 cpucp_scandump_mem: cpucp-scandump@82000000 { 360 reg = <0x0 0x82000000 0x0 0x380000>; 361 no-map; 362 }; 363 364 adsp_mhi_mem: adsp-mhi@82380000 { 365 reg = <0x0 0x82380000 0x0 0x20000>; 366 no-map; 367 }; 368 369 soccp_sdi_mem: soccp-sdi@823a0000 { 370 reg = <0x0 0x823a0000 0x0 0x40000>; 371 no-map; 372 }; 373 374 pmic_minii_dump_mem: pmic-minii-dump@823e0000 { 375 reg = <0x0 0x823e0000 0x0 0x80000>; 376 no-map; 377 }; 378 379 pvmfw_mem: pvmfw@824a0000 { 380 reg = <0x0 0x824a0000 0x0 0x100000>; 381 no-map; 382 }; 383 384 global_sync_mem: global-sync@82600000 { 385 reg = <0x0 0x82600000 0x0 0x100000>; 386 no-map; 387 }; 388 389 tz_stat_mem: tz-stat@82700000 { 390 reg = <0x0 0x82700000 0x0 0x100000>; 391 no-map; 392 }; 393 394 qdss_mem: qdss@82800000 { 395 reg = <0x0 0x82800000 0x0 0x2000000>; 396 no-map; 397 }; 398 399 dsm_partition_1_mem: dsm-partition-1@84a00000 { 400 reg = <0x0 0x84a00000 0x0 0x4900000>; 401 no-map; 402 }; 403 404 dsm_partition_2_mem: dsm-partition-2@89300000 { 405 reg = <0x0 0x89300000 0x0 0xa80000>; 406 no-map; 407 }; 408 409 mpss_mem: mpss@8ba00000 { 410 reg = <0x0 0x8ba00000 0x0 0xf600000>; 411 no-map; 412 }; 413 414 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 415 reg = <0x0 0x9b000000 0x0 0x80000>; 416 no-map; 417 }; 418 419 ipa_fw_mem: ipa-fw@9b080000 { 420 reg = <0x0 0x9b080000 0x0 0x10000>; 421 no-map; 422 }; 423 424 ipa_gsi_mem: ipa-gsi@9b090000 { 425 reg = <0x0 0x9b090000 0x0 0xa000>; 426 no-map; 427 }; 428 429 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 430 reg = <0x0 0x9b09a000 0x0 0x2000>; 431 no-map; 432 }; 433 434 spss_region_mem: spss@9b0a0000 { 435 reg = <0x0 0x9b0a0000 0x0 0x1e0000>; 436 no-map; 437 }; 438 439 /* First part of the "SPU secure shared memory" region */ 440 spu_tz_shared_mem: spu-tz-shared@9b280000 { 441 reg = <0x0 0x9b280000 0x0 0x40000>; 442 no-map; 443 }; 444 445 /* Second part of the "SPU secure shared memory" region */ 446 spu_modem_shared_mem: spu-modem-shared@9b2c0000 { 447 reg = <0x0 0x9b2c0000 0x0 0x40000>; 448 no-map; 449 }; 450 451 camera_mem: camera@9b300000 { 452 reg = <0x0 0x9b300000 0x0 0x800000>; 453 no-map; 454 }; 455 456 camera_2_mem: camera-2@9bb00000 { 457 reg = <0x0 0x9bb00000 0x0 0x800000>; 458 no-map; 459 }; 460 461 video_mem: video@9c300000 { 462 reg = <0x0 0x9c300000 0x0 0x800000>; 463 no-map; 464 }; 465 466 cvp_mem: cvp@9cb00000 { 467 reg = <0x0 0x9cb00000 0x0 0x700000>; 468 no-map; 469 }; 470 471 cdsp_mem: cdsp@9d200000 { 472 reg = <0x0 0x9d200000 0x0 0x1900000>; 473 no-map; 474 }; 475 476 q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 { 477 reg = <0x0 0x9eb00000 0x0 0x80000>; 478 no-map; 479 }; 480 481 soccp_mem: soccp@9ec00000 { 482 reg = <0x0 0x9ec00000 0x0 0x180000>; 483 no-map; 484 }; 485 486 q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 { 487 reg = <0x0 0x9ed80000 0x0 0x80000>; 488 no-map; 489 }; 490 491 adspslpi_mem: adspslpi@9ee00000 { 492 reg = <0x0 0x9ee00000 0x0 0x3a80000>; 493 no-map; 494 }; 495 496 xbl_ramdump_mem: xbl-ramdump@b8000000 { 497 reg = <0x0 0xb8000000 0x0 0x1c0000>; 498 no-map; 499 }; 500 501 hwfence_shbuf: hwfence-shbuf@d4e23000 { 502 no-map; 503 reg = <0x0 0xd4e23000 0x0 0x2dd000>; 504 }; 505 506 /* Merged tz_reserved, xbl_sc, and qtee regions */ 507 tz_merged_mem: tz-merged@d8000000 { 508 reg = <0x0 0xd8000000 0x0 0x600000>; 509 no-map; 510 }; 511 512 trust_ui_vm_mem: trust-ui-vm@f3800000 { 513 reg = <0x0 0xf3800000 0x0 0x4400000>; 514 no-map; 515 }; 516 517 oem_vm_mem: oem-vm@f7c00000 { 518 reg = <0x0 0xf7c00000 0x0 0x4c00000>; 519 no-map; 520 }; 521 522 llcc_lpi_mem: llcc-lpi@ff800000 { 523 reg = <0x0 0xff800000 0x0 0x800000>; 524 no-map; 525 }; 526 }; 527 528 smp2p-adsp { 529 compatible = "qcom,smp2p"; 530 531 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 532 IPCC_MPROC_SIGNAL_SMP2P 533 IRQ_TYPE_EDGE_RISING>; 534 535 mboxes = <&ipcc IPCC_CLIENT_LPASS 536 IPCC_MPROC_SIGNAL_SMP2P>; 537 538 qcom,smem = <443>, <429>; 539 qcom,local-pid = <0>; 540 qcom,remote-pid = <2>; 541 542 smp2p_adsp_out: master-kernel { 543 qcom,entry-name = "master-kernel"; 544 #qcom,smem-state-cells = <1>; 545 }; 546 547 smp2p_adsp_in: slave-kernel { 548 qcom,entry-name = "slave-kernel"; 549 interrupt-controller; 550 #interrupt-cells = <2>; 551 }; 552 }; 553 554 smp2p-cdsp { 555 compatible = "qcom,smp2p"; 556 557 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 558 IPCC_MPROC_SIGNAL_SMP2P 559 IRQ_TYPE_EDGE_RISING>; 560 561 mboxes = <&ipcc IPCC_CLIENT_CDSP 562 IPCC_MPROC_SIGNAL_SMP2P>; 563 564 qcom,smem = <94>, <432>; 565 qcom,local-pid = <0>; 566 qcom,remote-pid = <5>; 567 568 smp2p_cdsp_out: master-kernel { 569 qcom,entry-name = "master-kernel"; 570 #qcom,smem-state-cells = <1>; 571 }; 572 573 smp2p_cdsp_in: slave-kernel { 574 qcom,entry-name = "slave-kernel"; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 }; 578 }; 579 580 smp2p-modem { 581 compatible = "qcom,smp2p"; 582 583 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 584 IPCC_MPROC_SIGNAL_SMP2P 585 IRQ_TYPE_EDGE_RISING>; 586 587 mboxes = <&ipcc IPCC_CLIENT_MPSS 588 IPCC_MPROC_SIGNAL_SMP2P>; 589 590 qcom,smem = <435>, <428>; 591 qcom,local-pid = <0>; 592 qcom,remote-pid = <1>; 593 594 smp2p_modem_out: master-kernel { 595 qcom,entry-name = "master-kernel"; 596 #qcom,smem-state-cells = <1>; 597 }; 598 599 smp2p_modem_in: slave-kernel { 600 qcom,entry-name = "slave-kernel"; 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 }; 604 605 ipa_smp2p_out: ipa-ap-to-modem { 606 qcom,entry-name = "ipa"; 607 #qcom,smem-state-cells = <1>; 608 }; 609 610 ipa_smp2p_in: ipa-modem-to-ap { 611 qcom,entry-name = "ipa"; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 }; 615 616 /* TODO: smem mailbox in and out */ 617 }; 618 619 soc: soc@0 { 620 compatible = "simple-bus"; 621 622 #address-cells = <2>; 623 #size-cells = <2>; 624 dma-ranges = <0 0 0 0 0x10 0>; 625 ranges = <0 0 0 0 0x10 0>; 626 627 gcc: clock-controller@100000 { 628 compatible = "qcom,sm8750-gcc"; 629 reg = <0x0 0x00100000 0x0 0x1f4200>; 630 631 clocks = <&bi_tcxo_div2>, 632 <0>, 633 <&sleep_clk>, 634 <0>, 635 <0>, 636 <0>, 637 <0>, 638 <0>; 639 640 #clock-cells = <1>; 641 #reset-cells = <1>; 642 #power-domain-cells = <1>; 643 }; 644 645 ipcc: mailbox@406000 { 646 compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; 647 reg = <0x0 0x00406000 0x0 0x1000>; 648 649 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 650 interrupt-controller; 651 #interrupt-cells = <3>; 652 653 #mbox-cells = <2>; 654 }; 655 656 gpi_dma2: dma-controller@800000 { 657 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; 658 reg = <0x0 0x00800000 0x0 0x60000>; 659 660 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 672 673 dma-channels = <12>; 674 dma-channel-mask = <0x1e>; 675 #dma-cells = <3>; 676 677 iommus = <&apps_smmu 0x436 0x0>; 678 679 status = "disabled"; 680 }; 681 682 qupv3_2: geniqup@8c0000 { 683 compatible = "qcom,geni-se-qup"; 684 reg = <0x0 0x008c0000 0x0 0x2000>; 685 686 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 687 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 688 clock-names = "m-ahb", 689 "s-ahb"; 690 691 iommus = <&apps_smmu 0x423 0x0>; 692 693 #address-cells = <2>; 694 #size-cells = <2>; 695 ranges; 696 697 status = "disabled"; 698 699 i2c8: i2c@880000 { 700 compatible = "qcom,geni-i2c"; 701 reg = <0x0 0x00880000 0x0 0x4000>; 702 703 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 704 705 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 706 clock-names = "se"; 707 708 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 709 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 710 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 711 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 712 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 713 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 714 interconnect-names = "qup-core", 715 "qup-config", 716 "qup-memory"; 717 718 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 719 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 720 dma-names = "tx", 721 "rx"; 722 723 pinctrl-0 = <&qup_i2c8_data_clk>; 724 pinctrl-names = "default"; 725 726 #address-cells = <1>; 727 #size-cells = <0>; 728 729 status = "disabled"; 730 }; 731 732 spi8: spi@880000 { 733 compatible = "qcom,geni-spi"; 734 reg = <0x0 0x00880000 0x0 0x4000>; 735 736 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 737 738 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 739 clock-names = "se"; 740 741 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 742 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 743 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 744 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 745 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 746 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 747 interconnect-names = "qup-core", 748 "qup-config", 749 "qup-memory"; 750 751 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 752 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 753 dma-names = "tx", 754 "rx"; 755 756 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 757 pinctrl-names = "default"; 758 759 #address-cells = <1>; 760 #size-cells = <0>; 761 762 status = "disabled"; 763 }; 764 765 i2c9: i2c@884000 { 766 compatible = "qcom,geni-i2c"; 767 reg = <0x0 0x00884000 0x0 0x4000>; 768 769 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 770 771 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 772 clock-names = "se"; 773 774 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 775 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 776 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 777 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 778 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 779 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 780 interconnect-names = "qup-core", 781 "qup-config", 782 "qup-memory"; 783 784 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 785 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 786 dma-names = "tx", 787 "rx"; 788 789 pinctrl-0 = <&qup_i2c9_data_clk>; 790 pinctrl-names = "default"; 791 792 #address-cells = <1>; 793 #size-cells = <0>; 794 795 status = "disabled"; 796 }; 797 798 spi9: spi@884000 { 799 compatible = "qcom,geni-spi"; 800 reg = <0x0 0x00884000 0x0 0x4000>; 801 802 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 803 804 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 805 clock-names = "se"; 806 807 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 808 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 809 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 810 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 811 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 812 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 813 interconnect-names = "qup-core", 814 "qup-config", 815 "qup-memory"; 816 817 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 818 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 819 dma-names = "tx", 820 "rx"; 821 822 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 823 pinctrl-names = "default"; 824 825 #address-cells = <1>; 826 #size-cells = <0>; 827 828 status = "disabled"; 829 }; 830 831 i2c10: i2c@888000 { 832 compatible = "qcom,geni-i2c"; 833 reg = <0x0 0x00888000 0x0 0x4000>; 834 835 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 836 837 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 838 clock-names = "se"; 839 840 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 841 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 843 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 844 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 846 interconnect-names = "qup-core", 847 "qup-config", 848 "qup-memory"; 849 850 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 851 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 852 dma-names = "tx", 853 "rx"; 854 855 pinctrl-0 = <&qup_i2c10_data_clk>; 856 pinctrl-names = "default"; 857 858 #address-cells = <1>; 859 #size-cells = <0>; 860 861 status = "disabled"; 862 }; 863 864 spi10: spi@888000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0x0 0x00888000 0x0 0x4000>; 867 868 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 869 870 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 871 clock-names = "se"; 872 873 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 874 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 875 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 876 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 877 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 878 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 879 interconnect-names = "qup-core", 880 "qup-config", 881 "qup-memory"; 882 883 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 884 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 885 dma-names = "tx", 886 "rx"; 887 888 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 889 pinctrl-names = "default"; 890 891 #address-cells = <1>; 892 #size-cells = <0>; 893 894 status = "disabled"; 895 }; 896 897 i2c11: i2c@88c000 { 898 compatible = "qcom,geni-i2c"; 899 reg = <0x0 0x0088c000 0x0 0x4000>; 900 901 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 902 903 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 904 clock-names = "se"; 905 906 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 907 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 909 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 910 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 912 interconnect-names = "qup-core", 913 "qup-config", 914 "qup-memory"; 915 916 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 917 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 918 dma-names = "tx", 919 "rx"; 920 921 pinctrl-0 = <&qup_i2c11_data_clk>; 922 pinctrl-names = "default"; 923 924 #address-cells = <1>; 925 #size-cells = <0>; 926 927 status = "disabled"; 928 }; 929 930 spi11: spi@88c000 { 931 compatible = "qcom,geni-spi"; 932 reg = <0x0 0x0088c000 0x0 0x4000>; 933 934 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 935 936 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 937 clock-names = "se"; 938 939 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 940 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 941 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 942 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 943 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 944 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 945 interconnect-names = "qup-core", 946 "qup-config", 947 "qup-memory"; 948 949 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 950 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 951 dma-names = "tx", 952 "rx"; 953 954 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 955 pinctrl-names = "default"; 956 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 status = "disabled"; 961 }; 962 963 i2c12: i2c@890000 { 964 compatible = "qcom,geni-i2c"; 965 reg = <0x0 0x00890000 0x0 0x4000>; 966 967 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 968 969 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 970 clock-names = "se"; 971 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 973 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 975 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 976 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 978 interconnect-names = "qup-core", 979 "qup-config", 980 "qup-memory"; 981 982 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 983 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 984 dma-names = "tx", 985 "rx"; 986 987 pinctrl-0 = <&qup_i2c12_data_clk>; 988 pinctrl-names = "default"; 989 990 #address-cells = <1>; 991 #size-cells = <0>; 992 993 status = "disabled"; 994 }; 995 996 spi12: spi@890000 { 997 compatible = "qcom,geni-spi"; 998 reg = <0x0 0x00890000 0x0 0x4000>; 999 1000 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1001 1002 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1003 clock-names = "se"; 1004 1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1006 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1007 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1008 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1009 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1010 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1011 interconnect-names = "qup-core", 1012 "qup-config", 1013 "qup-memory"; 1014 1015 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1016 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1017 dma-names = "tx", 1018 "rx"; 1019 1020 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1021 pinctrl-names = "default"; 1022 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 1026 status = "disabled"; 1027 }; 1028 1029 i2c13: i2c@894000 { 1030 compatible = "qcom,geni-i2c"; 1031 reg = <0x0 0x00894000 0x0 0x4000>; 1032 1033 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1034 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1036 clock-names = "se"; 1037 1038 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1039 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1041 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1042 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1044 interconnect-names = "qup-core", 1045 "qup-config", 1046 "qup-memory"; 1047 1048 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1049 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1050 dma-names = "tx", 1051 "rx"; 1052 1053 pinctrl-0 = <&qup_i2c13_data_clk>; 1054 pinctrl-names = "default"; 1055 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 1059 status = "disabled"; 1060 }; 1061 1062 spi13: spi@894000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0x0 0x00894000 0x0 0x4000>; 1065 1066 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1067 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1069 clock-names = "se"; 1070 1071 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1072 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1074 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1075 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1076 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1077 interconnect-names = "qup-core", 1078 "qup-config", 1079 "qup-memory"; 1080 1081 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1082 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1083 dma-names = "tx", 1084 "rx"; 1085 1086 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1087 pinctrl-names = "default"; 1088 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 1092 status = "disabled"; 1093 }; 1094 1095 uart14: serial@898000 { 1096 compatible = "qcom,geni-uart"; 1097 reg = <0x0 0x00898000 0x0 0x4000>; 1098 1099 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1100 1101 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1102 clock-names = "se"; 1103 1104 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1105 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1106 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1107 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1108 interconnect-names = "qup-core", 1109 "qup-config"; 1110 1111 pinctrl-0 = <&qup_uart14_default>; 1112 pinctrl-names = "default"; 1113 1114 status = "disabled"; 1115 }; 1116 1117 i2c15: i2c@89c000 { 1118 compatible = "qcom,geni-i2c"; 1119 reg = <0x0 0x0089c000 0x0 0x4000>; 1120 1121 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1122 1123 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1124 clock-names = "se"; 1125 1126 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1127 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1128 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1129 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1130 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1131 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1132 interconnect-names = "qup-core", 1133 "qup-config", 1134 "qup-memory"; 1135 1136 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1137 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1138 dma-names = "tx", 1139 "rx"; 1140 1141 pinctrl-0 = <&qup_i2c15_data_clk>; 1142 pinctrl-names = "default"; 1143 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 1147 status = "disabled"; 1148 }; 1149 1150 spi15: spi@89c000 { 1151 compatible = "qcom,geni-spi"; 1152 reg = <0x0 0x0089c000 0x0 0x4000>; 1153 1154 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1155 1156 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1157 clock-names = "se"; 1158 1159 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1160 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1161 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1162 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1163 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1164 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1165 interconnect-names = "qup-core", 1166 "qup-config", 1167 "qup-memory"; 1168 1169 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1170 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1171 dma-names = "tx", 1172 "rx"; 1173 1174 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1175 pinctrl-names = "default"; 1176 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 1180 status = "disabled"; 1181 }; 1182 }; 1183 1184 i2c_master_hub_0: geniqup@9c0000 { 1185 compatible = "qcom,geni-se-i2c-master-hub"; 1186 reg = <0x0 0x009c0000 0x0 0x2000>; 1187 1188 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1189 clock-names = "s-ahb"; 1190 1191 #address-cells = <2>; 1192 #size-cells = <2>; 1193 ranges; 1194 1195 status = "disabled"; 1196 1197 i2c_hub_0: i2c@980000 { 1198 compatible = "qcom,geni-i2c-master-hub"; 1199 reg = <0x0 0x00980000 0x0 0x4000>; 1200 1201 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1202 1203 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1204 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1205 clock-names = "se", 1206 "core"; 1207 1208 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1209 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1210 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1211 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1212 interconnect-names = "qup-core", 1213 "qup-config"; 1214 1215 pinctrl-0 = <&hub_i2c0_data_clk>; 1216 pinctrl-names = "default"; 1217 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 1221 status = "disabled"; 1222 }; 1223 1224 i2c_hub_1: i2c@984000 { 1225 compatible = "qcom,geni-i2c-master-hub"; 1226 reg = <0x0 0x00984000 0x0 0x4000>; 1227 1228 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1229 1230 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1231 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1232 clock-names = "se", 1233 "core"; 1234 1235 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1236 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1237 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1238 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1239 interconnect-names = "qup-core", 1240 "qup-config"; 1241 1242 pinctrl-0 = <&hub_i2c1_data_clk>; 1243 pinctrl-names = "default"; 1244 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 1248 status = "disabled"; 1249 }; 1250 1251 i2c_hub_2: i2c@988000 { 1252 compatible = "qcom,geni-i2c-master-hub"; 1253 reg = <0x0 0x00988000 0x0 0x4000>; 1254 1255 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1256 1257 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1258 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1259 clock-names = "se", 1260 "core"; 1261 1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1263 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1264 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1265 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1266 interconnect-names = "qup-core", 1267 "qup-config"; 1268 1269 pinctrl-0 = <&hub_i2c2_data_clk>; 1270 pinctrl-names = "default"; 1271 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 1275 status = "disabled"; 1276 }; 1277 1278 i2c_hub_3: i2c@98c000 { 1279 compatible = "qcom,geni-i2c-master-hub"; 1280 reg = <0x0 0x0098c000 0x0 0x4000>; 1281 1282 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1283 1284 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1285 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1286 clock-names = "se", 1287 "core"; 1288 1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1290 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1291 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1292 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1293 interconnect-names = "qup-core", 1294 "qup-config"; 1295 1296 pinctrl-0 = <&hub_i2c3_data_clk>; 1297 pinctrl-names = "default"; 1298 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 1302 status = "disabled"; 1303 }; 1304 1305 i2c_hub_4: i2c@990000 { 1306 compatible = "qcom,geni-i2c-master-hub"; 1307 reg = <0x0 0x00990000 0x0 0x4000>; 1308 1309 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1310 1311 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1312 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1313 clock-names = "se", 1314 "core"; 1315 1316 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1317 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1318 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1319 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1320 interconnect-names = "qup-core", 1321 "qup-config"; 1322 1323 pinctrl-0 = <&hub_i2c4_data_clk>; 1324 pinctrl-names = "default"; 1325 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 1329 status = "disabled"; 1330 }; 1331 1332 i2c_hub_5: i2c@994000 { 1333 compatible = "qcom,geni-i2c-master-hub"; 1334 reg = <0x0 0x00994000 0x0 0x4000>; 1335 1336 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1337 1338 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1339 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1340 clock-names = "se", 1341 "core"; 1342 1343 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1344 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1346 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1347 interconnect-names = "qup-core", 1348 "qup-config"; 1349 1350 pinctrl-0 = <&hub_i2c5_data_clk>; 1351 pinctrl-names = "default"; 1352 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 1356 status = "disabled"; 1357 }; 1358 1359 i2c_hub_6: i2c@998000 { 1360 compatible = "qcom,geni-i2c-master-hub"; 1361 reg = <0x0 0x00998000 0x0 0x4000>; 1362 1363 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1364 1365 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1366 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1367 clock-names = "se", 1368 "core"; 1369 1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1371 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1372 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1373 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1374 interconnect-names = "qup-core", 1375 "qup-config"; 1376 1377 pinctrl-0 = <&hub_i2c6_data_clk>; 1378 pinctrl-names = "default"; 1379 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 1383 status = "disabled"; 1384 }; 1385 1386 i2c_hub_7: i2c@99c000 { 1387 compatible = "qcom,geni-i2c-master-hub"; 1388 reg = <0x0 0x0099c000 0x0 0x4000>; 1389 1390 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1391 1392 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1393 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1394 clock-names = "se", 1395 "core"; 1396 1397 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1398 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1399 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1400 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1401 interconnect-names = "qup-core", 1402 "qup-config"; 1403 1404 pinctrl-0 = <&hub_i2c7_data_clk>; 1405 pinctrl-names = "default"; 1406 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 1410 status = "disabled"; 1411 }; 1412 1413 i2c_hub_8: i2c@9a0000 { 1414 compatible = "qcom,geni-i2c-master-hub"; 1415 reg = <0x0 0x009a0000 0x0 0x4000>; 1416 1417 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1418 1419 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1420 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1421 clock-names = "se", 1422 "core"; 1423 1424 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1425 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1426 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1427 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1428 interconnect-names = "qup-core", 1429 "qup-config"; 1430 1431 pinctrl-0 = <&hub_i2c8_data_clk>; 1432 pinctrl-names = "default"; 1433 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 1437 status = "disabled"; 1438 }; 1439 1440 i2c_hub_9: i2c@9a4000 { 1441 compatible = "qcom,geni-i2c-master-hub"; 1442 reg = <0x0 0x009a4000 0x0 0x4000>; 1443 1444 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1445 1446 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1447 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1448 clock-names = "se", 1449 "core"; 1450 1451 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1452 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1454 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1455 interconnect-names = "qup-core", 1456 "qup-config"; 1457 1458 pinctrl-0 = <&hub_i2c9_data_clk>; 1459 pinctrl-names = "default"; 1460 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 1464 status = "disabled"; 1465 }; 1466 }; 1467 1468 gpi_dma1: dma-controller@a00000 { 1469 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; 1470 reg = <0x0 0x00a00000 0x0 0x60000>; 1471 1472 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1484 1485 dma-channels = <12>; 1486 dma-channel-mask = <0x1e>; 1487 #dma-cells = <3>; 1488 1489 iommus = <&apps_smmu 0xb6 0x0>; 1490 1491 status = "disabled"; 1492 }; 1493 1494 qupv3_1: geniqup@ac0000 { 1495 compatible = "qcom,geni-se-qup"; 1496 reg = <0x0 0x00ac0000 0x0 0x2000>; 1497 1498 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1499 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1500 clock-names = "m-ahb", 1501 "s-ahb"; 1502 1503 iommus = <&apps_smmu 0xa3 0x0>; 1504 1505 #address-cells = <2>; 1506 #size-cells = <2>; 1507 ranges; 1508 1509 status = "disabled"; 1510 1511 i2c0: i2c@a80000 { 1512 compatible = "qcom,geni-i2c"; 1513 reg = <0x0 0x00a80000 0x0 0x4000>; 1514 1515 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1516 1517 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1518 clock-names = "se"; 1519 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1521 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1523 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1524 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1525 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1526 interconnect-names = "qup-core", 1527 "qup-config", 1528 "qup-memory"; 1529 1530 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1531 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1532 dma-names = "tx", 1533 "rx"; 1534 1535 pinctrl-0 = <&qup_i2c0_data_clk>; 1536 pinctrl-names = "default"; 1537 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 status = "disabled"; 1542 }; 1543 1544 spi0: spi@a80000 { 1545 compatible = "qcom,geni-spi"; 1546 reg = <0x0 0x00a80000 0x0 0x4000>; 1547 1548 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1549 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1551 clock-names = "se"; 1552 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1554 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1555 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1556 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1557 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1558 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1559 interconnect-names = "qup-core", 1560 "qup-config", 1561 "qup-memory"; 1562 1563 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1564 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1565 dma-names = "tx", 1566 "rx"; 1567 1568 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1569 pinctrl-names = "default"; 1570 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 1574 status = "disabled"; 1575 }; 1576 1577 i2c1: i2c@a84000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0x0 0x00a84000 0x0 0x4000>; 1580 1581 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1582 1583 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1584 clock-names = "se"; 1585 1586 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1587 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1588 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1589 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1590 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1591 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1592 interconnect-names = "qup-core", 1593 "qup-config", 1594 "qup-memory"; 1595 1596 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1597 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1598 dma-names = "tx", 1599 "rx"; 1600 1601 pinctrl-0 = <&qup_i2c1_data_clk>; 1602 pinctrl-names = "default"; 1603 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 1607 status = "disabled"; 1608 }; 1609 1610 spi1: spi@a84000 { 1611 compatible = "qcom,geni-spi"; 1612 reg = <0x0 0x00a84000 0x0 0x4000>; 1613 1614 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1615 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1617 clock-names = "se"; 1618 1619 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1620 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1621 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1622 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1623 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1624 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1625 interconnect-names = "qup-core", 1626 "qup-config", 1627 "qup-memory"; 1628 1629 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1630 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1631 dma-names = "tx", 1632 "rx"; 1633 1634 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1635 pinctrl-names = "default"; 1636 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 1640 status = "disabled"; 1641 }; 1642 1643 i2c2: i2c@a88000 { 1644 compatible = "qcom,geni-i2c"; 1645 reg = <0x0 0x00a88000 0x0 0x4000>; 1646 1647 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1648 1649 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1650 clock-names = "se"; 1651 1652 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1653 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1654 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1655 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1656 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1657 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1658 interconnect-names = "qup-core", 1659 "qup-config", 1660 "qup-memory"; 1661 1662 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1663 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1664 dma-names = "tx", 1665 "rx"; 1666 1667 pinctrl-0 = <&qup_i2c2_data_clk>; 1668 pinctrl-names = "default"; 1669 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 1673 status = "disabled"; 1674 }; 1675 1676 spi2: spi@a88000 { 1677 compatible = "qcom,geni-spi"; 1678 reg = <0x0 0x00a88000 0x0 0x4000>; 1679 1680 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1681 1682 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1683 clock-names = "se"; 1684 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1686 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1687 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1688 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1689 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1690 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1691 interconnect-names = "qup-core", 1692 "qup-config", 1693 "qup-memory"; 1694 1695 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1696 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1697 dma-names = "tx", 1698 "rx"; 1699 1700 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1701 pinctrl-names = "default"; 1702 1703 #address-cells = <1>; 1704 #size-cells = <0>; 1705 1706 status = "disabled"; 1707 }; 1708 1709 i2c3: i2c@a8c000 { 1710 compatible = "qcom,geni-i2c"; 1711 reg = <0x0 0x00a8c000 0x0 0x4000>; 1712 1713 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1714 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1716 clock-names = "se"; 1717 1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1719 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1720 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1721 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1722 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1723 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1724 interconnect-names = "qup-core", 1725 "qup-config", 1726 "qup-memory"; 1727 1728 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1729 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1730 dma-names = "tx", 1731 "rx"; 1732 1733 pinctrl-0 = <&qup_i2c3_data_clk>; 1734 pinctrl-names = "default"; 1735 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 1739 status = "disabled"; 1740 }; 1741 1742 spi3: spi@a8c000 { 1743 compatible = "qcom,geni-spi"; 1744 reg = <0x0 0x00a8c000 0x0 0x4000>; 1745 1746 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1747 1748 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1749 clock-names = "se"; 1750 1751 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1752 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1753 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1754 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1755 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1756 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1757 interconnect-names = "qup-core", 1758 "qup-config", 1759 "qup-memory"; 1760 1761 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1762 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1763 dma-names = "tx", 1764 "rx"; 1765 1766 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1767 pinctrl-names = "default"; 1768 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 1772 status = "disabled"; 1773 }; 1774 1775 i2c4: i2c@a90000 { 1776 compatible = "qcom,geni-i2c"; 1777 reg = <0x0 0x00a90000 0x0 0x4000>; 1778 1779 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1780 1781 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1782 clock-names = "se"; 1783 1784 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1785 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1786 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1787 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1788 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1789 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1790 interconnect-names = "qup-core", 1791 "qup-config", 1792 "qup-memory"; 1793 1794 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1795 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1796 dma-names = "tx", 1797 "rx"; 1798 1799 pinctrl-0 = <&qup_i2c4_data_clk>; 1800 pinctrl-names = "default"; 1801 1802 #address-cells = <1>; 1803 #size-cells = <0>; 1804 1805 status = "disabled"; 1806 }; 1807 1808 spi4: spi@a90000 { 1809 compatible = "qcom,geni-spi"; 1810 reg = <0x0 0x00a90000 0x0 0x4000>; 1811 1812 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1813 1814 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1815 clock-names = "se"; 1816 1817 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1818 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1819 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1820 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1821 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1822 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1823 interconnect-names = "qup-core", 1824 "qup-config", 1825 "qup-memory"; 1826 1827 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1828 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1829 dma-names = "tx", 1830 "rx"; 1831 1832 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1833 pinctrl-names = "default"; 1834 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 1838 status = "disabled"; 1839 }; 1840 1841 i2c5: i2c@a94000 { 1842 compatible = "qcom,geni-i2c"; 1843 reg = <0x0 0x00a94000 0x0 0x4000>; 1844 1845 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1846 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1848 clock-names = "se"; 1849 1850 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1851 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1852 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1853 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1854 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1855 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1856 interconnect-names = "qup-core", 1857 "qup-config", 1858 "qup-memory"; 1859 1860 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1861 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1862 dma-names = "tx", 1863 "rx"; 1864 1865 pinctrl-0 = <&qup_i2c5_data_clk>; 1866 pinctrl-names = "default"; 1867 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 1871 status = "disabled"; 1872 }; 1873 1874 spi5: spi@a94000 { 1875 compatible = "qcom,geni-spi"; 1876 reg = <0x0 0x00a94000 0x0 0x4000>; 1877 1878 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1879 1880 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1881 clock-names = "se"; 1882 1883 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1884 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1885 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1886 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1887 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1888 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1889 interconnect-names = "qup-core", 1890 "qup-config", 1891 "qup-memory"; 1892 1893 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1894 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1895 dma-names = "tx", 1896 "rx"; 1897 1898 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1899 pinctrl-names = "default"; 1900 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 1904 status = "disabled"; 1905 }; 1906 1907 i2c6: i2c@a98000 { 1908 compatible = "qcom,geni-i2c"; 1909 reg = <0x0 0x00a98000 0x0 0x4000>; 1910 1911 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1912 1913 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1914 clock-names = "se"; 1915 1916 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1917 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1919 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1920 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1922 interconnect-names = "qup-core", 1923 "qup-config", 1924 "qup-memory"; 1925 1926 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1927 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1928 dma-names = "tx", 1929 "rx"; 1930 1931 pinctrl-0 = <&qup_i2c6_data_clk>; 1932 pinctrl-names = "default"; 1933 1934 #address-cells = <1>; 1935 #size-cells = <0>; 1936 1937 status = "disabled"; 1938 }; 1939 1940 spi6: spi@a98000 { 1941 compatible = "qcom,geni-spi"; 1942 reg = <0x0 0x00a98000 0x0 0x4000>; 1943 1944 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1945 1946 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1947 clock-names = "se"; 1948 1949 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1950 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1952 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1953 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1954 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1955 interconnect-names = "qup-core", 1956 "qup-config", 1957 "qup-memory"; 1958 1959 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1960 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1961 dma-names = "tx", 1962 "rx"; 1963 1964 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1965 pinctrl-names = "default"; 1966 1967 #address-cells = <1>; 1968 #size-cells = <0>; 1969 1970 status = "disabled"; 1971 }; 1972 1973 uart7: serial@a9c000 { 1974 compatible = "qcom,geni-debug-uart"; 1975 reg = <0x0 0x00a9c000 0x0 0x4000>; 1976 1977 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1978 1979 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1980 clock-names = "se"; 1981 1982 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1983 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1984 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1985 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1986 interconnect-names = "qup-core", 1987 "qup-config"; 1988 1989 pinctrl-0 = <&qup_uart7_default>; 1990 pinctrl-names = "default"; 1991 1992 status = "disabled"; 1993 }; 1994 }; 1995 1996 rng: rng@10c3000 { 1997 compatible = "qcom,sm8750-trng", "qcom,trng"; 1998 reg = <0x0 0x010c3000 0x0 0x1000>; 1999 }; 2000 2001 cnoc_main: interconnect@1500000 { 2002 compatible = "qcom,sm8750-cnoc-main"; 2003 reg = <0x0 0x01500000 0x0 0x16080>; 2004 qcom,bcm-voters = <&apps_bcm_voter>; 2005 #interconnect-cells = <2>; 2006 }; 2007 2008 config_noc: interconnect@1600000 { 2009 compatible = "qcom,sm8750-config-noc"; 2010 reg = <0x0 0x01600000 0x0 0x6200>; 2011 qcom,bcm-voters = <&apps_bcm_voter>; 2012 #interconnect-cells = <2>; 2013 }; 2014 2015 system_noc: interconnect@1680000 { 2016 compatible = "qcom,sm8750-system-noc"; 2017 reg = <0x0 0x01680000 0x0 0x1d080>; 2018 qcom,bcm-voters = <&apps_bcm_voter>; 2019 #interconnect-cells = <2>; 2020 }; 2021 2022 pcie_noc: interconnect@16c0000 { 2023 compatible = "qcom,sm8750-pcie-anoc"; 2024 reg = <0x0 0x016c0000 0x0 0x11400>; 2025 qcom,bcm-voters = <&apps_bcm_voter>; 2026 #interconnect-cells = <2>; 2027 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2028 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2029 }; 2030 2031 aggre1_noc: interconnect@16e0000 { 2032 compatible = "qcom,sm8750-aggre1-noc"; 2033 reg = <0x0 0x016e0000 0x0 0x16400>; 2034 qcom,bcm-voters = <&apps_bcm_voter>; 2035 #interconnect-cells = <2>; 2036 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2037 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2038 }; 2039 2040 aggre2_noc: interconnect@1700000 { 2041 compatible = "qcom,sm8750-aggre2-noc"; 2042 reg = <0x0 0x01700000 0x0 0x1f400>; 2043 qcom,bcm-voters = <&apps_bcm_voter>; 2044 #interconnect-cells = <2>; 2045 clocks = <&rpmhcc RPMH_IPA_CLK>; 2046 }; 2047 2048 mmss_noc: interconnect@1780000 { 2049 compatible = "qcom,sm8750-mmss-noc"; 2050 reg = <0x0 0x01780000 0x0 0x5b800>; 2051 qcom,bcm-voters = <&apps_bcm_voter>; 2052 #interconnect-cells = <2>; 2053 }; 2054 2055 ice: crypto@1d88000 { 2056 compatible = "qcom,sm8750-inline-crypto-engine", 2057 "qcom,inline-crypto-engine"; 2058 reg = <0x0 0x01d88000 0x0 0x18000>; 2059 2060 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2061 }; 2062 2063 cryptobam: dma-controller@1dc4000 { 2064 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2065 reg = <0x0 0x01dc4000 0x0 0x28000>; 2066 2067 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2068 2069 #dma-cells = <1>; 2070 2071 iommus = <&apps_smmu 0x480 0>, 2072 <&apps_smmu 0x481 0>; 2073 2074 qcom,ee = <0>; 2075 qcom,controlled-remotely; 2076 }; 2077 2078 crypto: crypto@1dfa000 { 2079 compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce"; 2080 reg = <0x0 0x01dfa000 0x0 0x6000>; 2081 2082 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2083 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2084 interconnect-names = "memory"; 2085 2086 dmas = <&cryptobam 4>, <&cryptobam 5>; 2087 dma-names = "rx", "tx"; 2088 2089 iommus = <&apps_smmu 0x480 0>, 2090 <&apps_smmu 0x481 0>; 2091 }; 2092 2093 tcsr_mutex: hwlock@1f40000 { 2094 compatible = "qcom,tcsr-mutex"; 2095 reg = <0x0 0x01f40000 0x0 0x20000>; 2096 #hwlock-cells = <1>; 2097 }; 2098 2099 remoteproc_mpss: remoteproc@4080000 { 2100 compatible = "qcom,sm8750-mpss-pas"; 2101 reg = <0x0 0x04080000 0x0 0x10000>; 2102 2103 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2104 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2105 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2106 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2107 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2108 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2109 interrupt-names = "wdog", 2110 "fatal", 2111 "ready", 2112 "handover", 2113 "stop-ack", 2114 "shutdown-ack"; 2115 2116 clocks = <&rpmhcc RPMH_CXO_CLK>; 2117 clock-names = "xo"; 2118 2119 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2120 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2121 2122 power-domains = <&rpmhpd RPMHPD_CX>, 2123 <&rpmhpd RPMHPD_MSS>; 2124 power-domain-names = "cx", 2125 "mss"; 2126 2127 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2128 <&dsm_partition_1_mem>, 2129 <&dsm_partition_2_mem>; 2130 2131 qcom,qmp = <&aoss_qmp>; 2132 2133 qcom,smem-states = <&smp2p_modem_out 0>; 2134 qcom,smem-state-names = "stop"; 2135 2136 status = "disabled"; 2137 2138 glink-edge { 2139 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2140 IPCC_MPROC_SIGNAL_GLINK_QMP 2141 IRQ_TYPE_EDGE_RISING>; 2142 2143 mboxes = <&ipcc IPCC_CLIENT_MPSS 2144 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2145 2146 qcom,remote-pid = <1>; 2147 2148 label = "mpss"; 2149 }; 2150 }; 2151 2152 remoteproc_adsp: remoteproc@6800000 { 2153 compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas"; 2154 reg = <0x0 0x06800000 0x0 0x10000>; 2155 2156 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2157 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2158 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2159 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2160 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2161 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2162 interrupt-names = "wdog", 2163 "fatal", 2164 "ready", 2165 "handover", 2166 "stop-ack", 2167 "shutdown-ack"; 2168 2169 clocks = <&rpmhcc RPMH_CXO_CLK>; 2170 clock-names = "xo"; 2171 2172 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2174 2175 power-domains = <&rpmhpd RPMHPD_LCX>, 2176 <&rpmhpd RPMHPD_LMX>; 2177 power-domain-names = "lcx", 2178 "lmx"; 2179 2180 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2181 2182 qcom,qmp = <&aoss_qmp>; 2183 2184 qcom,smem-states = <&smp2p_adsp_out 0>; 2185 qcom,smem-state-names = "stop"; 2186 2187 status = "disabled"; 2188 2189 remoteproc_adsp_glink: glink-edge { 2190 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2191 IPCC_MPROC_SIGNAL_GLINK_QMP 2192 IRQ_TYPE_EDGE_RISING>; 2193 mboxes = <&ipcc IPCC_CLIENT_LPASS 2194 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2195 qcom,remote-pid = <2>; 2196 label = "lpass"; 2197 2198 gpr { 2199 compatible = "qcom,gpr"; 2200 qcom,glink-channels = "adsp_apps"; 2201 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2202 qcom,intents = <512 20>; 2203 #address-cells = <1>; 2204 #size-cells = <0>; 2205 2206 q6apm: service@1 { 2207 compatible = "qcom,q6apm"; 2208 reg = <GPR_APM_MODULE_IID>; 2209 #sound-dai-cells = <0>; 2210 qcom,protection-domain = "avs/audio", 2211 "msm/adsp/audio_pd"; 2212 2213 q6apmbedai: bedais { 2214 compatible = "qcom,q6apm-lpass-dais"; 2215 #sound-dai-cells = <1>; 2216 }; 2217 2218 q6apmdai: dais { 2219 compatible = "qcom,q6apm-dais"; 2220 iommus = <&apps_smmu 0x1001 0x80>, 2221 <&apps_smmu 0x1041 0x20>; 2222 }; 2223 }; 2224 2225 q6prm: service@2 { 2226 compatible = "qcom,q6prm"; 2227 reg = <GPR_PRM_MODULE_IID>; 2228 qcom,protection-domain = "avs/audio", 2229 "msm/adsp/audio_pd"; 2230 2231 q6prmcc: clock-controller { 2232 compatible = "qcom,q6prm-lpass-clocks"; 2233 #clock-cells = <2>; 2234 }; 2235 }; 2236 }; 2237 }; 2238 }; 2239 2240 lpass_wsa2macro: codec@6aa0000 { 2241 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2242 reg = <0x0 0x06aa0000 0x0 0x1000>; 2243 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2244 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2245 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2246 <&lpass_vamacro>; 2247 clock-names = "mclk", 2248 "macro", 2249 "dcodec", 2250 "fsgen"; 2251 2252 #clock-cells = <0>; 2253 clock-output-names = "wsa2-mclk"; 2254 #sound-dai-cells = <1>; 2255 }; 2256 2257 swr3: soundwire@6ab0000 { 2258 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2259 reg = <0x0 0x06ab0000 0x0 0x10000>; 2260 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2261 clocks = <&lpass_wsa2macro>; 2262 clock-names = "iface"; 2263 label = "WSA2"; 2264 2265 pinctrl-0 = <&wsa2_swr_active>; 2266 pinctrl-names = "default"; 2267 2268 qcom,din-ports = <4>; 2269 qcom,dout-ports = <9>; 2270 2271 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; 2272 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; 2273 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2274 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2275 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2276 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; 2277 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; 2278 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2279 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2280 2281 #address-cells = <2>; 2282 #size-cells = <0>; 2283 #sound-dai-cells = <1>; 2284 status = "disabled"; 2285 }; 2286 2287 lpass_rxmacro: codec@6ac0000 { 2288 compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 2289 reg = <0x0 0x06ac0000 0x0 0x1000>; 2290 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2291 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2292 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2293 <&lpass_vamacro>; 2294 clock-names = "mclk", 2295 "macro", 2296 "dcodec", 2297 "fsgen"; 2298 2299 #clock-cells = <0>; 2300 clock-output-names = "mclk"; 2301 #sound-dai-cells = <1>; 2302 }; 2303 2304 swr1: soundwire@6ad0000 { 2305 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2306 reg = <0x0 0x06ad0000 0x0 0x10000>; 2307 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2308 clocks = <&lpass_rxmacro>; 2309 clock-names = "iface"; 2310 label = "RX"; 2311 2312 pinctrl-0 = <&rx_swr_active>; 2313 pinctrl-names = "default"; 2314 2315 qcom,din-ports = <1>; 2316 qcom,dout-ports = <11>; 2317 2318 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0x31 0xff 0xff 0xff>; 2319 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2320 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2321 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0x00 0xff 0xff 0xff>; 2322 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0x0f 0xff 0xff 0xff>; 2323 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0x18 0xff 0xff 0xff>; 2324 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2325 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2326 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2327 2328 #address-cells = <2>; 2329 #size-cells = <0>; 2330 #sound-dai-cells = <1>; 2331 status = "disabled"; 2332 }; 2333 2334 lpass_txmacro: codec@6ae0000 { 2335 compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 2336 reg = <0x0 0x06ae0000 0x0 0x1000>; 2337 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2338 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2339 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2340 <&lpass_vamacro>; 2341 clock-names = "mclk", 2342 "macro", 2343 "dcodec", 2344 "fsgen"; 2345 2346 #clock-cells = <0>; 2347 clock-output-names = "mclk"; 2348 #sound-dai-cells = <1>; 2349 }; 2350 2351 lpass_wsamacro: codec@6b00000 { 2352 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2353 reg = <0x0 0x06b00000 0x0 0x1000>; 2354 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2355 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2356 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2357 <&lpass_vamacro>; 2358 clock-names = "mclk", 2359 "macro", 2360 "dcodec", 2361 "fsgen"; 2362 2363 #clock-cells = <0>; 2364 clock-output-names = "mclk"; 2365 #sound-dai-cells = <1>; 2366 }; 2367 2368 swr0: soundwire@6b10000 { 2369 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2370 reg = <0x0 0x06b10000 0x0 0x10000>; 2371 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2372 clocks = <&lpass_wsamacro>; 2373 clock-names = "iface"; 2374 label = "WSA"; 2375 2376 pinctrl-0 = <&wsa_swr_active>; 2377 pinctrl-names = "default"; 2378 2379 qcom,din-ports = <4>; 2380 qcom,dout-ports = <9>; 2381 2382 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; 2383 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; 2384 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2385 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2386 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2387 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; 2388 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; 2389 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2390 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2391 2392 #address-cells = <2>; 2393 #size-cells = <0>; 2394 #sound-dai-cells = <1>; 2395 status = "disabled"; 2396 }; 2397 2398 lpass_ag_noc: interconnect@7e40000 { 2399 compatible = "qcom,sm8750-lpass-ag-noc"; 2400 reg = <0x0 0x07e40000 0x0 0xe080>; 2401 qcom,bcm-voters = <&apps_bcm_voter>; 2402 #interconnect-cells = <2>; 2403 }; 2404 2405 lpass_lpiaon_noc: interconnect@7400000 { 2406 compatible = "qcom,sm8750-lpass-lpiaon-noc"; 2407 reg = <0x0 0x07400000 0x0 0x19080>; 2408 qcom,bcm-voters = <&apps_bcm_voter>; 2409 #interconnect-cells = <2>; 2410 }; 2411 2412 lpass_lpicx_noc: interconnect@7420000 { 2413 compatible = "qcom,sm8750-lpass-lpicx-noc"; 2414 reg = <0x0 0x07420000 0x0 0x44080>; 2415 qcom,bcm-voters = <&apps_bcm_voter>; 2416 #interconnect-cells = <2>; 2417 }; 2418 2419 swr2: soundwire@7630000 { 2420 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2421 reg = <0x0 0x07630000 0x0 0x10000>; 2422 interrupts = <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 2424 interrupt-names = "core", "wakeup"; 2425 clocks = <&lpass_txmacro>; 2426 clock-names = "iface"; 2427 label = "TX"; 2428 2429 pinctrl-0 = <&tx_swr_active>; 2430 pinctrl-names = "default"; 2431 2432 qcom,din-ports = <4>; 2433 qcom,dout-ports = <0>; 2434 2435 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2436 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2437 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2438 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2439 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2440 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2441 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2442 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2443 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2444 2445 #address-cells = <2>; 2446 #size-cells = <0>; 2447 #sound-dai-cells = <1>; 2448 status = "disabled"; 2449 }; 2450 2451 lpass_vamacro: codec@7660000 { 2452 compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 2453 reg = <0x0 0x07660000 0x0 0x2000>; 2454 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2455 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2456 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2457 clock-names = "mclk", 2458 "macro", 2459 "dcodec"; 2460 2461 #clock-cells = <0>; 2462 clock-output-names = "fsgen"; 2463 #sound-dai-cells = <1>; 2464 }; 2465 2466 lpass_tlmm: pinctrl@7760000 { 2467 compatible = "qcom,sm8750-lpass-lpi-pinctrl", 2468 "qcom,sm8650-lpass-lpi-pinctrl"; 2469 reg = <0x0 0x07760000 0x0 0x20000>; 2470 2471 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2472 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2473 clock-names = "core", "audio"; 2474 2475 gpio-controller; 2476 #gpio-cells = <2>; 2477 gpio-ranges = <&lpass_tlmm 0 0 23>; 2478 2479 tx_swr_active: tx-swr-active-state { 2480 clk-pins { 2481 pins = "gpio0"; 2482 function = "swr_tx_clk"; 2483 drive-strength = <2>; 2484 slew-rate = <1>; 2485 bias-disable; 2486 }; 2487 2488 data-pins { 2489 pins = "gpio1", "gpio2", "gpio14"; 2490 function = "swr_tx_data"; 2491 drive-strength = <2>; 2492 slew-rate = <1>; 2493 bias-bus-hold; 2494 }; 2495 }; 2496 2497 rx_swr_active: rx-swr-active-state { 2498 clk-pins { 2499 pins = "gpio3"; 2500 function = "swr_rx_clk"; 2501 drive-strength = <2>; 2502 slew-rate = <1>; 2503 bias-disable; 2504 }; 2505 2506 data-pins { 2507 pins = "gpio4", "gpio5"; 2508 function = "swr_rx_data"; 2509 drive-strength = <2>; 2510 slew-rate = <1>; 2511 bias-bus-hold; 2512 }; 2513 }; 2514 2515 dmic01_default: dmic01-default-state { 2516 clk-pins { 2517 pins = "gpio6"; 2518 function = "dmic1_clk"; 2519 drive-strength = <8>; 2520 output-high; 2521 }; 2522 2523 data-pins { 2524 pins = "gpio7"; 2525 function = "dmic1_data"; 2526 drive-strength = <8>; 2527 input-enable; 2528 }; 2529 }; 2530 2531 dmic23_default: dmic23-default-state { 2532 clk-pins { 2533 pins = "gpio8"; 2534 function = "dmic2_clk"; 2535 drive-strength = <8>; 2536 output-high; 2537 }; 2538 2539 data-pins { 2540 pins = "gpio9"; 2541 function = "dmic2_data"; 2542 drive-strength = <8>; 2543 input-enable; 2544 }; 2545 }; 2546 2547 wsa_swr_active: wsa-swr-active-state { 2548 clk-pins { 2549 pins = "gpio10"; 2550 function = "wsa_swr_clk"; 2551 drive-strength = <2>; 2552 slew-rate = <1>; 2553 bias-disable; 2554 }; 2555 2556 data-pins { 2557 pins = "gpio11"; 2558 function = "wsa_swr_data"; 2559 drive-strength = <2>; 2560 slew-rate = <1>; 2561 bias-bus-hold; 2562 }; 2563 }; 2564 2565 wsa2_swr_active: wsa2-swr-active-state { 2566 clk-pins { 2567 pins = "gpio15"; 2568 function = "wsa2_swr_clk"; 2569 drive-strength = <2>; 2570 slew-rate = <1>; 2571 bias-disable; 2572 }; 2573 2574 data-pins { 2575 pins = "gpio16"; 2576 function = "wsa2_swr_data"; 2577 drive-strength = <2>; 2578 slew-rate = <1>; 2579 bias-bus-hold; 2580 }; 2581 }; 2582 }; 2583 2584 pdc: interrupt-controller@b220000 { 2585 compatible = "qcom,sm8750-pdc", "qcom,pdc"; 2586 reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; 2587 2588 qcom,pdc-ranges = <0 745 51>, <51 527 47>, 2589 <98 609 32>, <130 717 12>, 2590 <142 251 5>, <147 796 16>; 2591 #interrupt-cells = <2>; 2592 interrupt-parent = <&intc>; 2593 interrupt-controller; 2594 }; 2595 2596 aoss_qmp: power-management@c300000 { 2597 compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp"; 2598 reg = <0x0 0x0c300000 0x0 0x400>; 2599 2600 interrupt-parent = <&ipcc>; 2601 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2602 IRQ_TYPE_EDGE_RISING>; 2603 2604 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2605 2606 #clock-cells = <0>; 2607 }; 2608 2609 sram@c3f0000 { 2610 compatible = "qcom,rpmh-stats"; 2611 reg = <0x0 0x0c3f0000 0x0 0x400>; 2612 qcom,qmp = <&aoss_qmp>; 2613 }; 2614 2615 spmi_bus: spmi@c400000 { 2616 compatible = "qcom,spmi-pmic-arb"; 2617 reg = <0x0 0x0c400000 0x0 0x3000>, 2618 <0x0 0x0c500000 0x0 0x400000>, 2619 <0x0 0x0c440000 0x0 0x80000>, 2620 <0x0 0x0c4c0000 0x0 0x10000>, 2621 <0x0 0x0c42d000 0x0 0x4000>; 2622 reg-names = "core", 2623 "chnls", 2624 "obsrvr", 2625 "intr", 2626 "cnfg"; 2627 2628 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2629 interrupt-names = "periph_irq"; 2630 2631 qcom,ee = <0>; 2632 qcom,channel = <0>; 2633 qcom,bus-id = <0>; 2634 2635 interrupt-controller; 2636 #interrupt-cells = <4>; 2637 2638 #address-cells = <2>; 2639 #size-cells = <0>; 2640 }; 2641 2642 tlmm: pinctrl@f100000 { 2643 compatible = "qcom,sm8750-tlmm"; 2644 reg = <0x0 0x0f100000 0x0 0x102000>; 2645 2646 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2647 2648 gpio-controller; 2649 #gpio-cells = <2>; 2650 2651 interrupt-controller; 2652 #interrupt-cells = <2>; 2653 2654 gpio-ranges = <&tlmm 0 0 216>; 2655 wakeup-parent = <&pdc>; 2656 2657 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 2658 /* SDA, SCL */ 2659 pins = "gpio64", "gpio65"; 2660 function = "i2chub0_se0"; 2661 drive-strength = <2>; 2662 bias-pull-up; 2663 }; 2664 2665 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 2666 /* SDA, SCL */ 2667 pins = "gpio66", "gpio67"; 2668 function = "i2chub0_se1"; 2669 drive-strength = <2>; 2670 bias-pull-up; 2671 }; 2672 2673 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 2674 /* SDA, SCL */ 2675 pins = "gpio68", "gpio69"; 2676 function = "i2chub0_se2"; 2677 drive-strength = <2>; 2678 bias-pull-up; 2679 }; 2680 2681 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 2682 /* SDA, SCL */ 2683 pins = "gpio70", "gpio71"; 2684 function = "i2chub0_se3"; 2685 drive-strength = <2>; 2686 bias-pull-up; 2687 }; 2688 2689 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 2690 /* SDA, SCL */ 2691 pins = "gpio72", "gpio73"; 2692 function = "i2chub0_se4"; 2693 drive-strength = <2>; 2694 bias-pull-up; 2695 }; 2696 2697 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 2698 /* SDA, SCL */ 2699 pins = "gpio74", "gpio75"; 2700 function = "i2chub0_se5"; 2701 drive-strength = <2>; 2702 bias-pull-up; 2703 }; 2704 2705 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 2706 /* SDA, SCL */ 2707 pins = "gpio76", "gpio77"; 2708 function = "i2chub0_se6"; 2709 drive-strength = <2>; 2710 bias-pull-up; 2711 }; 2712 2713 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 2714 /* SDA, SCL */ 2715 pins = "gpio82", "gpio83"; 2716 function = "i2chub0_se7"; 2717 drive-strength = <2>; 2718 bias-pull-up; 2719 }; 2720 2721 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 2722 /* SDA, SCL */ 2723 pins = "gpio206", "gpio207"; 2724 function = "i2chub0_se8"; 2725 drive-strength = <2>; 2726 bias-pull-up; 2727 }; 2728 2729 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 2730 /* SDA, SCL */ 2731 pins = "gpio80", "gpio81"; 2732 function = "i2chub0_se9"; 2733 drive-strength = <2>; 2734 bias-pull-up; 2735 }; 2736 2737 pcie0_default_state: pcie0-default-state { 2738 perst-pins { 2739 pins = "gpio102"; 2740 function = "gpio"; 2741 drive-strength = <2>; 2742 bias-pull-down; 2743 }; 2744 2745 clkreq-pins { 2746 pins = "gpio103"; 2747 function = "pcie0_clk_req_n"; 2748 drive-strength = <2>; 2749 bias-pull-up; 2750 }; 2751 2752 wake-pins { 2753 pins = "gpio104"; 2754 function = "gpio"; 2755 drive-strength = <2>; 2756 bias-pull-up; 2757 }; 2758 }; 2759 2760 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2761 /* SDA, SCL */ 2762 pins = "gpio32", "gpio33"; 2763 function = "qup1_se0"; 2764 drive-strength = <2>; 2765 bias-pull-up; 2766 }; 2767 2768 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2769 /* SDA, SCL */ 2770 pins = "gpio36", "gpio37"; 2771 function = "qup1_se1"; 2772 drive-strength = <2>; 2773 bias-pull-up; 2774 }; 2775 2776 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2777 /* SDA, SCL */ 2778 pins = "gpio40", "gpio41"; 2779 function = "qup1_se2"; 2780 drive-strength = <2>; 2781 bias-pull-up; 2782 }; 2783 2784 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2785 /* SDA, SCL */ 2786 pins = "gpio44", "gpio45"; 2787 function = "qup1_se3"; 2788 drive-strength = <2>; 2789 bias-pull-up; 2790 }; 2791 2792 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2793 /* SDA, SCL */ 2794 pins = "gpio48", "gpio49"; 2795 function = "qup1_se4"; 2796 drive-strength = <2>; 2797 bias-pull-up; 2798 }; 2799 2800 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2801 /* SDA, SCL */ 2802 pins = "gpio52", "gpio53"; 2803 function = "qup1_se5"; 2804 drive-strength = <2>; 2805 bias-pull-up; 2806 }; 2807 2808 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2809 /* SDA, SCL */ 2810 pins = "gpio56", "gpio57"; 2811 function = "qup1_se6"; 2812 drive-strength = <2>; 2813 bias-pull-up; 2814 }; 2815 2816 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2817 /* SDA, SCL */ 2818 pins = "gpio0", "gpio1"; 2819 function = "qup2_se0"; 2820 drive-strength = <2>; 2821 bias-pull-up; 2822 }; 2823 2824 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2825 /* SDA, SCL */ 2826 pins = "gpio4", "gpio5"; 2827 function = "qup2_se1"; 2828 drive-strength = <2>; 2829 bias-pull-up; 2830 }; 2831 2832 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2833 /* SDA, SCL */ 2834 pins = "gpio8", "gpio9"; 2835 function = "qup2_se2"; 2836 drive-strength = <2>; 2837 bias-pull-up; 2838 }; 2839 2840 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2841 /* SDA, SCL */ 2842 pins = "gpio12", "gpio13"; 2843 function = "qup2_se3"; 2844 drive-strength = <2>; 2845 bias-pull-up; 2846 }; 2847 2848 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 2849 /* SDA, SCL */ 2850 pins = "gpio16", "gpio17"; 2851 function = "qup2_se4"; 2852 drive-strength = <2>; 2853 bias-pull-up; 2854 }; 2855 2856 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 2857 /* SDA, SCL */ 2858 pins = "gpio20", "gpio21"; 2859 function = "qup2_se5"; 2860 drive-strength = <2>; 2861 bias-pull-up; 2862 }; 2863 2864 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 2865 /* SDA, SCL */ 2866 pins = "gpio28", "gpio29"; 2867 function = "qup2_se7"; 2868 drive-strength = <2>; 2869 bias-pull-up; 2870 }; 2871 2872 qup_spi0_cs: qup-spi0-cs-state { 2873 pins = "gpio35"; 2874 function = "qup1_se0"; 2875 drive-strength = <6>; 2876 bias-disable; 2877 }; 2878 2879 qup_spi0_data_clk: qup-spi0-data-clk-state { 2880 /* MISO, MOSI, CLK */ 2881 pins = "gpio32", "gpio33", "gpio34"; 2882 function = "qup1_se0"; 2883 drive-strength = <6>; 2884 bias-disable; 2885 }; 2886 2887 qup_spi1_cs: qup-spi1-cs-state { 2888 pins = "gpio39"; 2889 function = "qup1_se1"; 2890 drive-strength = <6>; 2891 bias-disable; 2892 }; 2893 2894 qup_spi1_data_clk: qup-spi1-data-clk-state { 2895 /* MISO, MOSI, CLK */ 2896 pins = "gpio36", "gpio37", "gpio38"; 2897 function = "qup1_se1"; 2898 drive-strength = <6>; 2899 bias-disable; 2900 }; 2901 2902 qup_spi2_cs: qup-spi2-cs-state { 2903 pins = "gpio43"; 2904 function = "qup1_se2"; 2905 drive-strength = <6>; 2906 bias-disable; 2907 }; 2908 2909 qup_spi2_data_clk: qup-spi2-data-clk-state { 2910 /* MISO, MOSI, CLK */ 2911 pins = "gpio40", "gpio41", "gpio42"; 2912 function = "qup1_se2"; 2913 drive-strength = <6>; 2914 bias-disable; 2915 }; 2916 2917 qup_spi3_cs: qup-spi3-cs-state { 2918 pins = "gpio47"; 2919 function = "qup1_se3"; 2920 drive-strength = <6>; 2921 bias-disable; 2922 }; 2923 2924 qup_spi3_data_clk: qup-spi3-data-clk-state { 2925 /* MISO, MOSI, CLK */ 2926 pins = "gpio44", "gpio45", "gpio46"; 2927 function = "qup1_se3"; 2928 drive-strength = <6>; 2929 bias-disable; 2930 }; 2931 2932 qup_spi4_cs: qup-spi4-cs-state { 2933 pins = "gpio51"; 2934 function = "qup1_se4"; 2935 drive-strength = <6>; 2936 bias-disable; 2937 }; 2938 2939 qup_spi4_data_clk: qup-spi4-data-clk-state { 2940 /* MISO, MOSI, CLK */ 2941 pins = "gpio48", "gpio49", "gpio50"; 2942 function = "qup1_se4"; 2943 drive-strength = <6>; 2944 bias-disable; 2945 }; 2946 2947 qup_spi5_cs: qup-spi5-cs-state { 2948 pins = "gpio55"; 2949 function = "qup1_se5"; 2950 drive-strength = <6>; 2951 bias-disable; 2952 }; 2953 2954 qup_spi5_data_clk: qup-spi5-data-clk-state { 2955 /* MISO, MOSI, CLK */ 2956 pins = "gpio52", "gpio53", "gpio54"; 2957 function = "qup1_se5"; 2958 drive-strength = <6>; 2959 bias-disable; 2960 }; 2961 2962 qup_spi6_cs: qup-spi6-cs-state { 2963 pins = "gpio59"; 2964 function = "qup1_se6"; 2965 drive-strength = <6>; 2966 bias-disable; 2967 }; 2968 2969 qup_spi6_data_clk: qup-spi6-data-clk-state { 2970 /* MISO, MOSI, CLK */ 2971 pins = "gpio56", "gpio57", "gpio58"; 2972 function = "qup1_se6"; 2973 drive-strength = <6>; 2974 bias-disable; 2975 }; 2976 2977 qup_spi8_cs: qup-spi8-cs-state { 2978 pins = "gpio3"; 2979 function = "qup2_se0"; 2980 drive-strength = <6>; 2981 bias-disable; 2982 }; 2983 2984 qup_spi8_data_clk: qup-spi8-data-clk-state { 2985 /* MISO, MOSI, CLK */ 2986 pins = "gpio0", "gpio1", "gpio2"; 2987 function = "qup2_se0"; 2988 drive-strength = <6>; 2989 bias-disable; 2990 }; 2991 2992 qup_spi9_cs: qup-spi9-cs-state { 2993 pins = "gpio7"; 2994 function = "qup2_se1"; 2995 drive-strength = <6>; 2996 bias-disable; 2997 }; 2998 2999 qup_spi9_data_clk: qup-spi9-data-clk-state { 3000 /* MISO, MOSI, CLK */ 3001 pins = "gpio4", "gpio5", "gpio6"; 3002 function = "qup2_se1"; 3003 drive-strength = <6>; 3004 bias-disable; 3005 }; 3006 3007 qup_spi10_cs: qup-spi10-cs-state { 3008 pins = "gpio11"; 3009 function = "qup2_se2"; 3010 drive-strength = <6>; 3011 bias-disable; 3012 }; 3013 3014 qup_spi10_data_clk: qup-spi10-data-clk-state { 3015 /* MISO, MOSI, CLK */ 3016 pins = "gpio8", "gpio9", "gpio10"; 3017 function = "qup2_se2"; 3018 drive-strength = <6>; 3019 bias-disable; 3020 }; 3021 3022 qup_spi11_cs: qup-spi11-cs-state { 3023 pins = "gpio15"; 3024 function = "qup2_se3"; 3025 drive-strength = <6>; 3026 bias-disable; 3027 }; 3028 3029 qup_spi11_data_clk: qup-spi11-data-clk-state { 3030 /* MISO, MOSI, CLK */ 3031 pins = "gpio12", "gpio13", "gpio14"; 3032 function = "qup2_se3"; 3033 drive-strength = <6>; 3034 bias-disable; 3035 }; 3036 3037 qup_spi12_cs: qup-spi12-cs-state { 3038 pins = "gpio19"; 3039 function = "qup2_se4"; 3040 drive-strength = <6>; 3041 bias-disable; 3042 }; 3043 3044 qup_spi12_data_clk: qup-spi12-data-clk-state { 3045 /* MISO, MOSI, CLK */ 3046 pins = "gpio16", "gpio17", "gpio18"; 3047 function = "qup2_se4"; 3048 drive-strength = <6>; 3049 bias-disable; 3050 }; 3051 3052 qup_spi13_cs: qup-spi13-cs-state { 3053 pins = "gpio23"; 3054 function = "qup2_se5"; 3055 drive-strength = <6>; 3056 bias-pull-up; 3057 }; 3058 3059 qup_spi13_data_clk: qup-spi13-data-clk-state { 3060 /* MISO, MOSI, CLK */ 3061 pins = "gpio20", "gpio21", "gpio22"; 3062 function = "qup2_se5"; 3063 drive-strength = <6>; 3064 bias-disable; 3065 }; 3066 3067 qup_spi15_cs: qup-spi15-cs-state { 3068 pins = "gpio31"; 3069 function = "qup2_se7"; 3070 drive-strength = <6>; 3071 bias-disable; 3072 }; 3073 3074 qup_spi15_data_clk: qup-spi15-data-clk-state { 3075 /* MISO, MOSI, CLK */ 3076 pins = "gpio28", "gpio29", "gpio30"; 3077 function = "qup2_se7"; 3078 drive-strength = <6>; 3079 bias-disable; 3080 }; 3081 3082 qup_uart7_default: qup-uart7-default-state { 3083 /* TX, RX */ 3084 pins = "gpio62", "gpio63"; 3085 function = "qup1_se7"; 3086 drive-strength = <2>; 3087 bias-disable; 3088 }; 3089 3090 qup_uart14_default: qup-uart14-default-state { 3091 /* TX, RX */ 3092 pins = "gpio26", "gpio27"; 3093 function = "qup2_se6"; 3094 drive-strength = <2>; 3095 bias-pull-up; 3096 }; 3097 3098 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 3099 /* CTS, RTS */ 3100 pins = "gpio24", "gpio25"; 3101 function = "qup2_se6"; 3102 drive-strength = <2>; 3103 bias-pull-down; 3104 }; 3105 3106 sdc2_sleep: sdc2-sleep-state { 3107 clk-pins { 3108 pins = "sdc2_clk"; 3109 drive-strength = <2>; 3110 bias-disable; 3111 }; 3112 3113 cmd-pins { 3114 pins = "sdc2_cmd"; 3115 drive-strength = <2>; 3116 bias-pull-up; 3117 }; 3118 3119 data-pins { 3120 pins = "sdc2_data"; 3121 drive-strength = <2>; 3122 bias-pull-up; 3123 }; 3124 }; 3125 3126 sdc2_default: sdc2-default-state { 3127 clk-pins { 3128 pins = "sdc2_clk"; 3129 drive-strength = <16>; 3130 bias-disable; 3131 }; 3132 3133 cmd-pins { 3134 pins = "sdc2_cmd"; 3135 drive-strength = <10>; 3136 bias-pull-up; 3137 }; 3138 3139 data-pins { 3140 pins = "sdc2_data"; 3141 drive-strength = <10>; 3142 bias-pull-up; 3143 }; 3144 }; 3145 }; 3146 3147 tcsrcc: clock-controller@f204008 { 3148 compatible = "qcom,sm8750-tcsr", "syscon"; 3149 reg = <0x0 0x0f204008 0x0 0x3004>; 3150 3151 clocks = <&rpmhcc RPMH_CXO_CLK>; 3152 3153 #clock-cells = <1>; 3154 #reset-cells = <1>; 3155 }; 3156 3157 apps_smmu: iommu@15000000 { 3158 compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3159 reg = <0x0 0x15000000 0x0 0x100000>; 3160 3161 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3204 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3206 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3207 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3208 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3212 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3214 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3215 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3216 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3217 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3218 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3219 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3220 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 3274 3275 #iommu-cells = <2>; 3276 #global-interrupts = <1>; 3277 3278 dma-coherent; 3279 }; 3280 3281 intc: interrupt-controller@16000000 { 3282 compatible = "arm,gic-v3"; 3283 reg = <0x0 0x16000000 0x0 0x10000>, 3284 <0x0 0x16080000 0x0 0x200000>; 3285 3286 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3287 3288 #interrupt-cells = <3>; 3289 interrupt-controller; 3290 3291 #redistributor-regions = <1>; 3292 redistributor-stride = <0x0 0x40000>; 3293 3294 #address-cells = <2>; 3295 #size-cells = <2>; 3296 ranges; 3297 3298 gic_its: msi-controller@16040000 { 3299 compatible = "arm,gic-v3-its"; 3300 reg = <0x0 0x16040000 0x0 0x20000>; 3301 3302 msi-controller; 3303 #msi-cells = <1>; 3304 }; 3305 }; 3306 3307 ufs_mem_phy: phy@1d80000 { 3308 compatible = "qcom,sm8750-qmp-ufs-phy"; 3309 reg = <0x0 0x01d80000 0x0 0x2000>; 3310 3311 clocks = <&rpmhcc RPMH_CXO_CLK>, 3312 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3313 <&tcsrcc TCSR_UFS_CLKREF_EN>; 3314 3315 clock-names = "ref", 3316 "ref_aux", 3317 "qref"; 3318 3319 resets = <&ufs_mem_hc 0>; 3320 reset-names = "ufsphy"; 3321 3322 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 3323 3324 #clock-cells = <1>; 3325 #phy-cells = <0>; 3326 3327 status = "disabled"; 3328 }; 3329 3330 ufs_mem_hc: ufs@1d84000 { 3331 compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 3332 reg = <0x0 0x01d84000 0x0 0x3000>; 3333 3334 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3335 3336 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3337 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3338 <&gcc GCC_UFS_PHY_AHB_CLK>, 3339 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3340 <&rpmhcc RPMH_LN_BB_CLK3>, 3341 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3342 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3343 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3344 clock-names = "core_clk", 3345 "bus_aggr_clk", 3346 "iface_clk", 3347 "core_clk_unipro", 3348 "ref_clk", 3349 "tx_lane0_sync_clk", 3350 "rx_lane0_sync_clk", 3351 "rx_lane1_sync_clk"; 3352 3353 operating-points-v2 = <&ufs_opp_table>; 3354 3355 resets = <&gcc GCC_UFS_PHY_BCR>; 3356 reset-names = "rst"; 3357 3358 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 3359 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3361 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3362 interconnect-names = "ufs-ddr", 3363 "cpu-ufs"; 3364 3365 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 3366 required-opps = <&rpmhpd_opp_nom>; 3367 3368 iommus = <&apps_smmu 0x60 0>; 3369 dma-coherent; 3370 3371 lanes-per-direction = <2>; 3372 3373 phys = <&ufs_mem_phy>; 3374 phy-names = "ufsphy"; 3375 3376 #reset-cells = <1>; 3377 3378 status = "disabled"; 3379 3380 ufs_opp_table: opp-table { 3381 compatible = "operating-points-v2"; 3382 3383 opp-100000000 { 3384 opp-hz = /bits/ 64 <100000000>, 3385 /bits/ 64 <0>, 3386 /bits/ 64 <0>, 3387 /bits/ 64 <100000000>, 3388 /bits/ 64 <0>, 3389 /bits/ 64 <0>, 3390 /bits/ 64 <0>, 3391 /bits/ 64 <0>; 3392 required-opps = <&rpmhpd_opp_low_svs>; 3393 }; 3394 3395 opp-403000000 { 3396 opp-hz = /bits/ 64 <403000000>, 3397 /bits/ 64 <0>, 3398 /bits/ 64 <0>, 3399 /bits/ 64 <403000000>, 3400 /bits/ 64 <0>, 3401 /bits/ 64 <0>, 3402 /bits/ 64 <0>, 3403 /bits/ 64 <0>; 3404 required-opps = <&rpmhpd_opp_nom>; 3405 }; 3406 }; 3407 }; 3408 3409 apps_rsc: rsc@16500000 { 3410 compatible = "qcom,rpmh-rsc"; 3411 reg = <0x0 0x16500000 0x0 0x10000>, 3412 <0x0 0x16510000 0x0 0x10000>, 3413 <0x0 0x16520000 0x0 0x10000>; 3414 reg-names = "drv-0", 3415 "drv-1", 3416 "drv-2"; 3417 3418 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3421 qcom,tcs-offset = <0xd00>; 3422 qcom,drv-id = <2>; 3423 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3424 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3425 3426 label = "apps_rsc"; 3427 3428 power-domains = <&system_pd>; 3429 3430 apps_bcm_voter: bcm-voter { 3431 compatible = "qcom,bcm-voter"; 3432 }; 3433 3434 rpmhcc: clock-controller { 3435 compatible = "qcom,sm8750-rpmh-clk"; 3436 3437 clocks = <&xo_board>; 3438 clock-names = "xo"; 3439 3440 #clock-cells = <1>; 3441 }; 3442 3443 rpmhpd: power-controller { 3444 compatible = "qcom,sm8750-rpmhpd"; 3445 3446 operating-points-v2 = <&rpmhpd_opp_table>; 3447 3448 #power-domain-cells = <1>; 3449 3450 rpmhpd_opp_table: opp-table { 3451 compatible = "operating-points-v2"; 3452 3453 rpmhpd_opp_ret: opp-16 { 3454 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3455 }; 3456 3457 rpmhpd_opp_min_svs: opp-48 { 3458 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3459 }; 3460 3461 rpmhpd_opp_low_svs_d3: opp-50 { 3462 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 3463 }; 3464 3465 rpmhpd_opp_low_svs_d2: opp-52 { 3466 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3467 }; 3468 3469 rpmhpd_opp_low_svs_d1: opp-56 { 3470 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3471 }; 3472 3473 rpmhpd_opp_low_svs_d0: opp-60 { 3474 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3475 }; 3476 3477 rpmhpd_opp_low_svs: opp-64 { 3478 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3479 }; 3480 3481 rpmhpd_opp_low_svs_l1: opp-80 { 3482 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3483 }; 3484 3485 rpmhpd_opp_svs: opp-128 { 3486 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3487 }; 3488 3489 rpmhpd_opp_svs_l0: opp-144 { 3490 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3491 }; 3492 3493 rpmhpd_opp_svs_l1: opp-192 { 3494 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3495 }; 3496 3497 rpmhpd_opp_svs_l2: opp-224 { 3498 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3499 }; 3500 3501 rpmhpd_opp_nom: opp-256 { 3502 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3503 }; 3504 3505 rpmhpd_opp_nom_l1: opp-320 { 3506 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3507 }; 3508 3509 rpmhpd_opp_nom_l2: opp-336 { 3510 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3511 }; 3512 3513 rpmhpd_opp_turbo: opp-384 { 3514 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3515 }; 3516 3517 rpmhpd_opp_turbo_l1: opp-416 { 3518 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3519 }; 3520 3521 rpmhpd_opp_turbo_l2: opp-432 { 3522 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 3523 }; 3524 3525 rpmhpd_opp_turbo_l3: opp-448 { 3526 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3527 }; 3528 3529 rpmhpd_opp_turbo_l4: opp-452 { 3530 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 3531 }; 3532 3533 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 3534 opp-level = 3535 <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 3536 }; 3537 }; 3538 }; 3539 }; 3540 3541 timer@16800000 { 3542 compatible = "arm,armv7-timer-mem"; 3543 reg = <0x0 0x16800000 0x0 0x1000>; 3544 3545 #address-cells = <2>; 3546 #size-cells = <1>; 3547 ranges = <0 0 0 0 0x20000000>; 3548 3549 frame@16801000 { 3550 reg = <0x0 0x16801000 0x1000>, 3551 <0x0 0x16802000 0x1000>; 3552 3553 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3555 3556 frame-number = <0>; 3557 }; 3558 3559 frame@16803000 { 3560 reg = <0x0 0x16803000 0x1000>; 3561 3562 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3563 3564 frame-number = <1>; 3565 3566 status = "disabled"; 3567 }; 3568 3569 frame@16805000 { 3570 reg = <0x0 0x16805000 0x1000>; 3571 3572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3573 3574 frame-number = <2>; 3575 3576 status = "disabled"; 3577 }; 3578 3579 frame@16807000 { 3580 reg = <0x0 0x16807000 0x1000>; 3581 3582 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3583 3584 frame-number = <3>; 3585 3586 status = "disabled"; 3587 }; 3588 3589 frame@16809000 { 3590 reg = <0x0 0x16809000 0x1000>; 3591 3592 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3593 3594 frame-number = <4>; 3595 3596 status = "disabled"; 3597 }; 3598 3599 frame@1680b000 { 3600 reg = <0x0 0x1680b000 0x1000>; 3601 3602 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3603 3604 frame-number = <5>; 3605 3606 status = "disabled"; 3607 }; 3608 3609 frame@1680d000 { 3610 reg = <0x0 0x1680d000 0x1000>; 3611 3612 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3613 3614 frame-number = <6>; 3615 3616 status = "disabled"; 3617 }; 3618 }; 3619 3620 gem_noc: interconnect@24100000 { 3621 compatible = "qcom,sm8750-gem-noc"; 3622 reg = <0x0 0x24100000 0x0 0x14b080>; 3623 qcom,bcm-voters = <&apps_bcm_voter>; 3624 #interconnect-cells = <2>; 3625 }; 3626 3627 system-cache-controller@24800000 { 3628 compatible = "qcom,sm8750-llcc"; 3629 reg = <0x0 0x24800000 0x0 0x200000>, 3630 <0x0 0x25800000 0x0 0x200000>, 3631 <0x0 0x24c00000 0x0 0x200000>, 3632 <0x0 0x25c00000 0x0 0x200000>, 3633 <0x0 0x26800000 0x0 0x200000>, 3634 <0x0 0x26c00000 0x0 0x200000>; 3635 reg-names = "llcc0_base", 3636 "llcc1_base", 3637 "llcc2_base", 3638 "llcc3_base", 3639 "llcc_broadcast_base", 3640 "llcc_broadcast_and_base"; 3641 3642 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3643 }; 3644 3645 nsp_noc: interconnect@320c0000 { 3646 compatible = "qcom,sm8750-nsp-noc"; 3647 reg = <0x0 0x320c0000 0x0 0x13080>; 3648 qcom,bcm-voters = <&apps_bcm_voter>; 3649 #interconnect-cells = <2>; 3650 }; 3651 3652 remoteproc_cdsp: remoteproc@32300000 { 3653 compatible = "qcom,sm8750-cdsp-pas", "qcom,sm8650-cdsp-pas"; 3654 reg = <0x0 0x32300000 0x0 0x10000>; 3655 3656 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3657 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3658 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3659 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3660 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 3661 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 3662 interrupt-names = "wdog", 3663 "fatal", 3664 "ready", 3665 "handover", 3666 "stop-ack", 3667 "shutdown-ack"; 3668 3669 clocks = <&rpmhcc RPMH_CXO_CLK>; 3670 clock-names = "xo"; 3671 3672 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 3673 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3674 3675 power-domains = <&rpmhpd RPMHPD_CX>, 3676 <&rpmhpd RPMHPD_MXC>, 3677 <&rpmhpd RPMHPD_NSP>; 3678 power-domain-names = "cx", 3679 "mxc", 3680 "nsp"; 3681 3682 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 3683 qcom,qmp = <&aoss_qmp>; 3684 qcom,smem-states = <&smp2p_cdsp_out 0>; 3685 qcom,smem-state-names = "stop"; 3686 3687 status = "disabled"; 3688 3689 glink-edge { 3690 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3691 IPCC_MPROC_SIGNAL_GLINK_QMP 3692 IRQ_TYPE_EDGE_RISING>; 3693 mboxes = <&ipcc IPCC_CLIENT_CDSP 3694 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3695 qcom,remote-pid = <5>; 3696 label = "cdsp"; 3697 3698 fastrpc { 3699 compatible = "qcom,fastrpc"; 3700 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3701 label = "cdsp"; 3702 qcom,non-secure-domain; 3703 #address-cells = <1>; 3704 #size-cells = <0>; 3705 3706 compute-cb@1 { 3707 compatible = "qcom,fastrpc-compute-cb"; 3708 reg = <1>; 3709 iommus = <&apps_smmu 0x19c1 0x0>, 3710 <&apps_smmu 0x0c21 0x0>, 3711 <&apps_smmu 0x0c01 0x40>; 3712 dma-coherent; 3713 }; 3714 3715 compute-cb@2 { 3716 compatible = "qcom,fastrpc-compute-cb"; 3717 reg = <2>; 3718 iommus = <&apps_smmu 0x1962 0x0>, 3719 <&apps_smmu 0x0c02 0x20>, 3720 <&apps_smmu 0x0c42 0x0>, 3721 <&apps_smmu 0x19c2 0x0>; 3722 dma-coherent; 3723 }; 3724 3725 compute-cb@3 { 3726 compatible = "qcom,fastrpc-compute-cb"; 3727 reg = <3>; 3728 iommus = <&apps_smmu 0x1963 0x0>, 3729 <&apps_smmu 0x0c23 0x0>, 3730 <&apps_smmu 0x0c03 0x40>, 3731 <&apps_smmu 0x19c3 0x0>; 3732 dma-coherent; 3733 }; 3734 3735 compute-cb@4 { 3736 compatible = "qcom,fastrpc-compute-cb"; 3737 reg = <4>; 3738 iommus = <&apps_smmu 0x1964 0x0>, 3739 <&apps_smmu 0x0c24 0x0>, 3740 <&apps_smmu 0x0c04 0x40>, 3741 <&apps_smmu 0x19c4 0x0>; 3742 dma-coherent; 3743 }; 3744 3745 compute-cb@5 { 3746 compatible = "qcom,fastrpc-compute-cb"; 3747 reg = <5>; 3748 iommus = <&apps_smmu 0x1965 0x0>, 3749 <&apps_smmu 0x0c25 0x0>, 3750 <&apps_smmu 0x0c05 0x40>, 3751 <&apps_smmu 0x19c5 0x0>; 3752 dma-coherent; 3753 }; 3754 3755 compute-cb@6 { 3756 compatible = "qcom,fastrpc-compute-cb"; 3757 reg = <6>; 3758 iommus = <&apps_smmu 0x1966 0x0>, 3759 <&apps_smmu 0x0c06 0x20>, 3760 <&apps_smmu 0x0c46 0x0>, 3761 <&apps_smmu 0x19c6 0x0>; 3762 dma-coherent; 3763 }; 3764 3765 compute-cb@7 { 3766 compatible = "qcom,fastrpc-compute-cb"; 3767 reg = <7>; 3768 iommus = <&apps_smmu 0x1967 0x0>, 3769 <&apps_smmu 0x0c27 0x0>, 3770 <&apps_smmu 0x0c07 0x40>, 3771 <&apps_smmu 0x19c7 0x0>; 3772 dma-coherent; 3773 }; 3774 3775 compute-cb@8 { 3776 compatible = "qcom,fastrpc-compute-cb"; 3777 reg = <8>; 3778 iommus = <&apps_smmu 0x1968 0x0>, 3779 <&apps_smmu 0x0c08 0x20>, 3780 <&apps_smmu 0x0c48 0x0>, 3781 <&apps_smmu 0x19c8 0x0>; 3782 dma-coherent; 3783 }; 3784 3785 /* note: secure cb9 in downstream */ 3786 3787 compute-cb@12 { 3788 compatible = "qcom,fastrpc-compute-cb"; 3789 reg = <12>; 3790 iommus = <&apps_smmu 0x196c 0x0>, 3791 <&apps_smmu 0x0c2c 0x20>, 3792 <&apps_smmu 0x0c0c 0x40>, 3793 <&apps_smmu 0x19cc 0x0>; 3794 dma-coherent; 3795 }; 3796 3797 compute-cb@13 { 3798 compatible = "qcom,fastrpc-compute-cb"; 3799 reg = <13>; 3800 iommus = <&apps_smmu 0x196d 0x0>, 3801 <&apps_smmu 0x0c0d 0x20>, 3802 <&apps_smmu 0x0c2e 0x0>, 3803 <&apps_smmu 0x0c4d 0x0>, 3804 <&apps_smmu 0x19cd 0x0>; 3805 dma-coherent; 3806 }; 3807 3808 compute-cb@14 { 3809 compatible = "qcom,fastrpc-compute-cb"; 3810 reg = <14>; 3811 iommus = <&apps_smmu 0x196e 0x0>, 3812 <&apps_smmu 0x0c0e 0x20>, 3813 <&apps_smmu 0x19ce 0x0>; 3814 dma-coherent; 3815 }; 3816 }; 3817 }; 3818 }; 3819 }; 3820 3821 timer { 3822 compatible = "arm,armv8-timer"; 3823 3824 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3825 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3826 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3827 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3828 }; 3829}; 3830