1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8650-camcc.h> 9#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 10#include <dt-bindings/clock/qcom,sm8650-gcc.h> 11#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8650-videocc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,icc.h> 18#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/mailbox/qcom-ipcc.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/power/qcom,rpmhpd.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 26#include <dt-bindings/soc/qcom,gpr.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 29#include <dt-bindings/thermal/thermal.h> 30 31/ { 32 interrupt-parent = <&intc>; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 37 chosen { }; 38 39 clocks { 40 xo_board: xo-board { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 }; 44 45 sleep_clk: sleep-clk { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 }; 49 50 bi_tcxo_div2: bi-tcxo-div2-clk { 51 compatible = "fixed-factor-clock"; 52 #clock-cells = <0>; 53 54 clocks = <&rpmhcc RPMH_CXO_CLK>; 55 clock-mult = <1>; 56 clock-div = <2>; 57 }; 58 59 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 60 compatible = "fixed-factor-clock"; 61 #clock-cells = <0>; 62 63 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 64 clock-mult = <1>; 65 clock-div = <2>; 66 }; 67 }; 68 69 cpus { 70 #address-cells = <2>; 71 #size-cells = <0>; 72 73 cpu0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a520"; 76 reg = <0 0>; 77 78 clocks = <&cpufreq_hw 0>; 79 80 power-domains = <&cpu_pd0>; 81 power-domain-names = "psci"; 82 83 enable-method = "psci"; 84 next-level-cache = <&l2_0>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 88 qcom,freq-domain = <&cpufreq_hw 0>; 89 90 operating-points-v2 = <&cpu0_opp_table>; 91 92 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 93 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 94 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 95 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 96 <&epss_l3 MASTER_EPSS_L3_APPS 97 &epss_l3 SLAVE_EPSS_L3_SHARED>; 98 99 #cooling-cells = <2>; 100 101 l2_0: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&l3_0>; 106 107 l3_0: l3-cache { 108 compatible = "cache"; 109 cache-level = <3>; 110 cache-unified; 111 }; 112 }; 113 }; 114 115 cpu1: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a520"; 118 reg = <0 0x100>; 119 120 clocks = <&cpufreq_hw 0>; 121 122 power-domains = <&cpu_pd1>; 123 power-domain-names = "psci"; 124 125 enable-method = "psci"; 126 next-level-cache = <&l2_0>; 127 capacity-dmips-mhz = <1024>; 128 dynamic-power-coefficient = <100>; 129 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 132 operating-points-v2 = <&cpu0_opp_table>; 133 134 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 135 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 136 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 137 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 138 <&epss_l3 MASTER_EPSS_L3_APPS 139 &epss_l3 SLAVE_EPSS_L3_SHARED>; 140 141 #cooling-cells = <2>; 142 }; 143 144 cpu2: cpu@200 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a720"; 147 reg = <0 0x200>; 148 149 clocks = <&cpufreq_hw 3>; 150 151 power-domains = <&cpu_pd2>; 152 power-domain-names = "psci"; 153 154 enable-method = "psci"; 155 next-level-cache = <&l2_200>; 156 capacity-dmips-mhz = <1792>; 157 dynamic-power-coefficient = <238>; 158 159 qcom,freq-domain = <&cpufreq_hw 3>; 160 161 operating-points-v2 = <&cpu2_opp_table>; 162 163 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 164 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 165 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 166 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 167 <&epss_l3 MASTER_EPSS_L3_APPS 168 &epss_l3 SLAVE_EPSS_L3_SHARED>; 169 170 #cooling-cells = <2>; 171 172 l2_200: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&l3_0>; 177 }; 178 }; 179 180 cpu3: cpu@300 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a720"; 183 reg = <0 0x300>; 184 185 clocks = <&cpufreq_hw 3>; 186 187 power-domains = <&cpu_pd3>; 188 power-domain-names = "psci"; 189 190 enable-method = "psci"; 191 next-level-cache = <&l2_300>; 192 capacity-dmips-mhz = <1792>; 193 dynamic-power-coefficient = <238>; 194 195 qcom,freq-domain = <&cpufreq_hw 3>; 196 197 operating-points-v2 = <&cpu2_opp_table>; 198 199 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 200 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 201 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 203 <&epss_l3 MASTER_EPSS_L3_APPS 204 &epss_l3 SLAVE_EPSS_L3_SHARED>; 205 206 #cooling-cells = <2>; 207 208 l2_300: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 cache-unified; 212 next-level-cache = <&l3_0>; 213 }; 214 }; 215 216 cpu4: cpu@400 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a720"; 219 reg = <0 0x400>; 220 221 clocks = <&cpufreq_hw 3>; 222 223 power-domains = <&cpu_pd4>; 224 power-domain-names = "psci"; 225 226 enable-method = "psci"; 227 next-level-cache = <&l2_400>; 228 capacity-dmips-mhz = <1792>; 229 dynamic-power-coefficient = <238>; 230 231 qcom,freq-domain = <&cpufreq_hw 3>; 232 233 operating-points-v2 = <&cpu2_opp_table>; 234 235 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 236 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 237 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 238 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 239 <&epss_l3 MASTER_EPSS_L3_APPS 240 &epss_l3 SLAVE_EPSS_L3_SHARED>; 241 242 #cooling-cells = <2>; 243 244 l2_400: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&l3_0>; 249 }; 250 }; 251 252 cpu5: cpu@500 { 253 device_type = "cpu"; 254 compatible = "arm,cortex-a720"; 255 reg = <0 0x500>; 256 257 clocks = <&cpufreq_hw 1>; 258 259 power-domains = <&cpu_pd5>; 260 power-domain-names = "psci"; 261 262 enable-method = "psci"; 263 next-level-cache = <&l2_500>; 264 capacity-dmips-mhz = <1792>; 265 dynamic-power-coefficient = <238>; 266 267 qcom,freq-domain = <&cpufreq_hw 1>; 268 269 operating-points-v2 = <&cpu5_opp_table>; 270 271 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 272 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 273 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 275 <&epss_l3 MASTER_EPSS_L3_APPS 276 &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 278 #cooling-cells = <2>; 279 280 l2_500: l2-cache { 281 compatible = "cache"; 282 cache-level = <2>; 283 cache-unified; 284 next-level-cache = <&l3_0>; 285 }; 286 }; 287 288 cpu6: cpu@600 { 289 device_type = "cpu"; 290 compatible = "arm,cortex-a720"; 291 reg = <0 0x600>; 292 293 clocks = <&cpufreq_hw 1>; 294 295 power-domains = <&cpu_pd6>; 296 power-domain-names = "psci"; 297 298 enable-method = "psci"; 299 next-level-cache = <&l2_600>; 300 capacity-dmips-mhz = <1792>; 301 dynamic-power-coefficient = <238>; 302 303 qcom,freq-domain = <&cpufreq_hw 1>; 304 305 operating-points-v2 = <&cpu5_opp_table>; 306 307 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 308 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 309 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 311 <&epss_l3 MASTER_EPSS_L3_APPS 312 &epss_l3 SLAVE_EPSS_L3_SHARED>; 313 314 #cooling-cells = <2>; 315 316 l2_600: l2-cache { 317 compatible = "cache"; 318 cache-level = <2>; 319 cache-unified; 320 next-level-cache = <&l3_0>; 321 }; 322 }; 323 324 cpu7: cpu@700 { 325 device_type = "cpu"; 326 compatible = "arm,cortex-x4"; 327 reg = <0 0x700>; 328 329 clocks = <&cpufreq_hw 2>; 330 331 power-domains = <&cpu_pd7>; 332 power-domain-names = "psci"; 333 334 enable-method = "psci"; 335 next-level-cache = <&l2_700>; 336 capacity-dmips-mhz = <1894>; 337 dynamic-power-coefficient = <588>; 338 339 qcom,freq-domain = <&cpufreq_hw 2>; 340 341 operating-points-v2 = <&cpu7_opp_table>; 342 343 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 344 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 345 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 347 <&epss_l3 MASTER_EPSS_L3_APPS 348 &epss_l3 SLAVE_EPSS_L3_SHARED>; 349 350 #cooling-cells = <2>; 351 352 l2_700: l2-cache { 353 compatible = "cache"; 354 cache-level = <2>; 355 cache-unified; 356 next-level-cache = <&l3_0>; 357 }; 358 }; 359 360 cpu-map { 361 cluster0 { 362 core0 { 363 cpu = <&cpu0>; 364 }; 365 366 core1 { 367 cpu = <&cpu1>; 368 }; 369 370 core2 { 371 cpu = <&cpu2>; 372 }; 373 374 core3 { 375 cpu = <&cpu3>; 376 }; 377 378 core4 { 379 cpu = <&cpu4>; 380 }; 381 382 core5 { 383 cpu = <&cpu5>; 384 }; 385 386 core6 { 387 cpu = <&cpu6>; 388 }; 389 390 core7 { 391 cpu = <&cpu7>; 392 }; 393 }; 394 }; 395 396 idle-states { 397 entry-method = "psci"; 398 399 silver_cpu_sleep_0: cpu-sleep-0-0 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "silver-rail-power-collapse"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <550>; 404 exit-latency-us = <750>; 405 min-residency-us = <6700>; 406 local-timer-stop; 407 }; 408 409 gold_cpu_sleep_0: cpu-sleep-1-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "gold-rail-power-collapse"; 412 arm,psci-suspend-param = <0x40000004>; 413 entry-latency-us = <600>; 414 exit-latency-us = <1300>; 415 min-residency-us = <8136>; 416 local-timer-stop; 417 }; 418 419 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "gold-plus-rail-power-collapse"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <500>; 424 exit-latency-us = <1350>; 425 min-residency-us = <7480>; 426 local-timer-stop; 427 }; 428 }; 429 430 domain-idle-states { 431 cluster_sleep_0: cluster-sleep-0 { 432 compatible = "domain-idle-state"; 433 arm,psci-suspend-param = <0x41000044>; 434 entry-latency-us = <750>; 435 exit-latency-us = <2350>; 436 min-residency-us = <9144>; 437 }; 438 439 cluster_sleep_1: cluster-sleep-1 { 440 compatible = "domain-idle-state"; 441 arm,psci-suspend-param = <0x4100c344>; 442 entry-latency-us = <2800>; 443 exit-latency-us = <4400>; 444 min-residency-us = <10150>; 445 }; 446 }; 447 }; 448 449 ete-0 { 450 compatible = "arm,embedded-trace-extension"; 451 452 cpu = <&cpu0>; 453 454 out-ports { 455 port { 456 ete0_out_funnel_ete: endpoint { 457 remote-endpoint = <&funnel_ete_in_ete0>; 458 }; 459 }; 460 }; 461 }; 462 463 ete-1 { 464 compatible = "arm,embedded-trace-extension"; 465 466 cpu = <&cpu1>; 467 468 out-ports { 469 port { 470 ete1_out_funnel_ete: endpoint { 471 remote-endpoint = <&funnel_ete_in_ete1>; 472 }; 473 }; 474 }; 475 }; 476 477 ete-2 { 478 compatible = "arm,embedded-trace-extension"; 479 480 cpu = <&cpu2>; 481 482 out-ports { 483 port { 484 ete2_out_funnel_ete: endpoint { 485 remote-endpoint = <&funnel_ete_in_ete2>; 486 }; 487 }; 488 }; 489 }; 490 491 ete-3 { 492 compatible = "arm,embedded-trace-extension"; 493 494 cpu = <&cpu3>; 495 496 out-ports { 497 port { 498 ete3_out_funnel_ete: endpoint { 499 remote-endpoint = <&funnel_ete_in_ete3>; 500 }; 501 }; 502 }; 503 }; 504 505 ete-4 { 506 compatible = "arm,embedded-trace-extension"; 507 508 cpu = <&cpu4>; 509 510 out-ports { 511 port { 512 ete4_out_funnel_ete: endpoint { 513 remote-endpoint = <&funnel_ete_in_ete4>; 514 }; 515 }; 516 }; 517 }; 518 519 ete-5 { 520 compatible = "arm,embedded-trace-extension"; 521 522 cpu = <&cpu5>; 523 524 out-ports { 525 port { 526 ete5_out_funnel_ete: endpoint { 527 remote-endpoint = <&funnel_ete_in_ete5>; 528 }; 529 }; 530 }; 531 }; 532 533 ete-6 { 534 compatible = "arm,embedded-trace-extension"; 535 536 cpu = <&cpu6>; 537 538 out-ports { 539 port { 540 ete6_out_funnel_ete: endpoint { 541 remote-endpoint = <&funnel_ete_in_ete6>; 542 }; 543 }; 544 }; 545 }; 546 547 ete-7 { 548 compatible = "arm,embedded-trace-extension"; 549 550 cpu = <&cpu7>; 551 552 out-ports { 553 port { 554 ete7_out_funnel_ete: endpoint { 555 remote-endpoint = <&funnel_ete_in_ete7>; 556 }; 557 }; 558 }; 559 }; 560 561 funnel-ete { 562 compatible = "arm,coresight-static-funnel"; 563 564 in-ports { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 568 port@0 { 569 reg = <0>; 570 571 funnel_ete_in_ete0: endpoint { 572 remote-endpoint = <&ete0_out_funnel_ete>; 573 }; 574 }; 575 576 port@1 { 577 reg = <1>; 578 579 funnel_ete_in_ete1: endpoint { 580 remote-endpoint = <&ete1_out_funnel_ete>; 581 }; 582 }; 583 584 port@2 { 585 reg = <2>; 586 587 funnel_ete_in_ete2: endpoint { 588 remote-endpoint = <&ete2_out_funnel_ete>; 589 }; 590 }; 591 592 port@3 { 593 reg = <3>; 594 595 funnel_ete_in_ete3: endpoint { 596 remote-endpoint = <&ete3_out_funnel_ete>; 597 }; 598 }; 599 600 port@4 { 601 reg = <4>; 602 603 funnel_ete_in_ete4: endpoint { 604 remote-endpoint = <&ete4_out_funnel_ete>; 605 }; 606 }; 607 608 port@5 { 609 reg = <5>; 610 611 funnel_ete_in_ete5: endpoint { 612 remote-endpoint = <&ete5_out_funnel_ete>; 613 }; 614 }; 615 616 port@6 { 617 reg = <6>; 618 619 funnel_ete_in_ete6: endpoint { 620 remote-endpoint = <&ete6_out_funnel_ete>; 621 }; 622 }; 623 624 port@7 { 625 reg = <7>; 626 627 funnel_ete_in_ete7: endpoint { 628 remote-endpoint = <&ete7_out_funnel_ete>; 629 }; 630 }; 631 }; 632 633 out-ports { 634 port { 635 funnel_ete_out_funnel_apss: endpoint { 636 remote-endpoint = <&funnel_apss_in_funnel_ete>; 637 }; 638 }; 639 }; 640 }; 641 642 firmware { 643 scm: scm { 644 compatible = "qcom,scm-sm8650", "qcom,scm"; 645 qcom,dload-mode = <&tcsr 0x19000>; 646 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 647 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 648 }; 649 }; 650 651 clk_virt: interconnect-0 { 652 compatible = "qcom,sm8650-clk-virt"; 653 #interconnect-cells = <2>; 654 qcom,bcm-voters = <&apps_bcm_voter>; 655 }; 656 657 mc_virt: interconnect-1 { 658 compatible = "qcom,sm8650-mc-virt"; 659 #interconnect-cells = <2>; 660 qcom,bcm-voters = <&apps_bcm_voter>; 661 }; 662 663 qup_opp_table_100mhz: opp-table-qup100mhz { 664 compatible = "operating-points-v2"; 665 666 opp-75000000 { 667 opp-hz = /bits/ 64 <75000000>; 668 required-opps = <&rpmhpd_opp_low_svs>; 669 }; 670 671 opp-100000000 { 672 opp-hz = /bits/ 64 <100000000>; 673 required-opps = <&rpmhpd_opp_svs>; 674 }; 675 }; 676 677 qup_opp_table_120mhz: opp-table-qup120mhz { 678 compatible = "operating-points-v2"; 679 680 opp-75000000 { 681 opp-hz = /bits/ 64 <75000000>; 682 required-opps = <&rpmhpd_opp_low_svs>; 683 }; 684 685 opp-120000000 { 686 opp-hz = /bits/ 64 <120000000>; 687 required-opps = <&rpmhpd_opp_svs>; 688 }; 689 }; 690 691 qup_opp_table_128mhz: opp-table-qup128mhz { 692 compatible = "operating-points-v2"; 693 694 opp-75000000 { 695 opp-hz = /bits/ 64 <75000000>; 696 required-opps = <&rpmhpd_opp_low_svs>; 697 }; 698 699 opp-128000000 { 700 opp-hz = /bits/ 64 <128000000>; 701 required-opps = <&rpmhpd_opp_svs>; 702 }; 703 }; 704 705 qup_opp_table_240mhz: opp-table-qup240mhz { 706 compatible = "operating-points-v2"; 707 708 opp-150000000 { 709 opp-hz = /bits/ 64 <150000000>; 710 required-opps = <&rpmhpd_opp_low_svs>; 711 }; 712 713 opp-240000000 { 714 opp-hz = /bits/ 64 <240000000>; 715 required-opps = <&rpmhpd_opp_svs>; 716 }; 717 }; 718 719 memory@a0000000 { 720 device_type = "memory"; 721 /* We expect the bootloader to fill in the size */ 722 reg = <0 0xa0000000 0 0>; 723 }; 724 725 cpu0_opp_table: opp-table-cpu0 { 726 compatible = "operating-points-v2"; 727 opp-shared; 728 729 opp-307200000 { 730 opp-hz = /bits/ 64 <307200000>; 731 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 732 }; 733 734 opp-364800000 { 735 opp-hz = /bits/ 64 <364800000>; 736 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 737 }; 738 739 opp-460800000 { 740 opp-hz = /bits/ 64 <460800000>; 741 opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>; 742 }; 743 744 opp-556800000 { 745 opp-hz = /bits/ 64 <556800000>; 746 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 747 }; 748 749 opp-672000000 { 750 opp-hz = /bits/ 64 <672000000>; 751 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 752 }; 753 754 opp-787200000 { 755 opp-hz = /bits/ 64 <787200000>; 756 opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>; 757 }; 758 759 opp-902400000 { 760 opp-hz = /bits/ 64 <902400000>; 761 opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>; 762 }; 763 764 opp-1017600000 { 765 opp-hz = /bits/ 64 <1017600000>; 766 opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>; 767 }; 768 769 opp-1132800000 { 770 opp-hz = /bits/ 64 <1132800000>; 771 opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>; 772 }; 773 774 opp-1248000000 { 775 opp-hz = /bits/ 64 <1248000000>; 776 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>; 777 }; 778 779 opp-1344000000 { 780 opp-hz = /bits/ 64 <1344000000>; 781 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 782 }; 783 784 opp-1440000000 { 785 opp-hz = /bits/ 64 <1440000000>; 786 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 787 }; 788 789 opp-1459200000 { 790 opp-hz = /bits/ 64 <1459200000>; 791 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 792 }; 793 794 opp-1536000000 { 795 opp-hz = /bits/ 64 <1536000000>; 796 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; 797 }; 798 799 opp-1574400000 { 800 opp-hz = /bits/ 64 <1574400000>; 801 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; 802 }; 803 804 opp-1651200000 { 805 opp-hz = /bits/ 64 <1651200000>; 806 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 807 }; 808 809 opp-1689600000 { 810 opp-hz = /bits/ 64 <1689600000>; 811 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 812 }; 813 814 opp-1747200000 { 815 opp-hz = /bits/ 64 <1747200000>; 816 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 817 }; 818 819 opp-1804800000 { 820 opp-hz = /bits/ 64 <1804800000>; 821 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; 822 }; 823 824 opp-1843200000 { 825 opp-hz = /bits/ 64 <1843200000>; 826 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; 827 }; 828 829 opp-1920000000 { 830 opp-hz = /bits/ 64 <1920000000>; 831 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; 832 }; 833 834 opp-1939200000 { 835 opp-hz = /bits/ 64 <1939200000>; 836 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; 837 }; 838 839 opp-2035200000 { 840 opp-hz = /bits/ 64 <2035200000>; 841 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; 842 }; 843 844 opp-2150400000 { 845 opp-hz = /bits/ 64 <2150400000>; 846 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; 847 }; 848 849 opp-2265600000 { 850 opp-hz = /bits/ 64 <2265600000>; 851 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>; 852 }; 853 }; 854 855 cpu2_opp_table: opp-table-cpu2 { 856 compatible = "operating-points-v2"; 857 opp-shared; 858 859 opp-460800000 { 860 opp-hz = /bits/ 64 <460800000>; 861 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 862 }; 863 864 opp-499200000 { 865 opp-hz = /bits/ 64 <499200000>; 866 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 867 }; 868 869 opp-576000000 { 870 opp-hz = /bits/ 64 <576000000>; 871 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 872 }; 873 874 opp-614400000 { 875 opp-hz = /bits/ 64 <614400000>; 876 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 877 }; 878 879 opp-691200000 { 880 opp-hz = /bits/ 64 <691200000>; 881 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 882 }; 883 884 opp-729600000 { 885 opp-hz = /bits/ 64 <729600000>; 886 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 887 }; 888 889 opp-806400000 { 890 opp-hz = /bits/ 64 <806400000>; 891 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 892 }; 893 894 opp-844800000 { 895 opp-hz = /bits/ 64 <844800000>; 896 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 897 }; 898 899 opp-902400000 { 900 opp-hz = /bits/ 64 <902400000>; 901 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 902 }; 903 904 opp-960000000 { 905 opp-hz = /bits/ 64 <960000000>; 906 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; 907 }; 908 909 opp-1036800000 { 910 opp-hz = /bits/ 64 <1036800000>; 911 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 912 }; 913 914 opp-1075200000 { 915 opp-hz = /bits/ 64 <1075200000>; 916 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 917 }; 918 919 opp-1152000000 { 920 opp-hz = /bits/ 64 <1152000000>; 921 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 922 }; 923 924 opp-1190400000 { 925 opp-hz = /bits/ 64 <1190400000>; 926 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 927 }; 928 929 opp-1267200000 { 930 opp-hz = /bits/ 64 <1267200000>; 931 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 932 }; 933 934 opp-1286400000 { 935 opp-hz = /bits/ 64 <1286400000>; 936 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 937 }; 938 939 opp-1382400000 { 940 opp-hz = /bits/ 64 <1382400000>; 941 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 942 }; 943 944 opp-1401600000 { 945 opp-hz = /bits/ 64 <1401600000>; 946 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 947 }; 948 949 opp-1497600000 { 950 opp-hz = /bits/ 64 <1497600000>; 951 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 952 }; 953 954 opp-1612800000 { 955 opp-hz = /bits/ 64 <1612800000>; 956 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 957 }; 958 959 opp-1708800000 { 960 opp-hz = /bits/ 64 <1708800000>; 961 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 962 }; 963 964 opp-1728000000 { 965 opp-hz = /bits/ 64 <1728000000>; 966 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 967 }; 968 969 opp-1824000000 { 970 opp-hz = /bits/ 64 <1824000000>; 971 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 972 }; 973 974 opp-1843200000 { 975 opp-hz = /bits/ 64 <1843200000>; 976 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 977 }; 978 979 opp-1920000000 { 980 opp-hz = /bits/ 64 <1920000000>; 981 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; 982 }; 983 984 opp-1958400000 { 985 opp-hz = /bits/ 64 <1958400000>; 986 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 987 }; 988 989 opp-2035200000 { 990 opp-hz = /bits/ 64 <2035200000>; 991 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 992 }; 993 994 opp-2073600000 { 995 opp-hz = /bits/ 64 <2073600000>; 996 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 997 }; 998 999 opp-2131200000 { 1000 opp-hz = /bits/ 64 <2131200000>; 1001 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1002 }; 1003 1004 opp-2188800000 { 1005 opp-hz = /bits/ 64 <2188800000>; 1006 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1007 }; 1008 1009 opp-2246400000 { 1010 opp-hz = /bits/ 64 <2246400000>; 1011 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1012 }; 1013 1014 opp-2304000000 { 1015 opp-hz = /bits/ 64 <2304000000>; 1016 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1017 }; 1018 1019 opp-2323200000 { 1020 opp-hz = /bits/ 64 <2323200000>; 1021 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1022 }; 1023 1024 opp-2380800000 { 1025 opp-hz = /bits/ 64 <2380800000>; 1026 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1027 }; 1028 1029 opp-2400000000 { 1030 opp-hz = /bits/ 64 <2400000000>; 1031 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1032 }; 1033 1034 opp-2438400000 { 1035 opp-hz = /bits/ 64 <2438400000>; 1036 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1037 }; 1038 1039 opp-2515200000 { 1040 opp-hz = /bits/ 64 <2515200000>; 1041 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1042 }; 1043 1044 opp-2572800000 { 1045 opp-hz = /bits/ 64 <2572800000>; 1046 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1047 }; 1048 1049 opp-2630400000 { 1050 opp-hz = /bits/ 64 <2630400000>; 1051 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1052 }; 1053 1054 opp-2707200000 { 1055 opp-hz = /bits/ 64 <2707200000>; 1056 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1057 }; 1058 1059 opp-2764800000 { 1060 opp-hz = /bits/ 64 <2764800000>; 1061 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1062 }; 1063 1064 opp-2841600000 { 1065 opp-hz = /bits/ 64 <2841600000>; 1066 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1067 }; 1068 1069 opp-2899200000 { 1070 opp-hz = /bits/ 64 <2899200000>; 1071 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1072 }; 1073 1074 opp-2956800000 { 1075 opp-hz = /bits/ 64 <2956800000>; 1076 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1077 }; 1078 1079 opp-3014400000 { 1080 opp-hz = /bits/ 64 <3014400000>; 1081 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1082 }; 1083 1084 opp-3072000000 { 1085 opp-hz = /bits/ 64 <3072000000>; 1086 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1087 }; 1088 1089 opp-3148800000 { 1090 opp-hz = /bits/ 64 <3148800000>; 1091 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1092 }; 1093 }; 1094 1095 cpu5_opp_table: opp-table-cpu5 { 1096 compatible = "operating-points-v2"; 1097 opp-shared; 1098 1099 opp-460800000 { 1100 opp-hz = /bits/ 64 <460800000>; 1101 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1102 }; 1103 1104 opp-499200000 { 1105 opp-hz = /bits/ 64 <499200000>; 1106 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1107 }; 1108 1109 opp-576000000 { 1110 opp-hz = /bits/ 64 <576000000>; 1111 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1112 }; 1113 1114 opp-614400000 { 1115 opp-hz = /bits/ 64 <614400000>; 1116 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 1117 }; 1118 1119 opp-691200000 { 1120 opp-hz = /bits/ 64 <691200000>; 1121 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1122 }; 1123 1124 opp-729600000 { 1125 opp-hz = /bits/ 64 <729600000>; 1126 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1127 }; 1128 1129 opp-806400000 { 1130 opp-hz = /bits/ 64 <806400000>; 1131 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1132 }; 1133 1134 opp-844800000 { 1135 opp-hz = /bits/ 64 <844800000>; 1136 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1137 }; 1138 1139 opp-902400000 { 1140 opp-hz = /bits/ 64 <902400000>; 1141 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1142 }; 1143 1144 opp-960000000 { 1145 opp-hz = /bits/ 64 <960000000>; 1146 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; 1147 }; 1148 1149 opp-1036800000 { 1150 opp-hz = /bits/ 64 <1036800000>; 1151 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1152 }; 1153 1154 opp-1075200000 { 1155 opp-hz = /bits/ 64 <1075200000>; 1156 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1157 }; 1158 1159 opp-1152000000 { 1160 opp-hz = /bits/ 64 <1152000000>; 1161 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1162 }; 1163 1164 opp-1190400000 { 1165 opp-hz = /bits/ 64 <1190400000>; 1166 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 1167 }; 1168 1169 opp-1267200000 { 1170 opp-hz = /bits/ 64 <1267200000>; 1171 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1172 }; 1173 1174 opp-1286400000 { 1175 opp-hz = /bits/ 64 <1286400000>; 1176 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1177 }; 1178 1179 opp-1382400000 { 1180 opp-hz = /bits/ 64 <1382400000>; 1181 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1182 }; 1183 1184 opp-1401600000 { 1185 opp-hz = /bits/ 64 <1401600000>; 1186 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1187 }; 1188 1189 opp-1497600000 { 1190 opp-hz = /bits/ 64 <1497600000>; 1191 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1192 }; 1193 1194 opp-1612800000 { 1195 opp-hz = /bits/ 64 <1612800000>; 1196 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1197 }; 1198 1199 opp-1708800000 { 1200 opp-hz = /bits/ 64 <1708800000>; 1201 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1202 }; 1203 1204 opp-1728000000 { 1205 opp-hz = /bits/ 64 <1728000000>; 1206 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1207 }; 1208 1209 opp-1824000000 { 1210 opp-hz = /bits/ 64 <1824000000>; 1211 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1212 }; 1213 1214 opp-1843200000 { 1215 opp-hz = /bits/ 64 <1843200000>; 1216 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1217 }; 1218 1219 opp-1920000000 { 1220 opp-hz = /bits/ 64 <1920000000>; 1221 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; 1222 }; 1223 1224 opp-1958400000 { 1225 opp-hz = /bits/ 64 <1958400000>; 1226 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1227 }; 1228 1229 opp-2035200000 { 1230 opp-hz = /bits/ 64 <2035200000>; 1231 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1232 }; 1233 1234 opp-2073600000 { 1235 opp-hz = /bits/ 64 <2073600000>; 1236 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1237 }; 1238 1239 opp-2131200000 { 1240 opp-hz = /bits/ 64 <2131200000>; 1241 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1242 }; 1243 1244 opp-2188800000 { 1245 opp-hz = /bits/ 64 <2188800000>; 1246 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1247 }; 1248 1249 opp-2246400000 { 1250 opp-hz = /bits/ 64 <2246400000>; 1251 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1252 }; 1253 1254 opp-2304000000 { 1255 opp-hz = /bits/ 64 <2304000000>; 1256 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1257 }; 1258 1259 opp-2323200000 { 1260 opp-hz = /bits/ 64 <2323200000>; 1261 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1262 }; 1263 1264 opp-2380800000 { 1265 opp-hz = /bits/ 64 <2380800000>; 1266 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1267 }; 1268 1269 opp-2400000000 { 1270 opp-hz = /bits/ 64 <2400000000>; 1271 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1272 }; 1273 1274 opp-2438400000 { 1275 opp-hz = /bits/ 64 <2438400000>; 1276 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1277 }; 1278 1279 opp-2515200000 { 1280 opp-hz = /bits/ 64 <2515200000>; 1281 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1282 }; 1283 1284 opp-2572800000 { 1285 opp-hz = /bits/ 64 <2572800000>; 1286 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1287 }; 1288 1289 opp-2630400000 { 1290 opp-hz = /bits/ 64 <2630400000>; 1291 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1292 }; 1293 1294 opp-2707200000 { 1295 opp-hz = /bits/ 64 <2707200000>; 1296 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1297 }; 1298 1299 opp-2764800000 { 1300 opp-hz = /bits/ 64 <2764800000>; 1301 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1302 }; 1303 1304 opp-2841600000 { 1305 opp-hz = /bits/ 64 <2841600000>; 1306 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1307 }; 1308 1309 opp-2899200000 { 1310 opp-hz = /bits/ 64 <2899200000>; 1311 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1312 }; 1313 1314 opp-2956800000 { 1315 opp-hz = /bits/ 64 <2956800000>; 1316 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1317 }; 1318 1319 opp-3014400000 { 1320 opp-hz = /bits/ 64 <3014400000>; 1321 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1322 }; 1323 1324 opp-3072000000 { 1325 opp-hz = /bits/ 64 <3072000000>; 1326 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1327 }; 1328 1329 opp-3148800000 { 1330 opp-hz = /bits/ 64 <3148800000>; 1331 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1332 }; 1333 }; 1334 1335 cpu7_opp_table: opp-table-cpu7 { 1336 compatible = "operating-points-v2"; 1337 opp-shared; 1338 1339 opp-480000000 { 1340 opp-hz = /bits/ 64 <480000000>; 1341 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1342 }; 1343 1344 opp-499200000 { 1345 opp-hz = /bits/ 64 <499200000>; 1346 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1347 }; 1348 1349 opp-576000000 { 1350 opp-hz = /bits/ 64 <576000000>; 1351 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1352 }; 1353 1354 opp-614400000 { 1355 opp-hz = /bits/ 64 <614400000>; 1356 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 1357 }; 1358 1359 opp-672000000 { 1360 opp-hz = /bits/ 64 <672000000>; 1361 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1362 }; 1363 1364 opp-729600000 { 1365 opp-hz = /bits/ 64 <729600000>; 1366 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1367 }; 1368 1369 opp-787200000 { 1370 opp-hz = /bits/ 64 <787200000>; 1371 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1372 }; 1373 1374 opp-844800000 { 1375 opp-hz = /bits/ 64 <844800000>; 1376 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1377 }; 1378 1379 opp-902400000 { 1380 opp-hz = /bits/ 64 <902400000>; 1381 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1382 }; 1383 1384 opp-940800000 { 1385 opp-hz = /bits/ 64 <940800000>; 1386 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1387 }; 1388 1389 opp-1017600000 { 1390 opp-hz = /bits/ 64 <1017600000>; 1391 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1392 }; 1393 1394 opp-1075200000 { 1395 opp-hz = /bits/ 64 <1075200000>; 1396 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1397 }; 1398 1399 opp-1132800000 { 1400 opp-hz = /bits/ 64 <1132800000>; 1401 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1402 }; 1403 1404 opp-1190400000 { 1405 opp-hz = /bits/ 64 <1190400000>; 1406 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 1407 }; 1408 1409 opp-1248000000 { 1410 opp-hz = /bits/ 64 <1248000000>; 1411 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1412 }; 1413 1414 opp-1305600000 { 1415 opp-hz = /bits/ 64 <1305600000>; 1416 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1417 }; 1418 1419 opp-1363200000 { 1420 opp-hz = /bits/ 64 <1363200000>; 1421 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1422 }; 1423 1424 opp-1420800000 { 1425 opp-hz = /bits/ 64 <1420800000>; 1426 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1427 }; 1428 1429 opp-1478400000 { 1430 opp-hz = /bits/ 64 <1478400000>; 1431 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1432 }; 1433 1434 opp-1555200000 { 1435 opp-hz = /bits/ 64 <1555200000>; 1436 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1437 }; 1438 1439 opp-1593600000 { 1440 opp-hz = /bits/ 64 <1593600000>; 1441 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1442 }; 1443 1444 opp-1670400000 { 1445 opp-hz = /bits/ 64 <1670400000>; 1446 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1447 }; 1448 1449 opp-1708800000 { 1450 opp-hz = /bits/ 64 <1708800000>; 1451 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1452 }; 1453 1454 opp-1804800000 { 1455 opp-hz = /bits/ 64 <1804800000>; 1456 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1457 }; 1458 1459 opp-1824000000 { 1460 opp-hz = /bits/ 64 <1824000000>; 1461 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1462 }; 1463 1464 opp-1939200000 { 1465 opp-hz = /bits/ 64 <1939200000>; 1466 opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>; 1467 }; 1468 1469 opp-2035200000 { 1470 opp-hz = /bits/ 64 <2035200000>; 1471 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1472 }; 1473 1474 opp-2073600000 { 1475 opp-hz = /bits/ 64 <2073600000>; 1476 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1477 }; 1478 1479 opp-2112000000 { 1480 opp-hz = /bits/ 64 <2112000000>; 1481 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1482 }; 1483 1484 opp-2169600000 { 1485 opp-hz = /bits/ 64 <2169600000>; 1486 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1487 }; 1488 1489 opp-2208000000 { 1490 opp-hz = /bits/ 64 <2208000000>; 1491 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1492 }; 1493 1494 opp-2246400000 { 1495 opp-hz = /bits/ 64 <2246400000>; 1496 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1497 }; 1498 1499 opp-2304000000 { 1500 opp-hz = /bits/ 64 <2304000000>; 1501 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1502 }; 1503 1504 opp-2342400000 { 1505 opp-hz = /bits/ 64 <2342400000>; 1506 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1507 }; 1508 1509 opp-2380800000 { 1510 opp-hz = /bits/ 64 <2380800000>; 1511 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1512 }; 1513 1514 opp-2438400000 { 1515 opp-hz = /bits/ 64 <2438400000>; 1516 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1517 }; 1518 1519 opp-2457600000 { 1520 opp-hz = /bits/ 64 <2457600000>; 1521 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1522 }; 1523 1524 opp-2496000000 { 1525 opp-hz = /bits/ 64 <2496000000>; 1526 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1527 }; 1528 1529 opp-2553600000 { 1530 opp-hz = /bits/ 64 <2553600000>; 1531 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1532 }; 1533 1534 opp-2630400000 { 1535 opp-hz = /bits/ 64 <2630400000>; 1536 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1537 }; 1538 1539 opp-2688000000 { 1540 opp-hz = /bits/ 64 <2688000000>; 1541 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1542 }; 1543 1544 opp-2745600000 { 1545 opp-hz = /bits/ 64 <2745600000>; 1546 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1547 }; 1548 1549 opp-2803200000 { 1550 opp-hz = /bits/ 64 <2803200000>; 1551 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1552 }; 1553 1554 opp-2880000000 { 1555 opp-hz = /bits/ 64 <2880000000>; 1556 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1557 }; 1558 1559 opp-2937600000 { 1560 opp-hz = /bits/ 64 <2937600000>; 1561 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1562 }; 1563 1564 opp-2995200000 { 1565 opp-hz = /bits/ 64 <2995200000>; 1566 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1567 }; 1568 1569 opp-3052800000 { 1570 opp-hz = /bits/ 64 <3052800000>; 1571 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1572 }; 1573 1574 opp-3187200000 { 1575 opp-hz = /bits/ 64 <3187200000>; 1576 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1577 }; 1578 1579 opp-3302400000 { 1580 opp-hz = /bits/ 64 <3302400000>; 1581 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1582 }; 1583 }; 1584 1585 pmu-a520 { 1586 compatible = "arm,cortex-a520-pmu"; 1587 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 1588 }; 1589 1590 pmu-a720 { 1591 compatible = "arm,cortex-a720-pmu"; 1592 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 1593 }; 1594 1595 pmu-x4 { 1596 compatible = "arm,cortex-x4-pmu"; 1597 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; 1598 }; 1599 1600 psci { 1601 compatible = "arm,psci-1.0"; 1602 method = "smc"; 1603 1604 cpu_pd0: power-domain-cpu0 { 1605 #power-domain-cells = <0>; 1606 power-domains = <&cluster_pd>; 1607 domain-idle-states = <&silver_cpu_sleep_0>; 1608 }; 1609 1610 cpu_pd1: power-domain-cpu1 { 1611 #power-domain-cells = <0>; 1612 power-domains = <&cluster_pd>; 1613 domain-idle-states = <&silver_cpu_sleep_0>; 1614 }; 1615 1616 cpu_pd2: power-domain-cpu2 { 1617 #power-domain-cells = <0>; 1618 power-domains = <&cluster_pd>; 1619 domain-idle-states = <&gold_cpu_sleep_0>; 1620 }; 1621 1622 cpu_pd3: power-domain-cpu3 { 1623 #power-domain-cells = <0>; 1624 power-domains = <&cluster_pd>; 1625 domain-idle-states = <&gold_cpu_sleep_0>; 1626 }; 1627 1628 cpu_pd4: power-domain-cpu4 { 1629 #power-domain-cells = <0>; 1630 power-domains = <&cluster_pd>; 1631 domain-idle-states = <&gold_cpu_sleep_0>; 1632 }; 1633 1634 cpu_pd5: power-domain-cpu5 { 1635 #power-domain-cells = <0>; 1636 power-domains = <&cluster_pd>; 1637 domain-idle-states = <&gold_cpu_sleep_0>; 1638 }; 1639 1640 cpu_pd6: power-domain-cpu6 { 1641 #power-domain-cells = <0>; 1642 power-domains = <&cluster_pd>; 1643 domain-idle-states = <&gold_cpu_sleep_0>; 1644 }; 1645 1646 cpu_pd7: power-domain-cpu7 { 1647 #power-domain-cells = <0>; 1648 power-domains = <&cluster_pd>; 1649 domain-idle-states = <&gold_plus_cpu_sleep_0>; 1650 }; 1651 1652 cluster_pd: power-domain-cluster { 1653 #power-domain-cells = <0>; 1654 domain-idle-states = <&cluster_sleep_0>, 1655 <&cluster_sleep_1>; 1656 }; 1657 }; 1658 1659 reserved_memory: reserved-memory { 1660 #address-cells = <2>; 1661 #size-cells = <2>; 1662 ranges; 1663 1664 hyp_mem: hyp@80000000 { 1665 reg = <0 0x80000000 0 0xe00000>; 1666 no-map; 1667 }; 1668 1669 cpusys_vm_mem: cpusys-vm@80e00000 { 1670 reg = <0 0x80e00000 0 0x400000>; 1671 no-map; 1672 }; 1673 1674 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 1675 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 1676 reg = <0 0x81a00000 0 0x260000>; 1677 no-map; 1678 }; 1679 1680 aop_cmd_db_mem: aop-cmd-db@81c60000 { 1681 compatible = "qcom,cmd-db"; 1682 reg = <0 0x81c60000 0 0x20000>; 1683 no-map; 1684 }; 1685 1686 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ 1687 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 1688 reg = <0 0x81c80000 0 0x75000>; 1689 no-map; 1690 }; 1691 1692 /* Secdata region can be reused by apps */ 1693 1694 smem: smem@81d00000 { 1695 compatible = "qcom,smem"; 1696 reg = <0 0x81d00000 0 0x200000>; 1697 hwlocks = <&tcsr_mutex 3>; 1698 no-map; 1699 }; 1700 1701 adsp_mhi_mem: adsp-mhi@81f00000 { 1702 reg = <0 0x81f00000 0 0x20000>; 1703 no-map; 1704 }; 1705 1706 pvmfw_mem: pvmfw@824a0000 { 1707 reg = <0 0x824a0000 0 0x100000>; 1708 no-map; 1709 }; 1710 1711 global_sync_mem: global-sync@82600000 { 1712 reg = <0 0x82600000 0 0x100000>; 1713 no-map; 1714 }; 1715 1716 tz_stat_mem: tz-stat@82700000 { 1717 reg = <0 0x82700000 0 0x100000>; 1718 no-map; 1719 }; 1720 1721 qdss_mem: qdss@82800000 { 1722 reg = <0 0x82800000 0 0x2000000>; 1723 no-map; 1724 }; 1725 1726 qlink_logging_mem: qlink-logging@84800000 { 1727 reg = <0 0x84800000 0 0x200000>; 1728 no-map; 1729 }; 1730 1731 mpss_dsm_mem: mpss-dsm@86b00000 { 1732 reg = <0 0x86b00000 0 0x4900000>; 1733 no-map; 1734 }; 1735 1736 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 1737 reg = <0 0x8b400000 0 0x800000>; 1738 no-map; 1739 }; 1740 1741 mpss_mem: mpss@8bc00000 { 1742 reg = <0 0x8bc00000 0 0xf400000>; 1743 no-map; 1744 }; 1745 1746 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 1747 reg = <0 0x9b000000 0 0x80000>; 1748 no-map; 1749 }; 1750 1751 ipa_fw_mem: ipa-fw@9b080000 { 1752 reg = <0 0x9b080000 0 0x10000>; 1753 no-map; 1754 }; 1755 1756 ipa_gsi_mem: ipa-gsi@9b090000 { 1757 reg = <0 0x9b090000 0 0xa000>; 1758 no-map; 1759 }; 1760 1761 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 1762 reg = <0 0x9b09a000 0 0x2000>; 1763 no-map; 1764 }; 1765 1766 spss_region_mem: spss@9b0a0000 { 1767 reg = <0 0x9b0a0000 0 0x1e0000>; 1768 no-map; 1769 }; 1770 1771 /* First part of the "SPU secure shared memory" region */ 1772 spu_tz_shared_mem: spu-tz-shared@9b280000 { 1773 reg = <0 0x9b280000 0 0x60000>; 1774 no-map; 1775 }; 1776 1777 /* Second part of the "SPU secure shared memory" region */ 1778 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 1779 reg = <0 0x9b2e0000 0 0x20000>; 1780 no-map; 1781 }; 1782 1783 camera_mem: camera@9b300000 { 1784 reg = <0 0x9b300000 0 0x800000>; 1785 no-map; 1786 }; 1787 1788 video_mem: video@9bb00000 { 1789 reg = <0 0x9bb00000 0 0x800000>; 1790 no-map; 1791 }; 1792 1793 cvp_mem: cvp@9c300000 { 1794 reg = <0 0x9c300000 0 0x700000>; 1795 no-map; 1796 }; 1797 1798 cdsp_mem: cdsp@9ca00000 { 1799 reg = <0 0x9ca00000 0 0x1400000>; 1800 no-map; 1801 }; 1802 1803 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 1804 reg = <0 0x9de00000 0 0x80000>; 1805 no-map; 1806 }; 1807 1808 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 1809 reg = <0 0x9de80000 0 0x80000>; 1810 no-map; 1811 }; 1812 1813 adspslpi_mem: adspslpi@9df00000 { 1814 reg = <0 0x9df00000 0 0x4080000>; 1815 no-map; 1816 }; 1817 1818 rmtfs_mem: rmtfs@d7c00000 { 1819 compatible = "qcom,rmtfs-mem"; 1820 reg = <0 0xd7c00000 0 0x400000>; 1821 no-map; 1822 1823 qcom,client-id = <1>; 1824 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 1825 }; 1826 1827 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 1828 tz_merged_mem: tz-merged@d8000000 { 1829 reg = <0 0xd8000000 0 0x800000>; 1830 no-map; 1831 }; 1832 1833 hwfence_shbuf: hwfence-shbuf@e6440000 { 1834 reg = <0 0xe6440000 0 0x2dd000>; 1835 no-map; 1836 }; 1837 1838 trust_ui_vm_mem: trust-ui-vm@f3800000 { 1839 reg = <0 0xf3800000 0 0x4400000>; 1840 no-map; 1841 }; 1842 1843 oem_vm_mem: oem-vm@f7c00000 { 1844 reg = <0 0xf7c00000 0 0x4c00000>; 1845 no-map; 1846 }; 1847 1848 llcc_lpi_mem: llcc-lpi@ff800000 { 1849 reg = <0 0xff800000 0 0x600000>; 1850 no-map; 1851 }; 1852 }; 1853 1854 smp2p-adsp { 1855 compatible = "qcom,smp2p"; 1856 1857 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1858 IPCC_MPROC_SIGNAL_SMP2P 1859 IRQ_TYPE_EDGE_RISING>; 1860 1861 mboxes = <&ipcc IPCC_CLIENT_LPASS 1862 IPCC_MPROC_SIGNAL_SMP2P>; 1863 1864 qcom,smem = <443>, <429>; 1865 qcom,local-pid = <0>; 1866 qcom,remote-pid = <2>; 1867 1868 smp2p_adsp_out: master-kernel { 1869 qcom,entry-name = "master-kernel"; 1870 #qcom,smem-state-cells = <1>; 1871 }; 1872 1873 smp2p_adsp_in: slave-kernel { 1874 qcom,entry-name = "slave-kernel"; 1875 interrupt-controller; 1876 #interrupt-cells = <2>; 1877 }; 1878 }; 1879 1880 smp2p-cdsp { 1881 compatible = "qcom,smp2p"; 1882 1883 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1884 IPCC_MPROC_SIGNAL_SMP2P 1885 IRQ_TYPE_EDGE_RISING>; 1886 1887 mboxes = <&ipcc IPCC_CLIENT_CDSP 1888 IPCC_MPROC_SIGNAL_SMP2P>; 1889 1890 qcom,smem = <94>, <432>; 1891 qcom,local-pid = <0>; 1892 qcom,remote-pid = <5>; 1893 1894 smp2p_cdsp_out: master-kernel { 1895 qcom,entry-name = "master-kernel"; 1896 #qcom,smem-state-cells = <1>; 1897 }; 1898 1899 smp2p_cdsp_in: slave-kernel { 1900 qcom,entry-name = "slave-kernel"; 1901 interrupt-controller; 1902 #interrupt-cells = <2>; 1903 }; 1904 }; 1905 1906 smp2p-modem { 1907 compatible = "qcom,smp2p"; 1908 1909 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1910 IPCC_MPROC_SIGNAL_SMP2P 1911 IRQ_TYPE_EDGE_RISING>; 1912 1913 mboxes = <&ipcc IPCC_CLIENT_MPSS 1914 IPCC_MPROC_SIGNAL_SMP2P>; 1915 1916 qcom,smem = <435>, <428>; 1917 qcom,local-pid = <0>; 1918 qcom,remote-pid = <1>; 1919 1920 smp2p_modem_out: master-kernel { 1921 qcom,entry-name = "master-kernel"; 1922 #qcom,smem-state-cells = <1>; 1923 }; 1924 1925 smp2p_modem_in: slave-kernel { 1926 qcom,entry-name = "slave-kernel"; 1927 interrupt-controller; 1928 #interrupt-cells = <2>; 1929 }; 1930 1931 ipa_smp2p_out: ipa-ap-to-modem { 1932 qcom,entry-name = "ipa"; 1933 #qcom,smem-state-cells = <1>; 1934 }; 1935 1936 ipa_smp2p_in: ipa-modem-to-ap { 1937 qcom,entry-name = "ipa"; 1938 interrupt-controller; 1939 #interrupt-cells = <2>; 1940 }; 1941 }; 1942 1943 soc: soc@0 { 1944 compatible = "simple-bus"; 1945 1946 #address-cells = <2>; 1947 #size-cells = <2>; 1948 dma-ranges = <0 0 0 0 0x10 0>; 1949 ranges = <0 0 0 0 0x10 0>; 1950 1951 gcc: clock-controller@100000 { 1952 compatible = "qcom,sm8650-gcc"; 1953 reg = <0 0x00100000 0 0x1f4200>; 1954 1955 clocks = <&bi_tcxo_div2>, 1956 <&bi_tcxo_ao_div2>, 1957 <&sleep_clk>, 1958 <&pcie0_phy>, 1959 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 1960 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 1961 <&ufs_mem_phy 0>, 1962 <&ufs_mem_phy 1>, 1963 <&ufs_mem_phy 2>, 1964 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 1965 1966 #clock-cells = <1>; 1967 #reset-cells = <1>; 1968 #power-domain-cells = <1>; 1969 }; 1970 1971 ipcc: mailbox@406000 { 1972 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 1973 reg = <0 0x00406000 0 0x1000>; 1974 1975 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 1976 interrupt-controller; 1977 #interrupt-cells = <3>; 1978 1979 #mbox-cells = <2>; 1980 }; 1981 1982 gpi_dma2: dma-controller@800000 { 1983 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1984 reg = <0 0x00800000 0 0x60000>; 1985 1986 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 1987 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 1988 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 1989 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 1990 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 1991 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 1992 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 1993 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 1994 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 1995 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 1996 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 1997 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 1998 1999 dma-channels = <12>; 2000 dma-channel-mask = <0x3f>; 2001 #dma-cells = <3>; 2002 2003 iommus = <&apps_smmu 0x436 0>; 2004 2005 dma-coherent; 2006 2007 status = "disabled"; 2008 }; 2009 2010 qupv3_id_1: geniqup@8c0000 { 2011 compatible = "qcom,geni-se-qup"; 2012 reg = <0 0x008c0000 0 0x2000>; 2013 2014 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 2015 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 2016 clock-names = "m-ahb", 2017 "s-ahb"; 2018 2019 iommus = <&apps_smmu 0x423 0>; 2020 2021 dma-coherent; 2022 2023 #address-cells = <2>; 2024 #size-cells = <2>; 2025 ranges; 2026 2027 status = "disabled"; 2028 2029 i2c8: i2c@880000 { 2030 compatible = "qcom,geni-i2c"; 2031 reg = <0 0x00880000 0 0x4000>; 2032 2033 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 2034 2035 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 2036 clock-names = "se"; 2037 2038 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2039 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2041 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2042 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2044 interconnect-names = "qup-core", 2045 "qup-config", 2046 "qup-memory"; 2047 2048 power-domains = <&rpmhpd RPMHPD_CX>; 2049 2050 operating-points-v2 = <&qup_opp_table_120mhz>; 2051 2052 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 2053 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 2054 dma-names = "tx", 2055 "rx"; 2056 2057 pinctrl-0 = <&qup_i2c8_data_clk>; 2058 pinctrl-names = "default"; 2059 2060 #address-cells = <1>; 2061 #size-cells = <0>; 2062 2063 status = "disabled"; 2064 }; 2065 2066 spi8: spi@880000 { 2067 compatible = "qcom,geni-spi"; 2068 reg = <0 0x00880000 0 0x4000>; 2069 2070 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 2071 2072 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 2073 clock-names = "se"; 2074 2075 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2076 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2077 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2078 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2079 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2080 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2081 interconnect-names = "qup-core", 2082 "qup-config", 2083 "qup-memory"; 2084 2085 power-domains = <&rpmhpd RPMHPD_CX>; 2086 2087 operating-points-v2 = <&qup_opp_table_100mhz>; 2088 2089 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 2090 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 2091 dma-names = "tx", 2092 "rx"; 2093 2094 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 2095 pinctrl-names = "default"; 2096 2097 #address-cells = <1>; 2098 #size-cells = <0>; 2099 2100 status = "disabled"; 2101 }; 2102 2103 i2c9: i2c@884000 { 2104 compatible = "qcom,geni-i2c"; 2105 reg = <0 0x00884000 0 0x4000>; 2106 2107 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 2108 2109 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 2110 clock-names = "se"; 2111 2112 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2113 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2114 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2115 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2116 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2118 interconnect-names = "qup-core", 2119 "qup-config", 2120 "qup-memory"; 2121 2122 power-domains = <&rpmhpd RPMHPD_CX>; 2123 2124 operating-points-v2 = <&qup_opp_table_120mhz>; 2125 2126 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 2127 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 2128 dma-names = "tx", 2129 "rx"; 2130 2131 pinctrl-0 = <&qup_i2c9_data_clk>; 2132 pinctrl-names = "default"; 2133 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 2137 status = "disabled"; 2138 }; 2139 2140 spi9: spi@884000 { 2141 compatible = "qcom,geni-spi"; 2142 reg = <0 0x00884000 0 0x4000>; 2143 2144 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 2145 2146 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 2147 clock-names = "se"; 2148 2149 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2150 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2151 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2152 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2153 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2154 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2155 interconnect-names = "qup-core", 2156 "qup-config", 2157 "qup-memory"; 2158 2159 power-domains = <&rpmhpd RPMHPD_CX>; 2160 2161 operating-points-v2 = <&qup_opp_table_120mhz>; 2162 2163 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 2164 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 2165 dma-names = "tx", 2166 "rx"; 2167 2168 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 2169 pinctrl-names = "default"; 2170 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 2174 status = "disabled"; 2175 }; 2176 2177 i2c10: i2c@888000 { 2178 compatible = "qcom,geni-i2c"; 2179 reg = <0 0x00888000 0 0x4000>; 2180 2181 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 2182 2183 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 2184 clock-names = "se"; 2185 2186 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2187 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2189 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2190 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2192 interconnect-names = "qup-core", 2193 "qup-config", 2194 "qup-memory"; 2195 2196 power-domains = <&rpmhpd RPMHPD_CX>; 2197 2198 operating-points-v2 = <&qup_opp_table_120mhz>; 2199 2200 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 2201 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 2202 dma-names = "tx", 2203 "rx"; 2204 2205 pinctrl-0 = <&qup_i2c10_data_clk>; 2206 pinctrl-names = "default"; 2207 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 2211 status = "disabled"; 2212 }; 2213 2214 spi10: spi@888000 { 2215 compatible = "qcom,geni-spi"; 2216 reg = <0 0x00888000 0 0x4000>; 2217 2218 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 2219 2220 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 2221 clock-names = "se"; 2222 2223 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2224 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2225 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2226 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2227 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2228 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2229 interconnect-names = "qup-core", 2230 "qup-config", 2231 "qup-memory"; 2232 2233 power-domains = <&rpmhpd RPMHPD_CX>; 2234 2235 operating-points-v2 = <&qup_opp_table_120mhz>; 2236 2237 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 2238 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 2239 dma-names = "tx", 2240 "rx"; 2241 2242 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 2243 pinctrl-names = "default"; 2244 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 2248 status = "disabled"; 2249 }; 2250 2251 i2c11: i2c@88c000 { 2252 compatible = "qcom,geni-i2c"; 2253 reg = <0 0x0088c000 0 0x4000>; 2254 2255 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2256 2257 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 2258 clock-names = "se"; 2259 2260 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2261 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2262 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2263 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2264 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2266 interconnect-names = "qup-core", 2267 "qup-config", 2268 "qup-memory"; 2269 2270 power-domains = <&rpmhpd RPMHPD_CX>; 2271 2272 operating-points-v2 = <&qup_opp_table_120mhz>; 2273 2274 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 2275 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 2276 dma-names = "tx", 2277 "rx"; 2278 2279 pinctrl-0 = <&qup_i2c11_data_clk>; 2280 pinctrl-names = "default"; 2281 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 2285 status = "disabled"; 2286 }; 2287 2288 spi11: spi@88c000 { 2289 compatible = "qcom,geni-spi"; 2290 reg = <0 0x0088c000 0 0x4000>; 2291 2292 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2293 2294 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 2295 clock-names = "se"; 2296 2297 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2298 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2299 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2300 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2301 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2302 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2303 interconnect-names = "qup-core", 2304 "qup-config", 2305 "qup-memory"; 2306 2307 power-domains = <&rpmhpd RPMHPD_CX>; 2308 2309 operating-points-v2 = <&qup_opp_table_120mhz>; 2310 2311 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 2312 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 2313 dma-names = "tx", 2314 "rx"; 2315 2316 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 2317 pinctrl-names = "default"; 2318 2319 #address-cells = <1>; 2320 #size-cells = <0>; 2321 2322 status = "disabled"; 2323 }; 2324 2325 i2c12: i2c@890000 { 2326 compatible = "qcom,geni-i2c"; 2327 reg = <0 0x00890000 0 0x4000>; 2328 2329 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2330 2331 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 2332 clock-names = "se"; 2333 2334 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2335 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2336 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2337 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2338 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2340 interconnect-names = "qup-core", 2341 "qup-config", 2342 "qup-memory"; 2343 2344 power-domains = <&rpmhpd RPMHPD_CX>; 2345 2346 operating-points-v2 = <&qup_opp_table_100mhz>; 2347 2348 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 2349 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 2350 dma-names = "tx", 2351 "rx"; 2352 2353 pinctrl-0 = <&qup_i2c12_data_clk>; 2354 pinctrl-names = "default"; 2355 2356 #address-cells = <1>; 2357 #size-cells = <0>; 2358 2359 status = "disabled"; 2360 }; 2361 2362 spi12: spi@890000 { 2363 compatible = "qcom,geni-spi"; 2364 reg = <0 0x00890000 0 0x4000>; 2365 2366 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2367 2368 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 2369 clock-names = "se"; 2370 2371 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2372 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2373 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2374 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2375 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2376 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2377 interconnect-names = "qup-core", 2378 "qup-config", 2379 "qup-memory"; 2380 2381 power-domains = <&rpmhpd RPMHPD_CX>; 2382 2383 operating-points-v2 = <&qup_opp_table_100mhz>; 2384 2385 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 2386 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 2387 dma-names = "tx", 2388 "rx"; 2389 2390 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 2391 pinctrl-names = "default"; 2392 2393 #address-cells = <1>; 2394 #size-cells = <0>; 2395 2396 status = "disabled"; 2397 }; 2398 2399 i2c13: i2c@894000 { 2400 compatible = "qcom,geni-i2c"; 2401 reg = <0 0x00894000 0 0x4000>; 2402 2403 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 2404 2405 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 2406 clock-names = "se"; 2407 2408 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2409 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2410 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2411 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2412 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2413 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2414 interconnect-names = "qup-core", 2415 "qup-config", 2416 "qup-memory"; 2417 2418 power-domains = <&rpmhpd RPMHPD_CX>; 2419 2420 operating-points-v2 = <&qup_opp_table_100mhz>; 2421 2422 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 2423 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 2424 dma-names = "tx", 2425 "rx"; 2426 2427 pinctrl-0 = <&qup_i2c13_data_clk>; 2428 pinctrl-names = "default"; 2429 2430 #address-cells = <1>; 2431 #size-cells = <0>; 2432 2433 status = "disabled"; 2434 }; 2435 2436 spi13: spi@894000 { 2437 compatible = "qcom,geni-spi"; 2438 reg = <0 0x00894000 0 0x4000>; 2439 2440 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 2441 2442 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 2443 clock-names = "se"; 2444 2445 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2446 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2448 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2449 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2450 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2451 interconnect-names = "qup-core", 2452 "qup-config", 2453 "qup-memory"; 2454 2455 power-domains = <&rpmhpd RPMHPD_CX>; 2456 2457 operating-points-v2 = <&qup_opp_table_100mhz>; 2458 2459 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 2460 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 2461 dma-names = "tx", 2462 "rx"; 2463 2464 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 2465 pinctrl-names = "default"; 2466 2467 #address-cells = <1>; 2468 #size-cells = <0>; 2469 2470 status = "disabled"; 2471 }; 2472 2473 uart14: serial@898000 { 2474 compatible = "qcom,geni-uart"; 2475 reg = <0 0x00898000 0 0x4000>; 2476 2477 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; 2478 2479 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 2480 clock-names = "se"; 2481 2482 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2483 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2484 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2485 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2486 interconnect-names = "qup-core", 2487 "qup-config"; 2488 2489 power-domains = <&rpmhpd RPMHPD_CX>; 2490 2491 operating-points-v2 = <&qup_opp_table_128mhz>; 2492 2493 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 2494 pinctrl-names = "default"; 2495 2496 status = "disabled"; 2497 }; 2498 2499 uart15: serial@89c000 { 2500 compatible = "qcom,geni-debug-uart"; 2501 reg = <0 0x0089c000 0 0x4000>; 2502 2503 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 2504 2505 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 2506 clock-names = "se"; 2507 2508 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2509 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2510 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2511 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2512 interconnect-names = "qup-core", 2513 "qup-config"; 2514 2515 power-domains = <&rpmhpd RPMHPD_CX>; 2516 2517 operating-points-v2 = <&qup_opp_table_100mhz>; 2518 2519 pinctrl-0 = <&qup_uart15_default>; 2520 pinctrl-names = "default"; 2521 2522 status = "disabled"; 2523 }; 2524 }; 2525 2526 i2c_master_hub_0: geniqup@9c0000 { 2527 compatible = "qcom,geni-se-i2c-master-hub"; 2528 reg = <0 0x009c0000 0 0x2000>; 2529 2530 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 2531 clock-names = "s-ahb"; 2532 2533 #address-cells = <2>; 2534 #size-cells = <2>; 2535 ranges; 2536 2537 status = "disabled"; 2538 2539 i2c_hub_0: i2c@980000 { 2540 compatible = "qcom,geni-i2c-master-hub"; 2541 reg = <0 0x00980000 0 0x4000>; 2542 2543 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; 2544 2545 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 2546 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2547 clock-names = "se", 2548 "core"; 2549 2550 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2551 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2553 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2554 interconnect-names = "qup-core", 2555 "qup-config"; 2556 2557 power-domains = <&rpmhpd RPMHPD_CX>; 2558 2559 required-opps = <&rpmhpd_opp_low_svs>; 2560 2561 pinctrl-0 = <&hub_i2c0_data_clk>; 2562 pinctrl-names = "default"; 2563 2564 #address-cells = <1>; 2565 #size-cells = <0>; 2566 2567 status = "disabled"; 2568 }; 2569 2570 i2c_hub_1: i2c@984000 { 2571 compatible = "qcom,geni-i2c-master-hub"; 2572 reg = <0 0x00984000 0 0x4000>; 2573 2574 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; 2575 2576 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 2577 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2578 clock-names = "se", 2579 "core"; 2580 2581 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2582 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2584 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2585 interconnect-names = "qup-core", 2586 "qup-config"; 2587 2588 power-domains = <&rpmhpd RPMHPD_CX>; 2589 2590 required-opps = <&rpmhpd_opp_low_svs>; 2591 2592 pinctrl-0 = <&hub_i2c1_data_clk>; 2593 pinctrl-names = "default"; 2594 2595 #address-cells = <1>; 2596 #size-cells = <0>; 2597 2598 status = "disabled"; 2599 }; 2600 2601 i2c_hub_2: i2c@988000 { 2602 compatible = "qcom,geni-i2c-master-hub"; 2603 reg = <0 0x00988000 0 0x4000>; 2604 2605 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; 2606 2607 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 2608 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2609 clock-names = "se", 2610 "core"; 2611 2612 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2613 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2614 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2615 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2616 interconnect-names = "qup-core", 2617 "qup-config"; 2618 2619 power-domains = <&rpmhpd RPMHPD_CX>; 2620 2621 required-opps = <&rpmhpd_opp_low_svs>; 2622 2623 pinctrl-0 = <&hub_i2c2_data_clk>; 2624 pinctrl-names = "default"; 2625 2626 #address-cells = <1>; 2627 #size-cells = <0>; 2628 2629 status = "disabled"; 2630 }; 2631 2632 i2c_hub_3: i2c@98c000 { 2633 compatible = "qcom,geni-i2c-master-hub"; 2634 reg = <0 0x0098c000 0 0x4000>; 2635 2636 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; 2637 2638 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 2639 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2640 clock-names = "se", 2641 "core"; 2642 2643 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2644 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2645 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2646 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2647 interconnect-names = "qup-core", 2648 "qup-config"; 2649 2650 power-domains = <&rpmhpd RPMHPD_CX>; 2651 2652 required-opps = <&rpmhpd_opp_low_svs>; 2653 2654 pinctrl-0 = <&hub_i2c3_data_clk>; 2655 pinctrl-names = "default"; 2656 2657 #address-cells = <1>; 2658 #size-cells = <0>; 2659 2660 status = "disabled"; 2661 }; 2662 2663 i2c_hub_4: i2c@990000 { 2664 compatible = "qcom,geni-i2c-master-hub"; 2665 reg = <0 0x00990000 0 0x4000>; 2666 2667 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; 2668 2669 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 2670 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2671 clock-names = "se", 2672 "core"; 2673 2674 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2675 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2676 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2677 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2678 interconnect-names = "qup-core", 2679 "qup-config"; 2680 2681 power-domains = <&rpmhpd RPMHPD_CX>; 2682 2683 required-opps = <&rpmhpd_opp_low_svs>; 2684 2685 pinctrl-0 = <&hub_i2c4_data_clk>; 2686 pinctrl-names = "default"; 2687 2688 #address-cells = <1>; 2689 #size-cells = <0>; 2690 2691 status = "disabled"; 2692 }; 2693 2694 i2c_hub_5: i2c@994000 { 2695 compatible = "qcom,geni-i2c-master-hub"; 2696 reg = <0 0x00994000 0 0x4000>; 2697 2698 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; 2699 2700 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 2701 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2702 clock-names = "se", 2703 "core"; 2704 2705 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2706 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2707 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2708 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2709 interconnect-names = "qup-core", 2710 "qup-config"; 2711 2712 power-domains = <&rpmhpd RPMHPD_CX>; 2713 2714 required-opps = <&rpmhpd_opp_low_svs>; 2715 2716 pinctrl-0 = <&hub_i2c5_data_clk>; 2717 pinctrl-names = "default"; 2718 2719 #address-cells = <1>; 2720 #size-cells = <0>; 2721 2722 status = "disabled"; 2723 }; 2724 2725 i2c_hub_6: i2c@998000 { 2726 compatible = "qcom,geni-i2c-master-hub"; 2727 reg = <0 0x00998000 0 0x4000>; 2728 2729 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; 2730 2731 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 2732 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2733 clock-names = "se", 2734 "core"; 2735 2736 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2737 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2738 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2739 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2740 interconnect-names = "qup-core", 2741 "qup-config"; 2742 2743 power-domains = <&rpmhpd RPMHPD_CX>; 2744 2745 required-opps = <&rpmhpd_opp_low_svs>; 2746 2747 pinctrl-0 = <&hub_i2c6_data_clk>; 2748 pinctrl-names = "default"; 2749 2750 #address-cells = <1>; 2751 #size-cells = <0>; 2752 2753 status = "disabled"; 2754 }; 2755 2756 i2c_hub_7: i2c@99c000 { 2757 compatible = "qcom,geni-i2c-master-hub"; 2758 reg = <0 0x0099c000 0 0x4000>; 2759 2760 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 2761 2762 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 2763 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2764 clock-names = "se", 2765 "core"; 2766 2767 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2768 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2769 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2770 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2771 interconnect-names = "qup-core", 2772 "qup-config"; 2773 2774 power-domains = <&rpmhpd RPMHPD_CX>; 2775 2776 required-opps = <&rpmhpd_opp_low_svs>; 2777 2778 pinctrl-0 = <&hub_i2c7_data_clk>; 2779 pinctrl-names = "default"; 2780 2781 #address-cells = <1>; 2782 #size-cells = <0>; 2783 2784 status = "disabled"; 2785 }; 2786 2787 i2c_hub_8: i2c@9a0000 { 2788 compatible = "qcom,geni-i2c-master-hub"; 2789 reg = <0 0x009a0000 0 0x4000>; 2790 2791 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; 2792 2793 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 2794 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2795 clock-names = "se", 2796 "core"; 2797 2798 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2799 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2800 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2801 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2802 interconnect-names = "qup-core", 2803 "qup-config"; 2804 2805 power-domains = <&rpmhpd RPMHPD_CX>; 2806 2807 required-opps = <&rpmhpd_opp_low_svs>; 2808 2809 pinctrl-0 = <&hub_i2c8_data_clk>; 2810 pinctrl-names = "default"; 2811 2812 #address-cells = <1>; 2813 #size-cells = <0>; 2814 2815 status = "disabled"; 2816 }; 2817 2818 i2c_hub_9: i2c@9a4000 { 2819 compatible = "qcom,geni-i2c-master-hub"; 2820 reg = <0 0x009a4000 0 0x4000>; 2821 2822 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; 2823 2824 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 2825 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2826 clock-names = "se", 2827 "core"; 2828 2829 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2830 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2831 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2832 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2833 interconnect-names = "qup-core", 2834 "qup-config"; 2835 2836 power-domains = <&rpmhpd RPMHPD_CX>; 2837 2838 required-opps = <&rpmhpd_opp_low_svs>; 2839 2840 pinctrl-0 = <&hub_i2c9_data_clk>; 2841 pinctrl-names = "default"; 2842 2843 #address-cells = <1>; 2844 #size-cells = <0>; 2845 2846 status = "disabled"; 2847 }; 2848 }; 2849 2850 gpi_dma1: dma-controller@a00000 { 2851 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 2852 reg = <0 0x00a00000 0 0x60000>; 2853 2854 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 2855 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 2856 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 2857 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 2858 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 2859 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 2860 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 2861 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, 2862 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, 2863 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, 2864 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, 2865 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 2866 2867 dma-channels = <12>; 2868 dma-channel-mask = <0xc>; 2869 #dma-cells = <3>; 2870 2871 iommus = <&apps_smmu 0xb6 0>; 2872 dma-coherent; 2873 2874 status = "disabled"; 2875 }; 2876 2877 qupv3_id_0: geniqup@ac0000 { 2878 compatible = "qcom,geni-se-qup"; 2879 reg = <0 0x00ac0000 0 0x2000>; 2880 2881 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2882 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2883 clock-names = "m-ahb", 2884 "s-ahb"; 2885 2886 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2887 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 2888 interconnect-names = "qup-core"; 2889 2890 iommus = <&apps_smmu 0xa3 0>; 2891 2892 dma-coherent; 2893 2894 #address-cells = <2>; 2895 #size-cells = <2>; 2896 ranges; 2897 2898 status = "disabled"; 2899 2900 i2c0: i2c@a80000 { 2901 compatible = "qcom,geni-i2c"; 2902 reg = <0 0x00a80000 0 0x4000>; 2903 2904 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2905 2906 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2907 clock-names = "se"; 2908 2909 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2910 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2911 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2912 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2913 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2914 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2915 interconnect-names = "qup-core", 2916 "qup-config", 2917 "qup-memory"; 2918 2919 power-domains = <&rpmhpd RPMHPD_CX>; 2920 2921 operating-points-v2 = <&qup_opp_table_120mhz>; 2922 2923 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2924 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2925 dma-names = "tx", 2926 "rx"; 2927 2928 pinctrl-0 = <&qup_i2c0_data_clk>; 2929 pinctrl-names = "default"; 2930 2931 #address-cells = <1>; 2932 #size-cells = <0>; 2933 2934 status = "disabled"; 2935 }; 2936 2937 spi0: spi@a80000 { 2938 compatible = "qcom,geni-spi"; 2939 reg = <0 0x00a80000 0 0x4000>; 2940 2941 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2942 2943 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2944 clock-names = "se"; 2945 2946 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2947 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2948 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2949 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2950 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2951 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2952 interconnect-names = "qup-core", 2953 "qup-config", 2954 "qup-memory"; 2955 2956 power-domains = <&rpmhpd RPMHPD_CX>; 2957 2958 operating-points-v2 = <&qup_opp_table_120mhz>; 2959 2960 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2961 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2962 dma-names = "tx", 2963 "rx"; 2964 2965 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2966 pinctrl-names = "default"; 2967 2968 #address-cells = <1>; 2969 #size-cells = <0>; 2970 2971 status = "disabled"; 2972 }; 2973 2974 i2c1: i2c@a84000 { 2975 compatible = "qcom,geni-i2c"; 2976 reg = <0 0x00a84000 0 0x4000>; 2977 2978 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 2979 2980 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2981 clock-names = "se"; 2982 2983 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2984 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2985 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2986 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2987 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2988 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2989 interconnect-names = "qup-core", 2990 "qup-config", 2991 "qup-memory"; 2992 2993 power-domains = <&rpmhpd RPMHPD_CX>; 2994 2995 operating-points-v2 = <&qup_opp_table_120mhz>; 2996 2997 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2998 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2999 dma-names = "tx", 3000 "rx"; 3001 3002 pinctrl-0 = <&qup_i2c1_data_clk>; 3003 pinctrl-names = "default"; 3004 3005 #address-cells = <1>; 3006 #size-cells = <0>; 3007 3008 status = "disabled"; 3009 }; 3010 3011 spi1: spi@a84000 { 3012 compatible = "qcom,geni-spi"; 3013 reg = <0 0x00a84000 0 0x4000>; 3014 3015 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 3016 3017 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 3018 clock-names = "se"; 3019 3020 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3021 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3023 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3024 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3026 interconnect-names = "qup-core", 3027 "qup-config", 3028 "qup-memory"; 3029 3030 power-domains = <&rpmhpd RPMHPD_CX>; 3031 3032 operating-points-v2 = <&qup_opp_table_120mhz>; 3033 3034 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 3035 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 3036 dma-names = "tx", 3037 "rx"; 3038 3039 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 3040 pinctrl-names = "default"; 3041 3042 #address-cells = <1>; 3043 #size-cells = <0>; 3044 3045 status = "disabled"; 3046 }; 3047 3048 i2c2: i2c@a88000 { 3049 compatible = "qcom,geni-i2c"; 3050 reg = <0 0x00a88000 0 0x4000>; 3051 3052 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 3053 3054 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 3055 clock-names = "se"; 3056 3057 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3058 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3059 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3060 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3061 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3062 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3063 interconnect-names = "qup-core", 3064 "qup-config", 3065 "qup-memory"; 3066 3067 power-domains = <&rpmhpd RPMHPD_CX>; 3068 3069 operating-points-v2 = <&qup_opp_table_240mhz>; 3070 3071 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 3072 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 3073 dma-names = "tx", 3074 "rx"; 3075 3076 pinctrl-0 = <&qup_i2c2_data_clk>; 3077 pinctrl-names = "default"; 3078 3079 #address-cells = <1>; 3080 #size-cells = <0>; 3081 3082 status = "disabled"; 3083 }; 3084 3085 spi2: spi@a88000 { 3086 compatible = "qcom,geni-spi"; 3087 reg = <0 0x00a88000 0 0x4000>; 3088 3089 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 3090 3091 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 3092 clock-names = "se"; 3093 3094 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3095 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3097 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3098 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3100 interconnect-names = "qup-core", 3101 "qup-config", 3102 "qup-memory"; 3103 3104 power-domains = <&rpmhpd RPMHPD_CX>; 3105 3106 operating-points-v2 = <&qup_opp_table_240mhz>; 3107 3108 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 3109 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 3110 dma-names = "tx", 3111 "rx"; 3112 3113 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 3114 pinctrl-names = "default"; 3115 3116 #address-cells = <1>; 3117 #size-cells = <0>; 3118 3119 status = "disabled"; 3120 }; 3121 3122 i2c3: i2c@a8c000 { 3123 compatible = "qcom,geni-i2c"; 3124 reg = <0 0x00a8c000 0 0x4000>; 3125 3126 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 3127 3128 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 3129 clock-names = "se"; 3130 3131 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3132 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3133 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3134 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3135 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3137 interconnect-names = "qup-core", 3138 "qup-config", 3139 "qup-memory"; 3140 3141 power-domains = <&rpmhpd RPMHPD_CX>; 3142 3143 operating-points-v2 = <&qup_opp_table_100mhz>; 3144 3145 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 3146 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 3147 dma-names = "tx", 3148 "rx"; 3149 3150 pinctrl-0 = <&qup_i2c3_data_clk>; 3151 pinctrl-names = "default"; 3152 3153 #address-cells = <1>; 3154 #size-cells = <0>; 3155 3156 status = "disabled"; 3157 }; 3158 3159 spi3: spi@a8c000 { 3160 compatible = "qcom,geni-spi"; 3161 reg = <0 0x00a8c000 0 0x4000>; 3162 3163 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 3164 3165 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 3166 clock-names = "se"; 3167 3168 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3169 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3170 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3171 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3172 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3174 interconnect-names = "qup-core", 3175 "qup-config", 3176 "qup-memory"; 3177 3178 power-domains = <&rpmhpd RPMHPD_CX>; 3179 3180 operating-points-v2 = <&qup_opp_table_100mhz>; 3181 3182 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 3183 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 3184 dma-names = "tx", 3185 "rx"; 3186 3187 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 3188 pinctrl-names = "default"; 3189 3190 #address-cells = <1>; 3191 #size-cells = <0>; 3192 3193 status = "disabled"; 3194 }; 3195 3196 i2c4: i2c@a90000 { 3197 compatible = "qcom,geni-i2c"; 3198 reg = <0 0x00a90000 0 0x4000>; 3199 3200 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 3201 3202 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 3203 clock-names = "se"; 3204 3205 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3206 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3207 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3208 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3209 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3210 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3211 interconnect-names = "qup-core", 3212 "qup-config", 3213 "qup-memory"; 3214 3215 power-domains = <&rpmhpd RPMHPD_CX>; 3216 3217 operating-points-v2 = <&qup_opp_table_120mhz>; 3218 3219 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 3220 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 3221 dma-names = "tx", 3222 "rx"; 3223 3224 pinctrl-0 = <&qup_i2c4_data_clk>; 3225 pinctrl-names = "default"; 3226 3227 #address-cells = <1>; 3228 #size-cells = <0>; 3229 3230 status = "disabled"; 3231 }; 3232 3233 spi4: spi@a90000 { 3234 compatible = "qcom,geni-spi"; 3235 reg = <0 0x00a90000 0 0x4000>; 3236 3237 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 3238 3239 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 3240 clock-names = "se"; 3241 3242 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3243 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3245 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3246 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3248 interconnect-names = "qup-core", 3249 "qup-config", 3250 "qup-memory"; 3251 3252 power-domains = <&rpmhpd RPMHPD_CX>; 3253 3254 operating-points-v2 = <&qup_opp_table_120mhz>; 3255 3256 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 3257 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 3258 dma-names = "tx", 3259 "rx"; 3260 3261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 3262 pinctrl-names = "default"; 3263 3264 #address-cells = <1>; 3265 #size-cells = <0>; 3266 3267 status = "disabled"; 3268 }; 3269 3270 i2c5: i2c@a94000 { 3271 compatible = "qcom,geni-i2c"; 3272 reg = <0 0x00a94000 0 0x4000>; 3273 3274 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 3275 3276 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 3277 clock-names = "se"; 3278 3279 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3280 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3281 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3282 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3283 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3284 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3285 interconnect-names = "qup-core", 3286 "qup-config", 3287 "qup-memory"; 3288 3289 power-domains = <&rpmhpd RPMHPD_CX>; 3290 3291 operating-points-v2 = <&qup_opp_table_100mhz>; 3292 3293 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 3294 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 3295 dma-names = "tx", 3296 "rx"; 3297 3298 pinctrl-0 = <&qup_i2c5_data_clk>; 3299 pinctrl-names = "default"; 3300 3301 #address-cells = <1>; 3302 #size-cells = <0>; 3303 3304 status = "disabled"; 3305 }; 3306 3307 spi5: spi@a94000 { 3308 compatible = "qcom,geni-spi"; 3309 reg = <0 0x00a94000 0 0x4000>; 3310 3311 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 3312 3313 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 3314 clock-names = "se"; 3315 3316 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3317 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3318 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3319 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3320 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3321 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3322 interconnect-names = "qup-core", 3323 "qup-config", 3324 "qup-memory"; 3325 3326 power-domains = <&rpmhpd RPMHPD_CX>; 3327 3328 operating-points-v2 = <&qup_opp_table_100mhz>; 3329 3330 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 3331 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 3332 dma-names = "tx", 3333 "rx"; 3334 3335 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 3336 pinctrl-names = "default"; 3337 3338 #address-cells = <1>; 3339 #size-cells = <0>; 3340 3341 status = "disabled"; 3342 }; 3343 3344 i2c6: i2c@a98000 { 3345 compatible = "qcom,geni-i2c"; 3346 reg = <0 0x00a98000 0 0x4000>; 3347 3348 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 3349 3350 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 3351 clock-names = "se"; 3352 3353 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3354 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3355 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3356 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3357 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3358 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3359 interconnect-names = "qup-core", 3360 "qup-config", 3361 "qup-memory"; 3362 3363 power-domains = <&rpmhpd RPMHPD_CX>; 3364 3365 operating-points-v2 = <&qup_opp_table_120mhz>; 3366 3367 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 3368 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 3369 dma-names = "tx", 3370 "rx"; 3371 3372 pinctrl-0 = <&qup_i2c6_data_clk>; 3373 pinctrl-names = "default"; 3374 3375 #address-cells = <1>; 3376 #size-cells = <0>; 3377 3378 status = "disabled"; 3379 }; 3380 3381 spi6: spi@a98000 { 3382 compatible = "qcom,geni-spi"; 3383 reg = <0 0x00a98000 0 0x4000>; 3384 3385 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 3386 3387 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 3388 clock-names = "se"; 3389 3390 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3391 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3392 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3393 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3394 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3395 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3396 interconnect-names = "qup-core", 3397 "qup-config", 3398 "qup-memory"; 3399 3400 power-domains = <&rpmhpd RPMHPD_CX>; 3401 3402 operating-points-v2 = <&qup_opp_table_120mhz>; 3403 3404 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 3405 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 3406 dma-names = "tx", 3407 "rx"; 3408 3409 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 3410 pinctrl-names = "default"; 3411 3412 #address-cells = <1>; 3413 #size-cells = <0>; 3414 3415 status = "disabled"; 3416 }; 3417 3418 i2c7: i2c@a9c000 { 3419 compatible = "qcom,geni-i2c"; 3420 reg = <0 0x00a9c000 0 0x4000>; 3421 3422 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 3423 3424 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 3425 clock-names = "se"; 3426 3427 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3428 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3430 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3431 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3433 interconnect-names = "qup-core", 3434 "qup-config", 3435 "qup-memory"; 3436 3437 power-domains = <&rpmhpd RPMHPD_CX>; 3438 3439 operating-points-v2 = <&qup_opp_table_100mhz>; 3440 3441 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 3442 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 3443 dma-names = "tx", 3444 "rx"; 3445 3446 pinctrl-0 = <&qup_i2c7_data_clk>; 3447 pinctrl-names = "default"; 3448 3449 #address-cells = <1>; 3450 #size-cells = <0>; 3451 3452 status = "disabled"; 3453 }; 3454 3455 spi7: spi@a9c000 { 3456 compatible = "qcom,geni-spi"; 3457 reg = <0 0x00a9c000 0 0x4000>; 3458 3459 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 3460 3461 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 3462 clock-names = "se"; 3463 3464 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3465 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3466 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3467 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3468 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3469 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3470 interconnect-names = "qup-core", 3471 "qup-config", 3472 "qup-memory"; 3473 3474 power-domains = <&rpmhpd RPMHPD_CX>; 3475 3476 operating-points-v2 = <&qup_opp_table_100mhz>; 3477 3478 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 3479 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 3480 dma-names = "tx", 3481 "rx"; 3482 3483 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 3484 pinctrl-names = "default"; 3485 3486 #address-cells = <1>; 3487 #size-cells = <0>; 3488 3489 status = "disabled"; 3490 }; 3491 }; 3492 3493 cnoc_main: interconnect@1500000 { 3494 compatible = "qcom,sm8650-cnoc-main"; 3495 reg = <0 0x01500000 0 0x14080>; 3496 3497 qcom,bcm-voters = <&apps_bcm_voter>; 3498 3499 #interconnect-cells = <2>; 3500 }; 3501 3502 config_noc: interconnect@1600000 { 3503 compatible = "qcom,sm8650-config-noc"; 3504 reg = <0 0x01600000 0 0x6200>; 3505 3506 qcom,bcm-voters = <&apps_bcm_voter>; 3507 3508 #interconnect-cells = <2>; 3509 }; 3510 3511 system_noc: interconnect@1680000 { 3512 compatible = "qcom,sm8650-system-noc"; 3513 reg = <0 0x01680000 0 0x1d080>; 3514 3515 qcom,bcm-voters = <&apps_bcm_voter>; 3516 3517 #interconnect-cells = <2>; 3518 }; 3519 3520 pcie_noc: interconnect@16c0000 { 3521 compatible = "qcom,sm8650-pcie-anoc"; 3522 reg = <0 0x016c0000 0 0x12200>; 3523 3524 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3525 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 3526 3527 qcom,bcm-voters = <&apps_bcm_voter>; 3528 3529 #interconnect-cells = <2>; 3530 }; 3531 3532 aggre1_noc: interconnect@16e0000 { 3533 compatible = "qcom,sm8650-aggre1-noc"; 3534 reg = <0 0x016e0000 0 0x16400>; 3535 3536 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3537 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 3538 3539 qcom,bcm-voters = <&apps_bcm_voter>; 3540 3541 #interconnect-cells = <2>; 3542 }; 3543 3544 aggre2_noc: interconnect@1700000 { 3545 compatible = "qcom,sm8650-aggre2-noc"; 3546 reg = <0 0x01700000 0 0x1e400>; 3547 3548 clocks = <&rpmhcc RPMH_IPA_CLK>; 3549 3550 qcom,bcm-voters = <&apps_bcm_voter>; 3551 3552 #interconnect-cells = <2>; 3553 }; 3554 3555 mmss_noc: interconnect@1780000 { 3556 compatible = "qcom,sm8650-mmss-noc"; 3557 reg = <0 0x01780000 0 0x5b800>; 3558 3559 qcom,bcm-voters = <&apps_bcm_voter>; 3560 3561 #interconnect-cells = <2>; 3562 }; 3563 3564 rng: rng@10c3000 { 3565 compatible = "qcom,sm8650-trng", "qcom,trng"; 3566 reg = <0 0x010c3000 0 0x1000>; 3567 }; 3568 3569 pcie0: pcie@1c00000 { 3570 device_type = "pci"; 3571 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 3572 reg = <0 0x01c00000 0 0x3000>, 3573 <0 0x60000000 0 0xf1d>, 3574 <0 0x60000f20 0 0xa8>, 3575 <0 0x60001000 0 0x1000>, 3576 <0 0x60100000 0 0x100000>; 3577 reg-names = "parf", "dbi", "elbi", "atu", "config"; 3578 3579 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 3580 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 3581 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 3582 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 3583 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 3584 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 3585 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 3586 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 3587 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 3588 interrupt-names = "msi0", 3589 "msi1", 3590 "msi2", 3591 "msi3", 3592 "msi4", 3593 "msi5", 3594 "msi6", 3595 "msi7", 3596 "global"; 3597 3598 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3599 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3600 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 3601 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 3602 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 3603 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3604 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3605 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3606 clock-names = "aux", 3607 "cfg", 3608 "bus_master", 3609 "bus_slave", 3610 "slave_q2a", 3611 "ddrss_sf_tbu", 3612 "noc_aggr", 3613 "cnoc_sf_axi"; 3614 3615 resets = <&gcc GCC_PCIE_0_BCR>; 3616 reset-names = "pci"; 3617 3618 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 3619 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3620 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3621 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 3622 interconnect-names = "pcie-mem", 3623 "cpu-pcie"; 3624 3625 power-domains = <&gcc PCIE_0_GDSC>; 3626 3627 operating-points-v2 = <&pcie0_opp_table>; 3628 3629 iommu-map = <0 &apps_smmu 0x1400 0x1>, 3630 <0x100 &apps_smmu 0x1401 0x1>; 3631 3632 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, 3633 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, 3634 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, 3635 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; 3636 interrupt-map-mask = <0 0 0 0x7>; 3637 #interrupt-cells = <1>; 3638 3639 msi-map = <0x0 &gic_its 0x1400 0x1>, 3640 <0x100 &gic_its 0x1401 0x1>; 3641 msi-map-mask = <0xff00>; 3642 3643 linux,pci-domain = <0>; 3644 num-lanes = <2>; 3645 bus-range = <0 0xff>; 3646 3647 phys = <&pcie0_phy>; 3648 phy-names = "pciephy"; 3649 3650 #address-cells = <3>; 3651 #size-cells = <2>; 3652 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 3653 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 3654 3655 dma-coherent; 3656 3657 status = "disabled"; 3658 3659 pcie0_opp_table: opp-table { 3660 compatible = "operating-points-v2"; 3661 3662 /* GEN 1 x1 */ 3663 opp-2500000 { 3664 opp-hz = /bits/ 64 <2500000>; 3665 required-opps = <&rpmhpd_opp_low_svs>; 3666 opp-peak-kBps = <250000 1>; 3667 }; 3668 3669 /* GEN 1 x2 and GEN 2 x1 */ 3670 opp-5000000 { 3671 opp-hz = /bits/ 64 <5000000>; 3672 required-opps = <&rpmhpd_opp_low_svs>; 3673 opp-peak-kBps = <500000 1>; 3674 }; 3675 3676 /* GEN 2 x2 */ 3677 opp-10000000 { 3678 opp-hz = /bits/ 64 <10000000>; 3679 required-opps = <&rpmhpd_opp_low_svs>; 3680 opp-peak-kBps = <1000000 1>; 3681 }; 3682 3683 /* GEN 3 x1 */ 3684 opp-8000000 { 3685 opp-hz = /bits/ 64 <8000000>; 3686 required-opps = <&rpmhpd_opp_nom>; 3687 opp-peak-kBps = <984500 1>; 3688 }; 3689 3690 /* GEN 3 x2 */ 3691 opp-16000000 { 3692 opp-hz = /bits/ 64 <16000000>; 3693 required-opps = <&rpmhpd_opp_nom>; 3694 opp-peak-kBps = <1969000 1>; 3695 }; 3696 }; 3697 3698 pcieport0: pcie@0 { 3699 device_type = "pci"; 3700 reg = <0x0 0x0 0x0 0x0 0x0>; 3701 bus-range = <0x01 0xff>; 3702 3703 #address-cells = <3>; 3704 #size-cells = <2>; 3705 ranges; 3706 }; 3707 }; 3708 3709 pcie0_phy: phy@1c06000 { 3710 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 3711 reg = <0 0x01c06000 0 0x2000>; 3712 3713 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3714 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3715 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 3716 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 3717 <&gcc GCC_PCIE_0_PIPE_CLK>; 3718 clock-names = "aux", 3719 "cfg_ahb", 3720 "ref", 3721 "rchng", 3722 "pipe"; 3723 3724 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 3725 assigned-clock-rates = <100000000>; 3726 3727 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 3728 reset-names = "phy"; 3729 3730 power-domains = <&gcc PCIE_0_PHY_GDSC>; 3731 3732 #clock-cells = <0>; 3733 clock-output-names = "pcie0_pipe_clk"; 3734 3735 #phy-cells = <0>; 3736 3737 status = "disabled"; 3738 }; 3739 3740 pcie1: pcie@1c08000 { 3741 device_type = "pci"; 3742 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 3743 reg = <0 0x01c08000 0 0x3000>, 3744 <0 0x40000000 0 0xf1d>, 3745 <0 0x40000f20 0 0xa8>, 3746 <0 0x40001000 0 0x1000>, 3747 <0 0x40100000 0 0x100000>; 3748 reg-names = "parf", 3749 "dbi", 3750 "elbi", 3751 "atu", 3752 "config"; 3753 3754 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, 3755 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, 3756 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, 3757 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, 3758 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, 3759 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, 3760 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 3761 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, 3762 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 3763 interrupt-names = "msi0", 3764 "msi1", 3765 "msi2", 3766 "msi3", 3767 "msi4", 3768 "msi5", 3769 "msi6", 3770 "msi7", 3771 "global"; 3772 3773 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 3774 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3775 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 3776 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 3777 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 3778 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3779 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3780 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3781 clock-names = "aux", 3782 "cfg", 3783 "bus_master", 3784 "bus_slave", 3785 "slave_q2a", 3786 "ddrss_sf_tbu", 3787 "noc_aggr", 3788 "cnoc_sf_axi"; 3789 3790 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 3791 assigned-clock-rates = <19200000>; 3792 3793 resets = <&gcc GCC_PCIE_1_BCR>, 3794 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 3795 reset-names = "pci", 3796 "link_down"; 3797 3798 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 3799 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3800 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3801 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3802 interconnect-names = "pcie-mem", 3803 "cpu-pcie"; 3804 3805 power-domains = <&gcc PCIE_1_GDSC>; 3806 3807 operating-points-v2 = <&pcie1_opp_table>; 3808 3809 iommu-map = <0 &apps_smmu 0x1480 0x1>, 3810 <0x100 &apps_smmu 0x1481 0x1>; 3811 3812 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, 3813 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, 3814 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, 3815 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; 3816 interrupt-map-mask = <0 0 0 0x7>; 3817 #interrupt-cells = <1>; 3818 3819 msi-map = <0x0 &gic_its 0x1480 0x1>, 3820 <0x100 &gic_its 0x1481 0x1>; 3821 msi-map-mask = <0xff00>; 3822 3823 linux,pci-domain = <1>; 3824 num-lanes = <2>; 3825 bus-range = <0 0xff>; 3826 3827 phys = <&pcie1_phy>; 3828 phy-names = "pciephy"; 3829 3830 dma-coherent; 3831 3832 #address-cells = <3>; 3833 #size-cells = <2>; 3834 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 3835 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 3836 3837 status = "disabled"; 3838 3839 pcie1_opp_table: opp-table { 3840 compatible = "operating-points-v2"; 3841 3842 /* GEN 1 x1 */ 3843 opp-2500000 { 3844 opp-hz = /bits/ 64 <2500000>; 3845 required-opps = <&rpmhpd_opp_low_svs>; 3846 opp-peak-kBps = <250000 1>; 3847 }; 3848 3849 /* GEN 1 x2 and GEN 2 x1 */ 3850 opp-5000000 { 3851 opp-hz = /bits/ 64 <5000000>; 3852 required-opps = <&rpmhpd_opp_low_svs>; 3853 opp-peak-kBps = <500000 1>; 3854 }; 3855 3856 /* GEN 2 x2 */ 3857 opp-10000000 { 3858 opp-hz = /bits/ 64 <10000000>; 3859 required-opps = <&rpmhpd_opp_low_svs>; 3860 opp-peak-kBps = <1000000 1>; 3861 }; 3862 3863 /* GEN 3 x1 */ 3864 opp-8000000 { 3865 opp-hz = /bits/ 64 <8000000>; 3866 required-opps = <&rpmhpd_opp_nom>; 3867 opp-peak-kBps = <984500 1>; 3868 }; 3869 3870 /* GEN 3 x2 and GEN 4 x1 */ 3871 opp-16000000 { 3872 opp-hz = /bits/ 64 <16000000>; 3873 required-opps = <&rpmhpd_opp_nom>; 3874 opp-peak-kBps = <1969000 1>; 3875 }; 3876 3877 /* GEN 4 x2 */ 3878 opp-32000000 { 3879 opp-hz = /bits/ 64 <32000000>; 3880 required-opps = <&rpmhpd_opp_nom>; 3881 opp-peak-kBps = <3938000 1>; 3882 }; 3883 }; 3884 3885 pcie@0 { 3886 device_type = "pci"; 3887 reg = <0x0 0x0 0x0 0x0 0x0>; 3888 bus-range = <0x01 0xff>; 3889 3890 #address-cells = <3>; 3891 #size-cells = <2>; 3892 ranges; 3893 }; 3894 }; 3895 3896 pcie1_phy: phy@1c0e000 { 3897 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 3898 reg = <0 0x01c0e000 0 0x2000>; 3899 3900 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 3901 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3902 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3903 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 3904 <&gcc GCC_PCIE_1_PIPE_CLK>; 3905 clock-names = "aux", 3906 "cfg_ahb", 3907 "ref", 3908 "rchng", 3909 "pipe"; 3910 3911 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 3912 assigned-clock-rates = <100000000>; 3913 3914 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 3915 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 3916 reset-names = "phy", 3917 "phy_nocsr"; 3918 3919 power-domains = <&gcc PCIE_1_PHY_GDSC>; 3920 3921 #clock-cells = <1>; 3922 clock-output-names = "pcie1_pipe_clk"; 3923 3924 #phy-cells = <0>; 3925 3926 status = "disabled"; 3927 }; 3928 3929 cryptobam: dma-controller@1dc4000 { 3930 compatible = "qcom,bam-v1.7.0"; 3931 reg = <0 0x01dc4000 0 0x28000>; 3932 3933 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 3934 3935 #dma-cells = <1>; 3936 3937 iommus = <&apps_smmu 0x480 0>, 3938 <&apps_smmu 0x481 0>; 3939 3940 qcom,ee = <0>; 3941 qcom,num-ees = <4>; 3942 num-channels = <20>; 3943 qcom,controlled-remotely; 3944 }; 3945 3946 crypto: crypto@1dfa000 { 3947 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 3948 reg = <0 0x01dfa000 0 0x6000>; 3949 3950 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 3951 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3952 interconnect-names = "memory"; 3953 3954 dmas = <&cryptobam 4>, <&cryptobam 5>; 3955 dma-names = "rx", "tx"; 3956 3957 iommus = <&apps_smmu 0x480 0>, 3958 <&apps_smmu 0x481 0>; 3959 }; 3960 3961 ufs_mem_phy: phy@1d80000 { 3962 compatible = "qcom,sm8650-qmp-ufs-phy"; 3963 reg = <0 0x01d80000 0 0x2000>; 3964 3965 clocks = <&rpmhcc RPMH_CXO_CLK>, 3966 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3967 <&tcsr TCSR_UFS_CLKREF_EN>; 3968 clock-names = "ref", 3969 "ref_aux", 3970 "qref"; 3971 3972 resets = <&ufs_mem_hc 0>; 3973 reset-names = "ufsphy"; 3974 3975 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 3976 3977 #clock-cells = <1>; 3978 #phy-cells = <0>; 3979 3980 status = "disabled"; 3981 }; 3982 3983 ufs_mem_hc: ufshc@1d84000 { 3984 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 3985 reg = <0 0x01d84000 0 0x3000>; 3986 3987 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 3988 3989 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3990 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3991 <&gcc GCC_UFS_PHY_AHB_CLK>, 3992 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3993 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 3994 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3995 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3996 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3997 clock-names = "core_clk", 3998 "bus_aggr_clk", 3999 "iface_clk", 4000 "core_clk_unipro", 4001 "ref_clk", 4002 "tx_lane0_sync_clk", 4003 "rx_lane0_sync_clk", 4004 "rx_lane1_sync_clk"; 4005 4006 resets = <&gcc GCC_UFS_PHY_BCR>; 4007 reset-names = "rst"; 4008 4009 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 4010 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4011 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4012 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4013 interconnect-names = "ufs-ddr", 4014 "cpu-ufs"; 4015 4016 power-domains = <&gcc UFS_PHY_GDSC>; 4017 required-opps = <&rpmhpd_opp_nom>; 4018 4019 operating-points-v2 = <&ufs_opp_table>; 4020 4021 iommus = <&apps_smmu 0x60 0>; 4022 4023 lanes-per-direction = <2>; 4024 qcom,ice = <&ice>; 4025 4026 phys = <&ufs_mem_phy>; 4027 phy-names = "ufsphy"; 4028 4029 #reset-cells = <1>; 4030 4031 status = "disabled"; 4032 4033 ufs_opp_table: opp-table { 4034 compatible = "operating-points-v2"; 4035 4036 opp-100000000 { 4037 opp-hz = /bits/ 64 <100000000>, 4038 /bits/ 64 <0>, 4039 /bits/ 64 <0>, 4040 /bits/ 64 <100000000>, 4041 /bits/ 64 <0>, 4042 /bits/ 64 <0>, 4043 /bits/ 64 <0>, 4044 /bits/ 64 <0>; 4045 required-opps = <&rpmhpd_opp_low_svs>; 4046 }; 4047 4048 opp-201500000 { 4049 opp-hz = /bits/ 64 <201500000>, 4050 /bits/ 64 <0>, 4051 /bits/ 64 <0>, 4052 /bits/ 64 <201500000>, 4053 /bits/ 64 <0>, 4054 /bits/ 64 <0>, 4055 /bits/ 64 <0>, 4056 /bits/ 64 <0>; 4057 required-opps = <&rpmhpd_opp_svs>; 4058 }; 4059 4060 opp-403000000 { 4061 opp-hz = /bits/ 64 <403000000>, 4062 /bits/ 64 <0>, 4063 /bits/ 64 <0>, 4064 /bits/ 64 <403000000>, 4065 /bits/ 64 <0>, 4066 /bits/ 64 <0>, 4067 /bits/ 64 <0>, 4068 /bits/ 64 <0>; 4069 required-opps = <&rpmhpd_opp_nom>; 4070 }; 4071 }; 4072 }; 4073 4074 ice: crypto@1d88000 { 4075 compatible = "qcom,sm8650-inline-crypto-engine", 4076 "qcom,inline-crypto-engine"; 4077 reg = <0 0x01d88000 0 0x18000>; 4078 4079 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4080 }; 4081 4082 tcsr_mutex: hwlock@1f40000 { 4083 compatible = "qcom,tcsr-mutex"; 4084 reg = <0 0x01f40000 0 0x20000>; 4085 4086 #hwlock-cells = <1>; 4087 }; 4088 4089 tcsr: clock-controller@1fc0000 { 4090 compatible = "qcom,sm8650-tcsr", "syscon"; 4091 reg = <0 0x01fc0000 0 0xa0000>; 4092 4093 clocks = <&rpmhcc RPMH_CXO_CLK>; 4094 4095 #clock-cells = <1>; 4096 #reset-cells = <1>; 4097 }; 4098 4099 gpu: gpu@3d00000 { 4100 compatible = "qcom,adreno-43051401", "qcom,adreno"; 4101 reg = <0x0 0x03d00000 0x0 0x40000>, 4102 <0x0 0x03d9e000 0x0 0x2000>, 4103 <0x0 0x03d61000 0x0 0x800>; 4104 reg-names = "kgsl_3d0_reg_memory", 4105 "cx_mem", 4106 "cx_dbgc"; 4107 4108 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 4109 4110 iommus = <&adreno_smmu 0 0x0>, 4111 <&adreno_smmu 1 0x0>; 4112 4113 operating-points-v2 = <&gpu_opp_table>; 4114 4115 qcom,gmu = <&gmu>; 4116 #cooling-cells = <2>; 4117 4118 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4119 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4120 interconnect-names = "gfx-mem"; 4121 4122 status = "disabled"; 4123 4124 zap-shader { 4125 memory-region = <&gpu_micro_code_mem>; 4126 }; 4127 4128 /* Speedbin needs more work on A740+, keep only lower freqs */ 4129 gpu_opp_table: opp-table { 4130 compatible = "operating-points-v2"; 4131 4132 opp-231000000 { 4133 opp-hz = /bits/ 64 <231000000>; 4134 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4135 opp-peak-kBps = <2136718>; 4136 }; 4137 4138 opp-310000000 { 4139 opp-hz = /bits/ 64 <310000000>; 4140 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4141 opp-peak-kBps = <2136718>; 4142 }; 4143 4144 opp-366000000 { 4145 opp-hz = /bits/ 64 <366000000>; 4146 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4147 opp-peak-kBps = <6074218>; 4148 }; 4149 4150 opp-422000000 { 4151 opp-hz = /bits/ 64 <422000000>; 4152 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4153 opp-peak-kBps = <8171875>; 4154 }; 4155 4156 opp-500000000 { 4157 opp-hz = /bits/ 64 <500000000>; 4158 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4159 opp-peak-kBps = <8171875>; 4160 }; 4161 4162 opp-578000000 { 4163 opp-hz = /bits/ 64 <578000000>; 4164 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4165 opp-peak-kBps = <8171875>; 4166 }; 4167 4168 opp-629000000 { 4169 opp-hz = /bits/ 64 <629000000>; 4170 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4171 opp-peak-kBps = <10687500>; 4172 }; 4173 4174 opp-680000000 { 4175 opp-hz = /bits/ 64 <680000000>; 4176 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4177 opp-peak-kBps = <12449218>; 4178 }; 4179 4180 opp-720000000 { 4181 opp-hz = /bits/ 64 <720000000>; 4182 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4183 opp-peak-kBps = <12449218>; 4184 }; 4185 4186 opp-770000000 { 4187 opp-hz = /bits/ 64 <770000000>; 4188 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4189 opp-peak-kBps = <12449218>; 4190 }; 4191 4192 opp-834000000 { 4193 opp-hz = /bits/ 64 <834000000>; 4194 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4195 opp-peak-kBps = <14398437>; 4196 }; 4197 }; 4198 }; 4199 4200 gmu: gmu@3d6a000 { 4201 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; 4202 reg = <0x0 0x03d6a000 0x0 0x35000>, 4203 <0x0 0x03d50000 0x0 0x10000>, 4204 <0x0 0x0b280000 0x0 0x10000>; 4205 reg-names = "gmu", "rscc", "gmu_pdc"; 4206 4207 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 4208 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 4209 interrupt-names = "hfi", "gmu"; 4210 4211 clocks = <&gpucc GPU_CC_AHB_CLK>, 4212 <&gpucc GPU_CC_CX_GMU_CLK>, 4213 <&gpucc GPU_CC_CXO_CLK>, 4214 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4215 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4216 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4217 <&gpucc GPU_CC_DEMET_CLK>; 4218 clock-names = "ahb", 4219 "gmu", 4220 "cxo", 4221 "axi", 4222 "memnoc", 4223 "hub", 4224 "demet"; 4225 4226 power-domains = <&gpucc GPU_CX_GDSC>, 4227 <&gpucc GPU_GX_GDSC>; 4228 power-domain-names = "cx", 4229 "gx"; 4230 4231 iommus = <&adreno_smmu 5 0x0>; 4232 4233 qcom,qmp = <&aoss_qmp>; 4234 4235 operating-points-v2 = <&gmu_opp_table>; 4236 4237 gmu_opp_table: opp-table { 4238 compatible = "operating-points-v2"; 4239 4240 opp-260000000 { 4241 opp-hz = /bits/ 64 <260000000>; 4242 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4243 }; 4244 4245 opp-625000000 { 4246 opp-hz = /bits/ 64 <625000000>; 4247 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4248 }; 4249 }; 4250 }; 4251 4252 gpucc: clock-controller@3d90000 { 4253 compatible = "qcom,sm8650-gpucc"; 4254 reg = <0 0x03d90000 0 0xa000>; 4255 4256 clocks = <&bi_tcxo_div2>, 4257 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4258 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4259 4260 #clock-cells = <1>; 4261 #reset-cells = <1>; 4262 #power-domain-cells = <1>; 4263 }; 4264 4265 adreno_smmu: iommu@3da0000 { 4266 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", 4267 "qcom,smmu-500", "arm,mmu-500"; 4268 reg = <0x0 0x03da0000 0x0 0x40000>; 4269 #iommu-cells = <2>; 4270 #global-interrupts = <1>; 4271 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 4272 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 4273 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 4274 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 4275 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 4276 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 4277 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 4278 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 4279 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 4280 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 4281 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 4282 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 4283 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 4284 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 4285 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 4286 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 4287 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 4288 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 4289 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 4290 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 4291 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 4292 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 4293 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 4294 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 4295 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 4296 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 4297 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4298 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4299 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4300 <&gpucc GPU_CC_AHB_CLK>; 4301 clock-names = "hlos", 4302 "bus", 4303 "iface", 4304 "ahb"; 4305 power-domains = <&gpucc GPU_CX_GDSC>; 4306 dma-coherent; 4307 }; 4308 4309 ipa: ipa@3f40000 { 4310 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 4311 4312 iommus = <&apps_smmu 0x4a0 0x0>, 4313 <&apps_smmu 0x4a2 0x0>; 4314 reg = <0 0x3f40000 0 0x10000>, 4315 <0 0x3f50000 0 0x5000>, 4316 <0 0x3e04000 0 0xfc000>; 4317 reg-names = "ipa-reg", 4318 "ipa-shared", 4319 "gsi"; 4320 4321 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, 4322 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, 4323 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4324 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 4325 interrupt-names = "ipa", 4326 "gsi", 4327 "ipa-clock-query", 4328 "ipa-setup-ready"; 4329 4330 clocks = <&rpmhcc RPMH_IPA_CLK>; 4331 clock-names = "core"; 4332 4333 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 4334 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4335 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4336 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4337 interconnect-names = "memory", 4338 "config"; 4339 4340 qcom,qmp = <&aoss_qmp>; 4341 4342 qcom,smem-states = <&ipa_smp2p_out 0>, 4343 <&ipa_smp2p_out 1>; 4344 qcom,smem-state-names = "ipa-clock-enabled-valid", 4345 "ipa-clock-enabled"; 4346 4347 status = "disabled"; 4348 }; 4349 4350 remoteproc_mpss: remoteproc@4080000 { 4351 compatible = "qcom,sm8650-mpss-pas"; 4352 reg = <0x0 0x04080000 0x0 0x10000>; 4353 4354 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 4355 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 4356 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 4357 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 4358 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 4359 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 4360 interrupt-names = "wdog", 4361 "fatal", 4362 "ready", 4363 "handover", 4364 "stop-ack", 4365 "shutdown-ack"; 4366 4367 clocks = <&rpmhcc RPMH_CXO_CLK>; 4368 clock-names = "xo"; 4369 4370 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 4371 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4372 4373 power-domains = <&rpmhpd RPMHPD_CX>, 4374 <&rpmhpd RPMHPD_MSS>; 4375 power-domain-names = "cx", 4376 "mss"; 4377 4378 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 4379 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 4380 <&qlink_logging_mem>; 4381 4382 qcom,qmp = <&aoss_qmp>; 4383 4384 qcom,smem-states = <&smp2p_modem_out 0>; 4385 qcom,smem-state-names = "stop"; 4386 4387 status = "disabled"; 4388 4389 glink-edge { 4390 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 4391 IPCC_MPROC_SIGNAL_GLINK_QMP 4392 IRQ_TYPE_EDGE_RISING>; 4393 4394 mboxes = <&ipcc IPCC_CLIENT_MPSS 4395 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4396 4397 qcom,remote-pid = <1>; 4398 4399 label = "mpss"; 4400 }; 4401 }; 4402 4403 remoteproc_adsp: remoteproc@6800000 { 4404 compatible = "qcom,sm8650-adsp-pas"; 4405 reg = <0x0 0x06800000 0x0 0x10000>; 4406 4407 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4408 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4409 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4410 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4411 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4412 interrupt-names = "wdog", 4413 "fatal", 4414 "ready", 4415 "handover", 4416 "stop-ack"; 4417 4418 clocks = <&rpmhcc RPMH_CXO_CLK>; 4419 clock-names = "xo"; 4420 4421 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4422 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4423 4424 power-domains = <&rpmhpd RPMHPD_LCX>, 4425 <&rpmhpd RPMHPD_LMX>; 4426 power-domain-names = "lcx", 4427 "lmx"; 4428 4429 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4430 4431 qcom,qmp = <&aoss_qmp>; 4432 4433 qcom,smem-states = <&smp2p_adsp_out 0>; 4434 qcom,smem-state-names = "stop"; 4435 4436 status = "disabled"; 4437 4438 remoteproc_adsp_glink: glink-edge { 4439 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4440 IPCC_MPROC_SIGNAL_GLINK_QMP 4441 IRQ_TYPE_EDGE_RISING>; 4442 4443 mboxes = <&ipcc IPCC_CLIENT_LPASS 4444 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4445 4446 qcom,remote-pid = <2>; 4447 4448 label = "lpass"; 4449 4450 fastrpc { 4451 compatible = "qcom,fastrpc"; 4452 4453 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4454 4455 label = "adsp"; 4456 4457 qcom,non-secure-domain; 4458 4459 #address-cells = <1>; 4460 #size-cells = <0>; 4461 4462 compute-cb@3 { 4463 compatible = "qcom,fastrpc-compute-cb"; 4464 reg = <3>; 4465 4466 iommus = <&apps_smmu 0x1003 0x80>, 4467 <&apps_smmu 0x1043 0x20>; 4468 dma-coherent; 4469 }; 4470 4471 compute-cb@4 { 4472 compatible = "qcom,fastrpc-compute-cb"; 4473 reg = <4>; 4474 4475 iommus = <&apps_smmu 0x1004 0x80>, 4476 <&apps_smmu 0x1044 0x20>; 4477 dma-coherent; 4478 }; 4479 4480 compute-cb@5 { 4481 compatible = "qcom,fastrpc-compute-cb"; 4482 reg = <5>; 4483 4484 iommus = <&apps_smmu 0x1005 0x80>, 4485 <&apps_smmu 0x1045 0x20>; 4486 dma-coherent; 4487 }; 4488 4489 compute-cb@6 { 4490 compatible = "qcom,fastrpc-compute-cb"; 4491 reg = <6>; 4492 4493 iommus = <&apps_smmu 0x1006 0x80>, 4494 <&apps_smmu 0x1046 0x20>; 4495 dma-coherent; 4496 }; 4497 4498 compute-cb@7 { 4499 compatible = "qcom,fastrpc-compute-cb"; 4500 reg = <7>; 4501 4502 iommus = <&apps_smmu 0x1007 0x40>, 4503 <&apps_smmu 0x1067 0x0>, 4504 <&apps_smmu 0x1087 0x0>; 4505 dma-coherent; 4506 }; 4507 }; 4508 4509 gpr { 4510 compatible = "qcom,gpr"; 4511 qcom,glink-channels = "adsp_apps"; 4512 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4513 qcom,intents = <512 20>; 4514 #address-cells = <1>; 4515 #size-cells = <0>; 4516 4517 q6apm: service@1 { 4518 compatible = "qcom,q6apm"; 4519 reg = <GPR_APM_MODULE_IID>; 4520 #sound-dai-cells = <0>; 4521 qcom,protection-domain = "avs/audio", 4522 "msm/adsp/audio_pd"; 4523 4524 q6apmbedai: bedais { 4525 compatible = "qcom,q6apm-lpass-dais"; 4526 #sound-dai-cells = <1>; 4527 }; 4528 4529 q6apmdai: dais { 4530 compatible = "qcom,q6apm-dais"; 4531 iommus = <&apps_smmu 0x1001 0x80>, 4532 <&apps_smmu 0x1061 0x0>; 4533 }; 4534 }; 4535 4536 q6prm: service@2 { 4537 compatible = "qcom,q6prm"; 4538 reg = <GPR_PRM_MODULE_IID>; 4539 qcom,protection-domain = "avs/audio", 4540 "msm/adsp/audio_pd"; 4541 4542 q6prmcc: clock-controller { 4543 compatible = "qcom,q6prm-lpass-clocks"; 4544 #clock-cells = <2>; 4545 }; 4546 }; 4547 }; 4548 }; 4549 }; 4550 4551 lpass_wsa2macro: codec@6aa0000 { 4552 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4553 reg = <0 0x06aa0000 0 0x1000>; 4554 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4555 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4556 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4557 <&lpass_vamacro>; 4558 clock-names = "mclk", 4559 "macro", 4560 "dcodec", 4561 "fsgen"; 4562 4563 #clock-cells = <0>; 4564 clock-output-names = "wsa2-mclk"; 4565 #sound-dai-cells = <1>; 4566 }; 4567 4568 swr3: soundwire@6ab0000 { 4569 compatible = "qcom,soundwire-v2.0.0"; 4570 reg = <0 0x06ab0000 0 0x10000>; 4571 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 4572 clocks = <&lpass_wsa2macro>; 4573 clock-names = "iface"; 4574 label = "WSA2"; 4575 4576 pinctrl-0 = <&wsa2_swr_active>; 4577 pinctrl-names = "default"; 4578 4579 qcom,din-ports = <4>; 4580 qcom,dout-ports = <9>; 4581 4582 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4583 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4584 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4585 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4586 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4587 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4588 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4589 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4590 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4591 4592 #address-cells = <2>; 4593 #size-cells = <0>; 4594 #sound-dai-cells = <1>; 4595 status = "disabled"; 4596 }; 4597 4598 lpass_rxmacro: codec@6ac0000 { 4599 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4600 reg = <0 0x06ac0000 0 0x1000>; 4601 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4602 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4603 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4604 <&lpass_vamacro>; 4605 clock-names = "mclk", 4606 "macro", 4607 "dcodec", 4608 "fsgen"; 4609 4610 #clock-cells = <0>; 4611 clock-output-names = "mclk"; 4612 #sound-dai-cells = <1>; 4613 }; 4614 4615 swr1: soundwire@6ad0000 { 4616 compatible = "qcom,soundwire-v2.0.0"; 4617 reg = <0 0x06ad0000 0 0x10000>; 4618 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 4619 clocks = <&lpass_rxmacro>; 4620 clock-names = "iface"; 4621 label = "RX"; 4622 4623 pinctrl-0 = <&rx_swr_active>; 4624 pinctrl-names = "default"; 4625 4626 qcom,din-ports = <0>; 4627 qcom,dout-ports = <11>; 4628 4629 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 4630 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 4631 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 4632 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 4633 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 4634 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 4635 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 4636 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 4637 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 4638 4639 #address-cells = <2>; 4640 #size-cells = <0>; 4641 #sound-dai-cells = <1>; 4642 status = "disabled"; 4643 }; 4644 4645 lpass_txmacro: codec@6ae0000 { 4646 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4647 reg = <0 0x06ae0000 0 0x1000>; 4648 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4649 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4650 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4651 <&lpass_vamacro>; 4652 clock-names = "mclk", 4653 "macro", 4654 "dcodec", 4655 "fsgen"; 4656 4657 #clock-cells = <0>; 4658 clock-output-names = "mclk"; 4659 #sound-dai-cells = <1>; 4660 }; 4661 4662 lpass_wsamacro: codec@6b00000 { 4663 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4664 reg = <0 0x06b00000 0 0x1000>; 4665 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4666 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4667 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4668 <&lpass_vamacro>; 4669 clock-names = "mclk", 4670 "macro", 4671 "dcodec", 4672 "fsgen"; 4673 4674 #clock-cells = <0>; 4675 clock-output-names = "mclk"; 4676 #sound-dai-cells = <1>; 4677 }; 4678 4679 swr0: soundwire@6b10000 { 4680 compatible = "qcom,soundwire-v2.0.0"; 4681 reg = <0 0x06b10000 0 0x10000>; 4682 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 4683 clocks = <&lpass_wsamacro>; 4684 clock-names = "iface"; 4685 label = "WSA"; 4686 4687 pinctrl-0 = <&wsa_swr_active>; 4688 pinctrl-names = "default"; 4689 4690 qcom,din-ports = <4>; 4691 qcom,dout-ports = <9>; 4692 4693 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4694 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4695 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4696 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4697 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4698 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4699 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4700 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4701 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4702 4703 #address-cells = <2>; 4704 #size-cells = <0>; 4705 #sound-dai-cells = <1>; 4706 status = "disabled"; 4707 }; 4708 4709 swr2: soundwire@6d30000 { 4710 compatible = "qcom,soundwire-v2.0.0"; 4711 reg = <0 0x06d30000 0 0x10000>; 4712 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, 4713 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 4714 interrupt-names = "core", "wakeup"; 4715 clocks = <&lpass_txmacro>; 4716 clock-names = "iface"; 4717 label = "TX"; 4718 4719 pinctrl-0 = <&tx_swr_active>; 4720 pinctrl-names = "default"; 4721 4722 qcom,din-ports = <4>; 4723 qcom,dout-ports = <0>; 4724 4725 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 4726 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 4727 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 4728 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 4729 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 4730 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 4731 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 4732 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 4733 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 4734 4735 #address-cells = <2>; 4736 #size-cells = <0>; 4737 #sound-dai-cells = <1>; 4738 status = "disabled"; 4739 }; 4740 4741 lpass_vamacro: codec@6d44000 { 4742 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4743 reg = <0 0x06d44000 0 0x1000>; 4744 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4745 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4746 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4747 clock-names = "mclk", 4748 "macro", 4749 "dcodec"; 4750 4751 #clock-cells = <0>; 4752 clock-output-names = "fsgen"; 4753 #sound-dai-cells = <1>; 4754 }; 4755 4756 lpass_tlmm: pinctrl@6e80000 { 4757 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 4758 reg = <0 0x06e80000 0 0x20000>; 4759 4760 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4761 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4762 clock-names = "core", "audio"; 4763 4764 gpio-controller; 4765 #gpio-cells = <2>; 4766 gpio-ranges = <&lpass_tlmm 0 0 23>; 4767 4768 tx_swr_active: tx-swr-active-state { 4769 clk-pins { 4770 pins = "gpio0"; 4771 function = "swr_tx_clk"; 4772 drive-strength = <2>; 4773 slew-rate = <1>; 4774 bias-disable; 4775 }; 4776 4777 data-pins { 4778 pins = "gpio1", "gpio2", "gpio14"; 4779 function = "swr_tx_data"; 4780 drive-strength = <2>; 4781 slew-rate = <1>; 4782 bias-bus-hold; 4783 }; 4784 }; 4785 4786 rx_swr_active: rx-swr-active-state { 4787 clk-pins { 4788 pins = "gpio3"; 4789 function = "swr_rx_clk"; 4790 drive-strength = <2>; 4791 slew-rate = <1>; 4792 bias-disable; 4793 }; 4794 4795 data-pins { 4796 pins = "gpio4", "gpio5"; 4797 function = "swr_rx_data"; 4798 drive-strength = <2>; 4799 slew-rate = <1>; 4800 bias-bus-hold; 4801 }; 4802 }; 4803 4804 dmic01_default: dmic01-default-state { 4805 clk-pins { 4806 pins = "gpio6"; 4807 function = "dmic1_clk"; 4808 drive-strength = <8>; 4809 output-high; 4810 }; 4811 4812 data-pins { 4813 pins = "gpio7"; 4814 function = "dmic1_data"; 4815 drive-strength = <8>; 4816 input-enable; 4817 }; 4818 }; 4819 4820 dmic23_default: dmic23-default-state { 4821 clk-pins { 4822 pins = "gpio8"; 4823 function = "dmic2_clk"; 4824 drive-strength = <8>; 4825 output-high; 4826 }; 4827 4828 data-pins { 4829 pins = "gpio9"; 4830 function = "dmic2_data"; 4831 drive-strength = <8>; 4832 input-enable; 4833 }; 4834 }; 4835 4836 wsa_swr_active: wsa-swr-active-state { 4837 clk-pins { 4838 pins = "gpio10"; 4839 function = "wsa_swr_clk"; 4840 drive-strength = <2>; 4841 slew-rate = <1>; 4842 bias-disable; 4843 }; 4844 4845 data-pins { 4846 pins = "gpio11"; 4847 function = "wsa_swr_data"; 4848 drive-strength = <2>; 4849 slew-rate = <1>; 4850 bias-bus-hold; 4851 }; 4852 }; 4853 4854 wsa2_swr_active: wsa2-swr-active-state { 4855 clk-pins { 4856 pins = "gpio15"; 4857 function = "wsa2_swr_clk"; 4858 drive-strength = <2>; 4859 slew-rate = <1>; 4860 bias-disable; 4861 }; 4862 4863 data-pins { 4864 pins = "gpio16"; 4865 function = "wsa2_swr_data"; 4866 drive-strength = <2>; 4867 slew-rate = <1>; 4868 bias-bus-hold; 4869 }; 4870 }; 4871 }; 4872 4873 lpass_lpiaon_noc: interconnect@7400000 { 4874 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 4875 reg = <0 0x07400000 0 0x19080>; 4876 4877 #interconnect-cells = <2>; 4878 4879 qcom,bcm-voters = <&apps_bcm_voter>; 4880 }; 4881 4882 lpass_lpicx_noc: interconnect@7430000 { 4883 compatible = "qcom,sm8650-lpass-lpicx-noc"; 4884 reg = <0 0x07430000 0 0x3a200>; 4885 4886 #interconnect-cells = <2>; 4887 4888 qcom,bcm-voters = <&apps_bcm_voter>; 4889 }; 4890 4891 lpass_ag_noc: interconnect@7e40000 { 4892 compatible = "qcom,sm8650-lpass-ag-noc"; 4893 reg = <0 0x07e40000 0 0xe080>; 4894 4895 #interconnect-cells = <2>; 4896 4897 qcom,bcm-voters = <&apps_bcm_voter>; 4898 }; 4899 4900 sdhc_2: mmc@8804000 { 4901 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 4902 reg = <0 0x08804000 0 0x1000>; 4903 4904 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, 4905 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; 4906 interrupt-names = "hc_irq", 4907 "pwr_irq"; 4908 4909 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4910 <&gcc GCC_SDCC2_APPS_CLK>, 4911 <&rpmhcc RPMH_CXO_CLK>; 4912 clock-names = "iface", 4913 "core", 4914 "xo"; 4915 4916 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4919 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4920 interconnect-names = "sdhc-ddr", 4921 "cpu-sdhc"; 4922 4923 power-domains = <&rpmhpd RPMHPD_CX>; 4924 operating-points-v2 = <&sdhc2_opp_table>; 4925 4926 iommus = <&apps_smmu 0x540 0>; 4927 4928 bus-width = <4>; 4929 4930 /* Forbid SDR104/SDR50 - broken hw! */ 4931 sdhci-caps-mask = <0x3 0>; 4932 4933 qcom,dll-config = <0x0007642c>; 4934 qcom,ddr-config = <0x80040868>; 4935 4936 dma-coherent; 4937 4938 status = "disabled"; 4939 4940 sdhc2_opp_table: opp-table { 4941 compatible = "operating-points-v2"; 4942 4943 opp-19200000 { 4944 opp-hz = /bits/ 64 <19200000>; 4945 required-opps = <&rpmhpd_opp_min_svs>; 4946 }; 4947 4948 opp-50000000 { 4949 opp-hz = /bits/ 64 <50000000>; 4950 required-opps = <&rpmhpd_opp_low_svs>; 4951 }; 4952 4953 opp-100000000 { 4954 opp-hz = /bits/ 64 <100000000>; 4955 required-opps = <&rpmhpd_opp_svs>; 4956 }; 4957 4958 opp-202000000 { 4959 opp-hz = /bits/ 64 <202000000>; 4960 required-opps = <&rpmhpd_opp_svs_l1>; 4961 }; 4962 }; 4963 }; 4964 4965 iris: video-codec@aa00000 { 4966 compatible = "qcom,sm8650-iris"; 4967 reg = <0 0x0aa00000 0 0xf0000>; 4968 4969 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 4970 4971 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4972 <&videocc VIDEO_CC_MVS0_GDSC>, 4973 <&rpmhpd RPMHPD_MXC>, 4974 <&rpmhpd RPMHPD_MMCX>; 4975 power-domain-names = "venus", 4976 "vcodec0", 4977 "mxc", 4978 "mmcx"; 4979 4980 operating-points-v2 = <&iris_opp_table>; 4981 4982 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4983 <&videocc VIDEO_CC_MVS0C_CLK>, 4984 <&videocc VIDEO_CC_MVS0_CLK>; 4985 clock-names = "iface", 4986 "core", 4987 "vcodec0_core"; 4988 4989 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4990 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4991 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 4992 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4993 interconnect-names = "cpu-cfg", 4994 "video-mem"; 4995 4996 memory-region = <&video_mem>; 4997 4998 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 4999 <&videocc VIDEO_CC_XO_CLK_ARES>, 5000 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 5001 reset-names = "bus", 5002 "xo", 5003 "core"; 5004 5005 iommus = <&apps_smmu 0x1940 0>, 5006 <&apps_smmu 0x1947 0>; 5007 5008 dma-coherent; 5009 5010 /* 5011 * IRIS firmware is signed by vendors, only 5012 * enable in boards where the proper signed firmware 5013 * is available. 5014 */ 5015 status = "disabled"; 5016 5017 iris_opp_table: opp-table { 5018 compatible = "operating-points-v2"; 5019 5020 opp-196000000 { 5021 opp-hz = /bits/ 64 <196000000>; 5022 required-opps = <&rpmhpd_opp_low_svs_d1>, 5023 <&rpmhpd_opp_low_svs_d1>; 5024 }; 5025 5026 opp-300000000 { 5027 opp-hz = /bits/ 64 <300000000>; 5028 required-opps = <&rpmhpd_opp_low_svs>, 5029 <&rpmhpd_opp_low_svs>; 5030 }; 5031 5032 opp-380000000 { 5033 opp-hz = /bits/ 64 <380000000>; 5034 required-opps = <&rpmhpd_opp_svs>, 5035 <&rpmhpd_opp_svs>; 5036 }; 5037 5038 opp-435000000 { 5039 opp-hz = /bits/ 64 <435000000>; 5040 required-opps = <&rpmhpd_opp_svs_l1>, 5041 <&rpmhpd_opp_svs_l1>; 5042 }; 5043 5044 opp-480000000 { 5045 opp-hz = /bits/ 64 <480000000>; 5046 required-opps = <&rpmhpd_opp_nom>, 5047 <&rpmhpd_opp_nom>; 5048 }; 5049 5050 opp-533333334 { 5051 opp-hz = /bits/ 64 <533333334>; 5052 required-opps = <&rpmhpd_opp_turbo>, 5053 <&rpmhpd_opp_turbo>; 5054 }; 5055 }; 5056 }; 5057 5058 videocc: clock-controller@aaf0000 { 5059 compatible = "qcom,sm8650-videocc"; 5060 reg = <0 0x0aaf0000 0 0x10000>; 5061 clocks = <&bi_tcxo_div2>, 5062 <&gcc GCC_VIDEO_AHB_CLK>; 5063 power-domains = <&rpmhpd RPMHPD_MMCX>; 5064 #clock-cells = <1>; 5065 #reset-cells = <1>; 5066 #power-domain-cells = <1>; 5067 }; 5068 5069 cci0: cci@ac15000 { 5070 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5071 reg = <0 0x0ac15000 0 0x1000>; 5072 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 5073 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5074 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5075 <&camcc CAM_CC_CPAS_AHB_CLK>, 5076 <&camcc CAM_CC_CCI_0_CLK>; 5077 clock-names = "camnoc_axi", 5078 "cpas_ahb", 5079 "cci"; 5080 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5081 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5082 pinctrl-names = "default", "sleep"; 5083 status = "disabled"; 5084 #address-cells = <1>; 5085 #size-cells = <0>; 5086 5087 cci0_i2c0: i2c-bus@0 { 5088 reg = <0>; 5089 clock-frequency = <1000000>; 5090 #address-cells = <1>; 5091 #size-cells = <0>; 5092 }; 5093 5094 cci0_i2c1: i2c-bus@1 { 5095 reg = <1>; 5096 clock-frequency = <1000000>; 5097 #address-cells = <1>; 5098 #size-cells = <0>; 5099 }; 5100 }; 5101 5102 cci1: cci@ac16000 { 5103 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5104 reg = <0 0x0ac16000 0 0x1000>; 5105 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 5106 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5107 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5108 <&camcc CAM_CC_CPAS_AHB_CLK>, 5109 <&camcc CAM_CC_CCI_1_CLK>; 5110 clock-names = "camnoc_axi", 5111 "cpas_ahb", 5112 "cci"; 5113 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5114 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5115 pinctrl-names = "default", "sleep"; 5116 status = "disabled"; 5117 #address-cells = <1>; 5118 #size-cells = <0>; 5119 5120 cci1_i2c0: i2c-bus@0 { 5121 reg = <0>; 5122 clock-frequency = <1000000>; 5123 #address-cells = <1>; 5124 #size-cells = <0>; 5125 }; 5126 5127 cci1_i2c1: i2c-bus@1 { 5128 reg = <1>; 5129 clock-frequency = <1000000>; 5130 #address-cells = <1>; 5131 #size-cells = <0>; 5132 }; 5133 }; 5134 5135 cci2: cci@ac17000 { 5136 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5137 reg = <0 0x0ac17000 0 0x1000>; 5138 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; 5139 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5140 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5141 <&camcc CAM_CC_CPAS_AHB_CLK>, 5142 <&camcc CAM_CC_CCI_2_CLK>; 5143 clock-names = "camnoc_axi", 5144 "cpas_ahb", 5145 "cci"; 5146 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5147 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5148 pinctrl-names = "default", "sleep"; 5149 status = "disabled"; 5150 #address-cells = <1>; 5151 #size-cells = <0>; 5152 5153 cci2_i2c0: i2c-bus@0 { 5154 reg = <0>; 5155 clock-frequency = <1000000>; 5156 #address-cells = <1>; 5157 #size-cells = <0>; 5158 }; 5159 5160 cci2_i2c1: i2c-bus@1 { 5161 reg = <1>; 5162 clock-frequency = <1000000>; 5163 #address-cells = <1>; 5164 #size-cells = <0>; 5165 }; 5166 }; 5167 5168 camcc: clock-controller@ade0000 { 5169 compatible = "qcom,sm8650-camcc"; 5170 reg = <0 0x0ade0000 0 0x20000>; 5171 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5172 <&bi_tcxo_div2>, 5173 <&bi_tcxo_ao_div2>, 5174 <&sleep_clk>; 5175 power-domains = <&rpmhpd RPMHPD_MMCX>; 5176 #clock-cells = <1>; 5177 #reset-cells = <1>; 5178 #power-domain-cells = <1>; 5179 }; 5180 5181 mdss: display-subsystem@ae00000 { 5182 compatible = "qcom,sm8650-mdss"; 5183 reg = <0 0x0ae00000 0 0x1000>; 5184 reg-names = "mdss"; 5185 5186 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 5187 5188 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5189 <&gcc GCC_DISP_HF_AXI_CLK>, 5190 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5191 5192 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5193 5194 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5195 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5196 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5197 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5198 interconnect-names = "mdp0-mem", 5199 "cpu-cfg"; 5200 5201 power-domains = <&dispcc MDSS_GDSC>; 5202 5203 iommus = <&apps_smmu 0x1c00 0x2>; 5204 5205 interrupt-controller; 5206 #interrupt-cells = <1>; 5207 5208 #address-cells = <2>; 5209 #size-cells = <2>; 5210 ranges; 5211 5212 status = "disabled"; 5213 5214 mdss_mdp: display-controller@ae01000 { 5215 compatible = "qcom,sm8650-dpu"; 5216 reg = <0 0x0ae01000 0 0x8f000>, 5217 <0 0x0aeb0000 0 0x3000>; 5218 reg-names = "mdp", 5219 "vbif"; 5220 5221 interrupts-extended = <&mdss 0>; 5222 5223 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5224 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5225 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5226 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5227 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5228 clock-names = "nrt_bus", 5229 "iface", 5230 "lut", 5231 "core", 5232 "vsync"; 5233 5234 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5235 assigned-clock-rates = <19200000>; 5236 5237 operating-points-v2 = <&mdp_opp_table>; 5238 5239 power-domains = <&rpmhpd RPMHPD_MMCX>; 5240 5241 ports { 5242 #address-cells = <1>; 5243 #size-cells = <0>; 5244 5245 port@0 { 5246 reg = <0>; 5247 5248 dpu_intf1_out: endpoint { 5249 remote-endpoint = <&mdss_dsi0_in>; 5250 }; 5251 }; 5252 5253 port@1 { 5254 reg = <1>; 5255 5256 dpu_intf2_out: endpoint { 5257 remote-endpoint = <&mdss_dsi1_in>; 5258 }; 5259 }; 5260 5261 port@2 { 5262 reg = <2>; 5263 5264 dpu_intf0_out: endpoint { 5265 remote-endpoint = <&mdss_dp0_in>; 5266 }; 5267 }; 5268 }; 5269 5270 mdp_opp_table: opp-table { 5271 compatible = "operating-points-v2"; 5272 5273 opp-200000000 { 5274 opp-hz = /bits/ 64 <200000000>; 5275 required-opps = <&rpmhpd_opp_low_svs>; 5276 }; 5277 5278 opp-325000000 { 5279 opp-hz = /bits/ 64 <325000000>; 5280 required-opps = <&rpmhpd_opp_svs>; 5281 }; 5282 5283 opp-375000000 { 5284 opp-hz = /bits/ 64 <375000000>; 5285 required-opps = <&rpmhpd_opp_svs_l1>; 5286 }; 5287 5288 opp-514000000 { 5289 opp-hz = /bits/ 64 <514000000>; 5290 required-opps = <&rpmhpd_opp_nom>; 5291 }; 5292 }; 5293 }; 5294 5295 mdss_dsi0: dsi@ae94000 { 5296 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5297 reg = <0 0x0ae94000 0 0x400>; 5298 reg-names = "dsi_ctrl"; 5299 5300 interrupts-extended = <&mdss 4>; 5301 5302 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 5303 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 5304 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 5305 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 5306 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5307 <&gcc GCC_DISP_HF_AXI_CLK>; 5308 clock-names = "byte", 5309 "byte_intf", 5310 "pixel", 5311 "core", 5312 "iface", 5313 "bus"; 5314 5315 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 5316 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 5317 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5318 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 5319 5320 operating-points-v2 = <&mdss_dsi_opp_table>; 5321 5322 power-domains = <&rpmhpd RPMHPD_MMCX>; 5323 5324 phys = <&mdss_dsi0_phy>; 5325 phy-names = "dsi"; 5326 5327 #address-cells = <1>; 5328 #size-cells = <0>; 5329 5330 status = "disabled"; 5331 5332 ports { 5333 #address-cells = <1>; 5334 #size-cells = <0>; 5335 5336 port@0 { 5337 reg = <0>; 5338 5339 mdss_dsi0_in: endpoint { 5340 remote-endpoint = <&dpu_intf1_out>; 5341 }; 5342 }; 5343 5344 port@1 { 5345 reg = <1>; 5346 5347 mdss_dsi0_out: endpoint { 5348 }; 5349 }; 5350 }; 5351 5352 mdss_dsi_opp_table: opp-table { 5353 compatible = "operating-points-v2"; 5354 5355 opp-187500000 { 5356 opp-hz = /bits/ 64 <187500000>; 5357 required-opps = <&rpmhpd_opp_low_svs>; 5358 }; 5359 5360 opp-300000000 { 5361 opp-hz = /bits/ 64 <300000000>; 5362 required-opps = <&rpmhpd_opp_svs>; 5363 }; 5364 5365 opp-358000000 { 5366 opp-hz = /bits/ 64 <358000000>; 5367 required-opps = <&rpmhpd_opp_svs_l1>; 5368 }; 5369 }; 5370 }; 5371 5372 mdss_dsi0_phy: phy@ae95000 { 5373 compatible = "qcom,sm8650-dsi-phy-4nm"; 5374 reg = <0 0x0ae95000 0 0x200>, 5375 <0 0x0ae95200 0 0x280>, 5376 <0 0x0ae95500 0 0x400>; 5377 reg-names = "dsi_phy", 5378 "dsi_phy_lane", 5379 "dsi_pll"; 5380 5381 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5382 <&rpmhcc RPMH_CXO_CLK>; 5383 clock-names = "iface", 5384 "ref"; 5385 5386 #clock-cells = <1>; 5387 #phy-cells = <0>; 5388 5389 status = "disabled"; 5390 }; 5391 5392 mdss_dsi1: dsi@ae96000 { 5393 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5394 reg = <0 0x0ae96000 0 0x400>; 5395 reg-names = "dsi_ctrl"; 5396 5397 interrupts-extended = <&mdss 5>; 5398 5399 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 5400 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 5401 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 5402 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 5403 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5404 <&gcc GCC_DISP_HF_AXI_CLK>; 5405 clock-names = "byte", 5406 "byte_intf", 5407 "pixel", 5408 "core", 5409 "iface", 5410 "bus"; 5411 5412 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 5413 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 5414 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5415 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 5416 5417 operating-points-v2 = <&mdss_dsi_opp_table>; 5418 5419 power-domains = <&rpmhpd RPMHPD_MMCX>; 5420 5421 phys = <&mdss_dsi1_phy>; 5422 phy-names = "dsi"; 5423 5424 #address-cells = <1>; 5425 #size-cells = <0>; 5426 5427 status = "disabled"; 5428 5429 ports { 5430 #address-cells = <1>; 5431 #size-cells = <0>; 5432 5433 port@0 { 5434 reg = <0>; 5435 5436 mdss_dsi1_in: endpoint { 5437 remote-endpoint = <&dpu_intf2_out>; 5438 }; 5439 }; 5440 5441 port@1 { 5442 reg = <1>; 5443 5444 mdss_dsi1_out: endpoint { 5445 }; 5446 }; 5447 }; 5448 }; 5449 5450 mdss_dsi1_phy: phy@ae97000 { 5451 compatible = "qcom,sm8650-dsi-phy-4nm"; 5452 reg = <0 0x0ae97000 0 0x200>, 5453 <0 0x0ae97200 0 0x280>, 5454 <0 0x0ae97500 0 0x400>; 5455 reg-names = "dsi_phy", 5456 "dsi_phy_lane", 5457 "dsi_pll"; 5458 5459 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5460 <&rpmhcc RPMH_CXO_CLK>; 5461 clock-names = "iface", 5462 "ref"; 5463 5464 #clock-cells = <1>; 5465 #phy-cells = <0>; 5466 5467 status = "disabled"; 5468 }; 5469 5470 mdss_dp0: displayport-controller@af54000 { 5471 compatible = "qcom,sm8650-dp"; 5472 reg = <0 0xaf54000 0 0x104>, 5473 <0 0xaf54200 0 0xc0>, 5474 <0 0xaf55000 0 0x770>, 5475 <0 0xaf56000 0 0x9c>, 5476 <0 0xaf57000 0 0x9c>; 5477 5478 interrupts-extended = <&mdss 12>; 5479 5480 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5481 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5482 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5483 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5484 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 5485 clock-names = "core_iface", 5486 "core_aux", 5487 "ctrl_link", 5488 "ctrl_link_iface", 5489 "stream_pixel"; 5490 5491 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5492 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 5493 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5494 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5495 5496 operating-points-v2 = <&dp_opp_table>; 5497 5498 power-domains = <&rpmhpd RPMHPD_MMCX>; 5499 5500 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 5501 phy-names = "dp"; 5502 5503 #sound-dai-cells = <0>; 5504 5505 status = "disabled"; 5506 5507 dp_opp_table: opp-table { 5508 compatible = "operating-points-v2"; 5509 5510 opp-162000000 { 5511 opp-hz = /bits/ 64 <162000000>; 5512 required-opps = <&rpmhpd_opp_low_svs_d1>; 5513 }; 5514 5515 opp-270000000 { 5516 opp-hz = /bits/ 64 <270000000>; 5517 required-opps = <&rpmhpd_opp_low_svs>; 5518 }; 5519 5520 opp-540000000 { 5521 opp-hz = /bits/ 64 <540000000>; 5522 required-opps = <&rpmhpd_opp_svs_l1>; 5523 }; 5524 5525 opp-810000000 { 5526 opp-hz = /bits/ 64 <810000000>; 5527 required-opps = <&rpmhpd_opp_nom>; 5528 }; 5529 }; 5530 5531 ports { 5532 #address-cells = <1>; 5533 #size-cells = <0>; 5534 5535 port@0 { 5536 reg = <0>; 5537 5538 mdss_dp0_in: endpoint { 5539 remote-endpoint = <&dpu_intf0_out>; 5540 }; 5541 }; 5542 5543 port@1 { 5544 reg = <1>; 5545 5546 mdss_dp0_out: endpoint { 5547 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5548 }; 5549 }; 5550 }; 5551 }; 5552 }; 5553 5554 dispcc: clock-controller@af00000 { 5555 compatible = "qcom,sm8650-dispcc"; 5556 reg = <0 0x0af00000 0 0x20000>; 5557 5558 clocks = <&bi_tcxo_div2>, 5559 <&bi_tcxo_ao_div2>, 5560 <&gcc GCC_DISP_AHB_CLK>, 5561 <&sleep_clk>, 5562 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5563 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5564 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5565 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5566 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5567 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5568 <0>, /* dp1 */ 5569 <0>, 5570 <0>, /* dp2 */ 5571 <0>, 5572 <0>, /* dp3 */ 5573 <0>; 5574 5575 power-domains = <&rpmhpd RPMHPD_MMCX>; 5576 required-opps = <&rpmhpd_opp_low_svs>; 5577 5578 #clock-cells = <1>; 5579 #reset-cells = <1>; 5580 #power-domain-cells = <1>; 5581 }; 5582 5583 usb_1_hsphy: phy@88e3000 { 5584 compatible = "qcom,sm8650-snps-eusb2-phy", 5585 "qcom,sm8550-snps-eusb2-phy"; 5586 reg = <0 0x088e3000 0 0x154>; 5587 5588 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 5589 clock-names = "ref"; 5590 5591 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 5592 5593 #phy-cells = <0>; 5594 5595 status = "disabled"; 5596 }; 5597 5598 usb_dp_qmpphy: phy@88e8000 { 5599 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 5600 reg = <0 0x088e8000 0 0x3000>; 5601 5602 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 5603 <&rpmhcc RPMH_CXO_CLK>, 5604 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 5605 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 5606 clock-names = "aux", 5607 "ref", 5608 "com_aux", 5609 "usb3_pipe"; 5610 5611 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 5612 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 5613 reset-names = "phy", 5614 "common"; 5615 5616 power-domains = <&gcc USB3_PHY_GDSC>; 5617 5618 #clock-cells = <1>; 5619 #phy-cells = <1>; 5620 5621 orientation-switch; 5622 5623 status = "disabled"; 5624 5625 ports { 5626 #address-cells = <1>; 5627 #size-cells = <0>; 5628 5629 port@0 { 5630 reg = <0>; 5631 5632 usb_dp_qmpphy_out: endpoint { 5633 }; 5634 }; 5635 5636 port@1 { 5637 reg = <1>; 5638 5639 usb_dp_qmpphy_usb_ss_in: endpoint { 5640 remote-endpoint = <&usb_1_dwc3_ss>; 5641 }; 5642 }; 5643 5644 port@2 { 5645 reg = <2>; 5646 5647 usb_dp_qmpphy_dp_in: endpoint { 5648 remote-endpoint = <&mdss_dp0_out>; 5649 }; 5650 }; 5651 }; 5652 }; 5653 5654 usb_1: usb@a6f8800 { 5655 compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; 5656 reg = <0 0x0a6f8800 0 0x400>; 5657 5658 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 5659 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 5660 <&pdc 14 IRQ_TYPE_EDGE_RISING>, 5661 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 5662 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5663 interrupt-names = "pwr_event", 5664 "hs_phy_irq", 5665 "dp_hs_phy_irq", 5666 "dm_hs_phy_irq", 5667 "ss_phy_irq"; 5668 5669 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5670 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5671 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5672 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5673 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5674 <&tcsr TCSR_USB3_CLKREF_EN>; 5675 clock-names = "cfg_noc", 5676 "core", 5677 "iface", 5678 "sleep", 5679 "mock_utmi", 5680 "xo"; 5681 5682 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5683 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5684 assigned-clock-rates = <19200000>, <200000000>; 5685 5686 resets = <&gcc GCC_USB30_PRIM_BCR>; 5687 5688 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5689 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5690 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5691 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 5692 interconnect-names = "usb-ddr", 5693 "apps-usb"; 5694 5695 power-domains = <&gcc USB30_PRIM_GDSC>; 5696 required-opps = <&rpmhpd_opp_nom>; 5697 5698 #address-cells = <2>; 5699 #size-cells = <2>; 5700 ranges; 5701 5702 status = "disabled"; 5703 5704 usb_1_dwc3: usb@a600000 { 5705 compatible = "snps,dwc3"; 5706 reg = <0 0x0a600000 0 0xcd00>; 5707 5708 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>; 5709 5710 iommus = <&apps_smmu 0x40 0>; 5711 5712 phys = <&usb_1_hsphy>, 5713 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 5714 phy-names = "usb2-phy", 5715 "usb3-phy"; 5716 5717 snps,hird-threshold = /bits/ 8 <0x0>; 5718 snps,usb2-gadget-lpm-disable; 5719 snps,dis_u2_susphy_quirk; 5720 snps,dis_enblslpm_quirk; 5721 snps,dis-u1-entry-quirk; 5722 snps,dis-u2-entry-quirk; 5723 snps,is-utmi-l1-suspend; 5724 snps,usb3_lpm_capable; 5725 snps,usb2-lpm-disable; 5726 snps,has-lpm-erratum; 5727 tx-fifo-resize; 5728 5729 dma-coherent; 5730 5731 ports { 5732 #address-cells = <1>; 5733 #size-cells = <0>; 5734 5735 port@0 { 5736 reg = <0>; 5737 5738 usb_1_dwc3_hs: endpoint { 5739 }; 5740 }; 5741 5742 port@1 { 5743 reg = <1>; 5744 5745 usb_1_dwc3_ss: endpoint { 5746 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 5747 }; 5748 }; 5749 }; 5750 }; 5751 }; 5752 5753 pdc: interrupt-controller@b220000 { 5754 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 5755 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5756 5757 interrupt-parent = <&intc>; 5758 5759 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 5760 <125 63 1>, <126 716 12>, 5761 <138 251 5>, <143 244 4>; 5762 5763 #interrupt-cells = <2>; 5764 interrupt-controller; 5765 }; 5766 5767 tsens0: thermal-sensor@c228000 { 5768 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5769 reg = <0 0x0c228000 0 0x1000>, /* TM */ 5770 <0 0x0c222000 0 0x1000>; /* SROT */ 5771 5772 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 5773 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 5774 interrupt-names = "uplow", 5775 "critical"; 5776 5777 #qcom,sensors = <15>; 5778 5779 #thermal-sensor-cells = <1>; 5780 }; 5781 5782 tsens1: thermal-sensor@c229000 { 5783 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5784 reg = <0 0x0c229000 0 0x1000>, /* TM */ 5785 <0 0x0c223000 0 0x1000>; /* SROT */ 5786 5787 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, 5788 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 5789 interrupt-names = "uplow", 5790 "critical"; 5791 5792 #qcom,sensors = <16>; 5793 5794 #thermal-sensor-cells = <1>; 5795 }; 5796 5797 tsens2: thermal-sensor@c22a000 { 5798 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5799 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 5800 <0 0x0c224000 0 0x1000>; /* SROT */ 5801 5802 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, 5803 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 5804 interrupt-names = "uplow", 5805 "critical"; 5806 5807 #qcom,sensors = <13>; 5808 5809 #thermal-sensor-cells = <1>; 5810 }; 5811 5812 aoss_qmp: power-management@c300000 { 5813 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 5814 reg = <0 0x0c300000 0 0x400>; 5815 5816 interrupt-parent = <&ipcc>; 5817 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5818 IRQ_TYPE_EDGE_RISING>; 5819 5820 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5821 5822 #clock-cells = <0>; 5823 }; 5824 5825 sram@c3f0000 { 5826 compatible = "qcom,rpmh-stats"; 5827 reg = <0 0x0c3f0000 0 0x400>; 5828 qcom,qmp = <&aoss_qmp>; 5829 }; 5830 5831 spmi_bus: spmi@c400000 { 5832 compatible = "qcom,spmi-pmic-arb"; 5833 reg = <0 0x0c400000 0 0x3000>, 5834 <0 0x0c500000 0 0x400000>, 5835 <0 0x0c440000 0 0x80000>, 5836 <0 0x0c4c0000 0 0x20000>, 5837 <0 0x0c42d000 0 0x4000>; 5838 reg-names = "core", 5839 "chnls", 5840 "obsrvr", 5841 "intr", 5842 "cnfg"; 5843 5844 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5845 interrupt-names = "periph_irq"; 5846 5847 qcom,ee = <0>; 5848 qcom,channel = <0>; 5849 qcom,bus-id = <0>; 5850 5851 interrupt-controller; 5852 #interrupt-cells = <4>; 5853 5854 #address-cells = <2>; 5855 #size-cells = <0>; 5856 }; 5857 5858 tlmm: pinctrl@f100000 { 5859 compatible = "qcom,sm8650-tlmm"; 5860 reg = <0 0x0f100000 0 0x300000>; 5861 5862 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 5863 5864 gpio-controller; 5865 #gpio-cells = <2>; 5866 5867 interrupt-controller; 5868 #interrupt-cells = <2>; 5869 5870 gpio-ranges = <&tlmm 0 0 211>; 5871 5872 wakeup-parent = <&pdc>; 5873 5874 cci0_0_default: cci0-0-default-state { 5875 sda-pins { 5876 pins = "gpio113"; 5877 function = "cci_i2c_sda"; 5878 drive-strength = <2>; 5879 bias-pull-up = <2200>; 5880 }; 5881 5882 scl-pins { 5883 pins = "gpio114"; 5884 function = "cci_i2c_scl"; 5885 drive-strength = <2>; 5886 bias-pull-up = <2200>; 5887 }; 5888 }; 5889 5890 cci0_0_sleep: cci0-0-sleep-state { 5891 sda-pins { 5892 pins = "gpio113"; 5893 function = "cci_i2c_sda"; 5894 drive-strength = <2>; 5895 bias-pull-down; 5896 }; 5897 5898 scl-pins { 5899 pins = "gpio114"; 5900 function = "cci_i2c_scl"; 5901 drive-strength = <2>; 5902 bias-pull-down; 5903 }; 5904 }; 5905 5906 cci0_1_default: cci0-1-default-state { 5907 sda-pins { 5908 pins = "gpio115"; 5909 function = "cci_i2c_sda"; 5910 drive-strength = <2>; 5911 bias-pull-up = <2200>; 5912 }; 5913 5914 scl-pins { 5915 pins = "gpio116"; 5916 function = "cci_i2c_scl"; 5917 drive-strength = <2>; 5918 bias-pull-up = <2200>; 5919 }; 5920 }; 5921 5922 cci0_1_sleep: cci0-1-sleep-state { 5923 sda-pins { 5924 pins = "gpio115"; 5925 function = "cci_i2c_sda"; 5926 drive-strength = <2>; 5927 bias-pull-down; 5928 }; 5929 5930 scl-pins { 5931 pins = "gpio116"; 5932 function = "cci_i2c_scl"; 5933 drive-strength = <2>; 5934 bias-pull-down; 5935 }; 5936 }; 5937 5938 cci1_0_default: cci1-0-default-state { 5939 sda-pins { 5940 pins = "gpio117"; 5941 function = "cci_i2c_sda"; 5942 drive-strength = <2>; 5943 bias-pull-up = <2200>; 5944 }; 5945 5946 scl-pins { 5947 pins = "gpio118"; 5948 function = "cci_i2c_scl"; 5949 drive-strength = <2>; 5950 bias-pull-up = <2200>; 5951 }; 5952 }; 5953 5954 cci1_0_sleep: cci1-0-sleep-state { 5955 sda-pins { 5956 pins = "gpio117"; 5957 function = "cci_i2c_sda"; 5958 drive-strength = <2>; 5959 bias-pull-down; 5960 }; 5961 5962 scl-pins { 5963 pins = "gpio118"; 5964 function = "cci_i2c_scl"; 5965 drive-strength = <2>; 5966 bias-pull-down; 5967 }; 5968 }; 5969 5970 cci1_1_default: cci1-1-default-state { 5971 sda-pins { 5972 pins = "gpio12"; 5973 function = "cci_i2c_sda"; 5974 drive-strength = <2>; 5975 bias-pull-up = <2200>; 5976 }; 5977 5978 scl-pins { 5979 pins = "gpio13"; 5980 function = "cci_i2c_scl"; 5981 drive-strength = <2>; 5982 bias-pull-up = <2200>; 5983 }; 5984 }; 5985 5986 cci1_1_sleep: cci1-1-sleep-state { 5987 sda-pins { 5988 pins = "gpio12"; 5989 function = "cci_i2c_sda"; 5990 drive-strength = <2>; 5991 bias-pull-down; 5992 }; 5993 5994 scl-pins { 5995 pins = "gpio13"; 5996 function = "cci_i2c_scl"; 5997 drive-strength = <2>; 5998 bias-pull-down; 5999 }; 6000 }; 6001 6002 cci2_0_default: cci2-0-default-state { 6003 sda-pins { 6004 pins = "gpio112"; 6005 function = "cci_i2c_sda"; 6006 drive-strength = <2>; 6007 bias-pull-up = <2200>; 6008 }; 6009 6010 scl-pins { 6011 pins = "gpio153"; 6012 function = "cci_i2c_scl"; 6013 drive-strength = <2>; 6014 bias-pull-up = <2200>; 6015 }; 6016 }; 6017 6018 cci2_0_sleep: cci2-0-sleep-state { 6019 sda-pins { 6020 pins = "gpio112"; 6021 function = "cci_i2c_sda"; 6022 drive-strength = <2>; 6023 bias-pull-down; 6024 }; 6025 6026 scl-pins { 6027 pins = "gpio153"; 6028 function = "cci_i2c_scl"; 6029 drive-strength = <2>; 6030 bias-pull-down; 6031 }; 6032 }; 6033 6034 cci2_1_default: cci2-1-default-state { 6035 sda-pins { 6036 pins = "gpio119"; 6037 function = "cci_i2c_sda"; 6038 drive-strength = <2>; 6039 bias-pull-up = <2200>; 6040 }; 6041 6042 scl-pins { 6043 pins = "gpio120"; 6044 function = "cci_i2c_scl"; 6045 drive-strength = <2>; 6046 bias-pull-up = <2200>; 6047 }; 6048 }; 6049 6050 cci2_1_sleep: cci2-1-sleep-state { 6051 sda-pins { 6052 pins = "gpio119"; 6053 function = "cci_i2c_sda"; 6054 drive-strength = <2>; 6055 bias-pull-down; 6056 }; 6057 6058 scl-pins { 6059 pins = "gpio120"; 6060 function = "cci_i2c_scl"; 6061 drive-strength = <2>; 6062 bias-pull-down; 6063 }; 6064 }; 6065 6066 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 6067 /* SDA, SCL */ 6068 pins = "gpio64", "gpio65"; 6069 function = "i2chub0_se0"; 6070 drive-strength = <2>; 6071 bias-pull-up; 6072 }; 6073 6074 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 6075 /* SDA, SCL */ 6076 pins = "gpio66", "gpio67"; 6077 function = "i2chub0_se1"; 6078 drive-strength = <2>; 6079 bias-pull-up; 6080 }; 6081 6082 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 6083 /* SDA, SCL */ 6084 pins = "gpio68", "gpio69"; 6085 function = "i2chub0_se2"; 6086 drive-strength = <2>; 6087 bias-pull-up; 6088 }; 6089 6090 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 6091 /* SDA, SCL */ 6092 pins = "gpio70", "gpio71"; 6093 function = "i2chub0_se3"; 6094 drive-strength = <2>; 6095 bias-pull-up; 6096 }; 6097 6098 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 6099 /* SDA, SCL */ 6100 pins = "gpio72", "gpio73"; 6101 function = "i2chub0_se4"; 6102 drive-strength = <2>; 6103 bias-pull-up; 6104 }; 6105 6106 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 6107 /* SDA, SCL */ 6108 pins = "gpio74", "gpio75"; 6109 function = "i2chub0_se5"; 6110 drive-strength = <2>; 6111 bias-pull-up; 6112 }; 6113 6114 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 6115 /* SDA, SCL */ 6116 pins = "gpio76", "gpio77"; 6117 function = "i2chub0_se6"; 6118 drive-strength = <2>; 6119 bias-pull-up; 6120 }; 6121 6122 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 6123 /* SDA, SCL */ 6124 pins = "gpio78", "gpio79"; 6125 function = "i2chub0_se7"; 6126 drive-strength = <2>; 6127 bias-pull-up; 6128 }; 6129 6130 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 6131 /* SDA, SCL */ 6132 pins = "gpio206", "gpio207"; 6133 function = "i2chub0_se8"; 6134 drive-strength = <2>; 6135 bias-pull-up; 6136 }; 6137 6138 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 6139 /* SDA, SCL */ 6140 pins = "gpio80", "gpio81"; 6141 function = "i2chub0_se9"; 6142 drive-strength = <2>; 6143 bias-pull-up; 6144 }; 6145 6146 pcie0_default_state: pcie0-default-state { 6147 perst-pins { 6148 pins = "gpio94"; 6149 function = "gpio"; 6150 drive-strength = <2>; 6151 bias-pull-down; 6152 }; 6153 6154 clkreq-pins { 6155 pins = "gpio95"; 6156 function = "pcie0_clk_req_n"; 6157 drive-strength = <2>; 6158 bias-pull-up; 6159 }; 6160 6161 wake-pins { 6162 pins = "gpio96"; 6163 function = "gpio"; 6164 drive-strength = <2>; 6165 bias-pull-up; 6166 }; 6167 }; 6168 6169 pcie1_default_state: pcie1-default-state { 6170 perst-pins { 6171 pins = "gpio97"; 6172 function = "gpio"; 6173 drive-strength = <2>; 6174 bias-pull-down; 6175 }; 6176 6177 clkreq-pins { 6178 pins = "gpio98"; 6179 function = "pcie1_clk_req_n"; 6180 drive-strength = <2>; 6181 bias-pull-up; 6182 }; 6183 6184 wake-pins { 6185 pins = "gpio99"; 6186 function = "gpio"; 6187 drive-strength = <2>; 6188 bias-pull-up; 6189 }; 6190 }; 6191 6192 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6193 /* SDA, SCL */ 6194 pins = "gpio32", "gpio33"; 6195 function = "qup1_se0"; 6196 drive-strength = <2>; 6197 bias-pull-up; 6198 }; 6199 6200 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6201 /* SDA, SCL */ 6202 pins = "gpio36", "gpio37"; 6203 function = "qup1_se1"; 6204 drive-strength = <2>; 6205 bias-pull-up; 6206 }; 6207 6208 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6209 /* SDA, SCL */ 6210 pins = "gpio40", "gpio41"; 6211 function = "qup1_se2"; 6212 drive-strength = <2>; 6213 bias-pull-up; 6214 }; 6215 6216 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6217 /* SDA, SCL */ 6218 pins = "gpio44", "gpio45"; 6219 function = "qup1_se3"; 6220 drive-strength = <2>; 6221 bias-pull-up; 6222 }; 6223 6224 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6225 /* SDA, SCL */ 6226 pins = "gpio48", "gpio49"; 6227 function = "qup1_se4"; 6228 drive-strength = <2>; 6229 bias-pull-up; 6230 }; 6231 6232 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6233 /* SDA, SCL */ 6234 pins = "gpio52", "gpio53"; 6235 function = "qup1_se5"; 6236 drive-strength = <2>; 6237 bias-pull-up; 6238 }; 6239 6240 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6241 /* SDA, SCL */ 6242 pins = "gpio56", "gpio57"; 6243 function = "qup1_se6"; 6244 drive-strength = <2>; 6245 bias-pull-up; 6246 }; 6247 6248 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6249 /* SDA, SCL */ 6250 pins = "gpio60", "gpio61"; 6251 function = "qup1_se7"; 6252 drive-strength = <2>; 6253 bias-pull-up; 6254 }; 6255 6256 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6257 /* SDA, SCL */ 6258 pins = "gpio0", "gpio1"; 6259 function = "qup2_se0"; 6260 drive-strength = <2>; 6261 bias-pull-up; 6262 }; 6263 6264 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6265 /* SDA, SCL */ 6266 pins = "gpio4", "gpio5"; 6267 function = "qup2_se1"; 6268 drive-strength = <2>; 6269 bias-pull-up; 6270 }; 6271 6272 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6273 /* SDA, SCL */ 6274 pins = "gpio8", "gpio9"; 6275 function = "qup2_se2"; 6276 drive-strength = <2>; 6277 bias-pull-up; 6278 }; 6279 6280 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6281 /* SDA, SCL */ 6282 pins = "gpio12", "gpio13"; 6283 function = "qup2_se3"; 6284 drive-strength = <2>; 6285 bias-pull-up; 6286 }; 6287 6288 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6289 /* SDA, SCL */ 6290 pins = "gpio16", "gpio17"; 6291 function = "qup2_se4"; 6292 drive-strength = <2>; 6293 bias-pull-up; 6294 }; 6295 6296 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6297 /* SDA, SCL */ 6298 pins = "gpio20", "gpio21"; 6299 function = "qup2_se5"; 6300 drive-strength = <2>; 6301 bias-pull-up; 6302 }; 6303 6304 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6305 /* SDA, SCL */ 6306 pins = "gpio24", "gpio25"; 6307 function = "qup2_se6"; 6308 drive-strength = <2>; 6309 bias-pull-up; 6310 }; 6311 6312 qup_spi0_cs: qup-spi0-cs-state { 6313 pins = "gpio35"; 6314 function = "qup1_se0"; 6315 drive-strength = <6>; 6316 bias-disable; 6317 }; 6318 6319 qup_spi0_data_clk: qup-spi0-data-clk-state { 6320 /* MISO, MOSI, CLK */ 6321 pins = "gpio32", "gpio33", "gpio34"; 6322 function = "qup1_se0"; 6323 drive-strength = <6>; 6324 bias-disable; 6325 }; 6326 6327 qup_spi1_cs: qup-spi1-cs-state { 6328 pins = "gpio39"; 6329 function = "qup1_se1"; 6330 drive-strength = <6>; 6331 bias-disable; 6332 }; 6333 6334 qup_spi1_data_clk: qup-spi1-data-clk-state { 6335 /* MISO, MOSI, CLK */ 6336 pins = "gpio36", "gpio37", "gpio38"; 6337 function = "qup1_se1"; 6338 drive-strength = <6>; 6339 bias-disable; 6340 }; 6341 6342 qup_spi2_cs: qup-spi2-cs-state { 6343 pins = "gpio43"; 6344 function = "qup1_se2"; 6345 drive-strength = <6>; 6346 bias-disable; 6347 }; 6348 6349 qup_spi2_data_clk: qup-spi2-data-clk-state { 6350 /* MISO, MOSI, CLK */ 6351 pins = "gpio40", "gpio41", "gpio42"; 6352 function = "qup1_se2"; 6353 drive-strength = <6>; 6354 bias-disable; 6355 }; 6356 6357 qup_spi3_cs: qup-spi3-cs-state { 6358 pins = "gpio47"; 6359 function = "qup1_se3"; 6360 drive-strength = <6>; 6361 bias-disable; 6362 }; 6363 6364 qup_spi3_data_clk: qup-spi3-data-clk-state { 6365 /* MISO, MOSI, CLK */ 6366 pins = "gpio44", "gpio45", "gpio46"; 6367 function = "qup1_se3"; 6368 drive-strength = <6>; 6369 bias-disable; 6370 }; 6371 6372 qup_spi4_cs: qup-spi4-cs-state { 6373 pins = "gpio51"; 6374 function = "qup1_se4"; 6375 drive-strength = <6>; 6376 bias-disable; 6377 }; 6378 6379 qup_spi4_data_clk: qup-spi4-data-clk-state { 6380 /* MISO, MOSI, CLK */ 6381 pins = "gpio48", "gpio49", "gpio50"; 6382 function = "qup1_se4"; 6383 drive-strength = <6>; 6384 bias-disable; 6385 }; 6386 6387 qup_spi5_cs: qup-spi5-cs-state { 6388 pins = "gpio55"; 6389 function = "qup1_se5"; 6390 drive-strength = <6>; 6391 bias-disable; 6392 }; 6393 6394 qup_spi5_data_clk: qup-spi5-data-clk-state { 6395 /* MISO, MOSI, CLK */ 6396 pins = "gpio52", "gpio53", "gpio54"; 6397 function = "qup1_se5"; 6398 drive-strength = <6>; 6399 bias-disable; 6400 }; 6401 6402 qup_spi6_cs: qup-spi6-cs-state { 6403 pins = "gpio59"; 6404 function = "qup1_se6"; 6405 drive-strength = <6>; 6406 bias-disable; 6407 }; 6408 6409 qup_spi6_data_clk: qup-spi6-data-clk-state { 6410 /* MISO, MOSI, CLK */ 6411 pins = "gpio56", "gpio57", "gpio58"; 6412 function = "qup1_se6"; 6413 drive-strength = <6>; 6414 bias-disable; 6415 }; 6416 6417 qup_spi7_cs: qup-spi7-cs-state { 6418 pins = "gpio63"; 6419 function = "qup1_se7"; 6420 drive-strength = <6>; 6421 bias-disable; 6422 }; 6423 6424 qup_spi7_data_clk: qup-spi7-data-clk-state { 6425 /* MISO, MOSI, CLK */ 6426 pins = "gpio60", "gpio61", "gpio62"; 6427 function = "qup1_se7"; 6428 drive-strength = <6>; 6429 bias-disable; 6430 }; 6431 6432 qup_spi8_cs: qup-spi8-cs-state { 6433 pins = "gpio3"; 6434 function = "qup2_se0"; 6435 drive-strength = <6>; 6436 bias-disable; 6437 }; 6438 6439 qup_spi8_data_clk: qup-spi8-data-clk-state { 6440 /* MISO, MOSI, CLK */ 6441 pins = "gpio0", "gpio1", "gpio2"; 6442 function = "qup2_se0"; 6443 drive-strength = <6>; 6444 bias-disable; 6445 }; 6446 6447 qup_spi9_cs: qup-spi9-cs-state { 6448 pins = "gpio7"; 6449 function = "qup2_se1"; 6450 drive-strength = <6>; 6451 bias-disable; 6452 }; 6453 6454 qup_spi9_data_clk: qup-spi9-data-clk-state { 6455 /* MISO, MOSI, CLK */ 6456 pins = "gpio4", "gpio5", "gpio6"; 6457 function = "qup2_se1"; 6458 drive-strength = <6>; 6459 bias-disable; 6460 }; 6461 6462 qup_spi10_cs: qup-spi10-cs-state { 6463 pins = "gpio11"; 6464 function = "qup2_se2"; 6465 drive-strength = <6>; 6466 bias-disable; 6467 }; 6468 6469 qup_spi10_data_clk: qup-spi10-data-clk-state { 6470 /* MISO, MOSI, CLK */ 6471 pins = "gpio8", "gpio9", "gpio10"; 6472 function = "qup2_se2"; 6473 drive-strength = <6>; 6474 bias-disable; 6475 }; 6476 6477 qup_spi11_cs: qup-spi11-cs-state { 6478 pins = "gpio15"; 6479 function = "qup2_se3"; 6480 drive-strength = <6>; 6481 bias-disable; 6482 }; 6483 6484 qup_spi11_data_clk: qup-spi11-data-clk-state { 6485 /* MISO, MOSI, CLK */ 6486 pins = "gpio12", "gpio13", "gpio14"; 6487 function = "qup2_se3"; 6488 drive-strength = <6>; 6489 bias-disable; 6490 }; 6491 6492 qup_spi12_cs: qup-spi12-cs-state { 6493 pins = "gpio19"; 6494 function = "qup2_se4"; 6495 drive-strength = <6>; 6496 bias-disable; 6497 }; 6498 6499 qup_spi12_data_clk: qup-spi12-data-clk-state { 6500 /* MISO, MOSI, CLK */ 6501 pins = "gpio16", "gpio17", "gpio18"; 6502 function = "qup2_se4"; 6503 drive-strength = <6>; 6504 bias-disable; 6505 }; 6506 6507 qup_spi13_cs: qup-spi13-cs-state { 6508 pins = "gpio23"; 6509 function = "qup2_se5"; 6510 drive-strength = <6>; 6511 bias-disable; 6512 }; 6513 6514 qup_spi13_data_clk: qup-spi13-data-clk-state { 6515 /* MISO, MOSI, CLK */ 6516 pins = "gpio20", "gpio21", "gpio22"; 6517 function = "qup2_se5"; 6518 drive-strength = <6>; 6519 bias-disable; 6520 }; 6521 6522 qup_spi14_cs: qup-spi14-cs-state { 6523 pins = "gpio27"; 6524 function = "qup2_se6"; 6525 drive-strength = <6>; 6526 bias-disable; 6527 }; 6528 6529 qup_spi14_data_clk: qup-spi14-data-clk-state { 6530 /* MISO, MOSI, CLK */ 6531 pins = "gpio24", "gpio25", "gpio26"; 6532 function = "qup2_se6"; 6533 drive-strength = <6>; 6534 bias-disable; 6535 }; 6536 6537 qup_uart14_default: qup-uart14-default-state { 6538 /* TX, RX */ 6539 pins = "gpio26", "gpio27"; 6540 function = "qup2_se6"; 6541 drive-strength = <2>; 6542 bias-pull-up; 6543 }; 6544 6545 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 6546 /* CTS, RTS */ 6547 pins = "gpio24", "gpio25"; 6548 function = "qup2_se6"; 6549 drive-strength = <2>; 6550 bias-pull-down; 6551 }; 6552 6553 qup_uart15_default: qup-uart15-default-state { 6554 /* TX, RX */ 6555 pins = "gpio30", "gpio31"; 6556 function = "qup2_se7"; 6557 drive-strength = <2>; 6558 bias-disable; 6559 }; 6560 6561 sdc2_sleep: sdc2-sleep-state { 6562 clk-pins { 6563 pins = "sdc2_clk"; 6564 drive-strength = <2>; 6565 bias-disable; 6566 }; 6567 6568 cmd-pins { 6569 pins = "sdc2_cmd"; 6570 drive-strength = <2>; 6571 bias-pull-up; 6572 }; 6573 6574 data-pins { 6575 pins = "sdc2_data"; 6576 drive-strength = <2>; 6577 bias-pull-up; 6578 }; 6579 }; 6580 6581 sdc2_default: sdc2-default-state { 6582 clk-pins { 6583 pins = "sdc2_clk"; 6584 drive-strength = <16>; 6585 bias-disable; 6586 }; 6587 6588 cmd-pins { 6589 pins = "sdc2_cmd"; 6590 drive-strength = <10>; 6591 bias-pull-up; 6592 }; 6593 6594 data-pins { 6595 pins = "sdc2_data"; 6596 drive-strength = <10>; 6597 bias-pull-up; 6598 }; 6599 }; 6600 }; 6601 6602 funnel@10042000 { 6603 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6604 6605 reg = <0x0 0x10042000 0x0 0x1000>; 6606 6607 clocks = <&aoss_qmp>; 6608 clock-names = "apb_pclk"; 6609 6610 in-ports { 6611 #address-cells = <1>; 6612 #size-cells = <0>; 6613 6614 port@4 { 6615 reg = <4>; 6616 6617 funnel_in1_in_funnel_apss: endpoint { 6618 remote-endpoint = <&funnel_apss_out_funnel_in1>; 6619 }; 6620 }; 6621 }; 6622 6623 out-ports { 6624 port { 6625 funnel_in1_out_funnel_qdss: endpoint { 6626 remote-endpoint = <&funnel_qdss_in_funnel_in1>; 6627 }; 6628 }; 6629 }; 6630 }; 6631 6632 funnel@10045000 { 6633 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6634 6635 reg = <0x0 0x10045000 0x0 0x1000>; 6636 6637 clocks = <&aoss_qmp>; 6638 clock-names = "apb_pclk"; 6639 6640 in-ports { 6641 #address-cells = <1>; 6642 #size-cells = <0>; 6643 6644 port@1 { 6645 reg = <1>; 6646 6647 funnel_qdss_in_funnel_in1: endpoint { 6648 remote-endpoint = <&funnel_in1_out_funnel_qdss>; 6649 }; 6650 }; 6651 }; 6652 6653 out-ports { 6654 port { 6655 funnel_qdss_out_funnel_aoss: endpoint { 6656 remote-endpoint = <&funnel_aoss_in_funnel_qdss>; 6657 }; 6658 }; 6659 }; 6660 }; 6661 6662 funnel@10b04000 { 6663 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6664 6665 reg = <0x0 0x10b04000 0x0 0x1000>; 6666 6667 clocks = <&aoss_qmp>; 6668 clock-names = "apb_pclk"; 6669 6670 in-ports { 6671 #address-cells = <1>; 6672 #size-cells = <0>; 6673 6674 port@7 { 6675 reg = <7>; 6676 6677 funnel_aoss_in_funnel_qdss: endpoint { 6678 remote-endpoint = <&funnel_qdss_out_funnel_aoss>; 6679 }; 6680 }; 6681 }; 6682 6683 out-ports { 6684 port { 6685 funnel_aoss_out_tmc_etf: endpoint { 6686 remote-endpoint = <&tmc_etf_in_funnel_aoss>; 6687 }; 6688 }; 6689 }; 6690 }; 6691 6692 tmc@10b05000 { 6693 compatible = "arm,coresight-tmc", "arm,primecell"; 6694 6695 reg = <0x0 0x10b05000 0x0 0x1000>; 6696 6697 clocks = <&aoss_qmp>; 6698 clock-names = "apb_pclk"; 6699 6700 in-ports { 6701 port { 6702 tmc_etf_in_funnel_aoss: endpoint { 6703 remote-endpoint = <&funnel_aoss_out_tmc_etf>; 6704 }; 6705 }; 6706 }; 6707 }; 6708 6709 funnel@13810000 { 6710 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6711 6712 reg = <0x0 0x13810000 0x0 0x1000>; 6713 6714 clocks = <&aoss_qmp>; 6715 clock-names = "apb_pclk"; 6716 6717 in-ports { 6718 port { 6719 funnel_apss_in_funnel_ete: endpoint { 6720 remote-endpoint = <&funnel_ete_out_funnel_apss>; 6721 }; 6722 }; 6723 }; 6724 6725 out-ports { 6726 port { 6727 funnel_apss_out_funnel_in1: endpoint { 6728 remote-endpoint = <&funnel_in1_in_funnel_apss>; 6729 }; 6730 }; 6731 }; 6732 }; 6733 6734 apps_smmu: iommu@15000000 { 6735 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6736 reg = <0 0x15000000 0 0x100000>; 6737 6738 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 6739 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 6740 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 6741 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 6742 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 6743 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 6744 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 6745 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 6746 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 6747 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 6748 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 6749 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 6750 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 6751 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 6752 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 6753 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 6754 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 6755 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 6756 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 6757 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 6758 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 6759 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 6760 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 6761 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 6762 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 6763 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 6764 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 6765 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 6766 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 6767 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 6768 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 6769 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 6770 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 6771 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 6772 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 6773 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 6774 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 6775 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 6776 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 6777 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 6778 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 6779 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 6780 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 6781 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 6782 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 6783 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 6784 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 6785 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 6786 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 6787 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 6788 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 6789 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 6790 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 6791 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 6792 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 6793 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 6794 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 6795 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 6796 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 6797 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 6798 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 6799 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 6800 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 6801 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 6802 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 6803 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 6804 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 6805 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 6806 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 6807 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 6808 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 6809 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 6810 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 6811 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 6812 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 6813 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 6814 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 6815 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 6816 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 6817 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 6818 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 6819 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 6820 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 6821 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 6822 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 6823 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 6824 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 6825 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 6826 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 6827 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 6828 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 6829 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 6830 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 6831 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 6832 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 6833 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 6834 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 6835 6836 #iommu-cells = <2>; 6837 #global-interrupts = <1>; 6838 6839 dma-coherent; 6840 }; 6841 6842 intc: interrupt-controller@17100000 { 6843 compatible = "arm,gic-v3"; 6844 reg = <0 0x17100000 0 0x10000>, /* GICD */ 6845 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 6846 6847 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 6848 6849 #interrupt-cells = <4>; 6850 interrupt-controller; 6851 6852 #redistributor-regions = <1>; 6853 redistributor-stride = <0 0x40000>; 6854 6855 #address-cells = <2>; 6856 #size-cells = <2>; 6857 ranges; 6858 6859 ppi-partitions { 6860 ppi_cluster0: interrupt-partition-0 { 6861 affinity = <&cpu0 &cpu1>; 6862 }; 6863 6864 ppi_cluster1: interrupt-partition-1 { 6865 affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; 6866 }; 6867 6868 ppi_cluster2: interrupt-partition-2 { 6869 affinity = <&cpu7>; 6870 }; 6871 }; 6872 6873 gic_its: msi-controller@17140000 { 6874 compatible = "arm,gic-v3-its"; 6875 reg = <0 0x17140000 0 0x20000>; 6876 6877 msi-controller; 6878 #msi-cells = <1>; 6879 }; 6880 }; 6881 6882 timer@17420000 { 6883 compatible = "arm,armv7-timer-mem"; 6884 reg = <0 0x17420000 0 0x1000>; 6885 6886 ranges = <0 0 0 0x20000000>; 6887 #address-cells = <1>; 6888 #size-cells = <1>; 6889 6890 frame@17421000 { 6891 reg = <0x17421000 0x1000>, 6892 <0x17422000 0x1000>; 6893 6894 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 6895 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 6896 6897 frame-number = <0>; 6898 }; 6899 6900 frame@17423000 { 6901 reg = <0x17423000 0x1000>; 6902 6903 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 6904 6905 frame-number = <1>; 6906 6907 status = "disabled"; 6908 }; 6909 6910 frame@17425000 { 6911 reg = <0x17425000 0x1000>; 6912 6913 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 6914 6915 frame-number = <2>; 6916 6917 status = "disabled"; 6918 }; 6919 6920 frame@17427000 { 6921 reg = <0x17427000 0x1000>; 6922 6923 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 6924 6925 frame-number = <3>; 6926 6927 status = "disabled"; 6928 }; 6929 6930 frame@17429000 { 6931 reg = <0x17429000 0x1000>; 6932 6933 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 6934 6935 frame-number = <4>; 6936 6937 status = "disabled"; 6938 }; 6939 6940 frame@1742b000 { 6941 reg = <0x1742b000 0x1000>; 6942 6943 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 6944 6945 frame-number = <5>; 6946 6947 status = "disabled"; 6948 }; 6949 6950 frame@1742d000 { 6951 reg = <0x1742d000 0x1000>; 6952 6953 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 6954 6955 frame-number = <6>; 6956 6957 status = "disabled"; 6958 }; 6959 }; 6960 6961 apps_rsc: rsc@17a00000 { 6962 compatible = "qcom,rpmh-rsc"; 6963 reg = <0 0x17a00000 0 0x10000>, 6964 <0 0x17a10000 0 0x10000>, 6965 <0 0x17a20000 0 0x10000>; 6966 reg-names = "drv-0", 6967 "drv-1", 6968 "drv-2"; 6969 6970 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 6971 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 6972 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 6973 6974 power-domains = <&cluster_pd>; 6975 6976 qcom,tcs-offset = <0xd00>; 6977 qcom,drv-id = <2>; 6978 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 6979 <WAKE_TCS 2>, <CONTROL_TCS 0>; 6980 6981 label = "apps_rsc"; 6982 6983 apps_bcm_voter: bcm-voter { 6984 compatible = "qcom,bcm-voter"; 6985 }; 6986 6987 rpmhcc: clock-controller { 6988 compatible = "qcom,sm8650-rpmh-clk"; 6989 6990 clocks = <&xo_board>; 6991 clock-names = "xo"; 6992 6993 #clock-cells = <1>; 6994 }; 6995 6996 rpmhpd: power-controller { 6997 compatible = "qcom,sm8650-rpmhpd"; 6998 6999 operating-points-v2 = <&rpmhpd_opp_table>; 7000 7001 #power-domain-cells = <1>; 7002 7003 rpmhpd_opp_table: opp-table { 7004 compatible = "operating-points-v2"; 7005 7006 rpmhpd_opp_ret: opp-16 { 7007 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7008 }; 7009 7010 rpmhpd_opp_min_svs: opp-48 { 7011 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7012 }; 7013 7014 rpmhpd_opp_low_svs_d2: opp-52 { 7015 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 7016 }; 7017 7018 rpmhpd_opp_low_svs_d1: opp-56 { 7019 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 7020 }; 7021 7022 rpmhpd_opp_low_svs_d0: opp-60 { 7023 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 7024 }; 7025 7026 rpmhpd_opp_low_svs: opp-64 { 7027 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7028 }; 7029 7030 rpmhpd_opp_low_svs_l1: opp-80 { 7031 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 7032 }; 7033 7034 rpmhpd_opp_svs: opp-128 { 7035 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7036 }; 7037 7038 rpmhpd_opp_svs_l0: opp-144 { 7039 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 7040 }; 7041 7042 rpmhpd_opp_svs_l1: opp-192 { 7043 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7044 }; 7045 7046 rpmhpd_opp_nom: opp-256 { 7047 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7048 }; 7049 7050 rpmhpd_opp_nom_l1: opp-320 { 7051 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7052 }; 7053 7054 rpmhpd_opp_nom_l2: opp-336 { 7055 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7056 }; 7057 7058 rpmhpd_opp_turbo: opp-384 { 7059 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7060 }; 7061 7062 rpmhpd_opp_turbo_l1: opp-416 { 7063 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7064 }; 7065 }; 7066 }; 7067 }; 7068 7069 epss_l3: interconnect@17d90000 { 7070 compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3"; 7071 reg = <0 0x17d90000 0 0x1000>; 7072 7073 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 7074 clock-names = "xo", "alternate"; 7075 7076 #interconnect-cells = <1>; 7077 }; 7078 7079 cpufreq_hw: cpufreq@17d91000 { 7080 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 7081 reg = <0 0x17d91000 0 0x1000>, 7082 <0 0x17d92000 0 0x1000>, 7083 <0 0x17d93000 0 0x1000>, 7084 <0 0x17d94000 0 0x1000>; 7085 reg-names = "freq-domain0", 7086 "freq-domain1", 7087 "freq-domain2", 7088 "freq-domain3"; 7089 7090 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 7091 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 7092 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 7093 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH 0>; 7094 interrupt-names = "dcvsh-irq-0", 7095 "dcvsh-irq-1", 7096 "dcvsh-irq-2", 7097 "dcvsh-irq-3"; 7098 7099 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 7100 clock-names = "xo", "alternate"; 7101 7102 #freq-domain-cells = <1>; 7103 #clock-cells = <1>; 7104 }; 7105 7106 pmu@24091000 { 7107 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 7108 reg = <0 0x24091000 0 0x1000>; 7109 7110 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 7111 7112 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 7113 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 7114 7115 operating-points-v2 = <&llcc_bwmon_opp_table>; 7116 7117 llcc_bwmon_opp_table: opp-table { 7118 compatible = "operating-points-v2"; 7119 7120 opp-0 { 7121 opp-peak-kBps = <2086000>; 7122 }; 7123 7124 opp-1 { 7125 opp-peak-kBps = <2929000>; 7126 }; 7127 7128 opp-2 { 7129 opp-peak-kBps = <5931000>; 7130 }; 7131 7132 opp-3 { 7133 opp-peak-kBps = <6515000>; 7134 }; 7135 7136 opp-4 { 7137 opp-peak-kBps = <7980000>; 7138 }; 7139 7140 opp-5 { 7141 opp-peak-kBps = <10437000>; 7142 }; 7143 7144 opp-6 { 7145 opp-peak-kBps = <12157000>; 7146 }; 7147 7148 opp-7 { 7149 opp-peak-kBps = <14060000>; 7150 }; 7151 7152 opp-8 { 7153 opp-peak-kBps = <16113000>; 7154 }; 7155 }; 7156 }; 7157 7158 pmu@240b7400 { 7159 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 7160 reg = <0 0x240b7400 0 0x600>; 7161 7162 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 7163 7164 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 7165 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 7166 7167 operating-points-v2 = <&cpu_bwmon_opp_table>; 7168 7169 cpu_bwmon_opp_table: opp-table { 7170 compatible = "operating-points-v2"; 7171 7172 opp-0 { 7173 opp-peak-kBps = <4577000>; 7174 }; 7175 7176 opp-1 { 7177 opp-peak-kBps = <7110000>; 7178 }; 7179 7180 opp-2 { 7181 opp-peak-kBps = <9155000>; 7182 }; 7183 7184 opp-3 { 7185 opp-peak-kBps = <12298000>; 7186 }; 7187 7188 opp-4 { 7189 opp-peak-kBps = <14236000>; 7190 }; 7191 7192 opp-5 { 7193 opp-peak-kBps = <16265000>; 7194 }; 7195 }; 7196 }; 7197 7198 gem_noc: interconnect@24100000 { 7199 compatible = "qcom,sm8650-gem-noc"; 7200 reg = <0 0x24100000 0 0xc5080>; 7201 7202 qcom,bcm-voters = <&apps_bcm_voter>; 7203 7204 #interconnect-cells = <2>; 7205 }; 7206 7207 system-cache-controller@25000000 { 7208 compatible = "qcom,sm8650-llcc"; 7209 reg = <0 0x25000000 0 0x200000>, 7210 <0 0x25400000 0 0x200000>, 7211 <0 0x25200000 0 0x200000>, 7212 <0 0x25600000 0 0x200000>, 7213 <0 0x25800000 0 0x200000>, 7214 <0 0x25a00000 0 0x200000>; 7215 reg-names = "llcc0_base", 7216 "llcc1_base", 7217 "llcc2_base", 7218 "llcc3_base", 7219 "llcc_broadcast_base", 7220 "llcc_broadcast_and_base"; 7221 7222 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; 7223 }; 7224 7225 nsp_noc: interconnect@320c0000 { 7226 compatible = "qcom,sm8650-nsp-noc"; 7227 reg = <0 0x320c0000 0 0xf080>; 7228 7229 qcom,bcm-voters = <&apps_bcm_voter>; 7230 7231 #interconnect-cells = <2>; 7232 }; 7233 7234 remoteproc_cdsp: remoteproc@32300000 { 7235 compatible = "qcom,sm8650-cdsp-pas"; 7236 reg = <0x0 0x32300000 0x0 0x10000>; 7237 7238 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 7239 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7240 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7241 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7242 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7243 interrupt-names = "wdog", 7244 "fatal", 7245 "ready", 7246 "handover", 7247 "stop-ack"; 7248 7249 clocks = <&rpmhcc RPMH_CXO_CLK>; 7250 clock-names = "xo"; 7251 7252 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7253 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7254 7255 power-domains = <&rpmhpd RPMHPD_CX>, 7256 <&rpmhpd RPMHPD_MXC>, 7257 <&rpmhpd RPMHPD_NSP>; 7258 power-domain-names = "cx", 7259 "mxc", 7260 "nsp"; 7261 7262 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 7263 7264 qcom,qmp = <&aoss_qmp>; 7265 7266 qcom,smem-states = <&smp2p_cdsp_out 0>; 7267 qcom,smem-state-names = "stop"; 7268 7269 status = "disabled"; 7270 7271 glink-edge { 7272 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7273 IPCC_MPROC_SIGNAL_GLINK_QMP 7274 IRQ_TYPE_EDGE_RISING>; 7275 7276 mboxes = <&ipcc IPCC_CLIENT_CDSP 7277 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7278 7279 qcom,remote-pid = <5>; 7280 7281 label = "cdsp"; 7282 7283 fastrpc { 7284 compatible = "qcom,fastrpc"; 7285 7286 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7287 7288 label = "cdsp"; 7289 7290 qcom,non-secure-domain; 7291 7292 #address-cells = <1>; 7293 #size-cells = <0>; 7294 7295 compute-cb@1 { 7296 compatible = "qcom,fastrpc-compute-cb"; 7297 reg = <1>; 7298 7299 iommus = <&apps_smmu 0x1961 0x0>, 7300 <&apps_smmu 0x0c01 0x20>, 7301 <&apps_smmu 0x19c1 0x0>; 7302 dma-coherent; 7303 }; 7304 7305 compute-cb@2 { 7306 compatible = "qcom,fastrpc-compute-cb"; 7307 reg = <2>; 7308 7309 iommus = <&apps_smmu 0x1962 0x0>, 7310 <&apps_smmu 0x0c02 0x20>, 7311 <&apps_smmu 0x19c2 0x0>; 7312 dma-coherent; 7313 }; 7314 7315 compute-cb@3 { 7316 compatible = "qcom,fastrpc-compute-cb"; 7317 reg = <3>; 7318 7319 iommus = <&apps_smmu 0x1963 0x0>, 7320 <&apps_smmu 0x0c03 0x20>, 7321 <&apps_smmu 0x19c3 0x0>; 7322 dma-coherent; 7323 }; 7324 7325 compute-cb@4 { 7326 compatible = "qcom,fastrpc-compute-cb"; 7327 reg = <4>; 7328 7329 iommus = <&apps_smmu 0x1964 0x0>, 7330 <&apps_smmu 0x0c04 0x20>, 7331 <&apps_smmu 0x19c4 0x0>; 7332 dma-coherent; 7333 }; 7334 7335 compute-cb@5 { 7336 compatible = "qcom,fastrpc-compute-cb"; 7337 reg = <5>; 7338 7339 iommus = <&apps_smmu 0x1965 0x0>, 7340 <&apps_smmu 0x0c05 0x20>, 7341 <&apps_smmu 0x19c5 0x0>; 7342 dma-coherent; 7343 }; 7344 7345 compute-cb@6 { 7346 compatible = "qcom,fastrpc-compute-cb"; 7347 reg = <6>; 7348 7349 iommus = <&apps_smmu 0x1966 0x0>, 7350 <&apps_smmu 0x0c06 0x20>, 7351 <&apps_smmu 0x19c6 0x0>; 7352 dma-coherent; 7353 }; 7354 7355 compute-cb@7 { 7356 compatible = "qcom,fastrpc-compute-cb"; 7357 reg = <7>; 7358 7359 iommus = <&apps_smmu 0x1967 0x0>, 7360 <&apps_smmu 0x0c07 0x20>, 7361 <&apps_smmu 0x19c7 0x0>; 7362 dma-coherent; 7363 }; 7364 7365 compute-cb@8 { 7366 compatible = "qcom,fastrpc-compute-cb"; 7367 reg = <8>; 7368 7369 iommus = <&apps_smmu 0x1968 0x0>, 7370 <&apps_smmu 0x0c08 0x20>, 7371 <&apps_smmu 0x19c8 0x0>; 7372 dma-coherent; 7373 }; 7374 7375 /* note: secure cb9 in downstream */ 7376 7377 compute-cb@12 { 7378 compatible = "qcom,fastrpc-compute-cb"; 7379 reg = <12>; 7380 7381 iommus = <&apps_smmu 0x196c 0x0>, 7382 <&apps_smmu 0x0c0c 0x20>, 7383 <&apps_smmu 0x19cc 0x0>; 7384 dma-coherent; 7385 }; 7386 7387 compute-cb@13 { 7388 compatible = "qcom,fastrpc-compute-cb"; 7389 reg = <13>; 7390 7391 iommus = <&apps_smmu 0x196d 0x0>, 7392 <&apps_smmu 0x0c0d 0x20>, 7393 <&apps_smmu 0x19cd 0x0>; 7394 dma-coherent; 7395 }; 7396 7397 compute-cb@14 { 7398 compatible = "qcom,fastrpc-compute-cb"; 7399 reg = <14>; 7400 7401 iommus = <&apps_smmu 0x196e 0x0>, 7402 <&apps_smmu 0x0c0e 0x20>, 7403 <&apps_smmu 0x19ce 0x0>; 7404 dma-coherent; 7405 }; 7406 }; 7407 }; 7408 }; 7409 }; 7410 7411 thermal-zones { 7412 aoss0-thermal { 7413 thermal-sensors = <&tsens0 0>; 7414 7415 trips { 7416 aoss0-hot { 7417 temperature = <110000>; 7418 hysteresis = <1000>; 7419 type = "hot"; 7420 }; 7421 7422 aoss0-critical { 7423 temperature = <115000>; 7424 hysteresis = <0>; 7425 type = "critical"; 7426 }; 7427 }; 7428 }; 7429 7430 cpuss0-thermal { 7431 thermal-sensors = <&tsens0 1>; 7432 7433 trips { 7434 cpuss0-hot { 7435 temperature = <110000>; 7436 hysteresis = <1000>; 7437 type = "hot"; 7438 }; 7439 7440 cpuss0-critical { 7441 temperature = <115000>; 7442 hysteresis = <0>; 7443 type = "critical"; 7444 }; 7445 }; 7446 }; 7447 7448 cpuss1-thermal { 7449 thermal-sensors = <&tsens0 2>; 7450 7451 trips { 7452 cpuss1-hot { 7453 temperature = <110000>; 7454 hysteresis = <1000>; 7455 type = "hot"; 7456 }; 7457 7458 cpuss1-critical { 7459 temperature = <115000>; 7460 hysteresis = <0>; 7461 type = "critical"; 7462 }; 7463 }; 7464 }; 7465 7466 cpuss2-thermal { 7467 thermal-sensors = <&tsens0 3>; 7468 7469 trips { 7470 cpuss2-hot { 7471 temperature = <110000>; 7472 hysteresis = <1000>; 7473 type = "hot"; 7474 }; 7475 7476 cpuss2-critical { 7477 temperature = <115000>; 7478 hysteresis = <0>; 7479 type = "critical"; 7480 }; 7481 }; 7482 }; 7483 7484 cpuss3-thermal { 7485 thermal-sensors = <&tsens0 4>; 7486 7487 trips { 7488 cpuss3-hot { 7489 temperature = <110000>; 7490 hysteresis = <1000>; 7491 type = "hot"; 7492 }; 7493 7494 cpuss3-critical { 7495 temperature = <115000>; 7496 hysteresis = <0>; 7497 type = "critical"; 7498 }; 7499 }; 7500 }; 7501 7502 cpu2-top-thermal { 7503 thermal-sensors = <&tsens0 5>; 7504 7505 trips { 7506 cpu2-critical { 7507 temperature = <110000>; 7508 hysteresis = <1000>; 7509 type = "critical"; 7510 }; 7511 }; 7512 }; 7513 7514 cpu2-bottom-thermal { 7515 thermal-sensors = <&tsens0 6>; 7516 7517 trips { 7518 cpu2-critical { 7519 temperature = <110000>; 7520 hysteresis = <1000>; 7521 type = "critical"; 7522 }; 7523 }; 7524 }; 7525 7526 cpu3-top-thermal { 7527 thermal-sensors = <&tsens0 7>; 7528 7529 trips { 7530 cpu3-critical { 7531 temperature = <110000>; 7532 hysteresis = <1000>; 7533 type = "critical"; 7534 }; 7535 }; 7536 }; 7537 7538 cpu3-bottom-thermal { 7539 thermal-sensors = <&tsens0 8>; 7540 7541 trips { 7542 cpu3-critical { 7543 temperature = <110000>; 7544 hysteresis = <1000>; 7545 type = "critical"; 7546 }; 7547 }; 7548 }; 7549 7550 cpu4-top-thermal { 7551 thermal-sensors = <&tsens0 9>; 7552 7553 trips { 7554 cpu4-critical { 7555 temperature = <110000>; 7556 hysteresis = <1000>; 7557 type = "critical"; 7558 }; 7559 }; 7560 }; 7561 7562 cpu4-bottom-thermal { 7563 thermal-sensors = <&tsens0 10>; 7564 7565 trips { 7566 cpu4-critical { 7567 temperature = <110000>; 7568 hysteresis = <1000>; 7569 type = "critical"; 7570 }; 7571 }; 7572 }; 7573 7574 cpu5-top-thermal { 7575 thermal-sensors = <&tsens0 11>; 7576 7577 trips { 7578 cpu5-critical { 7579 temperature = <110000>; 7580 hysteresis = <1000>; 7581 type = "critical"; 7582 }; 7583 }; 7584 }; 7585 7586 cpu5-bottom-thermal { 7587 thermal-sensors = <&tsens0 12>; 7588 7589 trips { 7590 cpu5-critical { 7591 temperature = <110000>; 7592 hysteresis = <1000>; 7593 type = "critical"; 7594 }; 7595 }; 7596 }; 7597 7598 cpu6-top-thermal { 7599 thermal-sensors = <&tsens0 13>; 7600 7601 trips { 7602 cpu6-critical { 7603 temperature = <110000>; 7604 hysteresis = <1000>; 7605 type = "critical"; 7606 }; 7607 }; 7608 }; 7609 7610 cpu6-bottom-thermal { 7611 thermal-sensors = <&tsens0 14>; 7612 7613 trips { 7614 cpu6-critical { 7615 temperature = <110000>; 7616 hysteresis = <1000>; 7617 type = "critical"; 7618 }; 7619 }; 7620 }; 7621 7622 aoss1-thermal { 7623 thermal-sensors = <&tsens1 0>; 7624 7625 trips { 7626 aoss1-hot { 7627 temperature = <110000>; 7628 hysteresis = <1000>; 7629 type = "hot"; 7630 }; 7631 7632 aoss1-critical { 7633 temperature = <115000>; 7634 hysteresis = <0>; 7635 type = "critical"; 7636 }; 7637 }; 7638 }; 7639 7640 cpu7-top-thermal { 7641 thermal-sensors = <&tsens1 1>; 7642 7643 trips { 7644 cpu7-critical { 7645 temperature = <110000>; 7646 hysteresis = <1000>; 7647 type = "critical"; 7648 }; 7649 }; 7650 }; 7651 7652 cpu7-middle-thermal { 7653 thermal-sensors = <&tsens1 2>; 7654 7655 trips { 7656 cpu7-critical { 7657 temperature = <110000>; 7658 hysteresis = <1000>; 7659 type = "critical"; 7660 }; 7661 }; 7662 }; 7663 7664 cpu7-bottom-thermal { 7665 thermal-sensors = <&tsens1 3>; 7666 7667 trips { 7668 cpu7-critical { 7669 temperature = <110000>; 7670 hysteresis = <1000>; 7671 type = "critical"; 7672 }; 7673 }; 7674 }; 7675 7676 cpu0-thermal { 7677 thermal-sensors = <&tsens1 4>; 7678 7679 trips { 7680 cpu0-critical { 7681 temperature = <110000>; 7682 hysteresis = <1000>; 7683 type = "critical"; 7684 }; 7685 }; 7686 }; 7687 7688 cpu1-thermal { 7689 thermal-sensors = <&tsens1 5>; 7690 7691 trips { 7692 cpu1-critical { 7693 temperature = <110000>; 7694 hysteresis = <1000>; 7695 type = "critical"; 7696 }; 7697 }; 7698 }; 7699 7700 nsphvx0-thermal { 7701 thermal-sensors = <&tsens2 6>; 7702 7703 trips { 7704 nsphvx0-hot { 7705 temperature = <110000>; 7706 hysteresis = <1000>; 7707 type = "hot"; 7708 }; 7709 7710 nsphvx0-critical { 7711 temperature = <115000>; 7712 hysteresis = <0>; 7713 type = "critical"; 7714 }; 7715 }; 7716 }; 7717 7718 nsphvx1-thermal { 7719 thermal-sensors = <&tsens2 7>; 7720 7721 trips { 7722 nsphvx1-hot { 7723 temperature = <110000>; 7724 hysteresis = <1000>; 7725 type = "hot"; 7726 }; 7727 7728 nsphvx1-critical { 7729 temperature = <115000>; 7730 hysteresis = <0>; 7731 type = "critical"; 7732 }; 7733 }; 7734 }; 7735 7736 nsphmx0-thermal { 7737 thermal-sensors = <&tsens2 8>; 7738 7739 trips { 7740 nsphmx0-hot { 7741 temperature = <110000>; 7742 hysteresis = <1000>; 7743 type = "hot"; 7744 }; 7745 7746 nsphmx0-critical { 7747 temperature = <115000>; 7748 hysteresis = <0>; 7749 type = "critical"; 7750 }; 7751 }; 7752 }; 7753 7754 nsphmx1-thermal { 7755 thermal-sensors = <&tsens2 9>; 7756 7757 trips { 7758 nsphmx1-hot { 7759 temperature = <110000>; 7760 hysteresis = <1000>; 7761 type = "hot"; 7762 }; 7763 7764 nsphmx1-critical { 7765 temperature = <115000>; 7766 hysteresis = <0>; 7767 type = "critical"; 7768 }; 7769 }; 7770 }; 7771 7772 nsphmx2-thermal { 7773 thermal-sensors = <&tsens2 10>; 7774 7775 trips { 7776 nsphmx2-hot { 7777 temperature = <110000>; 7778 hysteresis = <1000>; 7779 type = "hot"; 7780 }; 7781 7782 nsphmx2-critical { 7783 temperature = <115000>; 7784 hysteresis = <0>; 7785 type = "critical"; 7786 }; 7787 }; 7788 }; 7789 7790 nsphmx3-thermal { 7791 thermal-sensors = <&tsens2 11>; 7792 7793 trips { 7794 nsphmx3-hot { 7795 temperature = <110000>; 7796 hysteresis = <1000>; 7797 type = "hot"; 7798 }; 7799 7800 nsphmx3-critical { 7801 temperature = <115000>; 7802 hysteresis = <0>; 7803 type = "critical"; 7804 }; 7805 }; 7806 }; 7807 7808 video-thermal { 7809 thermal-sensors = <&tsens1 12>; 7810 7811 trips { 7812 video-hot { 7813 temperature = <110000>; 7814 hysteresis = <1000>; 7815 type = "hot"; 7816 }; 7817 7818 video-critical { 7819 temperature = <115000>; 7820 hysteresis = <0>; 7821 type = "critical"; 7822 }; 7823 }; 7824 }; 7825 7826 ddr-thermal { 7827 thermal-sensors = <&tsens1 13>; 7828 7829 trips { 7830 ddr-hot { 7831 temperature = <110000>; 7832 hysteresis = <1000>; 7833 type = "hot"; 7834 }; 7835 7836 ddr-critical { 7837 temperature = <115000>; 7838 hysteresis = <0>; 7839 type = "critical"; 7840 }; 7841 }; 7842 }; 7843 7844 camera0-thermal { 7845 thermal-sensors = <&tsens1 14>; 7846 7847 trips { 7848 camera0-hot { 7849 temperature = <110000>; 7850 hysteresis = <1000>; 7851 type = "hot"; 7852 }; 7853 7854 camera0-critical { 7855 temperature = <115000>; 7856 hysteresis = <0>; 7857 type = "critical"; 7858 }; 7859 }; 7860 }; 7861 7862 camera1-thermal { 7863 thermal-sensors = <&tsens1 15>; 7864 7865 trips { 7866 camera1-hot { 7867 temperature = <110000>; 7868 hysteresis = <1000>; 7869 type = "hot"; 7870 }; 7871 7872 camera1-critical { 7873 temperature = <115000>; 7874 hysteresis = <0>; 7875 type = "critical"; 7876 }; 7877 }; 7878 }; 7879 7880 aoss2-thermal { 7881 thermal-sensors = <&tsens2 0>; 7882 7883 trips { 7884 aoss2-hot { 7885 temperature = <110000>; 7886 hysteresis = <1000>; 7887 type = "hot"; 7888 }; 7889 7890 aoss2-critical { 7891 temperature = <115000>; 7892 hysteresis = <0>; 7893 type = "critical"; 7894 }; 7895 }; 7896 }; 7897 7898 gpuss0-thermal { 7899 polling-delay-passive = <10>; 7900 7901 thermal-sensors = <&tsens2 1>; 7902 7903 cooling-maps { 7904 map0 { 7905 trip = <&gpu0_alert0>; 7906 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7907 }; 7908 }; 7909 7910 trips { 7911 gpu0_alert0: trip-point0 { 7912 temperature = <95000>; 7913 hysteresis = <1000>; 7914 type = "passive"; 7915 }; 7916 7917 trip-point1 { 7918 temperature = <110000>; 7919 hysteresis = <1000>; 7920 type = "hot"; 7921 }; 7922 7923 trip-point2 { 7924 temperature = <115000>; 7925 hysteresis = <0>; 7926 type = "critical"; 7927 }; 7928 }; 7929 }; 7930 7931 gpuss1-thermal { 7932 polling-delay-passive = <10>; 7933 7934 thermal-sensors = <&tsens2 2>; 7935 7936 cooling-maps { 7937 map0 { 7938 trip = <&gpu1_alert0>; 7939 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7940 }; 7941 }; 7942 7943 trips { 7944 gpu1_alert0: trip-point0 { 7945 temperature = <95000>; 7946 hysteresis = <1000>; 7947 type = "passive"; 7948 }; 7949 7950 trip-point1 { 7951 temperature = <110000>; 7952 hysteresis = <1000>; 7953 type = "hot"; 7954 }; 7955 7956 trip-point2 { 7957 temperature = <115000>; 7958 hysteresis = <0>; 7959 type = "critical"; 7960 }; 7961 }; 7962 }; 7963 7964 gpuss2-thermal { 7965 polling-delay-passive = <10>; 7966 7967 thermal-sensors = <&tsens2 3>; 7968 7969 cooling-maps { 7970 map0 { 7971 trip = <&gpu2_alert0>; 7972 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7973 }; 7974 }; 7975 7976 trips { 7977 gpu2_alert0: trip-point0 { 7978 temperature = <95000>; 7979 hysteresis = <1000>; 7980 type = "passive"; 7981 }; 7982 7983 trip-point1 { 7984 temperature = <110000>; 7985 hysteresis = <1000>; 7986 type = "hot"; 7987 }; 7988 7989 trip-point2 { 7990 temperature = <115000>; 7991 hysteresis = <0>; 7992 type = "critical"; 7993 }; 7994 }; 7995 }; 7996 7997 gpuss3-thermal { 7998 polling-delay-passive = <10>; 7999 8000 thermal-sensors = <&tsens2 4>; 8001 8002 cooling-maps { 8003 map0 { 8004 trip = <&gpu3_alert0>; 8005 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8006 }; 8007 }; 8008 8009 trips { 8010 gpu3_alert0: trip-point0 { 8011 temperature = <95000>; 8012 hysteresis = <1000>; 8013 type = "passive"; 8014 }; 8015 8016 trip-point1 { 8017 temperature = <110000>; 8018 hysteresis = <1000>; 8019 type = "hot"; 8020 }; 8021 8022 trip-point2 { 8023 temperature = <115000>; 8024 hysteresis = <0>; 8025 type = "critical"; 8026 }; 8027 }; 8028 }; 8029 8030 gpuss4-thermal { 8031 polling-delay-passive = <10>; 8032 8033 thermal-sensors = <&tsens2 5>; 8034 8035 cooling-maps { 8036 map0 { 8037 trip = <&gpu4_alert0>; 8038 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8039 }; 8040 }; 8041 8042 trips { 8043 gpu4_alert0: trip-point0 { 8044 temperature = <95000>; 8045 hysteresis = <1000>; 8046 type = "passive"; 8047 }; 8048 8049 trip-point1 { 8050 temperature = <110000>; 8051 hysteresis = <1000>; 8052 type = "hot"; 8053 }; 8054 8055 trip-point2 { 8056 temperature = <115000>; 8057 hysteresis = <0>; 8058 type = "critical"; 8059 }; 8060 }; 8061 }; 8062 8063 gpuss5-thermal { 8064 polling-delay-passive = <10>; 8065 8066 thermal-sensors = <&tsens2 6>; 8067 8068 cooling-maps { 8069 map0 { 8070 trip = <&gpu5_alert0>; 8071 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8072 }; 8073 }; 8074 8075 trips { 8076 gpu5_alert0: trip-point0 { 8077 temperature = <95000>; 8078 hysteresis = <1000>; 8079 type = "passive"; 8080 }; 8081 8082 trip-point1 { 8083 temperature = <110000>; 8084 hysteresis = <1000>; 8085 type = "hot"; 8086 }; 8087 8088 trip-point2 { 8089 temperature = <115000>; 8090 hysteresis = <0>; 8091 type = "critical"; 8092 }; 8093 }; 8094 }; 8095 8096 gpuss6-thermal { 8097 polling-delay-passive = <10>; 8098 8099 thermal-sensors = <&tsens2 7>; 8100 8101 cooling-maps { 8102 map0 { 8103 trip = <&gpu6_alert0>; 8104 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8105 }; 8106 }; 8107 8108 trips { 8109 gpu6_alert0: trip-point0 { 8110 temperature = <95000>; 8111 hysteresis = <1000>; 8112 type = "passive"; 8113 }; 8114 8115 trip-point1 { 8116 temperature = <110000>; 8117 hysteresis = <1000>; 8118 type = "hot"; 8119 }; 8120 8121 trip-point2 { 8122 temperature = <115000>; 8123 hysteresis = <0>; 8124 type = "critical"; 8125 }; 8126 }; 8127 }; 8128 8129 gpuss7-thermal { 8130 polling-delay-passive = <10>; 8131 8132 thermal-sensors = <&tsens2 8>; 8133 8134 cooling-maps { 8135 map0 { 8136 trip = <&gpu7_alert0>; 8137 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8138 }; 8139 }; 8140 8141 trips { 8142 gpu7_alert0: trip-point0 { 8143 temperature = <95000>; 8144 hysteresis = <1000>; 8145 type = "passive"; 8146 }; 8147 8148 trip-point1 { 8149 temperature = <110000>; 8150 hysteresis = <1000>; 8151 type = "hot"; 8152 }; 8153 8154 trip-point2 { 8155 temperature = <115000>; 8156 hysteresis = <0>; 8157 type = "critical"; 8158 }; 8159 }; 8160 }; 8161 8162 modem0-thermal { 8163 thermal-sensors = <&tsens2 9>; 8164 8165 trips { 8166 modem0-hot { 8167 temperature = <110000>; 8168 hysteresis = <1000>; 8169 type = "hot"; 8170 }; 8171 8172 modem0-critical { 8173 temperature = <115000>; 8174 hysteresis = <0>; 8175 type = "critical"; 8176 }; 8177 }; 8178 }; 8179 8180 modem1-thermal { 8181 thermal-sensors = <&tsens2 10>; 8182 8183 trips { 8184 modem1-hot { 8185 temperature = <110000>; 8186 hysteresis = <1000>; 8187 type = "hot"; 8188 }; 8189 8190 modem1-critical { 8191 temperature = <115000>; 8192 hysteresis = <0>; 8193 type = "critical"; 8194 }; 8195 }; 8196 }; 8197 8198 modem2-thermal { 8199 thermal-sensors = <&tsens2 11>; 8200 8201 trips { 8202 modem2-hot { 8203 temperature = <110000>; 8204 hysteresis = <1000>; 8205 type = "hot"; 8206 }; 8207 8208 modem2-critical { 8209 temperature = <115000>; 8210 hysteresis = <0>; 8211 type = "critical"; 8212 }; 8213 }; 8214 }; 8215 8216 modem3-thermal { 8217 thermal-sensors = <&tsens2 12>; 8218 8219 trips { 8220 modem3-hot { 8221 temperature = <110000>; 8222 hysteresis = <1000>; 8223 type = "hot"; 8224 }; 8225 8226 modem3-critical { 8227 temperature = <115000>; 8228 hysteresis = <0>; 8229 type = "critical"; 8230 }; 8231 }; 8232 }; 8233 }; 8234 8235 timer { 8236 compatible = "arm,armv8-timer"; 8237 8238 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 8239 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 8240 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 8241 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 8242 }; 8243}; 8244