1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,sm8550-camcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gcc.h> 11#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/power/qcom,rpmhpd.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/phy/phy-qcom-qmp.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 bi_tcxo_div2: bi-tcxo-div2-clk { 49 #clock-cells = <0>; 50 compatible = "fixed-factor-clock"; 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 #clock-cells = <0>; 58 compatible = "fixed-factor-clock"; 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a510"; 72 reg = <0 0>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>; 77 power-domain-names = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 #cooling-cells = <2>; 82 l2_0: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 next-level-cache = <&l3_0>; 87 l3_0: l3-cache { 88 compatible = "cache"; 89 cache-level = <3>; 90 cache-unified; 91 }; 92 }; 93 }; 94 95 cpu1: cpu@100 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a510"; 98 reg = <0 0x100>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_100>; 102 power-domains = <&cpu_pd1>; 103 power-domain-names = "psci"; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 capacity-dmips-mhz = <1024>; 106 dynamic-power-coefficient = <100>; 107 #cooling-cells = <2>; 108 l2_100: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu2: cpu@200 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a510"; 119 reg = <0 0x200>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_200>; 123 power-domains = <&cpu_pd2>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 #cooling-cells = <2>; 129 l2_200: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a715"; 140 reg = <0 0x300>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_300>; 144 power-domains = <&cpu_pd3>; 145 power-domain-names = "psci"; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 capacity-dmips-mhz = <1792>; 148 dynamic-power-coefficient = <270>; 149 #cooling-cells = <2>; 150 l2_300: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu4: cpu@400 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a715"; 161 reg = <0 0x400>; 162 clocks = <&cpufreq_hw 1>; 163 enable-method = "psci"; 164 next-level-cache = <&l2_400>; 165 power-domains = <&cpu_pd4>; 166 power-domain-names = "psci"; 167 qcom,freq-domain = <&cpufreq_hw 1>; 168 capacity-dmips-mhz = <1792>; 169 dynamic-power-coefficient = <270>; 170 #cooling-cells = <2>; 171 l2_400: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_0>; 176 }; 177 }; 178 179 cpu5: cpu@500 { 180 device_type = "cpu"; 181 compatible = "arm,cortex-a710"; 182 reg = <0 0x500>; 183 clocks = <&cpufreq_hw 1>; 184 enable-method = "psci"; 185 next-level-cache = <&l2_500>; 186 power-domains = <&cpu_pd5>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 1>; 189 capacity-dmips-mhz = <1792>; 190 dynamic-power-coefficient = <270>; 191 #cooling-cells = <2>; 192 l2_500: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&l3_0>; 197 }; 198 }; 199 200 cpu6: cpu@600 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-a710"; 203 reg = <0 0x600>; 204 clocks = <&cpufreq_hw 1>; 205 enable-method = "psci"; 206 next-level-cache = <&l2_600>; 207 power-domains = <&cpu_pd6>; 208 power-domain-names = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 capacity-dmips-mhz = <1792>; 211 dynamic-power-coefficient = <270>; 212 #cooling-cells = <2>; 213 l2_600: l2-cache { 214 compatible = "cache"; 215 cache-level = <2>; 216 cache-unified; 217 next-level-cache = <&l3_0>; 218 }; 219 }; 220 221 cpu7: cpu@700 { 222 device_type = "cpu"; 223 compatible = "arm,cortex-x3"; 224 reg = <0 0x700>; 225 clocks = <&cpufreq_hw 2>; 226 enable-method = "psci"; 227 next-level-cache = <&l2_700>; 228 power-domains = <&cpu_pd7>; 229 power-domain-names = "psci"; 230 qcom,freq-domain = <&cpufreq_hw 2>; 231 capacity-dmips-mhz = <1894>; 232 dynamic-power-coefficient = <588>; 233 #cooling-cells = <2>; 234 l2_700: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&l3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&cpu0>; 246 }; 247 248 core1 { 249 cpu = <&cpu1>; 250 }; 251 252 core2 { 253 cpu = <&cpu2>; 254 }; 255 256 core3 { 257 cpu = <&cpu3>; 258 }; 259 260 core4 { 261 cpu = <&cpu4>; 262 }; 263 264 core5 { 265 cpu = <&cpu5>; 266 }; 267 268 core6 { 269 cpu = <&cpu6>; 270 }; 271 272 core7 { 273 cpu = <&cpu7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 little_cpu_sleep_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "silver-rail-power-collapse"; 284 arm,psci-suspend-param = <0x40000004>; 285 entry-latency-us = <550>; 286 exit-latency-us = <750>; 287 min-residency-us = <6700>; 288 local-timer-stop; 289 }; 290 291 big_cpu_sleep_0: cpu-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "gold-rail-power-collapse"; 294 arm,psci-suspend-param = <0x40000004>; 295 entry-latency-us = <600>; 296 exit-latency-us = <1300>; 297 min-residency-us = <8136>; 298 local-timer-stop; 299 }; 300 301 prime_cpu_sleep_0: cpu-sleep-2-0 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "goldplus-rail-power-collapse"; 304 arm,psci-suspend-param = <0x40000004>; 305 entry-latency-us = <500>; 306 exit-latency-us = <1350>; 307 min-residency-us = <7480>; 308 local-timer-stop; 309 }; 310 }; 311 312 domain-idle-states { 313 cluster_sleep_0: cluster-sleep-0 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x41000044>; 316 entry-latency-us = <750>; 317 exit-latency-us = <2350>; 318 min-residency-us = <9144>; 319 }; 320 321 cluster_sleep_1: cluster-sleep-1 { 322 compatible = "domain-idle-state"; 323 arm,psci-suspend-param = <0x4100c344>; 324 entry-latency-us = <2800>; 325 exit-latency-us = <4400>; 326 min-residency-us = <10150>; 327 }; 328 }; 329 }; 330 331 firmware { 332 scm: scm { 333 compatible = "qcom,scm-sm8550", "qcom,scm"; 334 qcom,dload-mode = <&tcsr 0x19000>; 335 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 336 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 337 }; 338 }; 339 340 clk_virt: interconnect-0 { 341 compatible = "qcom,sm8550-clk-virt"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 mc_virt: interconnect-1 { 347 compatible = "qcom,sm8550-mc-virt"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 qup_opp_table_100mhz: opp-table-qup100mhz { 353 compatible = "operating-points-v2"; 354 355 opp-75000000 { 356 opp-hz = /bits/ 64 <75000000>; 357 required-opps = <&rpmhpd_opp_low_svs>; 358 }; 359 360 opp-100000000 { 361 opp-hz = /bits/ 64 <100000000>; 362 required-opps = <&rpmhpd_opp_svs>; 363 }; 364 }; 365 366 qup_opp_table_120mhz: opp-table-qup120mhz { 367 compatible = "operating-points-v2"; 368 369 opp-75000000 { 370 opp-hz = /bits/ 64 <75000000>; 371 required-opps = <&rpmhpd_opp_low_svs>; 372 }; 373 374 opp-120000000 { 375 opp-hz = /bits/ 64 <120000000>; 376 required-opps = <&rpmhpd_opp_svs>; 377 }; 378 }; 379 380 qup_opp_table_125mhz: opp-table-qup125mhz { 381 compatible = "operating-points-v2"; 382 383 opp-75000000 { 384 opp-hz = /bits/ 64 <75000000>; 385 required-opps = <&rpmhpd_opp_low_svs>; 386 }; 387 388 opp-125000000 { 389 opp-hz = /bits/ 64 <125000000>; 390 required-opps = <&rpmhpd_opp_svs>; 391 }; 392 }; 393 394 memory@a0000000 { 395 device_type = "memory"; 396 /* We expect the bootloader to fill in the size */ 397 reg = <0 0xa0000000 0 0>; 398 }; 399 400 pmu-a510 { 401 compatible = "arm,cortex-a510-pmu"; 402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 403 }; 404 405 pmu-a710 { 406 compatible = "arm,cortex-a710-pmu"; 407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 408 }; 409 410 pmu-a715 { 411 compatible = "arm,cortex-a715-pmu"; 412 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 413 }; 414 415 pmu-x3 { 416 compatible = "arm,cortex-x3-pmu"; 417 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 418 }; 419 420 psci { 421 compatible = "arm,psci-1.0"; 422 method = "smc"; 423 424 cpu_pd0: power-domain-cpu0 { 425 #power-domain-cells = <0>; 426 power-domains = <&cluster_pd>; 427 domain-idle-states = <&little_cpu_sleep_0>; 428 }; 429 430 cpu_pd1: power-domain-cpu1 { 431 #power-domain-cells = <0>; 432 power-domains = <&cluster_pd>; 433 domain-idle-states = <&little_cpu_sleep_0>; 434 }; 435 436 cpu_pd2: power-domain-cpu2 { 437 #power-domain-cells = <0>; 438 power-domains = <&cluster_pd>; 439 domain-idle-states = <&little_cpu_sleep_0>; 440 }; 441 442 cpu_pd3: power-domain-cpu3 { 443 #power-domain-cells = <0>; 444 power-domains = <&cluster_pd>; 445 domain-idle-states = <&big_cpu_sleep_0>; 446 }; 447 448 cpu_pd4: power-domain-cpu4 { 449 #power-domain-cells = <0>; 450 power-domains = <&cluster_pd>; 451 domain-idle-states = <&big_cpu_sleep_0>; 452 }; 453 454 cpu_pd5: power-domain-cpu5 { 455 #power-domain-cells = <0>; 456 power-domains = <&cluster_pd>; 457 domain-idle-states = <&big_cpu_sleep_0>; 458 }; 459 460 cpu_pd6: power-domain-cpu6 { 461 #power-domain-cells = <0>; 462 power-domains = <&cluster_pd>; 463 domain-idle-states = <&big_cpu_sleep_0>; 464 }; 465 466 cpu_pd7: power-domain-cpu7 { 467 #power-domain-cells = <0>; 468 power-domains = <&cluster_pd>; 469 domain-idle-states = <&prime_cpu_sleep_0>; 470 }; 471 472 cluster_pd: power-domain-cluster { 473 #power-domain-cells = <0>; 474 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 475 }; 476 }; 477 478 reserved_memory: reserved-memory { 479 #address-cells = <2>; 480 #size-cells = <2>; 481 ranges; 482 483 hyp_mem: hyp-region@80000000 { 484 reg = <0 0x80000000 0 0xa00000>; 485 no-map; 486 }; 487 488 cpusys_vm_mem: cpusys-vm-region@80a00000 { 489 reg = <0 0x80a00000 0 0x400000>; 490 no-map; 491 }; 492 493 hyp_tags_mem: hyp-tags-region@80e00000 { 494 reg = <0 0x80e00000 0 0x3d0000>; 495 no-map; 496 }; 497 498 xbl_sc_mem: xbl-sc-region@d8100000 { 499 reg = <0 0xd8100000 0 0x40000>; 500 no-map; 501 }; 502 503 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 504 reg = <0 0x811d0000 0 0x30000>; 505 no-map; 506 }; 507 508 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 509 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 510 reg = <0 0x81a00000 0 0x260000>; 511 no-map; 512 }; 513 514 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 515 compatible = "qcom,cmd-db"; 516 reg = <0 0x81c60000 0 0x20000>; 517 no-map; 518 }; 519 520 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 521 aop_config_merged_mem: aop-config-merged-region@81c80000 { 522 reg = <0 0x81c80000 0 0x74000>; 523 no-map; 524 }; 525 526 /* secdata region can be reused by apps */ 527 smem: smem@81d00000 { 528 compatible = "qcom,smem"; 529 reg = <0 0x81d00000 0 0x200000>; 530 hwlocks = <&tcsr_mutex 3>; 531 no-map; 532 }; 533 534 adsp_mhi_mem: adsp-mhi-region@81f00000 { 535 reg = <0 0x81f00000 0 0x20000>; 536 no-map; 537 }; 538 539 global_sync_mem: global-sync-region@82600000 { 540 reg = <0 0x82600000 0 0x100000>; 541 no-map; 542 }; 543 544 tz_stat_mem: tz-stat-region@82700000 { 545 reg = <0 0x82700000 0 0x100000>; 546 no-map; 547 }; 548 549 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 550 reg = <0 0x82800000 0 0x4600000>; 551 no-map; 552 }; 553 554 mpss_mem: mpss-region@8a800000 { 555 reg = <0 0x8a800000 0 0x10800000>; 556 no-map; 557 }; 558 559 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 560 reg = <0 0x9b000000 0 0x80000>; 561 no-map; 562 }; 563 564 ipa_fw_mem: ipa-fw-region@9b080000 { 565 reg = <0 0x9b080000 0 0x10000>; 566 no-map; 567 }; 568 569 ipa_gsi_mem: ipa-gsi-region@9b090000 { 570 reg = <0 0x9b090000 0 0xa000>; 571 no-map; 572 }; 573 574 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 575 reg = <0 0x9b09a000 0 0x2000>; 576 no-map; 577 }; 578 579 spss_region_mem: spss-region@9b100000 { 580 reg = <0 0x9b100000 0 0x180000>; 581 no-map; 582 }; 583 584 /* First part of the "SPU secure shared memory" region */ 585 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 586 reg = <0 0x9b280000 0 0x60000>; 587 no-map; 588 }; 589 590 /* Second part of the "SPU secure shared memory" region */ 591 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 592 reg = <0 0x9b2e0000 0 0x20000>; 593 no-map; 594 }; 595 596 camera_mem: camera-region@9b300000 { 597 reg = <0 0x9b300000 0 0x800000>; 598 no-map; 599 }; 600 601 video_mem: video-region@9bb00000 { 602 reg = <0 0x9bb00000 0 0x700000>; 603 no-map; 604 }; 605 606 cvp_mem: cvp-region@9c200000 { 607 reg = <0 0x9c200000 0 0x700000>; 608 no-map; 609 }; 610 611 cdsp_mem: cdsp-region@9c900000 { 612 reg = <0 0x9c900000 0 0x2000000>; 613 no-map; 614 }; 615 616 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 617 reg = <0 0x9e900000 0 0x80000>; 618 no-map; 619 }; 620 621 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 622 reg = <0 0x9e980000 0 0x80000>; 623 no-map; 624 }; 625 626 adspslpi_mem: adspslpi-region@9ea00000 { 627 reg = <0 0x9ea00000 0 0x4080000>; 628 no-map; 629 }; 630 631 /* uefi region can be reused by apps */ 632 633 /* Linux kernel image is loaded at 0xa8000000 */ 634 635 rmtfs_mem: rmtfs-region@d4a80000 { 636 compatible = "qcom,rmtfs-mem"; 637 reg = <0x0 0xd4a80000 0x0 0x280000>; 638 no-map; 639 640 qcom,client-id = <1>; 641 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 642 }; 643 644 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 645 reg = <0 0xd4d00000 0 0x3300000>; 646 no-map; 647 }; 648 649 tz_reserved_mem: tz-reserved-region@d8000000 { 650 reg = <0 0xd8000000 0 0x100000>; 651 no-map; 652 }; 653 654 cpucp_fw_mem: cpucp-fw-region@d8140000 { 655 reg = <0 0xd8140000 0 0x1c0000>; 656 no-map; 657 }; 658 659 qtee_mem: qtee-region@d8300000 { 660 reg = <0 0xd8300000 0 0x500000>; 661 no-map; 662 }; 663 664 ta_mem: ta-region@d8800000 { 665 reg = <0 0xd8800000 0 0x8a00000>; 666 no-map; 667 }; 668 669 tz_tags_mem: tz-tags-region@e1200000 { 670 reg = <0 0xe1200000 0 0x2740000>; 671 no-map; 672 }; 673 674 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 675 reg = <0 0xe6440000 0 0x279000>; 676 no-map; 677 }; 678 679 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 680 reg = <0 0xf3600000 0 0x4aee000>; 681 no-map; 682 }; 683 684 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 685 reg = <0 0xf80ee000 0 0x1000>; 686 no-map; 687 }; 688 689 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 690 reg = <0 0xf80ef000 0 0x9000>; 691 no-map; 692 }; 693 694 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 695 reg = <0 0xf80f8000 0 0x4000>; 696 no-map; 697 }; 698 699 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 700 reg = <0 0xf80fc000 0 0x4000>; 701 no-map; 702 }; 703 704 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 705 reg = <0 0xf8100000 0 0x100000>; 706 no-map; 707 }; 708 709 oem_vm_mem: oem-vm-region@f8400000 { 710 reg = <0 0xf8400000 0 0x4800000>; 711 no-map; 712 }; 713 714 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 715 reg = <0 0xfcc00000 0 0x4000>; 716 no-map; 717 }; 718 719 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 720 reg = <0 0xfcc04000 0 0x100000>; 721 no-map; 722 }; 723 724 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 725 reg = <0 0xfce00000 0 0x2900000>; 726 no-map; 727 }; 728 729 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 730 reg = <0 0xff700000 0 0x100000>; 731 no-map; 732 }; 733 }; 734 735 smp2p-adsp { 736 compatible = "qcom,smp2p"; 737 qcom,smem = <443>, <429>; 738 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 739 IPCC_MPROC_SIGNAL_SMP2P 740 IRQ_TYPE_EDGE_RISING>; 741 mboxes = <&ipcc IPCC_CLIENT_LPASS 742 IPCC_MPROC_SIGNAL_SMP2P>; 743 744 qcom,local-pid = <0>; 745 qcom,remote-pid = <2>; 746 747 smp2p_adsp_out: master-kernel { 748 qcom,entry-name = "master-kernel"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 smp2p_adsp_in: slave-kernel { 753 qcom,entry-name = "slave-kernel"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-cdsp { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <94>, <432>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_CDSP 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <5>; 770 771 smp2p_cdsp_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 smp2p_cdsp_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 smp2p-modem { 784 compatible = "qcom,smp2p"; 785 qcom,smem = <435>, <428>; 786 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 787 IPCC_MPROC_SIGNAL_SMP2P 788 IRQ_TYPE_EDGE_RISING>; 789 mboxes = <&ipcc IPCC_CLIENT_MPSS 790 IPCC_MPROC_SIGNAL_SMP2P>; 791 792 qcom,local-pid = <0>; 793 qcom,remote-pid = <1>; 794 795 smp2p_modem_out: master-kernel { 796 qcom,entry-name = "master-kernel"; 797 #qcom,smem-state-cells = <1>; 798 }; 799 800 smp2p_modem_in: slave-kernel { 801 qcom,entry-name = "slave-kernel"; 802 interrupt-controller; 803 #interrupt-cells = <2>; 804 }; 805 806 ipa_smp2p_out: ipa-ap-to-modem { 807 qcom,entry-name = "ipa"; 808 #qcom,smem-state-cells = <1>; 809 }; 810 811 ipa_smp2p_in: ipa-modem-to-ap { 812 qcom,entry-name = "ipa"; 813 interrupt-controller; 814 #interrupt-cells = <2>; 815 }; 816 }; 817 818 soc: soc@0 { 819 compatible = "simple-bus"; 820 ranges = <0 0 0 0 0x10 0>; 821 dma-ranges = <0 0 0 0 0x10 0>; 822 823 #address-cells = <2>; 824 #size-cells = <2>; 825 826 gcc: clock-controller@100000 { 827 compatible = "qcom,sm8550-gcc"; 828 reg = <0 0x00100000 0 0x1f4200>; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 833 <&pcie0_phy>, 834 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 835 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 836 <&ufs_mem_phy 0>, 837 <&ufs_mem_phy 1>, 838 <&ufs_mem_phy 2>, 839 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 840 }; 841 842 ipcc: mailbox@408000 { 843 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 844 reg = <0 0x00408000 0 0x1000>; 845 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-controller; 847 #interrupt-cells = <3>; 848 #mbox-cells = <2>; 849 }; 850 851 gpi_dma2: dma-controller@800000 { 852 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 853 #dma-cells = <3>; 854 reg = <0 0x00800000 0 0x60000>; 855 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 867 dma-channels = <12>; 868 dma-channel-mask = <0x3e>; 869 iommus = <&apps_smmu 0x436 0>; 870 dma-coherent; 871 status = "disabled"; 872 }; 873 874 qupv3_id_1: geniqup@8c0000 { 875 compatible = "qcom,geni-se-qup"; 876 reg = <0 0x008c0000 0 0x2000>; 877 ranges; 878 clock-names = "m-ahb", "s-ahb"; 879 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 880 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 881 iommus = <&apps_smmu 0x423 0>; 882 dma-coherent; 883 #address-cells = <2>; 884 #size-cells = <2>; 885 status = "disabled"; 886 887 i2c8: i2c@880000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00880000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c8_data_clk>; 894 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 898 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 899 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 900 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 901 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 903 interconnect-names = "qup-core", "qup-config", "qup-memory"; 904 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 905 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 906 dma-names = "tx", "rx"; 907 power-domains = <&rpmhpd RPMHPD_CX>; 908 operating-points-v2 = <&qup_opp_table_120mhz>; 909 status = "disabled"; 910 }; 911 912 spi8: spi@880000 { 913 compatible = "qcom,geni-spi"; 914 reg = <0 0x00880000 0 0x4000>; 915 clock-names = "se"; 916 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 917 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 923 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 924 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", "qup-config", "qup-memory"; 927 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 928 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 929 dma-names = "tx", "rx"; 930 power-domains = <&rpmhpd RPMHPD_CX>; 931 operating-points-v2 = <&qup_opp_table_120mhz>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 i2c9: i2c@884000 { 938 compatible = "qcom,geni-i2c"; 939 reg = <0 0x00884000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_i2c9_data_clk>; 944 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 951 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", "qup-config", "qup-memory"; 954 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 955 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 956 dma-names = "tx", "rx"; 957 power-domains = <&rpmhpd RPMHPD_CX>; 958 operating-points-v2 = <&qup_opp_table_120mhz>; 959 status = "disabled"; 960 }; 961 962 spi9: spi@884000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0 0x00884000 0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 967 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 970 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 971 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 973 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 974 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 975 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 976 interconnect-names = "qup-core", "qup-config", "qup-memory"; 977 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 978 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 979 dma-names = "tx", "rx"; 980 power-domains = <&rpmhpd RPMHPD_CX>; 981 operating-points-v2 = <&qup_opp_table_120mhz>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c10: i2c@888000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00888000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c10_data_clk>; 994 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 998 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 999 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1000 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1001 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1002 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1003 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1004 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1005 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1006 dma-names = "tx", "rx"; 1007 power-domains = <&rpmhpd RPMHPD_CX>; 1008 operating-points-v2 = <&qup_opp_table_120mhz>; 1009 status = "disabled"; 1010 }; 1011 1012 spi10: spi@888000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00888000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1017 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1021 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1023 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1024 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1026 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1027 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1028 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1029 dma-names = "tx", "rx"; 1030 power-domains = <&rpmhpd RPMHPD_CX>; 1031 operating-points-v2 = <&qup_opp_table_120mhz>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 i2c11: i2c@88c000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0 0x0088c000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_i2c11_data_clk>; 1044 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1048 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1049 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1050 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1051 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1052 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1053 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1054 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1055 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1056 dma-names = "tx", "rx"; 1057 power-domains = <&rpmhpd RPMHPD_CX>; 1058 operating-points-v2 = <&qup_opp_table_120mhz>; 1059 status = "disabled"; 1060 }; 1061 1062 spi11: spi@88c000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x0088c000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1067 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1071 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1072 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1073 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1074 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1075 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1076 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1077 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1078 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 power-domains = <&rpmhpd RPMHPD_CX>; 1081 operating-points-v2 = <&qup_opp_table_120mhz>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 i2c12: i2c@890000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00890000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_i2c12_data_clk>; 1094 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1098 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1099 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1100 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1101 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1102 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1103 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1104 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1106 dma-names = "tx", "rx"; 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 operating-points-v2 = <&qup_opp_table_120mhz>; 1109 status = "disabled"; 1110 }; 1111 1112 spi12: spi@890000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1117 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1126 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1127 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1128 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1129 dma-names = "tx", "rx"; 1130 power-domains = <&rpmhpd RPMHPD_CX>; 1131 operating-points-v2 = <&qup_opp_table_120mhz>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c13: i2c@894000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00894000 0 0x4000>; 1140 clock-names = "se"; 1141 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_i2c13_data_clk>; 1144 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1148 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1149 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1150 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1151 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1152 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1153 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1154 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1155 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 power-domains = <&rpmhpd RPMHPD_CX>; 1158 operating-points-v2 = <&qup_opp_table_120mhz>; 1159 status = "disabled"; 1160 }; 1161 1162 spi13: spi@894000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00894000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1167 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1174 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1177 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1178 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&rpmhpd RPMHPD_CX>; 1181 operating-points-v2 = <&qup_opp_table_120mhz>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart14: serial@898000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x898000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1194 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1196 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1197 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1198 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 power-domains = <&rpmhpd RPMHPD_CX>; 1201 operating-points-v2 = <&qup_opp_table_125mhz>; 1202 status = "disabled"; 1203 }; 1204 1205 i2c15: i2c@89c000 { 1206 compatible = "qcom,geni-i2c"; 1207 reg = <0 0x0089c000 0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_i2c15_data_clk>; 1212 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1216 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1217 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1218 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1219 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1222 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1223 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&rpmhpd RPMHPD_CX>; 1226 operating-points-v2 = <&qup_opp_table_100mhz>; 1227 status = "disabled"; 1228 }; 1229 1230 spi15: spi@89c000 { 1231 compatible = "qcom,geni-spi"; 1232 reg = <0 0x0089c000 0 0x4000>; 1233 clock-names = "se"; 1234 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1235 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1239 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1241 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1242 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1244 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1245 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1246 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1247 dma-names = "tx", "rx"; 1248 power-domains = <&rpmhpd RPMHPD_CX>; 1249 operating-points-v2 = <&qup_opp_table_100mhz>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 }; 1255 1256 i2c_master_hub_0: geniqup@9c0000 { 1257 compatible = "qcom,geni-se-i2c-master-hub"; 1258 reg = <0x0 0x009c0000 0x0 0x2000>; 1259 clock-names = "s-ahb"; 1260 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1261 #address-cells = <2>; 1262 #size-cells = <2>; 1263 ranges; 1264 status = "disabled"; 1265 1266 i2c_hub_0: i2c@980000 { 1267 compatible = "qcom,geni-i2c-master-hub"; 1268 reg = <0x0 0x00980000 0x0 0x4000>; 1269 clock-names = "se", "core"; 1270 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1271 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&hub_i2c0_data_clk>; 1274 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1278 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1280 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1281 interconnect-names = "qup-core", "qup-config"; 1282 power-domains = <&rpmhpd RPMHPD_CX>; 1283 required-opps = <&rpmhpd_opp_low_svs>; 1284 status = "disabled"; 1285 }; 1286 1287 i2c_hub_1: i2c@984000 { 1288 compatible = "qcom,geni-i2c-master-hub"; 1289 reg = <0x0 0x00984000 0x0 0x4000>; 1290 clock-names = "se", "core"; 1291 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1292 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&hub_i2c1_data_clk>; 1295 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1299 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1300 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1301 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1302 interconnect-names = "qup-core", "qup-config"; 1303 power-domains = <&rpmhpd RPMHPD_CX>; 1304 required-opps = <&rpmhpd_opp_low_svs>; 1305 status = "disabled"; 1306 }; 1307 1308 i2c_hub_2: i2c@988000 { 1309 compatible = "qcom,geni-i2c-master-hub"; 1310 reg = <0x0 0x00988000 0x0 0x4000>; 1311 clock-names = "se", "core"; 1312 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1313 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&hub_i2c2_data_clk>; 1316 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1320 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1321 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1322 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1323 interconnect-names = "qup-core", "qup-config"; 1324 power-domains = <&rpmhpd RPMHPD_CX>; 1325 required-opps = <&rpmhpd_opp_low_svs>; 1326 status = "disabled"; 1327 }; 1328 1329 i2c_hub_3: i2c@98c000 { 1330 compatible = "qcom,geni-i2c-master-hub"; 1331 reg = <0x0 0x0098c000 0x0 0x4000>; 1332 clock-names = "se", "core"; 1333 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1334 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&hub_i2c3_data_clk>; 1337 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1341 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1343 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1344 interconnect-names = "qup-core", "qup-config"; 1345 power-domains = <&rpmhpd RPMHPD_CX>; 1346 required-opps = <&rpmhpd_opp_low_svs>; 1347 status = "disabled"; 1348 }; 1349 1350 i2c_hub_4: i2c@990000 { 1351 compatible = "qcom,geni-i2c-master-hub"; 1352 reg = <0x0 0x00990000 0x0 0x4000>; 1353 clock-names = "se", "core"; 1354 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1355 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&hub_i2c4_data_clk>; 1358 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1362 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1363 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1364 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1365 interconnect-names = "qup-core", "qup-config"; 1366 power-domains = <&rpmhpd RPMHPD_CX>; 1367 required-opps = <&rpmhpd_opp_low_svs>; 1368 status = "disabled"; 1369 }; 1370 1371 i2c_hub_5: i2c@994000 { 1372 compatible = "qcom,geni-i2c-master-hub"; 1373 reg = <0 0x00994000 0 0x4000>; 1374 clock-names = "se", "core"; 1375 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1376 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&hub_i2c5_data_clk>; 1379 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1383 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1384 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1385 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1386 interconnect-names = "qup-core", "qup-config"; 1387 power-domains = <&rpmhpd RPMHPD_CX>; 1388 required-opps = <&rpmhpd_opp_low_svs>; 1389 status = "disabled"; 1390 }; 1391 1392 i2c_hub_6: i2c@998000 { 1393 compatible = "qcom,geni-i2c-master-hub"; 1394 reg = <0 0x00998000 0 0x4000>; 1395 clock-names = "se", "core"; 1396 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1397 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1398 pinctrl-names = "default"; 1399 pinctrl-0 = <&hub_i2c6_data_clk>; 1400 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1404 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1405 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1406 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1407 interconnect-names = "qup-core", "qup-config"; 1408 power-domains = <&rpmhpd RPMHPD_CX>; 1409 required-opps = <&rpmhpd_opp_low_svs>; 1410 status = "disabled"; 1411 }; 1412 1413 i2c_hub_7: i2c@99c000 { 1414 compatible = "qcom,geni-i2c-master-hub"; 1415 reg = <0 0x0099c000 0 0x4000>; 1416 clock-names = "se", "core"; 1417 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1418 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&hub_i2c7_data_clk>; 1421 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1425 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1426 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1427 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1428 interconnect-names = "qup-core", "qup-config"; 1429 power-domains = <&rpmhpd RPMHPD_CX>; 1430 required-opps = <&rpmhpd_opp_low_svs>; 1431 status = "disabled"; 1432 }; 1433 1434 i2c_hub_8: i2c@9a0000 { 1435 compatible = "qcom,geni-i2c-master-hub"; 1436 reg = <0 0x009a0000 0 0x4000>; 1437 clock-names = "se", "core"; 1438 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1439 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&hub_i2c8_data_clk>; 1442 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1446 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1448 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 power-domains = <&rpmhpd RPMHPD_CX>; 1451 required-opps = <&rpmhpd_opp_low_svs>; 1452 status = "disabled"; 1453 }; 1454 1455 i2c_hub_9: i2c@9a4000 { 1456 compatible = "qcom,geni-i2c-master-hub"; 1457 reg = <0 0x009a4000 0 0x4000>; 1458 clock-names = "se", "core"; 1459 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1460 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&hub_i2c9_data_clk>; 1463 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1469 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 power-domains = <&rpmhpd RPMHPD_CX>; 1472 required-opps = <&rpmhpd_opp_low_svs>; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 gpi_dma1: dma-controller@a00000 { 1478 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1479 #dma-cells = <3>; 1480 reg = <0 0x00a00000 0 0x60000>; 1481 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1493 dma-channels = <12>; 1494 dma-channel-mask = <0x1e>; 1495 iommus = <&apps_smmu 0xb6 0>; 1496 dma-coherent; 1497 status = "disabled"; 1498 }; 1499 1500 qupv3_id_0: geniqup@ac0000 { 1501 compatible = "qcom,geni-se-qup"; 1502 reg = <0 0x00ac0000 0 0x2000>; 1503 ranges; 1504 clock-names = "m-ahb", "s-ahb"; 1505 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1506 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1507 iommus = <&apps_smmu 0xa3 0>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1509 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1510 interconnect-names = "qup-core"; 1511 dma-coherent; 1512 #address-cells = <2>; 1513 #size-cells = <2>; 1514 status = "disabled"; 1515 1516 i2c0: i2c@a80000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00a80000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c0_data_clk>; 1523 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1527 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1528 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1529 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1530 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1531 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1532 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1533 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1534 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1535 dma-names = "tx", "rx"; 1536 power-domains = <&rpmhpd RPMHPD_CX>; 1537 operating-points-v2 = <&qup_opp_table_120mhz>; 1538 status = "disabled"; 1539 }; 1540 1541 spi0: spi@a80000 { 1542 compatible = "qcom,geni-spi"; 1543 reg = <0 0x00a80000 0 0x4000>; 1544 clock-names = "se"; 1545 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1546 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1549 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1550 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1552 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1553 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1555 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1556 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1557 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1558 dma-names = "tx", "rx"; 1559 power-domains = <&rpmhpd RPMHPD_CX>; 1560 operating-points-v2 = <&qup_opp_table_120mhz>; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 status = "disabled"; 1564 }; 1565 1566 i2c1: i2c@a84000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a84000 0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_i2c1_data_clk>; 1573 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1577 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1578 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1579 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1580 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1581 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1582 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1583 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 power-domains = <&rpmhpd RPMHPD_CX>; 1587 operating-points-v2 = <&qup_opp_table_120mhz>; 1588 status = "disabled"; 1589 }; 1590 1591 spi1: spi@a84000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a84000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1596 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1599 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1600 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1601 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1602 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1603 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1604 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 power-domains = <&rpmhpd RPMHPD_CX>; 1610 operating-points-v2 = <&qup_opp_table_120mhz>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c2: i2c@a88000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a88000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c2_data_clk>; 1623 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1627 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1629 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1630 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1632 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1633 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1634 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 power-domains = <&rpmhpd RPMHPD_CX>; 1637 operating-points-v2 = <&qup_opp_table_100mhz>; 1638 status = "disabled"; 1639 }; 1640 1641 spi2: spi@a88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00a88000 0 0x4000>; 1644 clock-names = "se"; 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1646 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1647 pinctrl-names = "default"; 1648 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1650 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1651 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1652 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1653 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1654 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1655 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1657 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1658 dma-names = "tx", "rx"; 1659 power-domains = <&rpmhpd RPMHPD_CX>; 1660 operating-points-v2 = <&qup_opp_table_100mhz>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 status = "disabled"; 1664 }; 1665 1666 i2c3: i2c@a8c000 { 1667 compatible = "qcom,geni-i2c"; 1668 reg = <0 0x00a8c000 0 0x4000>; 1669 clock-names = "se"; 1670 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&qup_i2c3_data_clk>; 1673 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1677 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1679 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1680 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1682 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1683 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1684 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1685 dma-names = "tx", "rx"; 1686 power-domains = <&rpmhpd RPMHPD_CX>; 1687 operating-points-v2 = <&qup_opp_table_100mhz>; 1688 status = "disabled"; 1689 }; 1690 1691 spi3: spi@a8c000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0 0x00a8c000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1696 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1699 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1700 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1701 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1702 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1703 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1704 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1705 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1706 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1707 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1708 dma-names = "tx", "rx"; 1709 power-domains = <&rpmhpd RPMHPD_CX>; 1710 operating-points-v2 = <&qup_opp_table_100mhz>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 i2c4: i2c@a90000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x00a90000 0 0x4000>; 1719 clock-names = "se"; 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&qup_i2c4_data_clk>; 1723 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1727 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1728 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1729 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1730 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1731 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1732 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1734 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1735 dma-names = "tx", "rx"; 1736 power-domains = <&rpmhpd RPMHPD_CX>; 1737 operating-points-v2 = <&qup_opp_table_100mhz>; 1738 status = "disabled"; 1739 }; 1740 1741 spi4: spi@a90000 { 1742 compatible = "qcom,geni-spi"; 1743 reg = <0 0x00a90000 0 0x4000>; 1744 clock-names = "se"; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1746 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1749 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1750 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1752 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1753 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1755 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1756 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1757 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1758 dma-names = "tx", "rx"; 1759 power-domains = <&rpmhpd RPMHPD_CX>; 1760 operating-points-v2 = <&qup_opp_table_100mhz>; 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 status = "disabled"; 1764 }; 1765 1766 i2c5: i2c@a94000 { 1767 compatible = "qcom,geni-i2c"; 1768 reg = <0 0x00a94000 0 0x4000>; 1769 clock-names = "se"; 1770 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1771 pinctrl-names = "default"; 1772 pinctrl-0 = <&qup_i2c5_data_clk>; 1773 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1774 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1775 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1776 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1777 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1778 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1779 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1780 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1781 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1782 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1783 dma-names = "tx", "rx"; 1784 power-domains = <&rpmhpd RPMHPD_CX>; 1785 operating-points-v2 = <&qup_opp_table_100mhz>; 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 status = "disabled"; 1789 }; 1790 1791 spi5: spi@a94000 { 1792 compatible = "qcom,geni-spi"; 1793 reg = <0 0x00a94000 0 0x4000>; 1794 clock-names = "se"; 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1796 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1799 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1800 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1801 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1802 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1803 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1804 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1805 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1806 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1807 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1808 dma-names = "tx", "rx"; 1809 power-domains = <&rpmhpd RPMHPD_CX>; 1810 operating-points-v2 = <&qup_opp_table_100mhz>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 status = "disabled"; 1814 }; 1815 1816 i2c6: i2c@a98000 { 1817 compatible = "qcom,geni-i2c"; 1818 reg = <0 0x00a98000 0 0x4000>; 1819 clock-names = "se"; 1820 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1821 pinctrl-names = "default"; 1822 pinctrl-0 = <&qup_i2c6_data_clk>; 1823 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1824 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1825 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1826 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1827 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1828 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1830 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1831 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1832 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1833 dma-names = "tx", "rx"; 1834 power-domains = <&rpmhpd RPMHPD_CX>; 1835 operating-points-v2 = <&qup_opp_table_100mhz>; 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 status = "disabled"; 1839 }; 1840 1841 spi6: spi@a98000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0 0x00a98000 0 0x4000>; 1844 clock-names = "se"; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1846 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1851 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1852 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1853 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1856 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 power-domains = <&rpmhpd RPMHPD_CX>; 1860 operating-points-v2 = <&qup_opp_table_100mhz>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 status = "disabled"; 1864 }; 1865 1866 uart7: serial@a9c000 { 1867 compatible = "qcom,geni-debug-uart"; 1868 reg = <0 0x00a9c000 0 0x4000>; 1869 clock-names = "se"; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1871 pinctrl-names = "default"; 1872 pinctrl-0 = <&qup_uart7_default>; 1873 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1876 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1877 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1878 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1879 power-domains = <&rpmhpd RPMHPD_CX>; 1880 operating-points-v2 = <&qup_opp_table_100mhz>; 1881 status = "disabled"; 1882 }; 1883 }; 1884 1885 cnoc_main: interconnect@1500000 { 1886 compatible = "qcom,sm8550-cnoc-main"; 1887 reg = <0 0x01500000 0 0x13080>; 1888 #interconnect-cells = <2>; 1889 qcom,bcm-voters = <&apps_bcm_voter>; 1890 }; 1891 1892 config_noc: interconnect@1600000 { 1893 compatible = "qcom,sm8550-config-noc"; 1894 reg = <0 0x01600000 0 0x6200>; 1895 #interconnect-cells = <2>; 1896 qcom,bcm-voters = <&apps_bcm_voter>; 1897 }; 1898 1899 system_noc: interconnect@1680000 { 1900 compatible = "qcom,sm8550-system-noc"; 1901 reg = <0 0x01680000 0 0x1d080>; 1902 #interconnect-cells = <2>; 1903 qcom,bcm-voters = <&apps_bcm_voter>; 1904 }; 1905 1906 pcie_noc: interconnect@16c0000 { 1907 compatible = "qcom,sm8550-pcie-anoc"; 1908 reg = <0 0x016c0000 0 0x12200>; 1909 #interconnect-cells = <2>; 1910 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1911 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1912 qcom,bcm-voters = <&apps_bcm_voter>; 1913 }; 1914 1915 aggre1_noc: interconnect@16e0000 { 1916 compatible = "qcom,sm8550-aggre1-noc"; 1917 reg = <0 0x016e0000 0 0x14400>; 1918 #interconnect-cells = <2>; 1919 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1920 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1921 qcom,bcm-voters = <&apps_bcm_voter>; 1922 }; 1923 1924 aggre2_noc: interconnect@1700000 { 1925 compatible = "qcom,sm8550-aggre2-noc"; 1926 reg = <0 0x01700000 0 0x1e400>; 1927 #interconnect-cells = <2>; 1928 clocks = <&rpmhcc RPMH_IPA_CLK>; 1929 qcom,bcm-voters = <&apps_bcm_voter>; 1930 }; 1931 1932 mmss_noc: interconnect@1780000 { 1933 compatible = "qcom,sm8550-mmss-noc"; 1934 reg = <0 0x01780000 0 0x5b800>; 1935 #interconnect-cells = <2>; 1936 qcom,bcm-voters = <&apps_bcm_voter>; 1937 }; 1938 1939 rng: rng@10c3000 { 1940 compatible = "qcom,sm8550-trng", "qcom,trng"; 1941 reg = <0 0x010c3000 0 0x1000>; 1942 }; 1943 1944 pcie0: pcie@1c00000 { 1945 device_type = "pci"; 1946 compatible = "qcom,pcie-sm8550"; 1947 reg = <0 0x01c00000 0 0x3000>, 1948 <0 0x60000000 0 0xf1d>, 1949 <0 0x60000f20 0 0xa8>, 1950 <0 0x60001000 0 0x1000>, 1951 <0 0x60100000 0 0x100000>; 1952 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1953 #address-cells = <3>; 1954 #size-cells = <2>; 1955 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1956 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1957 bus-range = <0x00 0xff>; 1958 1959 dma-coherent; 1960 1961 linux,pci-domain = <0>; 1962 num-lanes = <2>; 1963 1964 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "msi0", 1974 "msi1", 1975 "msi2", 1976 "msi3", 1977 "msi4", 1978 "msi5", 1979 "msi6", 1980 "msi7", 1981 "global"; 1982 #interrupt-cells = <1>; 1983 interrupt-map-mask = <0 0 0 0x7>; 1984 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1985 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1986 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1987 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1988 1989 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1990 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1991 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1992 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1993 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1994 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1995 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1996 clock-names = "aux", 1997 "cfg", 1998 "bus_master", 1999 "bus_slave", 2000 "slave_q2a", 2001 "ddrss_sf_tbu", 2002 "noc_aggr"; 2003 2004 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2006 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2007 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2008 interconnect-names = "pcie-mem", "cpu-pcie"; 2009 2010 msi-map = <0x0 &gic_its 0x1400 0x1>, 2011 <0x100 &gic_its 0x1401 0x1>; 2012 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 2013 <0x100 &apps_smmu 0x1401 0x1>; 2014 2015 resets = <&gcc GCC_PCIE_0_BCR>; 2016 reset-names = "pci"; 2017 2018 power-domains = <&gcc PCIE_0_GDSC>; 2019 2020 phys = <&pcie0_phy>; 2021 phy-names = "pciephy"; 2022 2023 operating-points-v2 = <&pcie0_opp_table>; 2024 2025 status = "disabled"; 2026 2027 pcie0_opp_table: opp-table { 2028 compatible = "operating-points-v2"; 2029 2030 /* GEN 1 x1 */ 2031 opp-2500000 { 2032 opp-hz = /bits/ 64 <2500000>; 2033 required-opps = <&rpmhpd_opp_low_svs>; 2034 opp-peak-kBps = <250000 1>; 2035 }; 2036 2037 /* GEN 1 x2 and GEN 2 x1 */ 2038 opp-5000000 { 2039 opp-hz = /bits/ 64 <5000000>; 2040 required-opps = <&rpmhpd_opp_low_svs>; 2041 opp-peak-kBps = <500000 1>; 2042 }; 2043 2044 /* GEN 2 x2 */ 2045 opp-10000000 { 2046 opp-hz = /bits/ 64 <10000000>; 2047 required-opps = <&rpmhpd_opp_low_svs>; 2048 opp-peak-kBps = <1000000 1>; 2049 }; 2050 2051 /* GEN 3 x1 */ 2052 opp-8000000 { 2053 opp-hz = /bits/ 64 <8000000>; 2054 required-opps = <&rpmhpd_opp_nom>; 2055 opp-peak-kBps = <984500 1>; 2056 }; 2057 2058 /* GEN 3 x2 */ 2059 opp-16000000 { 2060 opp-hz = /bits/ 64 <16000000>; 2061 required-opps = <&rpmhpd_opp_nom>; 2062 opp-peak-kBps = <1969000 1>; 2063 }; 2064 }; 2065 2066 pcieport0: pcie@0 { 2067 device_type = "pci"; 2068 reg = <0x0 0x0 0x0 0x0 0x0>; 2069 bus-range = <0x01 0xff>; 2070 2071 #address-cells = <3>; 2072 #size-cells = <2>; 2073 ranges; 2074 }; 2075 }; 2076 2077 pcie0_phy: phy@1c06000 { 2078 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 2079 reg = <0 0x01c06000 0 0x2000>; 2080 2081 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2082 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2083 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2084 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2085 <&gcc GCC_PCIE_0_PIPE_CLK>; 2086 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2087 "pipe"; 2088 2089 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2090 reset-names = "phy"; 2091 2092 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2093 assigned-clock-rates = <100000000>; 2094 2095 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2096 2097 #clock-cells = <0>; 2098 clock-output-names = "pcie0_pipe_clk"; 2099 2100 #phy-cells = <0>; 2101 2102 status = "disabled"; 2103 }; 2104 2105 pcie1: pcie@1c08000 { 2106 device_type = "pci"; 2107 compatible = "qcom,pcie-sm8550"; 2108 reg = <0x0 0x01c08000 0x0 0x3000>, 2109 <0x0 0x40000000 0x0 0xf1d>, 2110 <0x0 0x40000f20 0x0 0xa8>, 2111 <0x0 0x40001000 0x0 0x1000>, 2112 <0x0 0x40100000 0x0 0x100000>; 2113 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2114 #address-cells = <3>; 2115 #size-cells = <2>; 2116 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2117 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2118 bus-range = <0x00 0xff>; 2119 2120 dma-coherent; 2121 2122 linux,pci-domain = <1>; 2123 num-lanes = <2>; 2124 2125 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2134 interrupt-names = "msi0", 2135 "msi1", 2136 "msi2", 2137 "msi3", 2138 "msi4", 2139 "msi5", 2140 "msi6", 2141 "msi7", 2142 "global"; 2143 #interrupt-cells = <1>; 2144 interrupt-map-mask = <0 0 0 0x7>; 2145 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2146 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2147 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2148 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2149 2150 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2151 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2152 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2153 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2154 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2155 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2156 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2157 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2158 clock-names = "aux", 2159 "cfg", 2160 "bus_master", 2161 "bus_slave", 2162 "slave_q2a", 2163 "ddrss_sf_tbu", 2164 "noc_aggr", 2165 "cnoc_sf_axi"; 2166 2167 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2168 assigned-clock-rates = <19200000>; 2169 2170 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2173 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2174 interconnect-names = "pcie-mem", "cpu-pcie"; 2175 2176 msi-map = <0x0 &gic_its 0x1480 0x1>, 2177 <0x100 &gic_its 0x1481 0x1>; 2178 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 2179 <0x100 &apps_smmu 0x1481 0x1>; 2180 2181 resets = <&gcc GCC_PCIE_1_BCR>, 2182 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2183 reset-names = "pci", "link_down"; 2184 2185 power-domains = <&gcc PCIE_1_GDSC>; 2186 2187 phys = <&pcie1_phy>; 2188 phy-names = "pciephy"; 2189 2190 operating-points-v2 = <&pcie1_opp_table>; 2191 2192 status = "disabled"; 2193 2194 pcie1_opp_table: opp-table { 2195 compatible = "operating-points-v2"; 2196 2197 /* GEN 1 x1 */ 2198 opp-2500000 { 2199 opp-hz = /bits/ 64 <2500000>; 2200 required-opps = <&rpmhpd_opp_low_svs>; 2201 opp-peak-kBps = <250000 1>; 2202 }; 2203 2204 /* GEN 1 x2 and GEN 2 x1 */ 2205 opp-5000000 { 2206 opp-hz = /bits/ 64 <5000000>; 2207 required-opps = <&rpmhpd_opp_low_svs>; 2208 opp-peak-kBps = <500000 1>; 2209 }; 2210 2211 /* GEN 2 x2 */ 2212 opp-10000000 { 2213 opp-hz = /bits/ 64 <10000000>; 2214 required-opps = <&rpmhpd_opp_low_svs>; 2215 opp-peak-kBps = <1000000 1>; 2216 }; 2217 2218 /* GEN 3 x1 */ 2219 opp-8000000 { 2220 opp-hz = /bits/ 64 <8000000>; 2221 required-opps = <&rpmhpd_opp_nom>; 2222 opp-peak-kBps = <984500 1>; 2223 }; 2224 2225 /* GEN 3 x2 and GEN 4 x1 */ 2226 opp-16000000 { 2227 opp-hz = /bits/ 64 <16000000>; 2228 required-opps = <&rpmhpd_opp_nom>; 2229 opp-peak-kBps = <1969000 1>; 2230 }; 2231 2232 /* GEN 4 x2 */ 2233 opp-32000000 { 2234 opp-hz = /bits/ 64 <32000000>; 2235 required-opps = <&rpmhpd_opp_nom>; 2236 opp-peak-kBps = <3938000 1>; 2237 }; 2238 }; 2239 2240 pcie@0 { 2241 device_type = "pci"; 2242 reg = <0x0 0x0 0x0 0x0 0x0>; 2243 bus-range = <0x01 0xff>; 2244 2245 #address-cells = <3>; 2246 #size-cells = <2>; 2247 ranges; 2248 }; 2249 }; 2250 2251 pcie1_phy: phy@1c0e000 { 2252 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 2253 reg = <0x0 0x01c0e000 0x0 0x2000>; 2254 2255 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2256 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2257 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2258 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2259 <&gcc GCC_PCIE_1_PIPE_CLK>; 2260 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2261 "pipe"; 2262 2263 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2264 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2265 reset-names = "phy", "phy_nocsr"; 2266 2267 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2268 assigned-clock-rates = <100000000>; 2269 2270 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2271 2272 #clock-cells = <1>; 2273 clock-output-names = "pcie1_pipe_clk"; 2274 2275 #phy-cells = <0>; 2276 2277 status = "disabled"; 2278 }; 2279 2280 cryptobam: dma-controller@1dc4000 { 2281 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2282 reg = <0x0 0x01dc4000 0x0 0x28000>; 2283 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2284 #dma-cells = <1>; 2285 qcom,ee = <0>; 2286 qcom,num-ees = <4>; 2287 num-channels = <20>; 2288 qcom,controlled-remotely; 2289 iommus = <&apps_smmu 0x480 0x0>, 2290 <&apps_smmu 0x481 0x0>; 2291 }; 2292 2293 crypto: crypto@1dfa000 { 2294 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 2295 reg = <0x0 0x01dfa000 0x0 0x6000>; 2296 dmas = <&cryptobam 4>, <&cryptobam 5>; 2297 dma-names = "rx", "tx"; 2298 iommus = <&apps_smmu 0x480 0x0>, 2299 <&apps_smmu 0x481 0x0>; 2300 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2301 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2302 interconnect-names = "memory"; 2303 }; 2304 2305 ufs_mem_phy: phy@1d80000 { 2306 compatible = "qcom,sm8550-qmp-ufs-phy"; 2307 reg = <0x0 0x01d80000 0x0 0x2000>; 2308 clocks = <&rpmhcc RPMH_CXO_CLK>, 2309 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2310 <&tcsr TCSR_UFS_CLKREF_EN>; 2311 clock-names = "ref", 2312 "ref_aux", 2313 "qref"; 2314 2315 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2316 2317 resets = <&ufs_mem_hc 0>; 2318 reset-names = "ufsphy"; 2319 2320 #clock-cells = <1>; 2321 #phy-cells = <0>; 2322 2323 status = "disabled"; 2324 }; 2325 2326 ufs_mem_hc: ufshc@1d84000 { 2327 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 2328 "jedec,ufs-2.0"; 2329 reg = <0x0 0x01d84000 0x0 0x3000>; 2330 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2331 phys = <&ufs_mem_phy>; 2332 phy-names = "ufsphy"; 2333 lanes-per-direction = <2>; 2334 #reset-cells = <1>; 2335 resets = <&gcc GCC_UFS_PHY_BCR>; 2336 reset-names = "rst"; 2337 2338 power-domains = <&gcc UFS_PHY_GDSC>; 2339 required-opps = <&rpmhpd_opp_nom>; 2340 2341 iommus = <&apps_smmu 0x60 0x0>; 2342 dma-coherent; 2343 2344 operating-points-v2 = <&ufs_opp_table>; 2345 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2348 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2349 2350 interconnect-names = "ufs-ddr", "cpu-ufs"; 2351 clock-names = "core_clk", 2352 "bus_aggr_clk", 2353 "iface_clk", 2354 "core_clk_unipro", 2355 "ref_clk", 2356 "tx_lane0_sync_clk", 2357 "rx_lane0_sync_clk", 2358 "rx_lane1_sync_clk"; 2359 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2360 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2361 <&gcc GCC_UFS_PHY_AHB_CLK>, 2362 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2363 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2364 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2365 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2366 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2367 qcom,ice = <&ice>; 2368 2369 status = "disabled"; 2370 2371 ufs_opp_table: opp-table { 2372 compatible = "operating-points-v2"; 2373 2374 opp-75000000 { 2375 opp-hz = /bits/ 64 <75000000>, 2376 /bits/ 64 <0>, 2377 /bits/ 64 <0>, 2378 /bits/ 64 <75000000>, 2379 /bits/ 64 <0>, 2380 /bits/ 64 <0>, 2381 /bits/ 64 <0>, 2382 /bits/ 64 <0>; 2383 required-opps = <&rpmhpd_opp_low_svs>; 2384 }; 2385 2386 opp-150000000 { 2387 opp-hz = /bits/ 64 <150000000>, 2388 /bits/ 64 <0>, 2389 /bits/ 64 <0>, 2390 /bits/ 64 <150000000>, 2391 /bits/ 64 <0>, 2392 /bits/ 64 <0>, 2393 /bits/ 64 <0>, 2394 /bits/ 64 <0>; 2395 required-opps = <&rpmhpd_opp_svs>; 2396 }; 2397 2398 opp-300000000 { 2399 opp-hz = /bits/ 64 <300000000>, 2400 /bits/ 64 <0>, 2401 /bits/ 64 <0>, 2402 /bits/ 64 <300000000>, 2403 /bits/ 64 <0>, 2404 /bits/ 64 <0>, 2405 /bits/ 64 <0>, 2406 /bits/ 64 <0>; 2407 required-opps = <&rpmhpd_opp_nom>; 2408 }; 2409 }; 2410 }; 2411 2412 ice: crypto@1d88000 { 2413 compatible = "qcom,sm8550-inline-crypto-engine", 2414 "qcom,inline-crypto-engine"; 2415 reg = <0 0x01d88000 0 0x18000>; 2416 2417 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2418 }; 2419 2420 tcsr_mutex: hwlock@1f40000 { 2421 compatible = "qcom,tcsr-mutex"; 2422 reg = <0 0x01f40000 0 0x20000>; 2423 #hwlock-cells = <1>; 2424 }; 2425 2426 tcsr: clock-controller@1fc0000 { 2427 compatible = "qcom,sm8550-tcsr", "syscon"; 2428 reg = <0 0x01fc0000 0 0x30000>; 2429 clocks = <&rpmhcc RPMH_CXO_CLK>; 2430 #clock-cells = <1>; 2431 #reset-cells = <1>; 2432 }; 2433 2434 gpu: gpu@3d00000 { 2435 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2436 reg = <0x0 0x03d00000 0x0 0x40000>, 2437 <0x0 0x03d9e000 0x0 0x1000>, 2438 <0x0 0x03d61000 0x0 0x800>; 2439 reg-names = "kgsl_3d0_reg_memory", 2440 "cx_mem", 2441 "cx_dbgc"; 2442 2443 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2444 2445 iommus = <&adreno_smmu 0 0x0>, 2446 <&adreno_smmu 1 0x0>; 2447 2448 operating-points-v2 = <&gpu_opp_table>; 2449 2450 qcom,gmu = <&gmu>; 2451 #cooling-cells = <2>; 2452 2453 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 2454 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2455 interconnect-names = "gfx-mem"; 2456 2457 status = "disabled"; 2458 2459 zap-shader { 2460 memory-region = <&gpu_micro_code_mem>; 2461 }; 2462 2463 /* Speedbin needs more work on A740+, keep only lower freqs */ 2464 gpu_opp_table: opp-table { 2465 compatible = "operating-points-v2"; 2466 2467 opp-680000000 { 2468 opp-hz = /bits/ 64 <680000000>; 2469 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2470 opp-peak-kBps = <16500000>; 2471 }; 2472 2473 opp-615000000 { 2474 opp-hz = /bits/ 64 <615000000>; 2475 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2476 opp-peak-kBps = <12449218>; 2477 }; 2478 2479 opp-550000000 { 2480 opp-hz = /bits/ 64 <550000000>; 2481 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2482 opp-peak-kBps = <10687500>; 2483 }; 2484 2485 opp-475000000 { 2486 opp-hz = /bits/ 64 <475000000>; 2487 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2488 opp-peak-kBps = <6074218>; 2489 }; 2490 2491 opp-401000000 { 2492 opp-hz = /bits/ 64 <401000000>; 2493 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2494 opp-peak-kBps = <6074218>; 2495 }; 2496 2497 opp-348000000 { 2498 opp-hz = /bits/ 64 <348000000>; 2499 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2500 opp-peak-kBps = <6074218>; 2501 }; 2502 2503 opp-295000000 { 2504 opp-hz = /bits/ 64 <295000000>; 2505 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2506 opp-peak-kBps = <6074218>; 2507 }; 2508 2509 opp-220000000 { 2510 opp-hz = /bits/ 64 <220000000>; 2511 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2512 opp-peak-kBps = <2136718>; 2513 }; 2514 }; 2515 }; 2516 2517 gmu: gmu@3d6a000 { 2518 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2519 reg = <0x0 0x03d6a000 0x0 0x35000>, 2520 <0x0 0x03d50000 0x0 0x10000>, 2521 <0x0 0x0b280000 0x0 0x10000>; 2522 reg-names = "gmu", "rscc", "gmu_pdc"; 2523 2524 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2526 interrupt-names = "hfi", "gmu"; 2527 2528 clocks = <&gpucc GPU_CC_AHB_CLK>, 2529 <&gpucc GPU_CC_CX_GMU_CLK>, 2530 <&gpucc GPU_CC_CXO_CLK>, 2531 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2532 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2533 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2534 <&gpucc GPU_CC_DEMET_CLK>; 2535 clock-names = "ahb", 2536 "gmu", 2537 "cxo", 2538 "axi", 2539 "memnoc", 2540 "hub", 2541 "demet"; 2542 2543 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2544 <&gpucc GPU_CC_GX_GDSC>; 2545 power-domain-names = "cx", 2546 "gx"; 2547 2548 iommus = <&adreno_smmu 5 0x0>; 2549 2550 qcom,qmp = <&aoss_qmp>; 2551 2552 operating-points-v2 = <&gmu_opp_table>; 2553 2554 gmu_opp_table: opp-table { 2555 compatible = "operating-points-v2"; 2556 2557 opp-500000000 { 2558 opp-hz = /bits/ 64 <500000000>; 2559 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2560 }; 2561 2562 opp-200000000 { 2563 opp-hz = /bits/ 64 <200000000>; 2564 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2565 }; 2566 }; 2567 }; 2568 2569 gpucc: clock-controller@3d90000 { 2570 compatible = "qcom,sm8550-gpucc"; 2571 reg = <0 0x03d90000 0 0xa000>; 2572 clocks = <&bi_tcxo_div2>, 2573 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2574 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2575 #clock-cells = <1>; 2576 #reset-cells = <1>; 2577 #power-domain-cells = <1>; 2578 }; 2579 2580 adreno_smmu: iommu@3da0000 { 2581 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2582 "qcom,smmu-500", "arm,mmu-500"; 2583 reg = <0x0 0x03da0000 0x0 0x40000>; 2584 #iommu-cells = <2>; 2585 #global-interrupts = <1>; 2586 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2596 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2611 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2612 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2613 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2614 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2615 <&gpucc GPU_CC_AHB_CLK>; 2616 clock-names = "hlos", 2617 "bus", 2618 "iface", 2619 "ahb"; 2620 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2621 dma-coherent; 2622 }; 2623 2624 ipa: ipa@3f40000 { 2625 compatible = "qcom,sm8550-ipa"; 2626 2627 iommus = <&apps_smmu 0x4a0 0x0>, 2628 <&apps_smmu 0x4a2 0x0>; 2629 reg = <0 0x3f40000 0 0x10000>, 2630 <0 0x3f50000 0 0x5000>, 2631 <0 0x3e04000 0 0xfc000>; 2632 reg-names = "ipa-reg", 2633 "ipa-shared", 2634 "gsi"; 2635 2636 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2637 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2638 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2639 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2640 interrupt-names = "ipa", 2641 "gsi", 2642 "ipa-clock-query", 2643 "ipa-setup-ready"; 2644 2645 clocks = <&rpmhcc RPMH_IPA_CLK>; 2646 clock-names = "core"; 2647 2648 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 2649 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2651 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2652 interconnect-names = "memory", 2653 "config"; 2654 2655 qcom,qmp = <&aoss_qmp>; 2656 2657 qcom,smem-states = <&ipa_smp2p_out 0>, 2658 <&ipa_smp2p_out 1>; 2659 qcom,smem-state-names = "ipa-clock-enabled-valid", 2660 "ipa-clock-enabled"; 2661 2662 status = "disabled"; 2663 }; 2664 2665 remoteproc_mpss: remoteproc@4080000 { 2666 compatible = "qcom,sm8550-mpss-pas"; 2667 reg = <0x0 0x04080000 0x0 0x10000>; 2668 2669 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2670 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2671 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2672 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2673 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2674 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2675 interrupt-names = "wdog", "fatal", "ready", "handover", 2676 "stop-ack", "shutdown-ack"; 2677 2678 clocks = <&rpmhcc RPMH_CXO_CLK>; 2679 clock-names = "xo"; 2680 2681 power-domains = <&rpmhpd RPMHPD_CX>, 2682 <&rpmhpd RPMHPD_MSS>; 2683 power-domain-names = "cx", "mss"; 2684 2685 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2687 2688 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2689 2690 qcom,qmp = <&aoss_qmp>; 2691 2692 qcom,smem-states = <&smp2p_modem_out 0>; 2693 qcom,smem-state-names = "stop"; 2694 2695 status = "disabled"; 2696 2697 glink-edge { 2698 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2699 IPCC_MPROC_SIGNAL_GLINK_QMP 2700 IRQ_TYPE_EDGE_RISING>; 2701 mboxes = <&ipcc IPCC_CLIENT_MPSS 2702 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2703 label = "mpss"; 2704 qcom,remote-pid = <1>; 2705 }; 2706 }; 2707 2708 remoteproc_adsp: remoteproc@6800000 { 2709 compatible = "qcom,sm8550-adsp-pas"; 2710 reg = <0x0 0x06800000 0x0 0x10000>; 2711 2712 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2713 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2714 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2715 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2716 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2717 interrupt-names = "wdog", "fatal", "ready", 2718 "handover", "stop-ack"; 2719 2720 clocks = <&rpmhcc RPMH_CXO_CLK>; 2721 clock-names = "xo"; 2722 2723 power-domains = <&rpmhpd RPMHPD_LCX>, 2724 <&rpmhpd RPMHPD_LMX>; 2725 power-domain-names = "lcx", "lmx"; 2726 2727 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2728 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2729 2730 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2731 2732 qcom,qmp = <&aoss_qmp>; 2733 2734 qcom,smem-states = <&smp2p_adsp_out 0>; 2735 qcom,smem-state-names = "stop"; 2736 2737 status = "disabled"; 2738 2739 remoteproc_adsp_glink: glink-edge { 2740 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2741 IPCC_MPROC_SIGNAL_GLINK_QMP 2742 IRQ_TYPE_EDGE_RISING>; 2743 mboxes = <&ipcc IPCC_CLIENT_LPASS 2744 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2745 2746 label = "lpass"; 2747 qcom,remote-pid = <2>; 2748 2749 fastrpc { 2750 compatible = "qcom,fastrpc"; 2751 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2752 label = "adsp"; 2753 qcom,non-secure-domain; 2754 #address-cells = <1>; 2755 #size-cells = <0>; 2756 2757 compute-cb@3 { 2758 compatible = "qcom,fastrpc-compute-cb"; 2759 reg = <3>; 2760 iommus = <&apps_smmu 0x1003 0x80>, 2761 <&apps_smmu 0x1063 0x0>; 2762 dma-coherent; 2763 }; 2764 2765 compute-cb@4 { 2766 compatible = "qcom,fastrpc-compute-cb"; 2767 reg = <4>; 2768 iommus = <&apps_smmu 0x1004 0x80>, 2769 <&apps_smmu 0x1064 0x0>; 2770 dma-coherent; 2771 }; 2772 2773 compute-cb@5 { 2774 compatible = "qcom,fastrpc-compute-cb"; 2775 reg = <5>; 2776 iommus = <&apps_smmu 0x1005 0x80>, 2777 <&apps_smmu 0x1065 0x0>; 2778 dma-coherent; 2779 }; 2780 2781 compute-cb@6 { 2782 compatible = "qcom,fastrpc-compute-cb"; 2783 reg = <6>; 2784 iommus = <&apps_smmu 0x1006 0x80>, 2785 <&apps_smmu 0x1066 0x0>; 2786 dma-coherent; 2787 }; 2788 2789 compute-cb@7 { 2790 compatible = "qcom,fastrpc-compute-cb"; 2791 reg = <7>; 2792 iommus = <&apps_smmu 0x1007 0x80>, 2793 <&apps_smmu 0x1067 0x0>; 2794 dma-coherent; 2795 }; 2796 }; 2797 2798 gpr { 2799 compatible = "qcom,gpr"; 2800 qcom,glink-channels = "adsp_apps"; 2801 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2802 qcom,intents = <512 20>; 2803 #address-cells = <1>; 2804 #size-cells = <0>; 2805 2806 q6apm: service@1 { 2807 compatible = "qcom,q6apm"; 2808 reg = <GPR_APM_MODULE_IID>; 2809 #sound-dai-cells = <0>; 2810 qcom,protection-domain = "avs/audio", 2811 "msm/adsp/audio_pd"; 2812 2813 q6apmdai: dais { 2814 compatible = "qcom,q6apm-dais"; 2815 iommus = <&apps_smmu 0x1001 0x80>, 2816 <&apps_smmu 0x1061 0x0>; 2817 }; 2818 2819 q6apmbedai: bedais { 2820 compatible = "qcom,q6apm-lpass-dais"; 2821 #sound-dai-cells = <1>; 2822 }; 2823 }; 2824 2825 q6prm: service@2 { 2826 compatible = "qcom,q6prm"; 2827 reg = <GPR_PRM_MODULE_IID>; 2828 qcom,protection-domain = "avs/audio", 2829 "msm/adsp/audio_pd"; 2830 2831 q6prmcc: clock-controller { 2832 compatible = "qcom,q6prm-lpass-clocks"; 2833 #clock-cells = <2>; 2834 }; 2835 }; 2836 }; 2837 }; 2838 }; 2839 2840 lpass_wsa2macro: codec@6aa0000 { 2841 compatible = "qcom,sm8550-lpass-wsa-macro"; 2842 reg = <0 0x06aa0000 0 0x1000>; 2843 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2844 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2845 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2846 <&lpass_vamacro>; 2847 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2848 2849 #clock-cells = <0>; 2850 clock-output-names = "wsa2-mclk"; 2851 #sound-dai-cells = <1>; 2852 }; 2853 2854 swr3: soundwire@6ab0000 { 2855 compatible = "qcom,soundwire-v2.0.0"; 2856 reg = <0 0x06ab0000 0 0x10000>; 2857 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2858 clocks = <&lpass_wsa2macro>; 2859 clock-names = "iface"; 2860 label = "WSA2"; 2861 2862 pinctrl-0 = <&wsa2_swr_active>; 2863 pinctrl-names = "default"; 2864 2865 qcom,din-ports = <4>; 2866 qcom,dout-ports = <9>; 2867 2868 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2869 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2870 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2871 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2872 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2873 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2874 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2875 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2876 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2877 2878 #address-cells = <2>; 2879 #size-cells = <0>; 2880 #sound-dai-cells = <1>; 2881 status = "disabled"; 2882 }; 2883 2884 lpass_rxmacro: codec@6ac0000 { 2885 compatible = "qcom,sm8550-lpass-rx-macro"; 2886 reg = <0 0x06ac0000 0 0x1000>; 2887 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2888 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2889 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2890 <&lpass_vamacro>; 2891 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2892 2893 #clock-cells = <0>; 2894 clock-output-names = "mclk"; 2895 #sound-dai-cells = <1>; 2896 }; 2897 2898 swr1: soundwire@6ad0000 { 2899 compatible = "qcom,soundwire-v2.0.0"; 2900 reg = <0 0x06ad0000 0 0x10000>; 2901 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2902 clocks = <&lpass_rxmacro>; 2903 clock-names = "iface"; 2904 label = "RX"; 2905 2906 pinctrl-0 = <&rx_swr_active>; 2907 pinctrl-names = "default"; 2908 2909 qcom,din-ports = <1>; 2910 qcom,dout-ports = <11>; 2911 2912 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2913 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2914 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2915 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2916 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2917 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2918 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2919 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2920 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2921 2922 #address-cells = <2>; 2923 #size-cells = <0>; 2924 #sound-dai-cells = <1>; 2925 status = "disabled"; 2926 }; 2927 2928 lpass_txmacro: codec@6ae0000 { 2929 compatible = "qcom,sm8550-lpass-tx-macro"; 2930 reg = <0 0x06ae0000 0 0x1000>; 2931 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2932 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2933 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2934 <&lpass_vamacro>; 2935 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2936 2937 #clock-cells = <0>; 2938 clock-output-names = "mclk"; 2939 #sound-dai-cells = <1>; 2940 }; 2941 2942 lpass_wsamacro: codec@6b00000 { 2943 compatible = "qcom,sm8550-lpass-wsa-macro"; 2944 reg = <0 0x06b00000 0 0x1000>; 2945 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2946 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2947 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2948 <&lpass_vamacro>; 2949 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2950 2951 #clock-cells = <0>; 2952 clock-output-names = "mclk"; 2953 #sound-dai-cells = <1>; 2954 }; 2955 2956 swr0: soundwire@6b10000 { 2957 compatible = "qcom,soundwire-v2.0.0"; 2958 reg = <0 0x06b10000 0 0x10000>; 2959 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2960 clocks = <&lpass_wsamacro>; 2961 clock-names = "iface"; 2962 label = "WSA"; 2963 2964 pinctrl-0 = <&wsa_swr_active>; 2965 pinctrl-names = "default"; 2966 2967 qcom,din-ports = <4>; 2968 qcom,dout-ports = <9>; 2969 2970 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2971 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2972 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2973 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2974 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2975 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2976 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2977 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2978 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2979 2980 #address-cells = <2>; 2981 #size-cells = <0>; 2982 #sound-dai-cells = <1>; 2983 status = "disabled"; 2984 }; 2985 2986 swr2: soundwire@6d30000 { 2987 compatible = "qcom,soundwire-v2.0.0"; 2988 reg = <0 0x06d30000 0 0x10000>; 2989 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2990 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2991 interrupt-names = "core", "wakeup"; 2992 clocks = <&lpass_txmacro>; 2993 clock-names = "iface"; 2994 label = "TX"; 2995 2996 pinctrl-0 = <&tx_swr_active>; 2997 pinctrl-names = "default"; 2998 2999 qcom,din-ports = <4>; 3000 qcom,dout-ports = <0>; 3001 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3002 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3003 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3004 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3005 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3006 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3007 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3008 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3009 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3010 3011 #address-cells = <2>; 3012 #size-cells = <0>; 3013 #sound-dai-cells = <1>; 3014 status = "disabled"; 3015 }; 3016 3017 lpass_vamacro: codec@6d44000 { 3018 compatible = "qcom,sm8550-lpass-va-macro"; 3019 reg = <0 0x06d44000 0 0x1000>; 3020 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3021 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3022 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3023 clock-names = "mclk", "macro", "dcodec"; 3024 3025 #clock-cells = <0>; 3026 clock-output-names = "fsgen"; 3027 #sound-dai-cells = <1>; 3028 }; 3029 3030 lpass_tlmm: pinctrl@6e80000 { 3031 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 3032 reg = <0 0x06e80000 0 0x20000>, 3033 <0 0x07250000 0 0x10000>; 3034 gpio-controller; 3035 #gpio-cells = <2>; 3036 gpio-ranges = <&lpass_tlmm 0 0 23>; 3037 3038 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3039 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3040 clock-names = "core", "audio"; 3041 3042 tx_swr_active: tx-swr-active-state { 3043 clk-pins { 3044 pins = "gpio0"; 3045 function = "swr_tx_clk"; 3046 drive-strength = <2>; 3047 slew-rate = <1>; 3048 bias-disable; 3049 }; 3050 3051 data-pins { 3052 pins = "gpio1", "gpio2", "gpio14"; 3053 function = "swr_tx_data"; 3054 drive-strength = <2>; 3055 slew-rate = <1>; 3056 bias-bus-hold; 3057 }; 3058 }; 3059 3060 rx_swr_active: rx-swr-active-state { 3061 clk-pins { 3062 pins = "gpio3"; 3063 function = "swr_rx_clk"; 3064 drive-strength = <2>; 3065 slew-rate = <1>; 3066 bias-disable; 3067 }; 3068 3069 data-pins { 3070 pins = "gpio4", "gpio5"; 3071 function = "swr_rx_data"; 3072 drive-strength = <2>; 3073 slew-rate = <1>; 3074 bias-bus-hold; 3075 }; 3076 }; 3077 3078 dmic01_default: dmic01-default-state { 3079 clk-pins { 3080 pins = "gpio6"; 3081 function = "dmic1_clk"; 3082 drive-strength = <8>; 3083 output-high; 3084 }; 3085 3086 data-pins { 3087 pins = "gpio7"; 3088 function = "dmic1_data"; 3089 drive-strength = <8>; 3090 input-enable; 3091 }; 3092 }; 3093 3094 dmic23_default: dmic23-default-state { 3095 clk-pins { 3096 pins = "gpio8"; 3097 function = "dmic2_clk"; 3098 drive-strength = <8>; 3099 output-high; 3100 }; 3101 3102 data-pins { 3103 pins = "gpio9"; 3104 function = "dmic2_data"; 3105 drive-strength = <8>; 3106 input-enable; 3107 }; 3108 }; 3109 3110 wsa_swr_active: wsa-swr-active-state { 3111 clk-pins { 3112 pins = "gpio10"; 3113 function = "wsa_swr_clk"; 3114 drive-strength = <2>; 3115 slew-rate = <1>; 3116 bias-disable; 3117 }; 3118 3119 data-pins { 3120 pins = "gpio11"; 3121 function = "wsa_swr_data"; 3122 drive-strength = <2>; 3123 slew-rate = <1>; 3124 bias-bus-hold; 3125 }; 3126 }; 3127 3128 wsa2_swr_active: wsa2-swr-active-state { 3129 clk-pins { 3130 pins = "gpio15"; 3131 function = "wsa2_swr_clk"; 3132 drive-strength = <2>; 3133 slew-rate = <1>; 3134 bias-disable; 3135 }; 3136 3137 data-pins { 3138 pins = "gpio16"; 3139 function = "wsa2_swr_data"; 3140 drive-strength = <2>; 3141 slew-rate = <1>; 3142 bias-bus-hold; 3143 }; 3144 }; 3145 }; 3146 3147 lpass_lpiaon_noc: interconnect@7400000 { 3148 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 3149 reg = <0 0x07400000 0 0x19080>; 3150 #interconnect-cells = <2>; 3151 qcom,bcm-voters = <&apps_bcm_voter>; 3152 }; 3153 3154 lpass_lpicx_noc: interconnect@7430000 { 3155 compatible = "qcom,sm8550-lpass-lpicx-noc"; 3156 reg = <0 0x07430000 0 0x3a200>; 3157 #interconnect-cells = <2>; 3158 qcom,bcm-voters = <&apps_bcm_voter>; 3159 }; 3160 3161 lpass_ag_noc: interconnect@7e40000 { 3162 compatible = "qcom,sm8550-lpass-ag-noc"; 3163 reg = <0 0x07e40000 0 0xe080>; 3164 #interconnect-cells = <2>; 3165 qcom,bcm-voters = <&apps_bcm_voter>; 3166 }; 3167 3168 sdhc_2: mmc@8804000 { 3169 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 3170 reg = <0 0x08804000 0 0x1000>; 3171 3172 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3174 interrupt-names = "hc_irq", "pwr_irq"; 3175 3176 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3177 <&gcc GCC_SDCC2_APPS_CLK>, 3178 <&rpmhcc RPMH_CXO_CLK>; 3179 clock-names = "iface", "core", "xo"; 3180 iommus = <&apps_smmu 0x540 0>; 3181 qcom,dll-config = <0x0007642c>; 3182 qcom,ddr-config = <0x80040868>; 3183 power-domains = <&rpmhpd RPMHPD_CX>; 3184 operating-points-v2 = <&sdhc2_opp_table>; 3185 3186 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3187 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3189 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3190 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 3191 bus-width = <4>; 3192 dma-coherent; 3193 3194 /* Forbid SDR104/SDR50 - broken hw! */ 3195 sdhci-caps-mask = <0x3 0>; 3196 3197 status = "disabled"; 3198 3199 sdhc2_opp_table: opp-table { 3200 compatible = "operating-points-v2"; 3201 3202 opp-19200000 { 3203 opp-hz = /bits/ 64 <19200000>; 3204 required-opps = <&rpmhpd_opp_min_svs>; 3205 }; 3206 3207 opp-50000000 { 3208 opp-hz = /bits/ 64 <50000000>; 3209 required-opps = <&rpmhpd_opp_low_svs>; 3210 }; 3211 3212 opp-100000000 { 3213 opp-hz = /bits/ 64 <100000000>; 3214 required-opps = <&rpmhpd_opp_svs>; 3215 }; 3216 3217 opp-202000000 { 3218 opp-hz = /bits/ 64 <202000000>; 3219 required-opps = <&rpmhpd_opp_svs_l1>; 3220 }; 3221 }; 3222 }; 3223 3224 iris: video-codec@aa00000 { 3225 compatible = "qcom,sm8550-iris"; 3226 3227 reg = <0 0x0aa00000 0 0xf0000>; 3228 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3229 3230 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 3231 <&videocc VIDEO_CC_MVS0_GDSC>, 3232 <&rpmhpd RPMHPD_MXC>, 3233 <&rpmhpd RPMHPD_MMCX>; 3234 power-domain-names = "venus", 3235 "vcodec0", 3236 "mxc", 3237 "mmcx"; 3238 operating-points-v2 = <&iris_opp_table>; 3239 3240 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3241 <&videocc VIDEO_CC_MVS0C_CLK>, 3242 <&videocc VIDEO_CC_MVS0_CLK>; 3243 clock-names = "iface", 3244 "core", 3245 "vcodec0_core"; 3246 3247 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3248 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3249 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 3250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3251 interconnect-names = "cpu-cfg", 3252 "video-mem"; 3253 3254 memory-region = <&video_mem>; 3255 3256 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 3257 reset-names = "bus"; 3258 3259 iommus = <&apps_smmu 0x1940 0>, 3260 <&apps_smmu 0x1947 0>; 3261 dma-coherent; 3262 3263 /* 3264 * IRIS firmware is signed by vendors, only 3265 * enable in boards where the proper signed firmware 3266 * is available. 3267 */ 3268 status = "disabled"; 3269 3270 iris_opp_table: opp-table { 3271 compatible = "operating-points-v2"; 3272 3273 opp-240000000 { 3274 opp-hz = /bits/ 64 <240000000>; 3275 required-opps = <&rpmhpd_opp_svs>, 3276 <&rpmhpd_opp_low_svs>; 3277 }; 3278 3279 opp-338000000 { 3280 opp-hz = /bits/ 64 <338000000>; 3281 required-opps = <&rpmhpd_opp_svs>, 3282 <&rpmhpd_opp_svs>; 3283 }; 3284 3285 opp-366000000 { 3286 opp-hz = /bits/ 64 <366000000>; 3287 required-opps = <&rpmhpd_opp_svs_l1>, 3288 <&rpmhpd_opp_svs_l1>; 3289 }; 3290 3291 opp-444000000 { 3292 opp-hz = /bits/ 64 <444000000>; 3293 required-opps = <&rpmhpd_opp_nom>, 3294 <&rpmhpd_opp_nom>; 3295 }; 3296 3297 opp-533333334 { 3298 opp-hz = /bits/ 64 <533333334>; 3299 required-opps = <&rpmhpd_opp_turbo>, 3300 <&rpmhpd_opp_turbo>; 3301 }; 3302 }; 3303 }; 3304 3305 videocc: clock-controller@aaf0000 { 3306 compatible = "qcom,sm8550-videocc"; 3307 reg = <0 0x0aaf0000 0 0x10000>; 3308 clocks = <&bi_tcxo_div2>, 3309 <&gcc GCC_VIDEO_AHB_CLK>; 3310 power-domains = <&rpmhpd RPMHPD_MMCX>; 3311 required-opps = <&rpmhpd_opp_low_svs>; 3312 #clock-cells = <1>; 3313 #reset-cells = <1>; 3314 #power-domain-cells = <1>; 3315 }; 3316 3317 cci0: cci@ac15000 { 3318 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3319 reg = <0 0x0ac15000 0 0x1000>; 3320 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>; 3321 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3322 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3323 <&camcc CAM_CC_CPAS_AHB_CLK>, 3324 <&camcc CAM_CC_CCI_0_CLK>; 3325 clock-names = "camnoc_axi", 3326 "cpas_ahb", 3327 "cci"; 3328 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 3329 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 3330 pinctrl-names = "default", "sleep"; 3331 status = "disabled"; 3332 #address-cells = <1>; 3333 #size-cells = <0>; 3334 3335 cci0_i2c0: i2c-bus@0 { 3336 reg = <0>; 3337 clock-frequency = <1000000>; 3338 #address-cells = <1>; 3339 #size-cells = <0>; 3340 }; 3341 3342 cci0_i2c1: i2c-bus@1 { 3343 reg = <1>; 3344 clock-frequency = <1000000>; 3345 #address-cells = <1>; 3346 #size-cells = <0>; 3347 }; 3348 }; 3349 3350 cci1: cci@ac16000 { 3351 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3352 reg = <0 0x0ac16000 0 0x1000>; 3353 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>; 3354 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3355 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3356 <&camcc CAM_CC_CPAS_AHB_CLK>, 3357 <&camcc CAM_CC_CCI_1_CLK>; 3358 clock-names = "camnoc_axi", 3359 "cpas_ahb", 3360 "cci"; 3361 pinctrl-0 = <&cci1_0_default>; 3362 pinctrl-1 = <&cci1_0_sleep>; 3363 pinctrl-names = "default", "sleep"; 3364 status = "disabled"; 3365 #address-cells = <1>; 3366 #size-cells = <0>; 3367 3368 cci1_i2c0: i2c-bus@0 { 3369 reg = <0>; 3370 clock-frequency = <1000000>; 3371 #address-cells = <1>; 3372 #size-cells = <0>; 3373 }; 3374 }; 3375 3376 cci2: cci@ac17000 { 3377 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3378 reg = <0 0x0ac17000 0 0x1000>; 3379 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>; 3380 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3381 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3382 <&camcc CAM_CC_CPAS_AHB_CLK>, 3383 <&camcc CAM_CC_CCI_2_CLK>; 3384 clock-names = "camnoc_axi", 3385 "cpas_ahb", 3386 "cci"; 3387 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 3388 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 3389 pinctrl-names = "default", "sleep"; 3390 status = "disabled"; 3391 #address-cells = <1>; 3392 #size-cells = <0>; 3393 3394 cci2_i2c0: i2c-bus@0 { 3395 reg = <0>; 3396 clock-frequency = <1000000>; 3397 #address-cells = <1>; 3398 #size-cells = <0>; 3399 }; 3400 3401 cci2_i2c1: i2c-bus@1 { 3402 reg = <1>; 3403 clock-frequency = <1000000>; 3404 #address-cells = <1>; 3405 #size-cells = <0>; 3406 }; 3407 }; 3408 3409 camss: isp@acb7000 { 3410 compatible = "qcom,sm8550-camss"; 3411 3412 reg = <0x0 0x0acb7000 0x0 0x0d00>, 3413 <0x0 0x0acb9000 0x0 0x0d00>, 3414 <0x0 0x0acbb000 0x0 0x0d00>, 3415 <0x0 0x0acca000 0x0 0x0a00>, 3416 <0x0 0x0acce000 0x0 0x0a00>, 3417 <0x0 0x0acb6000 0x0 0x1000>, 3418 <0x0 0x0ace4000 0x0 0x2000>, 3419 <0x0 0x0ace6000 0x0 0x2000>, 3420 <0x0 0x0ace8000 0x0 0x2000>, 3421 <0x0 0x0acea000 0x0 0x2000>, 3422 <0x0 0x0acec000 0x0 0x2000>, 3423 <0x0 0x0acee000 0x0 0x2000>, 3424 <0x0 0x0acf0000 0x0 0x2000>, 3425 <0x0 0x0acf2000 0x0 0x2000>, 3426 <0x0 0x0ac62000 0x0 0xf000>, 3427 <0x0 0x0ac71000 0x0 0xf000>, 3428 <0x0 0x0ac80000 0x0 0xf000>, 3429 <0x0 0x0accb000 0x0 0x1800>, 3430 <0x0 0x0accf000 0x0 0x1800>; 3431 reg-names = "csid0", 3432 "csid1", 3433 "csid2", 3434 "csid_lite0", 3435 "csid_lite1", 3436 "csid_wrapper", 3437 "csiphy0", 3438 "csiphy1", 3439 "csiphy2", 3440 "csiphy3", 3441 "csiphy4", 3442 "csiphy5", 3443 "csiphy6", 3444 "csiphy7", 3445 "vfe0", 3446 "vfe1", 3447 "vfe2", 3448 "vfe_lite0", 3449 "vfe_lite1"; 3450 3451 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3452 <&camcc CAM_CC_CPAS_AHB_CLK>, 3453 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 3454 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 3455 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 3456 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 3457 <&camcc CAM_CC_CPAS_IFE_2_CLK>, 3458 <&camcc CAM_CC_CSID_CLK>, 3459 <&camcc CAM_CC_CSIPHY0_CLK>, 3460 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3461 <&camcc CAM_CC_CSIPHY1_CLK>, 3462 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3463 <&camcc CAM_CC_CSIPHY2_CLK>, 3464 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3465 <&camcc CAM_CC_CSIPHY3_CLK>, 3466 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3467 <&camcc CAM_CC_CSIPHY4_CLK>, 3468 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3469 <&camcc CAM_CC_CSIPHY5_CLK>, 3470 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3471 <&camcc CAM_CC_CSIPHY6_CLK>, 3472 <&camcc CAM_CC_CSI6PHYTIMER_CLK>, 3473 <&camcc CAM_CC_CSIPHY7_CLK>, 3474 <&camcc CAM_CC_CSI7PHYTIMER_CLK>, 3475 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 3476 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3477 <&camcc CAM_CC_IFE_0_CLK>, 3478 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 3479 <&camcc CAM_CC_IFE_1_CLK>, 3480 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 3481 <&camcc CAM_CC_IFE_2_CLK>, 3482 <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, 3483 <&camcc CAM_CC_IFE_LITE_CLK>, 3484 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3485 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3486 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3487 clock-names = "camnoc_axi", 3488 "cpas_ahb", 3489 "cpas_fast_ahb_clk", 3490 "cpas_ife_lite", 3491 "cpas_vfe0", 3492 "cpas_vfe1", 3493 "cpas_vfe2", 3494 "csid", 3495 "csiphy0", 3496 "csiphy0_timer", 3497 "csiphy1", 3498 "csiphy1_timer", 3499 "csiphy2", 3500 "csiphy2_timer", 3501 "csiphy3", 3502 "csiphy3_timer", 3503 "csiphy4", 3504 "csiphy4_timer", 3505 "csiphy5", 3506 "csiphy5_timer", 3507 "csiphy6", 3508 "csiphy6_timer", 3509 "csiphy7", 3510 "csiphy7_timer", 3511 "csiphy_rx", 3512 "gcc_axi_hf", 3513 "vfe0", 3514 "vfe0_fast_ahb", 3515 "vfe1", 3516 "vfe1_fast_ahb", 3517 "vfe2", 3518 "vfe2_fast_ahb", 3519 "vfe_lite", 3520 "vfe_lite_ahb", 3521 "vfe_lite_cphy_rx", 3522 "vfe_lite_csid"; 3523 3524 interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>, 3525 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 3526 <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, 3527 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>, 3528 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 3529 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 3530 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 3531 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 3532 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 3533 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 3534 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 3535 <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, 3536 <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, 3537 <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>, 3538 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 3539 <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, 3540 <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>, 3541 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>; 3542 interrupt-names = "csid0", 3543 "csid1", 3544 "csid2", 3545 "csid_lite0", 3546 "csid_lite1", 3547 "csiphy0", 3548 "csiphy1", 3549 "csiphy2", 3550 "csiphy3", 3551 "csiphy4", 3552 "csiphy5", 3553 "csiphy6", 3554 "csiphy7", 3555 "vfe0", 3556 "vfe1", 3557 "vfe2", 3558 "vfe_lite0", 3559 "vfe_lite1"; 3560 3561 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3562 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3563 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 3564 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3565 interconnect-names = "ahb", 3566 "hf_0_mnoc"; 3567 3568 iommus = <&apps_smmu 0x800 0x20>; 3569 3570 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 3571 <&camcc CAM_CC_IFE_1_GDSC>, 3572 <&camcc CAM_CC_IFE_2_GDSC>, 3573 <&camcc CAM_CC_TITAN_TOP_GDSC>; 3574 power-domain-names = "ife0", 3575 "ife1", 3576 "ife2", 3577 "top"; 3578 3579 status = "disabled"; 3580 3581 ports { 3582 #address-cells = <1>; 3583 #size-cells = <0>; 3584 3585 port@0 { 3586 reg = <0>; 3587 }; 3588 3589 port@1 { 3590 reg = <1>; 3591 }; 3592 3593 port@2 { 3594 reg = <2>; 3595 }; 3596 3597 port@3 { 3598 reg = <3>; 3599 }; 3600 3601 port@4 { 3602 reg = <4>; 3603 }; 3604 3605 port@5 { 3606 reg = <5>; 3607 }; 3608 3609 port@6 { 3610 reg = <6>; 3611 }; 3612 3613 port@7 { 3614 reg = <7>; 3615 }; 3616 }; 3617 }; 3618 3619 camcc: clock-controller@ade0000 { 3620 compatible = "qcom,sm8550-camcc"; 3621 reg = <0 0x0ade0000 0 0x20000>; 3622 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3623 <&bi_tcxo_div2>, 3624 <&bi_tcxo_ao_div2>, 3625 <&sleep_clk>; 3626 power-domains = <&rpmhpd SM8550_MMCX>; 3627 required-opps = <&rpmhpd_opp_low_svs>; 3628 #clock-cells = <1>; 3629 #reset-cells = <1>; 3630 #power-domain-cells = <1>; 3631 }; 3632 3633 mdss: display-subsystem@ae00000 { 3634 compatible = "qcom,sm8550-mdss"; 3635 reg = <0 0x0ae00000 0 0x1000>; 3636 reg-names = "mdss"; 3637 3638 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3639 interrupt-controller; 3640 #interrupt-cells = <1>; 3641 3642 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3643 <&gcc GCC_DISP_AHB_CLK>, 3644 <&gcc GCC_DISP_HF_AXI_CLK>, 3645 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3646 3647 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3648 3649 power-domains = <&dispcc MDSS_GDSC>; 3650 3651 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3653 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3654 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3655 interconnect-names = "mdp0-mem", "cpu-cfg"; 3656 3657 iommus = <&apps_smmu 0x1c00 0x2>; 3658 3659 #address-cells = <2>; 3660 #size-cells = <2>; 3661 ranges; 3662 3663 status = "disabled"; 3664 3665 mdss_mdp: display-controller@ae01000 { 3666 compatible = "qcom,sm8550-dpu"; 3667 reg = <0 0x0ae01000 0 0x8f000>, 3668 <0 0x0aeb0000 0 0x3000>; 3669 reg-names = "mdp", "vbif"; 3670 3671 interrupt-parent = <&mdss>; 3672 interrupts = <0>; 3673 3674 clocks = <&gcc GCC_DISP_AHB_CLK>, 3675 <&gcc GCC_DISP_HF_AXI_CLK>, 3676 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3677 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3678 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3679 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3680 clock-names = "bus", 3681 "nrt_bus", 3682 "iface", 3683 "lut", 3684 "core", 3685 "vsync"; 3686 3687 power-domains = <&rpmhpd RPMHPD_MMCX>; 3688 3689 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3690 assigned-clock-rates = <19200000>; 3691 3692 operating-points-v2 = <&mdp_opp_table>; 3693 3694 ports { 3695 #address-cells = <1>; 3696 #size-cells = <0>; 3697 3698 port@0 { 3699 reg = <0>; 3700 dpu_intf1_out: endpoint { 3701 remote-endpoint = <&mdss_dsi0_in>; 3702 }; 3703 }; 3704 3705 port@1 { 3706 reg = <1>; 3707 dpu_intf2_out: endpoint { 3708 remote-endpoint = <&mdss_dsi1_in>; 3709 }; 3710 }; 3711 3712 port@2 { 3713 reg = <2>; 3714 dpu_intf0_out: endpoint { 3715 remote-endpoint = <&mdss_dp0_in>; 3716 }; 3717 }; 3718 }; 3719 3720 mdp_opp_table: opp-table { 3721 compatible = "operating-points-v2"; 3722 3723 opp-200000000 { 3724 opp-hz = /bits/ 64 <200000000>; 3725 required-opps = <&rpmhpd_opp_low_svs>; 3726 }; 3727 3728 opp-325000000 { 3729 opp-hz = /bits/ 64 <325000000>; 3730 required-opps = <&rpmhpd_opp_svs>; 3731 }; 3732 3733 opp-375000000 { 3734 opp-hz = /bits/ 64 <375000000>; 3735 required-opps = <&rpmhpd_opp_svs_l1>; 3736 }; 3737 3738 opp-514000000 { 3739 opp-hz = /bits/ 64 <514000000>; 3740 required-opps = <&rpmhpd_opp_nom>; 3741 }; 3742 }; 3743 }; 3744 3745 mdss_dp0: displayport-controller@ae90000 { 3746 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 3747 reg = <0 0xae90000 0 0x200>, 3748 <0 0xae90200 0 0x200>, 3749 <0 0xae90400 0 0xc00>, 3750 <0 0xae91000 0 0x400>, 3751 <0 0xae91400 0 0x400>; 3752 interrupt-parent = <&mdss>; 3753 interrupts = <12>; 3754 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3755 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3756 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3757 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3758 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3759 clock-names = "core_iface", 3760 "core_aux", 3761 "ctrl_link", 3762 "ctrl_link_iface", 3763 "stream_pixel"; 3764 3765 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3766 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3767 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3768 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3769 3770 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3771 phy-names = "dp"; 3772 3773 #sound-dai-cells = <0>; 3774 3775 operating-points-v2 = <&dp_opp_table>; 3776 power-domains = <&rpmhpd RPMHPD_MMCX>; 3777 3778 status = "disabled"; 3779 3780 ports { 3781 #address-cells = <1>; 3782 #size-cells = <0>; 3783 3784 port@0 { 3785 reg = <0>; 3786 mdss_dp0_in: endpoint { 3787 remote-endpoint = <&dpu_intf0_out>; 3788 }; 3789 }; 3790 3791 port@1 { 3792 reg = <1>; 3793 mdss_dp0_out: endpoint { 3794 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3795 }; 3796 }; 3797 }; 3798 3799 dp_opp_table: opp-table { 3800 compatible = "operating-points-v2"; 3801 3802 opp-162000000 { 3803 opp-hz = /bits/ 64 <162000000>; 3804 required-opps = <&rpmhpd_opp_low_svs_d1>; 3805 }; 3806 3807 opp-270000000 { 3808 opp-hz = /bits/ 64 <270000000>; 3809 required-opps = <&rpmhpd_opp_low_svs>; 3810 }; 3811 3812 opp-540000000 { 3813 opp-hz = /bits/ 64 <540000000>; 3814 required-opps = <&rpmhpd_opp_svs_l1>; 3815 }; 3816 3817 opp-810000000 { 3818 opp-hz = /bits/ 64 <810000000>; 3819 required-opps = <&rpmhpd_opp_nom>; 3820 }; 3821 }; 3822 }; 3823 3824 mdss_dsi0: dsi@ae94000 { 3825 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3826 reg = <0 0x0ae94000 0 0x400>; 3827 reg-names = "dsi_ctrl"; 3828 3829 interrupt-parent = <&mdss>; 3830 interrupts = <4>; 3831 3832 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3833 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3834 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3835 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3836 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3837 <&gcc GCC_DISP_HF_AXI_CLK>; 3838 clock-names = "byte", 3839 "byte_intf", 3840 "pixel", 3841 "core", 3842 "iface", 3843 "bus"; 3844 3845 power-domains = <&rpmhpd RPMHPD_MMCX>; 3846 3847 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3848 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3849 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3850 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3851 3852 operating-points-v2 = <&mdss_dsi_opp_table>; 3853 3854 phys = <&mdss_dsi0_phy>; 3855 phy-names = "dsi"; 3856 3857 #address-cells = <1>; 3858 #size-cells = <0>; 3859 3860 status = "disabled"; 3861 3862 ports { 3863 #address-cells = <1>; 3864 #size-cells = <0>; 3865 3866 port@0 { 3867 reg = <0>; 3868 mdss_dsi0_in: endpoint { 3869 remote-endpoint = <&dpu_intf1_out>; 3870 }; 3871 }; 3872 3873 port@1 { 3874 reg = <1>; 3875 mdss_dsi0_out: endpoint { 3876 }; 3877 }; 3878 }; 3879 3880 mdss_dsi_opp_table: opp-table { 3881 compatible = "operating-points-v2"; 3882 3883 opp-187500000 { 3884 opp-hz = /bits/ 64 <187500000>; 3885 required-opps = <&rpmhpd_opp_low_svs>; 3886 }; 3887 3888 opp-300000000 { 3889 opp-hz = /bits/ 64 <300000000>; 3890 required-opps = <&rpmhpd_opp_svs>; 3891 }; 3892 3893 opp-358000000 { 3894 opp-hz = /bits/ 64 <358000000>; 3895 required-opps = <&rpmhpd_opp_svs_l1>; 3896 }; 3897 }; 3898 }; 3899 3900 mdss_dsi0_phy: phy@ae95000 { 3901 compatible = "qcom,sm8550-dsi-phy-4nm"; 3902 reg = <0 0x0ae95000 0 0x200>, 3903 <0 0x0ae95200 0 0x280>, 3904 <0 0x0ae95500 0 0x400>; 3905 reg-names = "dsi_phy", 3906 "dsi_phy_lane", 3907 "dsi_pll"; 3908 3909 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3910 <&rpmhcc RPMH_CXO_CLK>; 3911 clock-names = "iface", "ref"; 3912 3913 #clock-cells = <1>; 3914 #phy-cells = <0>; 3915 3916 status = "disabled"; 3917 }; 3918 3919 mdss_dsi1: dsi@ae96000 { 3920 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3921 reg = <0 0x0ae96000 0 0x400>; 3922 reg-names = "dsi_ctrl"; 3923 3924 interrupt-parent = <&mdss>; 3925 interrupts = <5>; 3926 3927 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3928 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3929 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3930 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3931 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3932 <&gcc GCC_DISP_HF_AXI_CLK>; 3933 clock-names = "byte", 3934 "byte_intf", 3935 "pixel", 3936 "core", 3937 "iface", 3938 "bus"; 3939 3940 power-domains = <&rpmhpd RPMHPD_MMCX>; 3941 3942 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3943 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3944 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3945 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3946 3947 operating-points-v2 = <&mdss_dsi_opp_table>; 3948 3949 phys = <&mdss_dsi1_phy>; 3950 phy-names = "dsi"; 3951 3952 #address-cells = <1>; 3953 #size-cells = <0>; 3954 3955 status = "disabled"; 3956 3957 ports { 3958 #address-cells = <1>; 3959 #size-cells = <0>; 3960 3961 port@0 { 3962 reg = <0>; 3963 mdss_dsi1_in: endpoint { 3964 remote-endpoint = <&dpu_intf2_out>; 3965 }; 3966 }; 3967 3968 port@1 { 3969 reg = <1>; 3970 mdss_dsi1_out: endpoint { 3971 }; 3972 }; 3973 }; 3974 }; 3975 3976 mdss_dsi1_phy: phy@ae97000 { 3977 compatible = "qcom,sm8550-dsi-phy-4nm"; 3978 reg = <0 0x0ae97000 0 0x200>, 3979 <0 0x0ae97200 0 0x280>, 3980 <0 0x0ae97500 0 0x400>; 3981 reg-names = "dsi_phy", 3982 "dsi_phy_lane", 3983 "dsi_pll"; 3984 3985 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3986 <&rpmhcc RPMH_CXO_CLK>; 3987 clock-names = "iface", "ref"; 3988 3989 #clock-cells = <1>; 3990 #phy-cells = <0>; 3991 3992 status = "disabled"; 3993 }; 3994 }; 3995 3996 dispcc: clock-controller@af00000 { 3997 compatible = "qcom,sm8550-dispcc"; 3998 reg = <0 0x0af00000 0 0x20000>; 3999 clocks = <&bi_tcxo_div2>, 4000 <&bi_tcxo_ao_div2>, 4001 <&gcc GCC_DISP_AHB_CLK>, 4002 <&sleep_clk>, 4003 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4004 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4005 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4006 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 4007 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4008 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4009 <0>, /* dp1 */ 4010 <0>, 4011 <0>, /* dp2 */ 4012 <0>, 4013 <0>, /* dp3 */ 4014 <0>; 4015 power-domains = <&rpmhpd RPMHPD_MMCX>; 4016 required-opps = <&rpmhpd_opp_low_svs>; 4017 #clock-cells = <1>; 4018 #reset-cells = <1>; 4019 #power-domain-cells = <1>; 4020 }; 4021 4022 usb_1_hsphy: phy@88e3000 { 4023 compatible = "qcom,sm8550-snps-eusb2-phy"; 4024 reg = <0x0 0x088e3000 0x0 0x154>; 4025 #phy-cells = <0>; 4026 4027 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 4028 clock-names = "ref"; 4029 4030 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4031 4032 status = "disabled"; 4033 }; 4034 4035 usb_dp_qmpphy: phy@88e8000 { 4036 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 4037 reg = <0x0 0x088e8000 0x0 0x3000>; 4038 4039 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4040 <&rpmhcc RPMH_CXO_CLK>, 4041 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4042 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4043 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 4044 4045 power-domains = <&gcc USB3_PHY_GDSC>; 4046 4047 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4048 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4049 reset-names = "phy", "common"; 4050 4051 #clock-cells = <1>; 4052 #phy-cells = <1>; 4053 4054 orientation-switch; 4055 4056 status = "disabled"; 4057 4058 ports { 4059 #address-cells = <1>; 4060 #size-cells = <0>; 4061 4062 port@0 { 4063 reg = <0>; 4064 4065 usb_dp_qmpphy_out: endpoint { 4066 }; 4067 }; 4068 4069 port@1 { 4070 reg = <1>; 4071 4072 usb_dp_qmpphy_usb_ss_in: endpoint { 4073 remote-endpoint = <&usb_1_dwc3_ss>; 4074 }; 4075 }; 4076 4077 port@2 { 4078 reg = <2>; 4079 4080 usb_dp_qmpphy_dp_in: endpoint { 4081 remote-endpoint = <&mdss_dp0_out>; 4082 }; 4083 }; 4084 }; 4085 }; 4086 4087 usb_1: usb@a6f8800 { 4088 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 4089 reg = <0x0 0x0a6f8800 0x0 0x400>; 4090 #address-cells = <2>; 4091 #size-cells = <2>; 4092 ranges; 4093 4094 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4095 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4096 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4097 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4098 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4099 <&tcsr TCSR_USB3_CLKREF_EN>; 4100 clock-names = "cfg_noc", 4101 "core", 4102 "iface", 4103 "sleep", 4104 "mock_utmi", 4105 "xo"; 4106 4107 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4108 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4109 assigned-clock-rates = <19200000>, <200000000>; 4110 4111 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4112 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4113 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4114 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4115 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4116 interrupt-names = "pwr_event", 4117 "hs_phy_irq", 4118 "dp_hs_phy_irq", 4119 "dm_hs_phy_irq", 4120 "ss_phy_irq"; 4121 4122 power-domains = <&gcc USB30_PRIM_GDSC>; 4123 required-opps = <&rpmhpd_opp_nom>; 4124 4125 resets = <&gcc GCC_USB30_PRIM_BCR>; 4126 4127 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 4128 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4129 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4130 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 4131 interconnect-names = "usb-ddr", "apps-usb"; 4132 4133 status = "disabled"; 4134 4135 usb_1_dwc3: usb@a600000 { 4136 compatible = "snps,dwc3"; 4137 reg = <0x0 0x0a600000 0x0 0xcd00>; 4138 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4139 iommus = <&apps_smmu 0x40 0x0>; 4140 phys = <&usb_1_hsphy>, 4141 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 4142 phy-names = "usb2-phy", "usb3-phy"; 4143 snps,hird-threshold = /bits/ 8 <0x0>; 4144 snps,usb2-gadget-lpm-disable; 4145 snps,dis_u2_susphy_quirk; 4146 snps,dis_enblslpm_quirk; 4147 snps,dis-u1-entry-quirk; 4148 snps,dis-u2-entry-quirk; 4149 snps,is-utmi-l1-suspend; 4150 snps,usb3_lpm_capable; 4151 snps,usb2-lpm-disable; 4152 snps,has-lpm-erratum; 4153 tx-fifo-resize; 4154 dma-coherent; 4155 usb-role-switch; 4156 4157 ports { 4158 #address-cells = <1>; 4159 #size-cells = <0>; 4160 4161 port@0 { 4162 reg = <0>; 4163 4164 usb_1_dwc3_hs: endpoint { 4165 }; 4166 }; 4167 4168 port@1 { 4169 reg = <1>; 4170 4171 usb_1_dwc3_ss: endpoint { 4172 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4173 }; 4174 }; 4175 }; 4176 }; 4177 }; 4178 4179 pdc: interrupt-controller@b220000 { 4180 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 4181 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4182 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4183 <125 63 1>, <126 716 12>, 4184 <138 251 5>; 4185 #interrupt-cells = <2>; 4186 interrupt-parent = <&intc>; 4187 interrupt-controller; 4188 }; 4189 4190 tsens0: thermal-sensor@c271000 { 4191 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4192 reg = <0 0x0c271000 0 0x1000>, /* TM */ 4193 <0 0x0c222000 0 0x1000>; /* SROT */ 4194 #qcom,sensors = <16>; 4195 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 4197 interrupt-names = "uplow", "critical"; 4198 #thermal-sensor-cells = <1>; 4199 }; 4200 4201 tsens1: thermal-sensor@c272000 { 4202 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4203 reg = <0 0x0c272000 0 0x1000>, /* TM */ 4204 <0 0x0c223000 0 0x1000>; /* SROT */ 4205 #qcom,sensors = <16>; 4206 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 4208 interrupt-names = "uplow", "critical"; 4209 #thermal-sensor-cells = <1>; 4210 }; 4211 4212 tsens2: thermal-sensor@c273000 { 4213 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4214 reg = <0 0x0c273000 0 0x1000>, /* TM */ 4215 <0 0x0c224000 0 0x1000>; /* SROT */ 4216 #qcom,sensors = <16>; 4217 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 4219 interrupt-names = "uplow", "critical"; 4220 #thermal-sensor-cells = <1>; 4221 }; 4222 4223 aoss_qmp: power-management@c300000 { 4224 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 4225 reg = <0 0x0c300000 0 0x400>; 4226 interrupt-parent = <&ipcc>; 4227 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4228 IRQ_TYPE_EDGE_RISING>; 4229 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4230 4231 #clock-cells = <0>; 4232 }; 4233 4234 sram@c3f0000 { 4235 compatible = "qcom,rpmh-stats"; 4236 reg = <0 0x0c3f0000 0 0x400>; 4237 qcom,qmp = <&aoss_qmp>; 4238 }; 4239 4240 spmi_bus: spmi@c400000 { 4241 compatible = "qcom,spmi-pmic-arb"; 4242 reg = <0 0x0c400000 0 0x3000>, 4243 <0 0x0c500000 0 0x400000>, 4244 <0 0x0c440000 0 0x80000>, 4245 <0 0x0c4c0000 0 0x20000>, 4246 <0 0x0c42d000 0 0x4000>; 4247 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4248 interrupt-names = "periph_irq"; 4249 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4250 qcom,ee = <0>; 4251 qcom,channel = <0>; 4252 qcom,bus-id = <0>; 4253 #address-cells = <2>; 4254 #size-cells = <0>; 4255 interrupt-controller; 4256 #interrupt-cells = <4>; 4257 }; 4258 4259 tlmm: pinctrl@f100000 { 4260 compatible = "qcom,sm8550-tlmm"; 4261 reg = <0 0x0f100000 0 0x300000>; 4262 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4263 gpio-controller; 4264 #gpio-cells = <2>; 4265 interrupt-controller; 4266 #interrupt-cells = <2>; 4267 gpio-ranges = <&tlmm 0 0 211>; 4268 wakeup-parent = <&pdc>; 4269 4270 cci0_0_default: cci0-0-default-state { 4271 sda-pins { 4272 pins = "gpio110"; 4273 function = "cci_i2c_sda"; 4274 drive-strength = <2>; 4275 bias-pull-up = <2200>; 4276 }; 4277 4278 scl-pins { 4279 pins = "gpio111"; 4280 function = "cci_i2c_scl"; 4281 drive-strength = <2>; 4282 bias-pull-up = <2200>; 4283 }; 4284 }; 4285 4286 cci0_0_sleep: cci0-0-sleep-state { 4287 sda-pins { 4288 pins = "gpio110"; 4289 function = "cci_i2c_sda"; 4290 drive-strength = <2>; 4291 bias-pull-down; 4292 }; 4293 4294 scl-pins { 4295 pins = "gpio111"; 4296 function = "cci_i2c_scl"; 4297 drive-strength = <2>; 4298 bias-pull-down; 4299 }; 4300 }; 4301 4302 cci0_1_default: cci0-1-default-state { 4303 sda-pins { 4304 pins = "gpio112"; 4305 function = "cci_i2c_sda"; 4306 drive-strength = <2>; 4307 bias-pull-up = <2200>; 4308 }; 4309 4310 scl-pins { 4311 pins = "gpio113"; 4312 function = "cci_i2c_scl"; 4313 drive-strength = <2>; 4314 bias-pull-up = <2200>; 4315 }; 4316 }; 4317 4318 cci0_1_sleep: cci0-1-sleep-state { 4319 sda-pins { 4320 pins = "gpio112"; 4321 function = "cci_i2c_sda"; 4322 drive-strength = <2>; 4323 bias-pull-down; 4324 }; 4325 4326 scl-pins { 4327 pins = "gpio113"; 4328 function = "cci_i2c_scl"; 4329 drive-strength = <2>; 4330 bias-pull-down; 4331 }; 4332 }; 4333 4334 cci1_0_default: cci1-0-default-state { 4335 sda-pins { 4336 pins = "gpio114"; 4337 function = "cci_i2c_sda"; 4338 drive-strength = <2>; 4339 bias-pull-up = <2200>; 4340 }; 4341 4342 scl-pins { 4343 pins = "gpio115"; 4344 function = "cci_i2c_scl"; 4345 drive-strength = <2>; 4346 bias-pull-up = <2200>; 4347 }; 4348 }; 4349 4350 cci1_0_sleep: cci1-0-sleep-state { 4351 sda-pins { 4352 pins = "gpio114"; 4353 function = "cci_i2c_sda"; 4354 drive-strength = <2>; 4355 bias-pull-down; 4356 }; 4357 4358 scl-pins { 4359 pins = "gpio115"; 4360 function = "cci_i2c_scl"; 4361 drive-strength = <2>; 4362 bias-pull-down; 4363 }; 4364 }; 4365 4366 cci2_0_default: cci2-0-default-state { 4367 sda-pins { 4368 pins = "gpio74"; 4369 function = "cci_i2c_sda"; 4370 drive-strength = <2>; 4371 bias-pull-up = <2200>; 4372 }; 4373 4374 scl-pins { 4375 pins = "gpio75"; 4376 function = "cci_i2c_scl"; 4377 drive-strength = <2>; 4378 bias-pull-up = <2200>; 4379 }; 4380 }; 4381 4382 cci2_0_sleep: cci2-0-sleep-state { 4383 sda-pins { 4384 pins = "gpio74"; 4385 function = "cci_i2c_sda"; 4386 drive-strength = <2>; 4387 bias-pull-down; 4388 }; 4389 4390 scl-pins { 4391 pins = "gpio75"; 4392 function = "cci_i2c_scl"; 4393 drive-strength = <2>; 4394 bias-pull-down; 4395 }; 4396 }; 4397 4398 cci2_1_default: cci2-1-default-state { 4399 sda-pins { 4400 pins = "gpio0"; 4401 function = "cci_i2c_sda"; 4402 drive-strength = <2>; 4403 bias-pull-up = <2200>; 4404 }; 4405 4406 scl-pins { 4407 pins = "gpio1"; 4408 function = "cci_i2c_scl"; 4409 drive-strength = <2>; 4410 bias-pull-up = <2200>; 4411 }; 4412 }; 4413 4414 cci2_1_sleep: cci2-1-sleep-state { 4415 sda-pins { 4416 pins = "gpio0"; 4417 function = "cci_i2c_sda"; 4418 drive-strength = <2>; 4419 bias-pull-down; 4420 }; 4421 4422 scl-pins { 4423 pins = "gpio1"; 4424 function = "cci_i2c_scl"; 4425 drive-strength = <2>; 4426 bias-pull-down; 4427 }; 4428 }; 4429 4430 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 4431 /* SDA, SCL */ 4432 pins = "gpio16", "gpio17"; 4433 function = "i2chub0_se0"; 4434 drive-strength = <2>; 4435 bias-pull-up; 4436 }; 4437 4438 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4439 /* SDA, SCL */ 4440 pins = "gpio18", "gpio19"; 4441 function = "i2chub0_se1"; 4442 drive-strength = <2>; 4443 bias-pull-up; 4444 }; 4445 4446 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4447 /* SDA, SCL */ 4448 pins = "gpio20", "gpio21"; 4449 function = "i2chub0_se2"; 4450 drive-strength = <2>; 4451 bias-pull-up; 4452 }; 4453 4454 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4455 /* SDA, SCL */ 4456 pins = "gpio22", "gpio23"; 4457 function = "i2chub0_se3"; 4458 drive-strength = <2>; 4459 bias-pull-up; 4460 }; 4461 4462 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4463 /* SDA, SCL */ 4464 pins = "gpio4", "gpio5"; 4465 function = "i2chub0_se4"; 4466 drive-strength = <2>; 4467 bias-pull-up; 4468 }; 4469 4470 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4471 /* SDA, SCL */ 4472 pins = "gpio6", "gpio7"; 4473 function = "i2chub0_se5"; 4474 drive-strength = <2>; 4475 bias-pull-up; 4476 }; 4477 4478 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4479 /* SDA, SCL */ 4480 pins = "gpio8", "gpio9"; 4481 function = "i2chub0_se6"; 4482 drive-strength = <2>; 4483 bias-pull-up; 4484 }; 4485 4486 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4487 /* SDA, SCL */ 4488 pins = "gpio10", "gpio11"; 4489 function = "i2chub0_se7"; 4490 drive-strength = <2>; 4491 bias-pull-up; 4492 }; 4493 4494 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4495 /* SDA, SCL */ 4496 pins = "gpio206", "gpio207"; 4497 function = "i2chub0_se8"; 4498 drive-strength = <2>; 4499 bias-pull-up; 4500 }; 4501 4502 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4503 /* SDA, SCL */ 4504 pins = "gpio84", "gpio85"; 4505 function = "i2chub0_se9"; 4506 drive-strength = <2>; 4507 bias-pull-up; 4508 }; 4509 4510 pcie0_default_state: pcie0-default-state { 4511 perst-pins { 4512 pins = "gpio94"; 4513 function = "gpio"; 4514 drive-strength = <2>; 4515 bias-pull-down; 4516 }; 4517 4518 clkreq-pins { 4519 pins = "gpio95"; 4520 function = "pcie0_clk_req_n"; 4521 drive-strength = <2>; 4522 bias-pull-up; 4523 }; 4524 4525 wake-pins { 4526 pins = "gpio96"; 4527 function = "gpio"; 4528 drive-strength = <2>; 4529 bias-pull-up; 4530 }; 4531 }; 4532 4533 pcie1_default_state: pcie1-default-state { 4534 perst-pins { 4535 pins = "gpio97"; 4536 function = "gpio"; 4537 drive-strength = <2>; 4538 bias-pull-down; 4539 }; 4540 4541 clkreq-pins { 4542 pins = "gpio98"; 4543 function = "pcie1_clk_req_n"; 4544 drive-strength = <2>; 4545 bias-pull-up; 4546 }; 4547 4548 wake-pins { 4549 pins = "gpio99"; 4550 function = "gpio"; 4551 drive-strength = <2>; 4552 bias-pull-up; 4553 }; 4554 }; 4555 4556 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4557 /* SDA, SCL */ 4558 pins = "gpio28", "gpio29"; 4559 function = "qup1_se0"; 4560 drive-strength = <2>; 4561 bias-pull-up = <2200>; 4562 }; 4563 4564 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4565 /* SDA, SCL */ 4566 pins = "gpio32", "gpio33"; 4567 function = "qup1_se1"; 4568 drive-strength = <2>; 4569 bias-pull-up = <2200>; 4570 }; 4571 4572 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4573 /* SDA, SCL */ 4574 pins = "gpio36", "gpio37"; 4575 function = "qup1_se2"; 4576 drive-strength = <2>; 4577 bias-pull-up = <2200>; 4578 }; 4579 4580 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4581 /* SDA, SCL */ 4582 pins = "gpio40", "gpio41"; 4583 function = "qup1_se3"; 4584 drive-strength = <2>; 4585 bias-pull-up = <2200>; 4586 }; 4587 4588 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4589 /* SDA, SCL */ 4590 pins = "gpio44", "gpio45"; 4591 function = "qup1_se4"; 4592 drive-strength = <2>; 4593 bias-pull-up = <2200>; 4594 }; 4595 4596 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4597 /* SDA, SCL */ 4598 pins = "gpio52", "gpio53"; 4599 function = "qup1_se5"; 4600 drive-strength = <2>; 4601 bias-pull-up = <2200>; 4602 }; 4603 4604 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4605 /* SDA, SCL */ 4606 pins = "gpio48", "gpio49"; 4607 function = "qup1_se6"; 4608 drive-strength = <2>; 4609 bias-pull-up = <2200>; 4610 }; 4611 4612 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4613 scl-pins { 4614 pins = "gpio57"; 4615 function = "qup2_se0_l1_mira"; 4616 drive-strength = <2>; 4617 bias-pull-up = <2200>; 4618 }; 4619 4620 sda-pins { 4621 pins = "gpio56"; 4622 function = "qup2_se0_l0_mira"; 4623 drive-strength = <2>; 4624 bias-pull-up = <2200>; 4625 }; 4626 }; 4627 4628 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4629 /* SDA, SCL */ 4630 pins = "gpio60", "gpio61"; 4631 function = "qup2_se1"; 4632 drive-strength = <2>; 4633 bias-pull-up = <2200>; 4634 }; 4635 4636 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4637 /* SDA, SCL */ 4638 pins = "gpio64", "gpio65"; 4639 function = "qup2_se2"; 4640 drive-strength = <2>; 4641 bias-pull-up = <2200>; 4642 }; 4643 4644 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4645 /* SDA, SCL */ 4646 pins = "gpio68", "gpio69"; 4647 function = "qup2_se3"; 4648 drive-strength = <2>; 4649 bias-pull-up = <2200>; 4650 }; 4651 4652 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4653 /* SDA, SCL */ 4654 pins = "gpio2", "gpio3"; 4655 function = "qup2_se4"; 4656 drive-strength = <2>; 4657 bias-pull-up = <2200>; 4658 }; 4659 4660 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4661 /* SDA, SCL */ 4662 pins = "gpio80", "gpio81"; 4663 function = "qup2_se5"; 4664 drive-strength = <2>; 4665 bias-pull-up = <2200>; 4666 }; 4667 4668 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4669 /* SDA, SCL */ 4670 pins = "gpio72", "gpio106"; 4671 function = "qup2_se7"; 4672 drive-strength = <2>; 4673 bias-pull-up = <2200>; 4674 }; 4675 4676 qup_spi0_cs: qup-spi0-cs-state { 4677 pins = "gpio31"; 4678 function = "qup1_se0"; 4679 drive-strength = <6>; 4680 bias-disable; 4681 }; 4682 4683 qup_spi0_data_clk: qup-spi0-data-clk-state { 4684 /* MISO, MOSI, CLK */ 4685 pins = "gpio28", "gpio29", "gpio30"; 4686 function = "qup1_se0"; 4687 drive-strength = <6>; 4688 bias-disable; 4689 }; 4690 4691 qup_spi1_cs: qup-spi1-cs-state { 4692 pins = "gpio35"; 4693 function = "qup1_se1"; 4694 drive-strength = <6>; 4695 bias-disable; 4696 }; 4697 4698 qup_spi1_data_clk: qup-spi1-data-clk-state { 4699 /* MISO, MOSI, CLK */ 4700 pins = "gpio32", "gpio33", "gpio34"; 4701 function = "qup1_se1"; 4702 drive-strength = <6>; 4703 bias-disable; 4704 }; 4705 4706 qup_spi2_cs: qup-spi2-cs-state { 4707 pins = "gpio39"; 4708 function = "qup1_se2"; 4709 drive-strength = <6>; 4710 bias-disable; 4711 }; 4712 4713 qup_spi2_data_clk: qup-spi2-data-clk-state { 4714 /* MISO, MOSI, CLK */ 4715 pins = "gpio36", "gpio37", "gpio38"; 4716 function = "qup1_se2"; 4717 drive-strength = <6>; 4718 bias-disable; 4719 }; 4720 4721 qup_spi3_cs: qup-spi3-cs-state { 4722 pins = "gpio43"; 4723 function = "qup1_se3"; 4724 drive-strength = <6>; 4725 bias-disable; 4726 }; 4727 4728 qup_spi3_data_clk: qup-spi3-data-clk-state { 4729 /* MISO, MOSI, CLK */ 4730 pins = "gpio40", "gpio41", "gpio42"; 4731 function = "qup1_se3"; 4732 drive-strength = <6>; 4733 bias-disable; 4734 }; 4735 4736 qup_spi4_cs: qup-spi4-cs-state { 4737 pins = "gpio47"; 4738 function = "qup1_se4"; 4739 drive-strength = <6>; 4740 bias-disable; 4741 }; 4742 4743 qup_spi4_data_clk: qup-spi4-data-clk-state { 4744 /* MISO, MOSI, CLK */ 4745 pins = "gpio44", "gpio45", "gpio46"; 4746 function = "qup1_se4"; 4747 drive-strength = <6>; 4748 bias-disable; 4749 }; 4750 4751 qup_spi5_cs: qup-spi5-cs-state { 4752 pins = "gpio55"; 4753 function = "qup1_se5"; 4754 drive-strength = <6>; 4755 bias-disable; 4756 }; 4757 4758 qup_spi5_data_clk: qup-spi5-data-clk-state { 4759 /* MISO, MOSI, CLK */ 4760 pins = "gpio52", "gpio53", "gpio54"; 4761 function = "qup1_se5"; 4762 drive-strength = <6>; 4763 bias-disable; 4764 }; 4765 4766 qup_spi6_cs: qup-spi6-cs-state { 4767 pins = "gpio51"; 4768 function = "qup1_se6"; 4769 drive-strength = <6>; 4770 bias-disable; 4771 }; 4772 4773 qup_spi6_data_clk: qup-spi6-data-clk-state { 4774 /* MISO, MOSI, CLK */ 4775 pins = "gpio48", "gpio49", "gpio50"; 4776 function = "qup1_se6"; 4777 drive-strength = <6>; 4778 bias-disable; 4779 }; 4780 4781 qup_spi8_cs: qup-spi8-cs-state { 4782 pins = "gpio59"; 4783 function = "qup2_se0_l3_mira"; 4784 drive-strength = <6>; 4785 bias-disable; 4786 }; 4787 4788 qup_spi8_data_clk: qup-spi8-data-clk-state { 4789 /* MISO, MOSI, CLK */ 4790 pins = "gpio56", "gpio57", "gpio58"; 4791 function = "qup2_se0_l2_mira"; 4792 drive-strength = <6>; 4793 bias-disable; 4794 }; 4795 4796 qup_spi9_cs: qup-spi9-cs-state { 4797 pins = "gpio63"; 4798 function = "qup2_se1"; 4799 drive-strength = <6>; 4800 bias-disable; 4801 }; 4802 4803 qup_spi9_data_clk: qup-spi9-data-clk-state { 4804 /* MISO, MOSI, CLK */ 4805 pins = "gpio60", "gpio61", "gpio62"; 4806 function = "qup2_se1"; 4807 drive-strength = <6>; 4808 bias-disable; 4809 }; 4810 4811 qup_spi10_cs: qup-spi10-cs-state { 4812 pins = "gpio67"; 4813 function = "qup2_se2"; 4814 drive-strength = <6>; 4815 bias-disable; 4816 }; 4817 4818 qup_spi10_data_clk: qup-spi10-data-clk-state { 4819 /* MISO, MOSI, CLK */ 4820 pins = "gpio64", "gpio65", "gpio66"; 4821 function = "qup2_se2"; 4822 drive-strength = <6>; 4823 bias-disable; 4824 }; 4825 4826 qup_spi11_cs: qup-spi11-cs-state { 4827 pins = "gpio71"; 4828 function = "qup2_se3"; 4829 drive-strength = <6>; 4830 bias-disable; 4831 }; 4832 4833 qup_spi11_data_clk: qup-spi11-data-clk-state { 4834 /* MISO, MOSI, CLK */ 4835 pins = "gpio68", "gpio69", "gpio70"; 4836 function = "qup2_se3"; 4837 drive-strength = <6>; 4838 bias-disable; 4839 }; 4840 4841 qup_spi12_cs: qup-spi12-cs-state { 4842 pins = "gpio119"; 4843 function = "qup2_se4"; 4844 drive-strength = <6>; 4845 bias-disable; 4846 }; 4847 4848 qup_spi12_data_clk: qup-spi12-data-clk-state { 4849 /* MISO, MOSI, CLK */ 4850 pins = "gpio2", "gpio3", "gpio118"; 4851 function = "qup2_se4"; 4852 drive-strength = <6>; 4853 bias-disable; 4854 }; 4855 4856 qup_spi13_cs: qup-spi13-cs-state { 4857 pins = "gpio83"; 4858 function = "qup2_se5"; 4859 drive-strength = <6>; 4860 bias-disable; 4861 }; 4862 4863 qup_spi13_data_clk: qup-spi13-data-clk-state { 4864 /* MISO, MOSI, CLK */ 4865 pins = "gpio80", "gpio81", "gpio82"; 4866 function = "qup2_se5"; 4867 drive-strength = <6>; 4868 bias-disable; 4869 }; 4870 4871 qup_spi15_cs: qup-spi15-cs-state { 4872 pins = "gpio75"; 4873 function = "qup2_se7"; 4874 drive-strength = <6>; 4875 bias-disable; 4876 }; 4877 4878 qup_spi15_data_clk: qup-spi15-data-clk-state { 4879 /* MISO, MOSI, CLK */ 4880 pins = "gpio72", "gpio106", "gpio74"; 4881 function = "qup2_se7"; 4882 drive-strength = <6>; 4883 bias-disable; 4884 }; 4885 4886 qup_uart7_default: qup-uart7-default-state { 4887 /* TX, RX */ 4888 pins = "gpio26", "gpio27"; 4889 function = "qup1_se7"; 4890 drive-strength = <2>; 4891 bias-disable; 4892 }; 4893 4894 qup_uart14_default: qup-uart14-default-state { 4895 /* TX, RX */ 4896 pins = "gpio78", "gpio79"; 4897 function = "qup2_se6"; 4898 drive-strength = <2>; 4899 bias-pull-up; 4900 }; 4901 4902 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4903 /* CTS, RTS */ 4904 pins = "gpio76", "gpio77"; 4905 function = "qup2_se6"; 4906 drive-strength = <2>; 4907 bias-pull-down; 4908 }; 4909 4910 sdc2_sleep: sdc2-sleep-state { 4911 clk-pins { 4912 pins = "sdc2_clk"; 4913 bias-disable; 4914 drive-strength = <2>; 4915 }; 4916 4917 cmd-pins { 4918 pins = "sdc2_cmd"; 4919 bias-pull-up; 4920 drive-strength = <2>; 4921 }; 4922 4923 data-pins { 4924 pins = "sdc2_data"; 4925 bias-pull-up; 4926 drive-strength = <2>; 4927 }; 4928 }; 4929 4930 sdc2_default: sdc2-default-state { 4931 clk-pins { 4932 pins = "sdc2_clk"; 4933 bias-disable; 4934 drive-strength = <16>; 4935 }; 4936 4937 cmd-pins { 4938 pins = "sdc2_cmd"; 4939 bias-pull-up; 4940 drive-strength = <10>; 4941 }; 4942 4943 data-pins { 4944 pins = "sdc2_data"; 4945 bias-pull-up; 4946 drive-strength = <10>; 4947 }; 4948 }; 4949 }; 4950 4951 apps_smmu: iommu@15000000 { 4952 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4953 reg = <0 0x15000000 0 0x100000>; 4954 #iommu-cells = <2>; 4955 #global-interrupts = <1>; 4956 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4957 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4958 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4959 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4960 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4961 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4962 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4963 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4964 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4965 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4966 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4967 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4968 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4969 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4970 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4971 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4972 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4973 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4974 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4976 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4977 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4978 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4979 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4980 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4981 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4982 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4983 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4984 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4985 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4986 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4987 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4988 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4989 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4990 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4991 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4992 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4993 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4994 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4995 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4996 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4997 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4998 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4999 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5000 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5001 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5002 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5003 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5004 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5005 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5006 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5007 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5008 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5009 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5010 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5011 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5012 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5013 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5014 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5015 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5016 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5017 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5018 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5019 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5020 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 5053 dma-coherent; 5054 }; 5055 5056 intc: interrupt-controller@17100000 { 5057 compatible = "arm,gic-v3"; 5058 reg = <0 0x17100000 0 0x10000>, /* GICD */ 5059 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 5060 ranges; 5061 #interrupt-cells = <3>; 5062 interrupt-controller; 5063 #redistributor-regions = <1>; 5064 redistributor-stride = <0 0x40000>; 5065 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5066 #address-cells = <2>; 5067 #size-cells = <2>; 5068 5069 gic_its: msi-controller@17140000 { 5070 compatible = "arm,gic-v3-its"; 5071 reg = <0 0x17140000 0 0x20000>; 5072 msi-controller; 5073 #msi-cells = <1>; 5074 }; 5075 }; 5076 5077 timer@17420000 { 5078 compatible = "arm,armv7-timer-mem"; 5079 reg = <0 0x17420000 0 0x1000>; 5080 ranges = <0 0 0 0x20000000>; 5081 #address-cells = <1>; 5082 #size-cells = <1>; 5083 5084 frame@17421000 { 5085 reg = <0x17421000 0x1000>, 5086 <0x17422000 0x1000>; 5087 frame-number = <0>; 5088 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5090 }; 5091 5092 frame@17423000 { 5093 reg = <0x17423000 0x1000>; 5094 frame-number = <1>; 5095 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5096 status = "disabled"; 5097 }; 5098 5099 frame@17425000 { 5100 reg = <0x17425000 0x1000>; 5101 frame-number = <2>; 5102 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5103 status = "disabled"; 5104 }; 5105 5106 frame@17427000 { 5107 reg = <0x17427000 0x1000>; 5108 frame-number = <3>; 5109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5110 status = "disabled"; 5111 }; 5112 5113 frame@17429000 { 5114 reg = <0x17429000 0x1000>; 5115 frame-number = <4>; 5116 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5117 status = "disabled"; 5118 }; 5119 5120 frame@1742b000 { 5121 reg = <0x1742b000 0x1000>; 5122 frame-number = <5>; 5123 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5124 status = "disabled"; 5125 }; 5126 5127 frame@1742d000 { 5128 reg = <0x1742d000 0x1000>; 5129 frame-number = <6>; 5130 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5131 status = "disabled"; 5132 }; 5133 }; 5134 5135 apps_rsc: rsc@17a00000 { 5136 label = "apps_rsc"; 5137 compatible = "qcom,rpmh-rsc"; 5138 reg = <0 0x17a00000 0 0x10000>, 5139 <0 0x17a10000 0 0x10000>, 5140 <0 0x17a20000 0 0x10000>, 5141 <0 0x17a30000 0 0x10000>; 5142 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 5143 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5146 qcom,tcs-offset = <0xd00>; 5147 qcom,drv-id = <2>; 5148 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5149 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5150 power-domains = <&cluster_pd>; 5151 5152 apps_bcm_voter: bcm-voter { 5153 compatible = "qcom,bcm-voter"; 5154 }; 5155 5156 rpmhcc: clock-controller { 5157 compatible = "qcom,sm8550-rpmh-clk"; 5158 #clock-cells = <1>; 5159 clock-names = "xo"; 5160 clocks = <&xo_board>; 5161 }; 5162 5163 rpmhpd: power-controller { 5164 compatible = "qcom,sm8550-rpmhpd"; 5165 #power-domain-cells = <1>; 5166 operating-points-v2 = <&rpmhpd_opp_table>; 5167 5168 rpmhpd_opp_table: opp-table { 5169 compatible = "operating-points-v2"; 5170 5171 rpmhpd_opp_ret: opp-16 { 5172 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5173 }; 5174 5175 rpmhpd_opp_min_svs: opp-48 { 5176 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5177 }; 5178 5179 rpmhpd_opp_low_svs_d2: opp-52 { 5180 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5181 }; 5182 5183 rpmhpd_opp_low_svs_d1: opp-56 { 5184 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5185 }; 5186 5187 rpmhpd_opp_low_svs_d0: opp-60 { 5188 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5189 }; 5190 5191 rpmhpd_opp_low_svs: opp-64 { 5192 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5193 }; 5194 5195 rpmhpd_opp_low_svs_l1: opp-80 { 5196 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5197 }; 5198 5199 rpmhpd_opp_svs: opp-128 { 5200 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5201 }; 5202 5203 rpmhpd_opp_svs_l0: opp-144 { 5204 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5205 }; 5206 5207 rpmhpd_opp_svs_l1: opp-192 { 5208 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5209 }; 5210 5211 rpmhpd_opp_nom: opp-256 { 5212 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5213 }; 5214 5215 rpmhpd_opp_nom_l1: opp-320 { 5216 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5217 }; 5218 5219 rpmhpd_opp_nom_l2: opp-336 { 5220 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5221 }; 5222 5223 rpmhpd_opp_turbo: opp-384 { 5224 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5225 }; 5226 5227 rpmhpd_opp_turbo_l1: opp-416 { 5228 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5229 }; 5230 }; 5231 }; 5232 }; 5233 5234 cpufreq_hw: cpufreq@17d91000 { 5235 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 5236 reg = <0 0x17d91000 0 0x1000>, 5237 <0 0x17d92000 0 0x1000>, 5238 <0 0x17d93000 0 0x1000>; 5239 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 5240 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 5241 clock-names = "xo", "alternate"; 5242 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5243 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5244 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5245 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5246 #freq-domain-cells = <1>; 5247 #clock-cells = <1>; 5248 }; 5249 5250 pmu@24091000 { 5251 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5252 reg = <0 0x24091000 0 0x1000>; 5253 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 5254 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5255 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5256 5257 operating-points-v2 = <&llcc_bwmon_opp_table>; 5258 5259 llcc_bwmon_opp_table: opp-table { 5260 compatible = "operating-points-v2"; 5261 5262 opp-0 { 5263 opp-peak-kBps = <2086000>; 5264 }; 5265 5266 opp-1 { 5267 opp-peak-kBps = <2929000>; 5268 }; 5269 5270 opp-2 { 5271 opp-peak-kBps = <5931000>; 5272 }; 5273 5274 opp-3 { 5275 opp-peak-kBps = <6515000>; 5276 }; 5277 5278 opp-4 { 5279 opp-peak-kBps = <7980000>; 5280 }; 5281 5282 opp-5 { 5283 opp-peak-kBps = <10437000>; 5284 }; 5285 5286 opp-6 { 5287 opp-peak-kBps = <12157000>; 5288 }; 5289 5290 opp-7 { 5291 opp-peak-kBps = <14060000>; 5292 }; 5293 5294 opp-8 { 5295 opp-peak-kBps = <16113000>; 5296 }; 5297 }; 5298 }; 5299 5300 pmu@240b6400 { 5301 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 5302 reg = <0 0x240b6400 0 0x600>; 5303 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5304 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5305 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5306 5307 operating-points-v2 = <&cpu_bwmon_opp_table>; 5308 5309 cpu_bwmon_opp_table: opp-table { 5310 compatible = "operating-points-v2"; 5311 5312 opp-0 { 5313 opp-peak-kBps = <4577000>; 5314 }; 5315 5316 opp-1 { 5317 opp-peak-kBps = <7110000>; 5318 }; 5319 5320 opp-2 { 5321 opp-peak-kBps = <9155000>; 5322 }; 5323 5324 opp-3 { 5325 opp-peak-kBps = <12298000>; 5326 }; 5327 5328 opp-4 { 5329 opp-peak-kBps = <14236000>; 5330 }; 5331 5332 opp-5 { 5333 opp-peak-kBps = <16265000>; 5334 }; 5335 }; 5336 }; 5337 5338 gem_noc: interconnect@24100000 { 5339 compatible = "qcom,sm8550-gem-noc"; 5340 reg = <0 0x24100000 0 0xbb800>; 5341 #interconnect-cells = <2>; 5342 qcom,bcm-voters = <&apps_bcm_voter>; 5343 }; 5344 5345 system-cache-controller@25000000 { 5346 compatible = "qcom,sm8550-llcc"; 5347 reg = <0 0x25000000 0 0x200000>, 5348 <0 0x25200000 0 0x200000>, 5349 <0 0x25400000 0 0x200000>, 5350 <0 0x25600000 0 0x200000>, 5351 <0 0x25800000 0 0x200000>, 5352 <0 0x25a00000 0 0x200000>; 5353 reg-names = "llcc0_base", 5354 "llcc1_base", 5355 "llcc2_base", 5356 "llcc3_base", 5357 "llcc_broadcast_base", 5358 "llcc_broadcast_and_base"; 5359 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5360 }; 5361 5362 nsp_noc: interconnect@320c0000 { 5363 compatible = "qcom,sm8550-nsp-noc"; 5364 reg = <0 0x320c0000 0 0xe080>; 5365 #interconnect-cells = <2>; 5366 qcom,bcm-voters = <&apps_bcm_voter>; 5367 }; 5368 5369 remoteproc_cdsp: remoteproc@32300000 { 5370 compatible = "qcom,sm8550-cdsp-pas"; 5371 reg = <0x0 0x32300000 0x0 0x10000>; 5372 5373 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5374 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5375 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5376 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5377 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5378 interrupt-names = "wdog", "fatal", "ready", 5379 "handover", "stop-ack"; 5380 5381 clocks = <&rpmhcc RPMH_CXO_CLK>; 5382 clock-names = "xo"; 5383 5384 power-domains = <&rpmhpd RPMHPD_CX>, 5385 <&rpmhpd RPMHPD_MXC>, 5386 <&rpmhpd RPMHPD_NSP>; 5387 power-domain-names = "cx", "mxc", "nsp"; 5388 5389 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5391 5392 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 5393 5394 qcom,qmp = <&aoss_qmp>; 5395 5396 qcom,smem-states = <&smp2p_cdsp_out 0>; 5397 qcom,smem-state-names = "stop"; 5398 5399 status = "disabled"; 5400 5401 glink-edge { 5402 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5403 IPCC_MPROC_SIGNAL_GLINK_QMP 5404 IRQ_TYPE_EDGE_RISING>; 5405 mboxes = <&ipcc IPCC_CLIENT_CDSP 5406 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5407 5408 label = "cdsp"; 5409 qcom,remote-pid = <5>; 5410 5411 fastrpc { 5412 compatible = "qcom,fastrpc"; 5413 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5414 label = "cdsp"; 5415 qcom,non-secure-domain; 5416 #address-cells = <1>; 5417 #size-cells = <0>; 5418 5419 compute-cb@1 { 5420 compatible = "qcom,fastrpc-compute-cb"; 5421 reg = <1>; 5422 iommus = <&apps_smmu 0x1961 0x0>, 5423 <&apps_smmu 0x0c01 0x20>, 5424 <&apps_smmu 0x19c1 0x10>; 5425 dma-coherent; 5426 }; 5427 5428 compute-cb@2 { 5429 compatible = "qcom,fastrpc-compute-cb"; 5430 reg = <2>; 5431 iommus = <&apps_smmu 0x1962 0x0>, 5432 <&apps_smmu 0x0c02 0x20>, 5433 <&apps_smmu 0x19c2 0x10>; 5434 dma-coherent; 5435 }; 5436 5437 compute-cb@3 { 5438 compatible = "qcom,fastrpc-compute-cb"; 5439 reg = <3>; 5440 iommus = <&apps_smmu 0x1963 0x0>, 5441 <&apps_smmu 0x0c03 0x20>, 5442 <&apps_smmu 0x19c3 0x10>; 5443 dma-coherent; 5444 }; 5445 5446 compute-cb@4 { 5447 compatible = "qcom,fastrpc-compute-cb"; 5448 reg = <4>; 5449 iommus = <&apps_smmu 0x1964 0x0>, 5450 <&apps_smmu 0x0c04 0x20>, 5451 <&apps_smmu 0x19c4 0x10>; 5452 dma-coherent; 5453 }; 5454 5455 compute-cb@5 { 5456 compatible = "qcom,fastrpc-compute-cb"; 5457 reg = <5>; 5458 iommus = <&apps_smmu 0x1965 0x0>, 5459 <&apps_smmu 0x0c05 0x20>, 5460 <&apps_smmu 0x19c5 0x10>; 5461 dma-coherent; 5462 }; 5463 5464 compute-cb@6 { 5465 compatible = "qcom,fastrpc-compute-cb"; 5466 reg = <6>; 5467 iommus = <&apps_smmu 0x1966 0x0>, 5468 <&apps_smmu 0x0c06 0x20>, 5469 <&apps_smmu 0x19c6 0x10>; 5470 dma-coherent; 5471 }; 5472 5473 compute-cb@7 { 5474 compatible = "qcom,fastrpc-compute-cb"; 5475 reg = <7>; 5476 iommus = <&apps_smmu 0x1967 0x0>, 5477 <&apps_smmu 0x0c07 0x20>, 5478 <&apps_smmu 0x19c7 0x10>; 5479 dma-coherent; 5480 }; 5481 5482 compute-cb@8 { 5483 compatible = "qcom,fastrpc-compute-cb"; 5484 reg = <8>; 5485 iommus = <&apps_smmu 0x1968 0x0>, 5486 <&apps_smmu 0x0c08 0x20>, 5487 <&apps_smmu 0x19c8 0x10>; 5488 dma-coherent; 5489 }; 5490 5491 /* note: secure cb9 in downstream */ 5492 }; 5493 }; 5494 }; 5495 }; 5496 5497 thermal-zones { 5498 aoss0-thermal { 5499 thermal-sensors = <&tsens0 0>; 5500 5501 trips { 5502 thermal-engine-config { 5503 temperature = <125000>; 5504 hysteresis = <1000>; 5505 type = "passive"; 5506 }; 5507 5508 reset-mon-config { 5509 temperature = <115000>; 5510 hysteresis = <5000>; 5511 type = "passive"; 5512 }; 5513 }; 5514 }; 5515 5516 cpuss0-thermal { 5517 thermal-sensors = <&tsens0 1>; 5518 5519 trips { 5520 thermal-engine-config { 5521 temperature = <125000>; 5522 hysteresis = <1000>; 5523 type = "passive"; 5524 }; 5525 5526 reset-mon-config { 5527 temperature = <115000>; 5528 hysteresis = <5000>; 5529 type = "passive"; 5530 }; 5531 }; 5532 }; 5533 5534 cpuss1-thermal { 5535 thermal-sensors = <&tsens0 2>; 5536 5537 trips { 5538 thermal-engine-config { 5539 temperature = <125000>; 5540 hysteresis = <1000>; 5541 type = "passive"; 5542 }; 5543 5544 reset-mon-config { 5545 temperature = <115000>; 5546 hysteresis = <5000>; 5547 type = "passive"; 5548 }; 5549 }; 5550 }; 5551 5552 cpuss2-thermal { 5553 thermal-sensors = <&tsens0 3>; 5554 5555 trips { 5556 thermal-engine-config { 5557 temperature = <125000>; 5558 hysteresis = <1000>; 5559 type = "passive"; 5560 }; 5561 5562 reset-mon-config { 5563 temperature = <115000>; 5564 hysteresis = <5000>; 5565 type = "passive"; 5566 }; 5567 }; 5568 }; 5569 5570 cpuss3-thermal { 5571 thermal-sensors = <&tsens0 4>; 5572 5573 trips { 5574 thermal-engine-config { 5575 temperature = <125000>; 5576 hysteresis = <1000>; 5577 type = "passive"; 5578 }; 5579 5580 reset-mon-config { 5581 temperature = <115000>; 5582 hysteresis = <5000>; 5583 type = "passive"; 5584 }; 5585 }; 5586 }; 5587 5588 cpu3-top-thermal { 5589 thermal-sensors = <&tsens0 5>; 5590 5591 trips { 5592 cpu3_top_alert0: trip-point0 { 5593 temperature = <90000>; 5594 hysteresis = <2000>; 5595 type = "passive"; 5596 }; 5597 5598 cpu3_top_alert1: trip-point1 { 5599 temperature = <95000>; 5600 hysteresis = <2000>; 5601 type = "passive"; 5602 }; 5603 5604 cpu3_top_crit: cpu-critical { 5605 temperature = <110000>; 5606 hysteresis = <1000>; 5607 type = "critical"; 5608 }; 5609 }; 5610 }; 5611 5612 cpu3-bottom-thermal { 5613 thermal-sensors = <&tsens0 6>; 5614 5615 trips { 5616 cpu3_bottom_alert0: trip-point0 { 5617 temperature = <90000>; 5618 hysteresis = <2000>; 5619 type = "passive"; 5620 }; 5621 5622 cpu3_bottom_alert1: trip-point1 { 5623 temperature = <95000>; 5624 hysteresis = <2000>; 5625 type = "passive"; 5626 }; 5627 5628 cpu3_bottom_crit: cpu-critical { 5629 temperature = <110000>; 5630 hysteresis = <1000>; 5631 type = "critical"; 5632 }; 5633 }; 5634 }; 5635 5636 cpu4-top-thermal { 5637 thermal-sensors = <&tsens0 7>; 5638 5639 trips { 5640 cpu4_top_alert0: trip-point0 { 5641 temperature = <90000>; 5642 hysteresis = <2000>; 5643 type = "passive"; 5644 }; 5645 5646 cpu4_top_alert1: trip-point1 { 5647 temperature = <95000>; 5648 hysteresis = <2000>; 5649 type = "passive"; 5650 }; 5651 5652 cpu4_top_crit: cpu-critical { 5653 temperature = <110000>; 5654 hysteresis = <1000>; 5655 type = "critical"; 5656 }; 5657 }; 5658 }; 5659 5660 cpu4-bottom-thermal { 5661 thermal-sensors = <&tsens0 8>; 5662 5663 trips { 5664 cpu4_bottom_alert0: trip-point0 { 5665 temperature = <90000>; 5666 hysteresis = <2000>; 5667 type = "passive"; 5668 }; 5669 5670 cpu4_bottom_alert1: trip-point1 { 5671 temperature = <95000>; 5672 hysteresis = <2000>; 5673 type = "passive"; 5674 }; 5675 5676 cpu4_bottom_crit: cpu-critical { 5677 temperature = <110000>; 5678 hysteresis = <1000>; 5679 type = "critical"; 5680 }; 5681 }; 5682 }; 5683 5684 cpu5-top-thermal { 5685 thermal-sensors = <&tsens0 9>; 5686 5687 trips { 5688 cpu5_top_alert0: trip-point0 { 5689 temperature = <90000>; 5690 hysteresis = <2000>; 5691 type = "passive"; 5692 }; 5693 5694 cpu5_top_alert1: trip-point1 { 5695 temperature = <95000>; 5696 hysteresis = <2000>; 5697 type = "passive"; 5698 }; 5699 5700 cpu5_top_crit: cpu-critical { 5701 temperature = <110000>; 5702 hysteresis = <1000>; 5703 type = "critical"; 5704 }; 5705 }; 5706 }; 5707 5708 cpu5-bottom-thermal { 5709 thermal-sensors = <&tsens0 10>; 5710 5711 trips { 5712 cpu5_bottom_alert0: trip-point0 { 5713 temperature = <90000>; 5714 hysteresis = <2000>; 5715 type = "passive"; 5716 }; 5717 5718 cpu5_bottom_alert1: trip-point1 { 5719 temperature = <95000>; 5720 hysteresis = <2000>; 5721 type = "passive"; 5722 }; 5723 5724 cpu5_bottom_crit: cpu-critical { 5725 temperature = <110000>; 5726 hysteresis = <1000>; 5727 type = "critical"; 5728 }; 5729 }; 5730 }; 5731 5732 cpu6-top-thermal { 5733 thermal-sensors = <&tsens0 11>; 5734 5735 trips { 5736 cpu6_top_alert0: trip-point0 { 5737 temperature = <90000>; 5738 hysteresis = <2000>; 5739 type = "passive"; 5740 }; 5741 5742 cpu6_top_alert1: trip-point1 { 5743 temperature = <95000>; 5744 hysteresis = <2000>; 5745 type = "passive"; 5746 }; 5747 5748 cpu6_top_crit: cpu-critical { 5749 temperature = <110000>; 5750 hysteresis = <1000>; 5751 type = "critical"; 5752 }; 5753 }; 5754 }; 5755 5756 cpu6-bottom-thermal { 5757 thermal-sensors = <&tsens0 12>; 5758 5759 trips { 5760 cpu6_bottom_alert0: trip-point0 { 5761 temperature = <90000>; 5762 hysteresis = <2000>; 5763 type = "passive"; 5764 }; 5765 5766 cpu6_bottom_alert1: trip-point1 { 5767 temperature = <95000>; 5768 hysteresis = <2000>; 5769 type = "passive"; 5770 }; 5771 5772 cpu6_bottom_crit: cpu-critical { 5773 temperature = <110000>; 5774 hysteresis = <1000>; 5775 type = "critical"; 5776 }; 5777 }; 5778 }; 5779 5780 cpu7-top-thermal { 5781 thermal-sensors = <&tsens0 13>; 5782 5783 trips { 5784 cpu7_top_alert0: trip-point0 { 5785 temperature = <90000>; 5786 hysteresis = <2000>; 5787 type = "passive"; 5788 }; 5789 5790 cpu7_top_alert1: trip-point1 { 5791 temperature = <95000>; 5792 hysteresis = <2000>; 5793 type = "passive"; 5794 }; 5795 5796 cpu7_top_crit: cpu-critical { 5797 temperature = <110000>; 5798 hysteresis = <1000>; 5799 type = "critical"; 5800 }; 5801 }; 5802 }; 5803 5804 cpu7-middle-thermal { 5805 thermal-sensors = <&tsens0 14>; 5806 5807 trips { 5808 cpu7_middle_alert0: trip-point0 { 5809 temperature = <90000>; 5810 hysteresis = <2000>; 5811 type = "passive"; 5812 }; 5813 5814 cpu7_middle_alert1: trip-point1 { 5815 temperature = <95000>; 5816 hysteresis = <2000>; 5817 type = "passive"; 5818 }; 5819 5820 cpu7_middle_crit: cpu-critical { 5821 temperature = <110000>; 5822 hysteresis = <1000>; 5823 type = "critical"; 5824 }; 5825 }; 5826 }; 5827 5828 cpu7-bottom-thermal { 5829 thermal-sensors = <&tsens0 15>; 5830 5831 trips { 5832 cpu7_bottom_alert0: trip-point0 { 5833 temperature = <90000>; 5834 hysteresis = <2000>; 5835 type = "passive"; 5836 }; 5837 5838 cpu7_bottom_alert1: trip-point1 { 5839 temperature = <95000>; 5840 hysteresis = <2000>; 5841 type = "passive"; 5842 }; 5843 5844 cpu7_bottom_crit: cpu-critical { 5845 temperature = <110000>; 5846 hysteresis = <1000>; 5847 type = "critical"; 5848 }; 5849 }; 5850 }; 5851 5852 aoss1-thermal { 5853 thermal-sensors = <&tsens1 0>; 5854 5855 trips { 5856 thermal-engine-config { 5857 temperature = <125000>; 5858 hysteresis = <1000>; 5859 type = "passive"; 5860 }; 5861 5862 reset-mon-config { 5863 temperature = <115000>; 5864 hysteresis = <5000>; 5865 type = "passive"; 5866 }; 5867 }; 5868 }; 5869 5870 cpu0-thermal { 5871 thermal-sensors = <&tsens1 1>; 5872 5873 trips { 5874 cpu0_alert0: trip-point0 { 5875 temperature = <90000>; 5876 hysteresis = <2000>; 5877 type = "passive"; 5878 }; 5879 5880 cpu0_alert1: trip-point1 { 5881 temperature = <95000>; 5882 hysteresis = <2000>; 5883 type = "passive"; 5884 }; 5885 5886 cpu0_crit: cpu-critical { 5887 temperature = <110000>; 5888 hysteresis = <1000>; 5889 type = "critical"; 5890 }; 5891 }; 5892 }; 5893 5894 cpu1-thermal { 5895 thermal-sensors = <&tsens1 2>; 5896 5897 trips { 5898 cpu1_alert0: trip-point0 { 5899 temperature = <90000>; 5900 hysteresis = <2000>; 5901 type = "passive"; 5902 }; 5903 5904 cpu1_alert1: trip-point1 { 5905 temperature = <95000>; 5906 hysteresis = <2000>; 5907 type = "passive"; 5908 }; 5909 5910 cpu1_crit: cpu-critical { 5911 temperature = <110000>; 5912 hysteresis = <1000>; 5913 type = "critical"; 5914 }; 5915 }; 5916 }; 5917 5918 cpu2-thermal { 5919 thermal-sensors = <&tsens1 3>; 5920 5921 trips { 5922 cpu2_alert0: trip-point0 { 5923 temperature = <90000>; 5924 hysteresis = <2000>; 5925 type = "passive"; 5926 }; 5927 5928 cpu2_alert1: trip-point1 { 5929 temperature = <95000>; 5930 hysteresis = <2000>; 5931 type = "passive"; 5932 }; 5933 5934 cpu2_crit: cpu-critical { 5935 temperature = <110000>; 5936 hysteresis = <1000>; 5937 type = "critical"; 5938 }; 5939 }; 5940 }; 5941 5942 cdsp0-thermal { 5943 polling-delay-passive = <10>; 5944 5945 thermal-sensors = <&tsens2 4>; 5946 5947 trips { 5948 thermal-engine-config { 5949 temperature = <125000>; 5950 hysteresis = <1000>; 5951 type = "passive"; 5952 }; 5953 5954 thermal-hal-config { 5955 temperature = <125000>; 5956 hysteresis = <1000>; 5957 type = "passive"; 5958 }; 5959 5960 reset-mon-config { 5961 temperature = <115000>; 5962 hysteresis = <5000>; 5963 type = "passive"; 5964 }; 5965 5966 cdsp0_junction_config: junction-config { 5967 temperature = <95000>; 5968 hysteresis = <5000>; 5969 type = "passive"; 5970 }; 5971 }; 5972 }; 5973 5974 cdsp1-thermal { 5975 polling-delay-passive = <10>; 5976 5977 thermal-sensors = <&tsens2 5>; 5978 5979 trips { 5980 thermal-engine-config { 5981 temperature = <125000>; 5982 hysteresis = <1000>; 5983 type = "passive"; 5984 }; 5985 5986 thermal-hal-config { 5987 temperature = <125000>; 5988 hysteresis = <1000>; 5989 type = "passive"; 5990 }; 5991 5992 reset-mon-config { 5993 temperature = <115000>; 5994 hysteresis = <5000>; 5995 type = "passive"; 5996 }; 5997 5998 cdsp1_junction_config: junction-config { 5999 temperature = <95000>; 6000 hysteresis = <5000>; 6001 type = "passive"; 6002 }; 6003 }; 6004 }; 6005 6006 cdsp2-thermal { 6007 polling-delay-passive = <10>; 6008 6009 thermal-sensors = <&tsens2 6>; 6010 6011 trips { 6012 thermal-engine-config { 6013 temperature = <125000>; 6014 hysteresis = <1000>; 6015 type = "passive"; 6016 }; 6017 6018 thermal-hal-config { 6019 temperature = <125000>; 6020 hysteresis = <1000>; 6021 type = "passive"; 6022 }; 6023 6024 reset-mon-config { 6025 temperature = <115000>; 6026 hysteresis = <5000>; 6027 type = "passive"; 6028 }; 6029 6030 cdsp2_junction_config: junction-config { 6031 temperature = <95000>; 6032 hysteresis = <5000>; 6033 type = "passive"; 6034 }; 6035 }; 6036 }; 6037 6038 cdsp3-thermal { 6039 polling-delay-passive = <10>; 6040 6041 thermal-sensors = <&tsens2 7>; 6042 6043 trips { 6044 thermal-engine-config { 6045 temperature = <125000>; 6046 hysteresis = <1000>; 6047 type = "passive"; 6048 }; 6049 6050 thermal-hal-config { 6051 temperature = <125000>; 6052 hysteresis = <1000>; 6053 type = "passive"; 6054 }; 6055 6056 reset-mon-config { 6057 temperature = <115000>; 6058 hysteresis = <5000>; 6059 type = "passive"; 6060 }; 6061 6062 cdsp3_junction_config: junction-config { 6063 temperature = <95000>; 6064 hysteresis = <5000>; 6065 type = "passive"; 6066 }; 6067 }; 6068 }; 6069 6070 video-thermal { 6071 thermal-sensors = <&tsens1 8>; 6072 6073 trips { 6074 thermal-engine-config { 6075 temperature = <125000>; 6076 hysteresis = <1000>; 6077 type = "passive"; 6078 }; 6079 6080 reset-mon-config { 6081 temperature = <115000>; 6082 hysteresis = <5000>; 6083 type = "passive"; 6084 }; 6085 }; 6086 }; 6087 6088 mem-thermal { 6089 polling-delay-passive = <10>; 6090 6091 thermal-sensors = <&tsens1 9>; 6092 6093 trips { 6094 thermal-engine-config { 6095 temperature = <125000>; 6096 hysteresis = <1000>; 6097 type = "passive"; 6098 }; 6099 6100 ddr_config0: ddr0-config { 6101 temperature = <90000>; 6102 hysteresis = <5000>; 6103 type = "passive"; 6104 }; 6105 6106 reset-mon-config { 6107 temperature = <115000>; 6108 hysteresis = <5000>; 6109 type = "passive"; 6110 }; 6111 }; 6112 }; 6113 6114 modem0-thermal { 6115 thermal-sensors = <&tsens1 10>; 6116 6117 trips { 6118 thermal-engine-config { 6119 temperature = <125000>; 6120 hysteresis = <1000>; 6121 type = "passive"; 6122 }; 6123 6124 mdmss0_config0: mdmss0-config0 { 6125 temperature = <102000>; 6126 hysteresis = <3000>; 6127 type = "passive"; 6128 }; 6129 6130 mdmss0_config1: mdmss0-config1 { 6131 temperature = <105000>; 6132 hysteresis = <3000>; 6133 type = "passive"; 6134 }; 6135 6136 reset-mon-config { 6137 temperature = <115000>; 6138 hysteresis = <5000>; 6139 type = "passive"; 6140 }; 6141 }; 6142 }; 6143 6144 modem1-thermal { 6145 thermal-sensors = <&tsens1 11>; 6146 6147 trips { 6148 thermal-engine-config { 6149 temperature = <125000>; 6150 hysteresis = <1000>; 6151 type = "passive"; 6152 }; 6153 6154 mdmss1_config0: mdmss1-config0 { 6155 temperature = <102000>; 6156 hysteresis = <3000>; 6157 type = "passive"; 6158 }; 6159 6160 mdmss1_config1: mdmss1-config1 { 6161 temperature = <105000>; 6162 hysteresis = <3000>; 6163 type = "passive"; 6164 }; 6165 6166 reset-mon-config { 6167 temperature = <115000>; 6168 hysteresis = <5000>; 6169 type = "passive"; 6170 }; 6171 }; 6172 }; 6173 6174 modem2-thermal { 6175 thermal-sensors = <&tsens1 12>; 6176 6177 trips { 6178 thermal-engine-config { 6179 temperature = <125000>; 6180 hysteresis = <1000>; 6181 type = "passive"; 6182 }; 6183 6184 mdmss2_config0: mdmss2-config0 { 6185 temperature = <102000>; 6186 hysteresis = <3000>; 6187 type = "passive"; 6188 }; 6189 6190 mdmss2_config1: mdmss2-config1 { 6191 temperature = <105000>; 6192 hysteresis = <3000>; 6193 type = "passive"; 6194 }; 6195 6196 reset-mon-config { 6197 temperature = <115000>; 6198 hysteresis = <5000>; 6199 type = "passive"; 6200 }; 6201 }; 6202 }; 6203 6204 modem3-thermal { 6205 thermal-sensors = <&tsens1 13>; 6206 6207 trips { 6208 thermal-engine-config { 6209 temperature = <125000>; 6210 hysteresis = <1000>; 6211 type = "passive"; 6212 }; 6213 6214 mdmss3_config0: mdmss3-config0 { 6215 temperature = <102000>; 6216 hysteresis = <3000>; 6217 type = "passive"; 6218 }; 6219 6220 mdmss3_config1: mdmss3-config1 { 6221 temperature = <105000>; 6222 hysteresis = <3000>; 6223 type = "passive"; 6224 }; 6225 6226 reset-mon-config { 6227 temperature = <115000>; 6228 hysteresis = <5000>; 6229 type = "passive"; 6230 }; 6231 }; 6232 }; 6233 6234 camera0-thermal { 6235 thermal-sensors = <&tsens1 14>; 6236 6237 trips { 6238 thermal-engine-config { 6239 temperature = <125000>; 6240 hysteresis = <1000>; 6241 type = "passive"; 6242 }; 6243 6244 reset-mon-config { 6245 temperature = <115000>; 6246 hysteresis = <5000>; 6247 type = "passive"; 6248 }; 6249 }; 6250 }; 6251 6252 camera1-thermal { 6253 thermal-sensors = <&tsens1 15>; 6254 6255 trips { 6256 thermal-engine-config { 6257 temperature = <125000>; 6258 hysteresis = <1000>; 6259 type = "passive"; 6260 }; 6261 6262 reset-mon-config { 6263 temperature = <115000>; 6264 hysteresis = <5000>; 6265 type = "passive"; 6266 }; 6267 }; 6268 }; 6269 6270 aoss2-thermal { 6271 thermal-sensors = <&tsens2 0>; 6272 6273 trips { 6274 thermal-engine-config { 6275 temperature = <125000>; 6276 hysteresis = <1000>; 6277 type = "passive"; 6278 }; 6279 6280 reset-mon-config { 6281 temperature = <115000>; 6282 hysteresis = <5000>; 6283 type = "passive"; 6284 }; 6285 }; 6286 }; 6287 6288 gpuss-0-thermal { 6289 polling-delay-passive = <10>; 6290 6291 thermal-sensors = <&tsens2 1>; 6292 6293 cooling-maps { 6294 map0 { 6295 trip = <&gpu0_alert0>; 6296 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6297 }; 6298 }; 6299 6300 trips { 6301 gpu0_alert0: trip-point0 { 6302 temperature = <85000>; 6303 hysteresis = <1000>; 6304 type = "passive"; 6305 }; 6306 6307 trip-point1 { 6308 temperature = <90000>; 6309 hysteresis = <1000>; 6310 type = "hot"; 6311 }; 6312 6313 trip-point2 { 6314 temperature = <110000>; 6315 hysteresis = <1000>; 6316 type = "critical"; 6317 }; 6318 }; 6319 }; 6320 6321 gpuss-1-thermal { 6322 polling-delay-passive = <10>; 6323 6324 thermal-sensors = <&tsens2 2>; 6325 6326 cooling-maps { 6327 map0 { 6328 trip = <&gpu1_alert0>; 6329 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6330 }; 6331 }; 6332 6333 trips { 6334 gpu1_alert0: trip-point0 { 6335 temperature = <85000>; 6336 hysteresis = <1000>; 6337 type = "passive"; 6338 }; 6339 6340 trip-point1 { 6341 temperature = <90000>; 6342 hysteresis = <1000>; 6343 type = "hot"; 6344 }; 6345 6346 trip-point2 { 6347 temperature = <110000>; 6348 hysteresis = <1000>; 6349 type = "critical"; 6350 }; 6351 }; 6352 }; 6353 6354 gpuss-2-thermal { 6355 polling-delay-passive = <10>; 6356 6357 thermal-sensors = <&tsens2 3>; 6358 6359 cooling-maps { 6360 map0 { 6361 trip = <&gpu2_alert0>; 6362 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6363 }; 6364 }; 6365 6366 trips { 6367 gpu2_alert0: trip-point0 { 6368 temperature = <85000>; 6369 hysteresis = <1000>; 6370 type = "passive"; 6371 }; 6372 6373 trip-point1 { 6374 temperature = <90000>; 6375 hysteresis = <1000>; 6376 type = "hot"; 6377 }; 6378 6379 trip-point2 { 6380 temperature = <110000>; 6381 hysteresis = <1000>; 6382 type = "critical"; 6383 }; 6384 }; 6385 }; 6386 6387 gpuss-3-thermal { 6388 polling-delay-passive = <10>; 6389 6390 thermal-sensors = <&tsens2 4>; 6391 6392 cooling-maps { 6393 map0 { 6394 trip = <&gpu3_alert0>; 6395 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6396 }; 6397 }; 6398 6399 trips { 6400 gpu3_alert0: trip-point0 { 6401 temperature = <85000>; 6402 hysteresis = <1000>; 6403 type = "passive"; 6404 }; 6405 6406 trip-point1 { 6407 temperature = <90000>; 6408 hysteresis = <1000>; 6409 type = "hot"; 6410 }; 6411 6412 trip-point2 { 6413 temperature = <110000>; 6414 hysteresis = <1000>; 6415 type = "critical"; 6416 }; 6417 }; 6418 }; 6419 6420 gpuss-4-thermal { 6421 polling-delay-passive = <10>; 6422 6423 thermal-sensors = <&tsens2 5>; 6424 6425 cooling-maps { 6426 map0 { 6427 trip = <&gpu4_alert0>; 6428 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6429 }; 6430 }; 6431 6432 trips { 6433 gpu4_alert0: trip-point0 { 6434 temperature = <85000>; 6435 hysteresis = <1000>; 6436 type = "passive"; 6437 }; 6438 6439 trip-point1 { 6440 temperature = <90000>; 6441 hysteresis = <1000>; 6442 type = "hot"; 6443 }; 6444 6445 trip-point2 { 6446 temperature = <110000>; 6447 hysteresis = <1000>; 6448 type = "critical"; 6449 }; 6450 }; 6451 }; 6452 6453 gpuss-5-thermal { 6454 polling-delay-passive = <10>; 6455 6456 thermal-sensors = <&tsens2 6>; 6457 6458 cooling-maps { 6459 map0 { 6460 trip = <&gpu5_alert0>; 6461 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6462 }; 6463 }; 6464 6465 trips { 6466 gpu5_alert0: trip-point0 { 6467 temperature = <85000>; 6468 hysteresis = <1000>; 6469 type = "passive"; 6470 }; 6471 6472 trip-point1 { 6473 temperature = <90000>; 6474 hysteresis = <1000>; 6475 type = "hot"; 6476 }; 6477 6478 trip-point2 { 6479 temperature = <110000>; 6480 hysteresis = <1000>; 6481 type = "critical"; 6482 }; 6483 }; 6484 }; 6485 6486 gpuss-6-thermal { 6487 polling-delay-passive = <10>; 6488 6489 thermal-sensors = <&tsens2 7>; 6490 6491 cooling-maps { 6492 map0 { 6493 trip = <&gpu6_alert0>; 6494 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6495 }; 6496 }; 6497 6498 trips { 6499 gpu6_alert0: trip-point0 { 6500 temperature = <85000>; 6501 hysteresis = <1000>; 6502 type = "passive"; 6503 }; 6504 6505 trip-point1 { 6506 temperature = <90000>; 6507 hysteresis = <1000>; 6508 type = "hot"; 6509 }; 6510 6511 trip-point2 { 6512 temperature = <110000>; 6513 hysteresis = <1000>; 6514 type = "critical"; 6515 }; 6516 }; 6517 }; 6518 6519 gpuss-7-thermal { 6520 polling-delay-passive = <10>; 6521 6522 thermal-sensors = <&tsens2 8>; 6523 6524 cooling-maps { 6525 map0 { 6526 trip = <&gpu7_alert0>; 6527 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6528 }; 6529 }; 6530 6531 trips { 6532 gpu7_alert0: trip-point0 { 6533 temperature = <85000>; 6534 hysteresis = <1000>; 6535 type = "passive"; 6536 }; 6537 6538 trip-point1 { 6539 temperature = <90000>; 6540 hysteresis = <1000>; 6541 type = "hot"; 6542 }; 6543 6544 trip-point2 { 6545 temperature = <110000>; 6546 hysteresis = <1000>; 6547 type = "critical"; 6548 }; 6549 }; 6550 }; 6551 }; 6552 6553 timer { 6554 compatible = "arm,armv8-timer"; 6555 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6556 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6557 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6558 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6559 }; 6560}; 6561