1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/firmware/qcom,scm.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/phy/phy-qcom-qmp.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 15#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 16#include <dt-bindings/clock/qcom,gcc-sm8150.h> 17#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 18#include <dt-bindings/clock/qcom,videocc-sm8150.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interconnect/qcom,sm8150.h> 21#include <dt-bindings/clock/qcom,sm8150-camcc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <38400000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32764>; 44 clock-output-names = "sleep_clk"; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "qcom,kryo485"; 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 57 enable-method = "psci"; 58 capacity-dmips-mhz = <488>; 59 dynamic-power-coefficient = <232>; 60 next-level-cache = <&l2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 64 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 65 power-domains = <&cpu_pd0>; 66 power-domain-names = "psci"; 67 #cooling-cells = <2>; 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 l3_0: l3-cache { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 }; 78 }; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo485"; 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <488>; 88 dynamic-power-coefficient = <232>; 89 next-level-cache = <&l2_100>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 93 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 94 power-domains = <&cpu_pd1>; 95 power-domain-names = "psci"; 96 #cooling-cells = <2>; 97 l2_100: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&l3_0>; 102 }; 103 }; 104 105 cpu2: cpu@200 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo485"; 108 reg = <0x0 0x200>; 109 clocks = <&cpufreq_hw 0>; 110 enable-method = "psci"; 111 capacity-dmips-mhz = <488>; 112 dynamic-power-coefficient = <232>; 113 next-level-cache = <&l2_200>; 114 qcom,freq-domain = <&cpufreq_hw 0>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 117 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 118 power-domains = <&cpu_pd2>; 119 power-domain-names = "psci"; 120 #cooling-cells = <2>; 121 l2_200: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 cache-unified; 125 next-level-cache = <&l3_0>; 126 }; 127 }; 128 129 cpu3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo485"; 132 reg = <0x0 0x300>; 133 clocks = <&cpufreq_hw 0>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <488>; 136 dynamic-power-coefficient = <232>; 137 next-level-cache = <&l2_300>; 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 141 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 142 power-domains = <&cpu_pd3>; 143 power-domain-names = "psci"; 144 #cooling-cells = <2>; 145 l2_300: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu4: cpu@400 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x400>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 dynamic-power-coefficient = <369>; 161 next-level-cache = <&l2_400>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 operating-points-v2 = <&cpu4_opp_table>; 164 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 power-domains = <&cpu_pd4>; 167 power-domain-names = "psci"; 168 #cooling-cells = <2>; 169 l2_400: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&l3_0>; 174 }; 175 }; 176 177 cpu5: cpu@500 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x500>; 181 clocks = <&cpufreq_hw 1>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 dynamic-power-coefficient = <369>; 185 next-level-cache = <&l2_500>; 186 qcom,freq-domain = <&cpufreq_hw 1>; 187 operating-points-v2 = <&cpu4_opp_table>; 188 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 189 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 190 power-domains = <&cpu_pd5>; 191 power-domain-names = "psci"; 192 #cooling-cells = <2>; 193 l2_500: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&l3_0>; 198 }; 199 }; 200 201 cpu6: cpu@600 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo485"; 204 reg = <0x0 0x600>; 205 clocks = <&cpufreq_hw 1>; 206 enable-method = "psci"; 207 capacity-dmips-mhz = <1024>; 208 dynamic-power-coefficient = <369>; 209 next-level-cache = <&l2_600>; 210 qcom,freq-domain = <&cpufreq_hw 1>; 211 operating-points-v2 = <&cpu4_opp_table>; 212 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 power-domains = <&cpu_pd6>; 215 power-domain-names = "psci"; 216 #cooling-cells = <2>; 217 l2_600: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&l3_0>; 222 }; 223 }; 224 225 cpu7: cpu@700 { 226 device_type = "cpu"; 227 compatible = "qcom,kryo485"; 228 reg = <0x0 0x700>; 229 clocks = <&cpufreq_hw 2>; 230 enable-method = "psci"; 231 capacity-dmips-mhz = <1024>; 232 dynamic-power-coefficient = <421>; 233 next-level-cache = <&l2_700>; 234 qcom,freq-domain = <&cpufreq_hw 2>; 235 operating-points-v2 = <&cpu7_opp_table>; 236 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 237 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 238 power-domains = <&cpu_pd7>; 239 power-domain-names = "psci"; 240 #cooling-cells = <2>; 241 l2_700: l2-cache { 242 compatible = "cache"; 243 cache-level = <2>; 244 cache-unified; 245 next-level-cache = <&l3_0>; 246 }; 247 }; 248 249 cpu-map { 250 cluster0 { 251 core0 { 252 cpu = <&cpu0>; 253 }; 254 255 core1 { 256 cpu = <&cpu1>; 257 }; 258 259 core2 { 260 cpu = <&cpu2>; 261 }; 262 263 core3 { 264 cpu = <&cpu3>; 265 }; 266 267 core4 { 268 cpu = <&cpu4>; 269 }; 270 271 core5 { 272 cpu = <&cpu5>; 273 }; 274 275 core6 { 276 cpu = <&cpu6>; 277 }; 278 279 core7 { 280 cpu = <&cpu7>; 281 }; 282 }; 283 }; 284 285 idle-states { 286 entry-method = "psci"; 287 288 little_cpu_sleep_0: cpu-sleep-0-0 { 289 compatible = "arm,idle-state"; 290 idle-state-name = "little-rail-power-collapse"; 291 arm,psci-suspend-param = <0x40000004>; 292 entry-latency-us = <355>; 293 exit-latency-us = <909>; 294 min-residency-us = <3934>; 295 local-timer-stop; 296 }; 297 298 big_cpu_sleep_0: cpu-sleep-1-0 { 299 compatible = "arm,idle-state"; 300 idle-state-name = "big-rail-power-collapse"; 301 arm,psci-suspend-param = <0x40000004>; 302 entry-latency-us = <241>; 303 exit-latency-us = <1461>; 304 min-residency-us = <4488>; 305 local-timer-stop; 306 }; 307 }; 308 309 domain-idle-states { 310 cluster_sleep_0: cluster-sleep-0 { 311 compatible = "domain-idle-state"; 312 arm,psci-suspend-param = <0x4100c244>; 313 entry-latency-us = <3263>; 314 exit-latency-us = <6562>; 315 min-residency-us = <9987>; 316 }; 317 }; 318 }; 319 320 cpu0_opp_table: opp-table-cpu0 { 321 compatible = "operating-points-v2"; 322 opp-shared; 323 324 cpu0_opp1: opp-300000000 { 325 opp-hz = /bits/ 64 <300000000>; 326 opp-peak-kBps = <800000 9600000>; 327 }; 328 329 cpu0_opp2: opp-403200000 { 330 opp-hz = /bits/ 64 <403200000>; 331 opp-peak-kBps = <800000 9600000>; 332 }; 333 334 cpu0_opp3: opp-499200000 { 335 opp-hz = /bits/ 64 <499200000>; 336 opp-peak-kBps = <800000 12902400>; 337 }; 338 339 cpu0_opp4: opp-576000000 { 340 opp-hz = /bits/ 64 <576000000>; 341 opp-peak-kBps = <800000 12902400>; 342 }; 343 344 cpu0_opp5: opp-672000000 { 345 opp-hz = /bits/ 64 <672000000>; 346 opp-peak-kBps = <800000 15974400>; 347 }; 348 349 cpu0_opp6: opp-768000000 { 350 opp-hz = /bits/ 64 <768000000>; 351 opp-peak-kBps = <1804000 19660800>; 352 }; 353 354 cpu0_opp7: opp-844800000 { 355 opp-hz = /bits/ 64 <844800000>; 356 opp-peak-kBps = <1804000 19660800>; 357 }; 358 359 cpu0_opp8: opp-940800000 { 360 opp-hz = /bits/ 64 <940800000>; 361 opp-peak-kBps = <1804000 22732800>; 362 }; 363 364 cpu0_opp9: opp-1036800000 { 365 opp-hz = /bits/ 64 <1036800000>; 366 opp-peak-kBps = <1804000 22732800>; 367 }; 368 369 cpu0_opp10: opp-1113600000 { 370 opp-hz = /bits/ 64 <1113600000>; 371 opp-peak-kBps = <2188000 25804800>; 372 }; 373 374 cpu0_opp11: opp-1209600000 { 375 opp-hz = /bits/ 64 <1209600000>; 376 opp-peak-kBps = <2188000 31948800>; 377 }; 378 379 cpu0_opp12: opp-1305600000 { 380 opp-hz = /bits/ 64 <1305600000>; 381 opp-peak-kBps = <3072000 31948800>; 382 }; 383 384 cpu0_opp13: opp-1382400000 { 385 opp-hz = /bits/ 64 <1382400000>; 386 opp-peak-kBps = <3072000 31948800>; 387 }; 388 389 cpu0_opp14: opp-1478400000 { 390 opp-hz = /bits/ 64 <1478400000>; 391 opp-peak-kBps = <3072000 31948800>; 392 }; 393 394 cpu0_opp15: opp-1555200000 { 395 opp-hz = /bits/ 64 <1555200000>; 396 opp-peak-kBps = <3072000 40550400>; 397 }; 398 399 cpu0_opp16: opp-1632000000 { 400 opp-hz = /bits/ 64 <1632000000>; 401 opp-peak-kBps = <3072000 40550400>; 402 }; 403 404 cpu0_opp17: opp-1708800000 { 405 opp-hz = /bits/ 64 <1708800000>; 406 opp-peak-kBps = <3072000 43008000>; 407 }; 408 409 cpu0_opp18: opp-1785600000 { 410 opp-hz = /bits/ 64 <1785600000>; 411 opp-peak-kBps = <3072000 43008000>; 412 }; 413 }; 414 415 cpu4_opp_table: opp-table-cpu4 { 416 compatible = "operating-points-v2"; 417 opp-shared; 418 419 cpu4_opp1: opp-710400000 { 420 opp-hz = /bits/ 64 <710400000>; 421 opp-peak-kBps = <1804000 15974400>; 422 }; 423 424 cpu4_opp2: opp-825600000 { 425 opp-hz = /bits/ 64 <825600000>; 426 opp-peak-kBps = <2188000 19660800>; 427 }; 428 429 cpu4_opp3: opp-940800000 { 430 opp-hz = /bits/ 64 <940800000>; 431 opp-peak-kBps = <2188000 22732800>; 432 }; 433 434 cpu4_opp4: opp-1056000000 { 435 opp-hz = /bits/ 64 <1056000000>; 436 opp-peak-kBps = <3072000 25804800>; 437 }; 438 439 cpu4_opp5: opp-1171200000 { 440 opp-hz = /bits/ 64 <1171200000>; 441 opp-peak-kBps = <3072000 31948800>; 442 }; 443 444 cpu4_opp6: opp-1286400000 { 445 opp-hz = /bits/ 64 <1286400000>; 446 opp-peak-kBps = <4068000 31948800>; 447 }; 448 449 cpu4_opp7: opp-1401600000 { 450 opp-hz = /bits/ 64 <1401600000>; 451 opp-peak-kBps = <4068000 31948800>; 452 }; 453 454 cpu4_opp8: opp-1497600000 { 455 opp-hz = /bits/ 64 <1497600000>; 456 opp-peak-kBps = <4068000 40550400>; 457 }; 458 459 cpu4_opp9: opp-1612800000 { 460 opp-hz = /bits/ 64 <1612800000>; 461 opp-peak-kBps = <4068000 40550400>; 462 }; 463 464 cpu4_opp10: opp-1708800000 { 465 opp-hz = /bits/ 64 <1708800000>; 466 opp-peak-kBps = <4068000 43008000>; 467 }; 468 469 cpu4_opp11: opp-1804800000 { 470 opp-hz = /bits/ 64 <1804800000>; 471 opp-peak-kBps = <6220000 43008000>; 472 }; 473 474 cpu4_opp12: opp-1920000000 { 475 opp-hz = /bits/ 64 <1920000000>; 476 opp-peak-kBps = <6220000 49152000>; 477 }; 478 479 cpu4_opp13: opp-2016000000 { 480 opp-hz = /bits/ 64 <2016000000>; 481 opp-peak-kBps = <7216000 49152000>; 482 }; 483 484 cpu4_opp14: opp-2131200000 { 485 opp-hz = /bits/ 64 <2131200000>; 486 opp-peak-kBps = <8368000 49152000>; 487 }; 488 489 cpu4_opp15: opp-2227200000 { 490 opp-hz = /bits/ 64 <2227200000>; 491 opp-peak-kBps = <8368000 51609600>; 492 }; 493 494 cpu4_opp16: opp-2323200000 { 495 opp-hz = /bits/ 64 <2323200000>; 496 opp-peak-kBps = <8368000 51609600>; 497 }; 498 499 cpu4_opp17: opp-2419200000 { 500 opp-hz = /bits/ 64 <2419200000>; 501 opp-peak-kBps = <8368000 51609600>; 502 }; 503 }; 504 505 cpu7_opp_table: opp-table-cpu7 { 506 compatible = "operating-points-v2"; 507 opp-shared; 508 509 cpu7_opp1: opp-825600000 { 510 opp-hz = /bits/ 64 <825600000>; 511 opp-peak-kBps = <2188000 19660800>; 512 }; 513 514 cpu7_opp2: opp-940800000 { 515 opp-hz = /bits/ 64 <940800000>; 516 opp-peak-kBps = <2188000 22732800>; 517 }; 518 519 cpu7_opp3: opp-1056000000 { 520 opp-hz = /bits/ 64 <1056000000>; 521 opp-peak-kBps = <3072000 25804800>; 522 }; 523 524 cpu7_opp4: opp-1171200000 { 525 opp-hz = /bits/ 64 <1171200000>; 526 opp-peak-kBps = <3072000 31948800>; 527 }; 528 529 cpu7_opp5: opp-1286400000 { 530 opp-hz = /bits/ 64 <1286400000>; 531 opp-peak-kBps = <4068000 31948800>; 532 }; 533 534 cpu7_opp6: opp-1401600000 { 535 opp-hz = /bits/ 64 <1401600000>; 536 opp-peak-kBps = <4068000 31948800>; 537 }; 538 539 cpu7_opp7: opp-1497600000 { 540 opp-hz = /bits/ 64 <1497600000>; 541 opp-peak-kBps = <4068000 40550400>; 542 }; 543 544 cpu7_opp8: opp-1612800000 { 545 opp-hz = /bits/ 64 <1612800000>; 546 opp-peak-kBps = <4068000 40550400>; 547 }; 548 549 cpu7_opp9: opp-1708800000 { 550 opp-hz = /bits/ 64 <1708800000>; 551 opp-peak-kBps = <4068000 43008000>; 552 }; 553 554 cpu7_opp10: opp-1804800000 { 555 opp-hz = /bits/ 64 <1804800000>; 556 opp-peak-kBps = <6220000 43008000>; 557 }; 558 559 cpu7_opp11: opp-1920000000 { 560 opp-hz = /bits/ 64 <1920000000>; 561 opp-peak-kBps = <6220000 49152000>; 562 }; 563 564 cpu7_opp12: opp-2016000000 { 565 opp-hz = /bits/ 64 <2016000000>; 566 opp-peak-kBps = <7216000 49152000>; 567 }; 568 569 cpu7_opp13: opp-2131200000 { 570 opp-hz = /bits/ 64 <2131200000>; 571 opp-peak-kBps = <8368000 49152000>; 572 }; 573 574 cpu7_opp14: opp-2227200000 { 575 opp-hz = /bits/ 64 <2227200000>; 576 opp-peak-kBps = <8368000 51609600>; 577 }; 578 579 cpu7_opp15: opp-2323200000 { 580 opp-hz = /bits/ 64 <2323200000>; 581 opp-peak-kBps = <8368000 51609600>; 582 }; 583 584 cpu7_opp16: opp-2419200000 { 585 opp-hz = /bits/ 64 <2419200000>; 586 opp-peak-kBps = <8368000 51609600>; 587 }; 588 589 cpu7_opp17: opp-2534400000 { 590 opp-hz = /bits/ 64 <2534400000>; 591 opp-peak-kBps = <8368000 51609600>; 592 }; 593 594 cpu7_opp18: opp-2649600000 { 595 opp-hz = /bits/ 64 <2649600000>; 596 opp-peak-kBps = <8368000 51609600>; 597 }; 598 599 cpu7_opp19: opp-2745600000 { 600 opp-hz = /bits/ 64 <2745600000>; 601 opp-peak-kBps = <8368000 51609600>; 602 }; 603 604 cpu7_opp20: opp-2841600000 { 605 opp-hz = /bits/ 64 <2841600000>; 606 opp-peak-kBps = <8368000 51609600>; 607 }; 608 }; 609 610 firmware { 611 scm: scm { 612 compatible = "qcom,scm-sm8150", "qcom,scm"; 613 #reset-cells = <1>; 614 }; 615 }; 616 617 memory@80000000 { 618 device_type = "memory"; 619 /* We expect the bootloader to fill in the size */ 620 reg = <0x0 0x80000000 0x0 0x0>; 621 }; 622 623 pmu { 624 compatible = "arm,armv8-pmuv3"; 625 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 626 }; 627 628 psci { 629 compatible = "arm,psci-1.0"; 630 method = "smc"; 631 632 cpu_pd0: power-domain-cpu0 { 633 #power-domain-cells = <0>; 634 power-domains = <&cluster_pd>; 635 domain-idle-states = <&little_cpu_sleep_0>; 636 }; 637 638 cpu_pd1: power-domain-cpu1 { 639 #power-domain-cells = <0>; 640 power-domains = <&cluster_pd>; 641 domain-idle-states = <&little_cpu_sleep_0>; 642 }; 643 644 cpu_pd2: power-domain-cpu2 { 645 #power-domain-cells = <0>; 646 power-domains = <&cluster_pd>; 647 domain-idle-states = <&little_cpu_sleep_0>; 648 }; 649 650 cpu_pd3: power-domain-cpu3 { 651 #power-domain-cells = <0>; 652 power-domains = <&cluster_pd>; 653 domain-idle-states = <&little_cpu_sleep_0>; 654 }; 655 656 cpu_pd4: power-domain-cpu4 { 657 #power-domain-cells = <0>; 658 power-domains = <&cluster_pd>; 659 domain-idle-states = <&big_cpu_sleep_0>; 660 }; 661 662 cpu_pd5: power-domain-cpu5 { 663 #power-domain-cells = <0>; 664 power-domains = <&cluster_pd>; 665 domain-idle-states = <&big_cpu_sleep_0>; 666 }; 667 668 cpu_pd6: power-domain-cpu6 { 669 #power-domain-cells = <0>; 670 power-domains = <&cluster_pd>; 671 domain-idle-states = <&big_cpu_sleep_0>; 672 }; 673 674 cpu_pd7: power-domain-cpu7 { 675 #power-domain-cells = <0>; 676 power-domains = <&cluster_pd>; 677 domain-idle-states = <&big_cpu_sleep_0>; 678 }; 679 680 cluster_pd: power-domain-cpu-cluster0 { 681 #power-domain-cells = <0>; 682 domain-idle-states = <&cluster_sleep_0>; 683 }; 684 }; 685 686 reserved-memory { 687 #address-cells = <2>; 688 #size-cells = <2>; 689 ranges; 690 691 hyp_mem: memory@85700000 { 692 reg = <0x0 0x85700000 0x0 0x600000>; 693 no-map; 694 }; 695 696 xbl_mem: memory@85d00000 { 697 reg = <0x0 0x85d00000 0x0 0x140000>; 698 no-map; 699 }; 700 701 aop_mem: memory@85f00000 { 702 reg = <0x0 0x85f00000 0x0 0x20000>; 703 no-map; 704 }; 705 706 aop_cmd_db: memory@85f20000 { 707 compatible = "qcom,cmd-db"; 708 reg = <0x0 0x85f20000 0x0 0x20000>; 709 no-map; 710 }; 711 712 smem_mem: memory@86000000 { 713 reg = <0x0 0x86000000 0x0 0x200000>; 714 no-map; 715 }; 716 717 tz_mem: memory@86200000 { 718 reg = <0x0 0x86200000 0x0 0x3900000>; 719 no-map; 720 }; 721 722 rmtfs_mem: memory@89b00000 { 723 compatible = "qcom,rmtfs-mem"; 724 reg = <0x0 0x89b00000 0x0 0x200000>; 725 no-map; 726 727 qcom,client-id = <1>; 728 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 729 }; 730 731 camera_mem: memory@8b700000 { 732 reg = <0x0 0x8b700000 0x0 0x500000>; 733 no-map; 734 }; 735 736 wlan_mem: memory@8bc00000 { 737 reg = <0x0 0x8bc00000 0x0 0x180000>; 738 no-map; 739 }; 740 741 npu_mem: memory@8bd80000 { 742 reg = <0x0 0x8bd80000 0x0 0x80000>; 743 no-map; 744 }; 745 746 adsp_mem: memory@8be00000 { 747 reg = <0x0 0x8be00000 0x0 0x1a00000>; 748 no-map; 749 }; 750 751 mpss_mem: memory@8d800000 { 752 reg = <0x0 0x8d800000 0x0 0x9600000>; 753 no-map; 754 }; 755 756 venus_mem: memory@96e00000 { 757 reg = <0x0 0x96e00000 0x0 0x500000>; 758 no-map; 759 }; 760 761 slpi_mem: memory@97300000 { 762 reg = <0x0 0x97300000 0x0 0x1400000>; 763 no-map; 764 }; 765 766 ipa_fw_mem: memory@98700000 { 767 reg = <0x0 0x98700000 0x0 0x10000>; 768 no-map; 769 }; 770 771 ipa_gsi_mem: memory@98710000 { 772 reg = <0x0 0x98710000 0x0 0x5000>; 773 no-map; 774 }; 775 776 gpu_mem: memory@98715000 { 777 reg = <0x0 0x98715000 0x0 0x2000>; 778 no-map; 779 }; 780 781 spss_mem: memory@98800000 { 782 reg = <0x0 0x98800000 0x0 0x100000>; 783 no-map; 784 }; 785 786 cdsp_mem: memory@98900000 { 787 reg = <0x0 0x98900000 0x0 0x1400000>; 788 no-map; 789 }; 790 791 qseecom_mem: memory@9e400000 { 792 reg = <0x0 0x9e400000 0x0 0x1400000>; 793 no-map; 794 }; 795 }; 796 797 smem { 798 compatible = "qcom,smem"; 799 memory-region = <&smem_mem>; 800 hwlocks = <&tcsr_mutex 3>; 801 }; 802 803 smp2p-cdsp { 804 compatible = "qcom,smp2p"; 805 qcom,smem = <94>, <432>; 806 807 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 808 809 mboxes = <&apss_shared 6>; 810 811 qcom,local-pid = <0>; 812 qcom,remote-pid = <5>; 813 814 cdsp_smp2p_out: master-kernel { 815 qcom,entry-name = "master-kernel"; 816 #qcom,smem-state-cells = <1>; 817 }; 818 819 cdsp_smp2p_in: slave-kernel { 820 qcom,entry-name = "slave-kernel"; 821 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 }; 825 }; 826 827 smp2p-lpass { 828 compatible = "qcom,smp2p"; 829 qcom,smem = <443>, <429>; 830 831 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 832 833 mboxes = <&apss_shared 10>; 834 835 qcom,local-pid = <0>; 836 qcom,remote-pid = <2>; 837 838 adsp_smp2p_out: master-kernel { 839 qcom,entry-name = "master-kernel"; 840 #qcom,smem-state-cells = <1>; 841 }; 842 843 adsp_smp2p_in: slave-kernel { 844 qcom,entry-name = "slave-kernel"; 845 846 interrupt-controller; 847 #interrupt-cells = <2>; 848 }; 849 }; 850 851 smp2p-mpss { 852 compatible = "qcom,smp2p"; 853 qcom,smem = <435>, <428>; 854 855 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 856 857 mboxes = <&apss_shared 14>; 858 859 qcom,local-pid = <0>; 860 qcom,remote-pid = <1>; 861 862 modem_smp2p_out: master-kernel { 863 qcom,entry-name = "master-kernel"; 864 #qcom,smem-state-cells = <1>; 865 }; 866 867 modem_smp2p_in: slave-kernel { 868 qcom,entry-name = "slave-kernel"; 869 870 interrupt-controller; 871 #interrupt-cells = <2>; 872 }; 873 }; 874 875 smp2p-slpi { 876 compatible = "qcom,smp2p"; 877 qcom,smem = <481>, <430>; 878 879 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 880 881 mboxes = <&apss_shared 26>; 882 883 qcom,local-pid = <0>; 884 qcom,remote-pid = <3>; 885 886 slpi_smp2p_out: master-kernel { 887 qcom,entry-name = "master-kernel"; 888 #qcom,smem-state-cells = <1>; 889 }; 890 891 slpi_smp2p_in: slave-kernel { 892 qcom,entry-name = "slave-kernel"; 893 894 interrupt-controller; 895 #interrupt-cells = <2>; 896 }; 897 }; 898 899 soc: soc@0 { 900 #address-cells = <2>; 901 #size-cells = <2>; 902 ranges = <0 0 0 0 0x10 0>; 903 dma-ranges = <0 0 0 0 0x10 0>; 904 compatible = "simple-bus"; 905 906 gcc: clock-controller@100000 { 907 compatible = "qcom,gcc-sm8150"; 908 reg = <0x0 0x00100000 0x0 0x1f0000>; 909 #clock-cells = <1>; 910 #reset-cells = <1>; 911 #power-domain-cells = <1>; 912 clock-names = "bi_tcxo", 913 "sleep_clk"; 914 clocks = <&rpmhcc RPMH_CXO_CLK>, 915 <&sleep_clk>; 916 }; 917 918 gpi_dma0: dma-controller@800000 { 919 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 920 reg = <0 0x00800000 0 0x60000>; 921 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 934 dma-channels = <13>; 935 dma-channel-mask = <0xfa>; 936 iommus = <&apps_smmu 0x00d6 0x0>; 937 #dma-cells = <3>; 938 status = "disabled"; 939 }; 940 941 ethernet: ethernet@20000 { 942 compatible = "qcom,sm8150-ethqos"; 943 reg = <0x0 0x00020000 0x0 0x10000>, 944 <0x0 0x00036000 0x0 0x100>; 945 reg-names = "stmmaceth", "rgmii"; 946 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 947 clocks = <&gcc GCC_EMAC_AXI_CLK>, 948 <&gcc GCC_EMAC_SLV_AHB_CLK>, 949 <&gcc GCC_EMAC_PTP_CLK>, 950 <&gcc GCC_EMAC_RGMII_CLK>; 951 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "macirq", "eth_lpi"; 954 955 power-domains = <&gcc EMAC_GDSC>; 956 resets = <&gcc GCC_EMAC_BCR>; 957 958 iommus = <&apps_smmu 0x3c0 0x0>; 959 960 snps,tso; 961 rx-fifo-depth = <4096>; 962 tx-fifo-depth = <4096>; 963 964 status = "disabled"; 965 }; 966 967 qfprom: efuse@784000 { 968 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 969 reg = <0 0x00784000 0 0x8ff>; 970 #address-cells = <1>; 971 #size-cells = <1>; 972 973 gpu_speed_bin: gpu-speed-bin@133 { 974 reg = <0x133 0x1>; 975 bits = <5 3>; 976 }; 977 }; 978 979 qupv3_id_0: geniqup@8c0000 { 980 compatible = "qcom,geni-se-qup"; 981 reg = <0x0 0x008c0000 0x0 0x6000>; 982 clock-names = "m-ahb", "s-ahb"; 983 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 984 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 985 iommus = <&apps_smmu 0xc3 0x0>; 986 #address-cells = <2>; 987 #size-cells = <2>; 988 ranges; 989 status = "disabled"; 990 991 i2c0: i2c@880000 { 992 compatible = "qcom,geni-i2c"; 993 reg = <0 0x00880000 0 0x4000>; 994 clock-names = "se"; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 996 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 997 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 998 dma-names = "tx", "rx"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c0_default>; 1001 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 spi0: spi@880000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0 0x00880000 0 0x4000>; 1010 reg-names = "se"; 1011 clock-names = "se"; 1012 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1013 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1014 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1015 dma-names = "tx", "rx"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_spi0_default>; 1018 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1019 spi-max-frequency = <50000000>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 i2c1: i2c@884000 { 1026 compatible = "qcom,geni-i2c"; 1027 reg = <0 0x00884000 0 0x4000>; 1028 clock-names = "se"; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1030 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1031 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1032 dma-names = "tx", "rx"; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_i2c1_default>; 1035 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 status = "disabled"; 1039 }; 1040 1041 spi1: spi@884000 { 1042 compatible = "qcom,geni-spi"; 1043 reg = <0 0x00884000 0 0x4000>; 1044 reg-names = "se"; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1047 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1048 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1049 dma-names = "tx", "rx"; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&qup_spi1_default>; 1052 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1053 spi-max-frequency = <50000000>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c2: i2c@888000 { 1060 compatible = "qcom,geni-i2c"; 1061 reg = <0 0x00888000 0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1064 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1065 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1066 dma-names = "tx", "rx"; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&qup_i2c2_default>; 1069 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 spi2: spi@888000 { 1076 compatible = "qcom,geni-spi"; 1077 reg = <0 0x00888000 0 0x4000>; 1078 reg-names = "se"; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1081 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1082 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1083 dma-names = "tx", "rx"; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_spi2_default>; 1086 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1087 spi-max-frequency = <50000000>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 status = "disabled"; 1091 }; 1092 1093 i2c3: i2c@88c000 { 1094 compatible = "qcom,geni-i2c"; 1095 reg = <0 0x0088c000 0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1098 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1099 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1100 dma-names = "tx", "rx"; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_i2c3_default>; 1103 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 spi3: spi@88c000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x0088c000 0 0x4000>; 1112 reg-names = "se"; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1115 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1116 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1117 dma-names = "tx", "rx"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi3_default>; 1120 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1121 spi-max-frequency = <50000000>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c4: i2c@890000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x00890000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1132 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1133 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1134 dma-names = "tx", "rx"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_i2c4_default>; 1137 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 spi4: spi@890000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00890000 0 0x4000>; 1146 reg-names = "se"; 1147 clock-names = "se"; 1148 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1149 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1150 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1151 dma-names = "tx", "rx"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_spi4_default>; 1154 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1155 spi-max-frequency = <50000000>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 i2c5: i2c@894000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00894000 0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1166 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1167 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1168 dma-names = "tx", "rx"; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c5_default>; 1171 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 spi5: spi@894000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00894000 0 0x4000>; 1180 reg-names = "se"; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1183 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1184 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1185 dma-names = "tx", "rx"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi5_default>; 1188 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1189 spi-max-frequency = <50000000>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 i2c6: i2c@898000 { 1196 compatible = "qcom,geni-i2c"; 1197 reg = <0 0x00898000 0 0x4000>; 1198 clock-names = "se"; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1200 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1201 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1202 dma-names = "tx", "rx"; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&qup_i2c6_default>; 1205 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 spi6: spi@898000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0 0x00898000 0 0x4000>; 1214 reg-names = "se"; 1215 clock-names = "se"; 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1217 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1218 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1219 dma-names = "tx", "rx"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&qup_spi6_default>; 1222 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1223 spi-max-frequency = <50000000>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 status = "disabled"; 1227 }; 1228 1229 i2c7: i2c@89c000 { 1230 compatible = "qcom,geni-i2c"; 1231 reg = <0 0x0089c000 0 0x4000>; 1232 clock-names = "se"; 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1234 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1235 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1236 dma-names = "tx", "rx"; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_i2c7_default>; 1239 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 spi7: spi@89c000 { 1246 compatible = "qcom,geni-spi"; 1247 reg = <0 0x0089c000 0 0x4000>; 1248 reg-names = "se"; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1251 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1252 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1253 dma-names = "tx", "rx"; 1254 pinctrl-names = "default"; 1255 pinctrl-0 = <&qup_spi7_default>; 1256 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1257 spi-max-frequency = <50000000>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 }; 1263 1264 gpi_dma1: dma-controller@a00000 { 1265 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1266 reg = <0 0x00a00000 0 0x60000>; 1267 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1280 dma-channels = <13>; 1281 dma-channel-mask = <0xfa>; 1282 iommus = <&apps_smmu 0x0616 0x0>; 1283 #dma-cells = <3>; 1284 status = "disabled"; 1285 }; 1286 1287 qupv3_id_1: geniqup@ac0000 { 1288 compatible = "qcom,geni-se-qup"; 1289 reg = <0x0 0x00ac0000 0x0 0x6000>; 1290 clock-names = "m-ahb", "s-ahb"; 1291 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1292 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1293 iommus = <&apps_smmu 0x603 0x0>; 1294 #address-cells = <2>; 1295 #size-cells = <2>; 1296 ranges; 1297 status = "disabled"; 1298 1299 i2c8: i2c@a80000 { 1300 compatible = "qcom,geni-i2c"; 1301 reg = <0 0x00a80000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1304 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1305 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1306 dma-names = "tx", "rx"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_i2c8_default>; 1309 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 spi8: spi@a80000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0 0x00a80000 0 0x4000>; 1318 reg-names = "se"; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1321 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1322 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1323 dma-names = "tx", "rx"; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_spi8_default>; 1326 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1327 spi-max-frequency = <50000000>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c9: i2c@a84000 { 1334 compatible = "qcom,geni-i2c"; 1335 reg = <0 0x00a84000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1338 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1339 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1340 dma-names = "tx", "rx"; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_i2c9_default>; 1343 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 spi9: spi@a84000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00a84000 0 0x4000>; 1352 reg-names = "se"; 1353 clock-names = "se"; 1354 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1355 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1356 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1357 dma-names = "tx", "rx"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi9_default>; 1360 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1361 spi-max-frequency = <50000000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 1367 uart9: serial@a84000 { 1368 compatible = "qcom,geni-uart"; 1369 reg = <0x0 0x00a84000 0x0 0x4000>; 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1371 clock-names = "se"; 1372 pinctrl-0 = <&qup_uart9_default>; 1373 pinctrl-names = "default"; 1374 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1375 status = "disabled"; 1376 }; 1377 1378 i2c10: i2c@a88000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0 0x00a88000 0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1383 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1384 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1385 dma-names = "tx", "rx"; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_i2c10_default>; 1388 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 spi10: spi@a88000 { 1395 compatible = "qcom,geni-spi"; 1396 reg = <0 0x00a88000 0 0x4000>; 1397 reg-names = "se"; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1400 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1401 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1402 dma-names = "tx", "rx"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_spi10_default>; 1405 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1406 spi-max-frequency = <50000000>; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 status = "disabled"; 1410 }; 1411 1412 i2c11: i2c@a8c000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x00a8c000 0 0x4000>; 1415 clock-names = "se"; 1416 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1417 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1418 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1419 dma-names = "tx", "rx"; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_i2c11_default>; 1422 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 }; 1427 1428 spi11: spi@a8c000 { 1429 compatible = "qcom,geni-spi"; 1430 reg = <0 0x00a8c000 0 0x4000>; 1431 reg-names = "se"; 1432 clock-names = "se"; 1433 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1434 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1435 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1436 dma-names = "tx", "rx"; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_spi11_default>; 1439 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1440 spi-max-frequency = <50000000>; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 uart2: serial@a90000 { 1447 compatible = "qcom,geni-debug-uart"; 1448 reg = <0x0 0x00a90000 0x0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1451 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1452 status = "disabled"; 1453 }; 1454 1455 i2c12: i2c@a90000 { 1456 compatible = "qcom,geni-i2c"; 1457 reg = <0 0x00a90000 0 0x4000>; 1458 clock-names = "se"; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1460 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1461 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1462 dma-names = "tx", "rx"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_i2c12_default>; 1465 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 status = "disabled"; 1469 }; 1470 1471 spi12: spi@a90000 { 1472 compatible = "qcom,geni-spi"; 1473 reg = <0 0x00a90000 0 0x4000>; 1474 reg-names = "se"; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1477 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1478 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1479 dma-names = "tx", "rx"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_spi12_default>; 1482 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1483 spi-max-frequency = <50000000>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 }; 1488 1489 i2c16: i2c@94000 { 1490 compatible = "qcom,geni-i2c"; 1491 reg = <0 0x00094000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1494 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1495 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1496 dma-names = "tx", "rx"; 1497 pinctrl-names = "default"; 1498 pinctrl-0 = <&qup_i2c16_default>; 1499 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 spi16: spi@a94000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0 0x00a94000 0 0x4000>; 1508 reg-names = "se"; 1509 clock-names = "se"; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1511 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1512 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1513 dma-names = "tx", "rx"; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_spi16_default>; 1516 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1517 spi-max-frequency = <50000000>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 }; 1523 1524 gpi_dma2: dma-controller@c00000 { 1525 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1526 reg = <0 0x00c00000 0 0x60000>; 1527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1540 dma-channels = <13>; 1541 dma-channel-mask = <0xfa>; 1542 iommus = <&apps_smmu 0x07b6 0x0>; 1543 #dma-cells = <3>; 1544 status = "disabled"; 1545 }; 1546 1547 qupv3_id_2: geniqup@cc0000 { 1548 compatible = "qcom,geni-se-qup"; 1549 reg = <0x0 0x00cc0000 0x0 0x6000>; 1550 1551 clock-names = "m-ahb", "s-ahb"; 1552 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1553 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1554 iommus = <&apps_smmu 0x7a3 0x0>; 1555 #address-cells = <2>; 1556 #size-cells = <2>; 1557 ranges; 1558 status = "disabled"; 1559 1560 i2c17: i2c@c80000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0 0x00c80000 0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1565 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1566 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1567 dma-names = "tx", "rx"; 1568 pinctrl-names = "default"; 1569 pinctrl-0 = <&qup_i2c17_default>; 1570 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 spi17: spi@c80000 { 1577 compatible = "qcom,geni-spi"; 1578 reg = <0 0x00c80000 0 0x4000>; 1579 reg-names = "se"; 1580 clock-names = "se"; 1581 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1582 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1583 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1584 dma-names = "tx", "rx"; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_spi17_default>; 1587 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1588 spi-max-frequency = <50000000>; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 status = "disabled"; 1592 }; 1593 1594 i2c18: i2c@c84000 { 1595 compatible = "qcom,geni-i2c"; 1596 reg = <0 0x00c84000 0 0x4000>; 1597 clock-names = "se"; 1598 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1599 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1600 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1601 dma-names = "tx", "rx"; 1602 pinctrl-names = "default"; 1603 pinctrl-0 = <&qup_i2c18_default>; 1604 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 status = "disabled"; 1608 }; 1609 1610 spi18: spi@c84000 { 1611 compatible = "qcom,geni-spi"; 1612 reg = <0 0x00c84000 0 0x4000>; 1613 reg-names = "se"; 1614 clock-names = "se"; 1615 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1616 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1617 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1618 dma-names = "tx", "rx"; 1619 pinctrl-names = "default"; 1620 pinctrl-0 = <&qup_spi18_default>; 1621 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1622 spi-max-frequency = <50000000>; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 1628 i2c19: i2c@c88000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00c88000 0 0x4000>; 1631 clock-names = "se"; 1632 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1633 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1634 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 pinctrl-names = "default"; 1637 pinctrl-0 = <&qup_i2c19_default>; 1638 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 status = "disabled"; 1642 }; 1643 1644 spi19: spi@c88000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0 0x00c88000 0 0x4000>; 1647 reg-names = "se"; 1648 clock-names = "se"; 1649 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1650 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1651 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1652 dma-names = "tx", "rx"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_spi19_default>; 1655 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1656 spi-max-frequency = <50000000>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 status = "disabled"; 1660 }; 1661 1662 i2c13: i2c@c8c000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00c8c000 0 0x4000>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1667 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1668 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1669 dma-names = "tx", "rx"; 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&qup_i2c13_default>; 1672 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 spi13: spi@c8c000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x00c8c000 0 0x4000>; 1681 reg-names = "se"; 1682 clock-names = "se"; 1683 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1684 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1685 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1686 dma-names = "tx", "rx"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_spi13_default>; 1689 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1690 spi-max-frequency = <50000000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 i2c14: i2c@c90000 { 1697 compatible = "qcom,geni-i2c"; 1698 reg = <0 0x00c90000 0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1701 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1702 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1703 dma-names = "tx", "rx"; 1704 pinctrl-names = "default"; 1705 pinctrl-0 = <&qup_i2c14_default>; 1706 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 spi14: spi@c90000 { 1713 compatible = "qcom,geni-spi"; 1714 reg = <0 0x00c90000 0 0x4000>; 1715 reg-names = "se"; 1716 clock-names = "se"; 1717 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1718 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1719 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1720 dma-names = "tx", "rx"; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&qup_spi14_default>; 1723 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1724 spi-max-frequency = <50000000>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 status = "disabled"; 1728 }; 1729 1730 i2c15: i2c@c94000 { 1731 compatible = "qcom,geni-i2c"; 1732 reg = <0 0x00c94000 0 0x4000>; 1733 clock-names = "se"; 1734 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1735 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1736 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1737 dma-names = "tx", "rx"; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_i2c15_default>; 1740 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 status = "disabled"; 1744 }; 1745 1746 spi15: spi@c94000 { 1747 compatible = "qcom,geni-spi"; 1748 reg = <0 0x00c94000 0 0x4000>; 1749 reg-names = "se"; 1750 clock-names = "se"; 1751 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1752 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1753 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1754 dma-names = "tx", "rx"; 1755 pinctrl-names = "default"; 1756 pinctrl-0 = <&qup_spi15_default>; 1757 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1758 spi-max-frequency = <50000000>; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 status = "disabled"; 1762 }; 1763 }; 1764 1765 config_noc: interconnect@1500000 { 1766 compatible = "qcom,sm8150-config-noc"; 1767 reg = <0 0x01500000 0 0x7400>; 1768 #interconnect-cells = <2>; 1769 qcom,bcm-voters = <&apps_bcm_voter>; 1770 }; 1771 1772 system_noc: interconnect@1620000 { 1773 compatible = "qcom,sm8150-system-noc"; 1774 reg = <0 0x01620000 0 0x19400>; 1775 #interconnect-cells = <2>; 1776 qcom,bcm-voters = <&apps_bcm_voter>; 1777 }; 1778 1779 mc_virt: interconnect@163a000 { 1780 compatible = "qcom,sm8150-mc-virt"; 1781 reg = <0 0x0163a000 0 0x1000>; 1782 #interconnect-cells = <2>; 1783 qcom,bcm-voters = <&apps_bcm_voter>; 1784 }; 1785 1786 aggre1_noc: interconnect@16e0000 { 1787 compatible = "qcom,sm8150-aggre1-noc"; 1788 reg = <0 0x016e0000 0 0xd080>; 1789 #interconnect-cells = <2>; 1790 qcom,bcm-voters = <&apps_bcm_voter>; 1791 }; 1792 1793 aggre2_noc: interconnect@1700000 { 1794 compatible = "qcom,sm8150-aggre2-noc"; 1795 reg = <0 0x01700000 0 0x20000>; 1796 #interconnect-cells = <2>; 1797 qcom,bcm-voters = <&apps_bcm_voter>; 1798 }; 1799 1800 compute_noc: interconnect@1720000 { 1801 compatible = "qcom,sm8150-compute-noc"; 1802 reg = <0 0x01720000 0 0x7000>; 1803 #interconnect-cells = <2>; 1804 qcom,bcm-voters = <&apps_bcm_voter>; 1805 }; 1806 1807 mmss_noc: interconnect@1740000 { 1808 compatible = "qcom,sm8150-mmss-noc"; 1809 reg = <0 0x01740000 0 0x1c100>; 1810 #interconnect-cells = <2>; 1811 qcom,bcm-voters = <&apps_bcm_voter>; 1812 }; 1813 1814 system-cache-controller@9200000 { 1815 compatible = "qcom,sm8150-llcc"; 1816 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1817 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1818 <0 0x09600000 0 0x50000>; 1819 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1820 "llcc3_base", "llcc_broadcast_base"; 1821 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1822 }; 1823 1824 dma@10a2000 { 1825 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1826 reg = <0x0 0x010a2000 0x0 0x1000>, 1827 <0x0 0x010ad000 0x0 0x3000>; 1828 }; 1829 1830 pcie0: pcie@1c00000 { 1831 compatible = "qcom,pcie-sm8150"; 1832 reg = <0 0x01c00000 0 0x3000>, 1833 <0 0x60000000 0 0xf1d>, 1834 <0 0x60000f20 0 0xa8>, 1835 <0 0x60001000 0 0x1000>, 1836 <0 0x60100000 0 0x100000>; 1837 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1838 device_type = "pci"; 1839 linux,pci-domain = <0>; 1840 bus-range = <0x00 0xff>; 1841 num-lanes = <1>; 1842 1843 #address-cells = <3>; 1844 #size-cells = <2>; 1845 1846 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1847 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1848 1849 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1858 interrupt-names = "msi0", 1859 "msi1", 1860 "msi2", 1861 "msi3", 1862 "msi4", 1863 "msi5", 1864 "msi6", 1865 "msi7", 1866 "global"; 1867 #interrupt-cells = <1>; 1868 interrupt-map-mask = <0 0 0 0x7>; 1869 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1870 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1871 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1872 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1873 1874 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1875 <&gcc GCC_PCIE_0_AUX_CLK>, 1876 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1877 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1878 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1879 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1880 clock-names = "pipe", 1881 "aux", 1882 "cfg", 1883 "bus_master", 1884 "bus_slave", 1885 "slave_q2a"; 1886 1887 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1888 <0x100 &apps_smmu 0x1d81 0x1>; 1889 1890 resets = <&gcc GCC_PCIE_0_BCR>; 1891 reset-names = "pci"; 1892 1893 power-domains = <&gcc PCIE_0_GDSC>; 1894 1895 phys = <&pcie0_phy>; 1896 phy-names = "pciephy"; 1897 1898 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1899 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1900 1901 pinctrl-names = "default"; 1902 pinctrl-0 = <&pcie0_default_state>; 1903 1904 status = "disabled"; 1905 1906 pcie@0 { 1907 device_type = "pci"; 1908 reg = <0x0 0x0 0x0 0x0 0x0>; 1909 bus-range = <0x01 0xff>; 1910 1911 #address-cells = <3>; 1912 #size-cells = <2>; 1913 ranges; 1914 }; 1915 }; 1916 1917 pcie0_phy: phy@1c06000 { 1918 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1919 reg = <0 0x01c06000 0 0x1000>; 1920 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1921 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1922 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1923 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1924 <&gcc GCC_PCIE_0_PIPE_CLK>; 1925 clock-names = "aux", 1926 "cfg_ahb", 1927 "ref", 1928 "refgen", 1929 "pipe"; 1930 1931 clock-output-names = "pcie_0_pipe_clk"; 1932 #clock-cells = <0>; 1933 1934 #phy-cells = <0>; 1935 1936 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1937 reset-names = "phy"; 1938 1939 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1940 assigned-clock-rates = <100000000>; 1941 1942 status = "disabled"; 1943 }; 1944 1945 pcie1: pcie@1c08000 { 1946 compatible = "qcom,pcie-sm8150"; 1947 reg = <0 0x01c08000 0 0x3000>, 1948 <0 0x40000000 0 0xf1d>, 1949 <0 0x40000f20 0 0xa8>, 1950 <0 0x40001000 0 0x1000>, 1951 <0 0x40100000 0 0x100000>; 1952 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1953 device_type = "pci"; 1954 linux,pci-domain = <1>; 1955 bus-range = <0x00 0xff>; 1956 num-lanes = <2>; 1957 1958 #address-cells = <3>; 1959 #size-cells = <2>; 1960 1961 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1962 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1963 1964 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "msi0", 1974 "msi1", 1975 "msi2", 1976 "msi3", 1977 "msi4", 1978 "msi5", 1979 "msi6", 1980 "msi7", 1981 "global"; 1982 #interrupt-cells = <1>; 1983 interrupt-map-mask = <0 0 0 0x7>; 1984 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1985 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1986 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1987 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1988 1989 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1990 <&gcc GCC_PCIE_1_AUX_CLK>, 1991 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1992 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1993 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1994 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 1995 clock-names = "pipe", 1996 "aux", 1997 "cfg", 1998 "bus_master", 1999 "bus_slave", 2000 "slave_q2a"; 2001 2002 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2003 assigned-clock-rates = <19200000>; 2004 2005 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 2006 <0x100 &apps_smmu 0x1e01 0x1>; 2007 2008 resets = <&gcc GCC_PCIE_1_BCR>; 2009 reset-names = "pci"; 2010 2011 power-domains = <&gcc PCIE_1_GDSC>; 2012 2013 phys = <&pcie1_phy>; 2014 phy-names = "pciephy"; 2015 2016 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 2017 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 2018 2019 pinctrl-names = "default"; 2020 pinctrl-0 = <&pcie1_default_state>; 2021 2022 status = "disabled"; 2023 2024 pcie@0 { 2025 device_type = "pci"; 2026 reg = <0x0 0x0 0x0 0x0 0x0>; 2027 bus-range = <0x01 0xff>; 2028 2029 #address-cells = <3>; 2030 #size-cells = <2>; 2031 ranges; 2032 }; 2033 }; 2034 2035 pcie1_phy: phy@1c0e000 { 2036 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 2037 reg = <0 0x01c0e000 0 0x1000>; 2038 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2039 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2040 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2041 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2042 <&gcc GCC_PCIE_1_PIPE_CLK>; 2043 clock-names = "aux", 2044 "cfg_ahb", 2045 "ref", 2046 "refgen", 2047 "pipe"; 2048 2049 clock-output-names = "pcie_1_pipe_clk"; 2050 #clock-cells = <0>; 2051 2052 #phy-cells = <0>; 2053 2054 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2055 reset-names = "phy"; 2056 2057 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2058 assigned-clock-rates = <100000000>; 2059 2060 status = "disabled"; 2061 }; 2062 2063 ufs_mem_hc: ufshc@1d84000 { 2064 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2065 "jedec,ufs-2.0"; 2066 reg = <0 0x01d84000 0 0x2500>, 2067 <0 0x01d90000 0 0x8000>; 2068 reg-names = "std", "ice"; 2069 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2070 phys = <&ufs_mem_phy>; 2071 phy-names = "ufsphy"; 2072 lanes-per-direction = <2>; 2073 #reset-cells = <1>; 2074 resets = <&gcc GCC_UFS_PHY_BCR>; 2075 reset-names = "rst"; 2076 2077 iommus = <&apps_smmu 0x300 0>; 2078 2079 clock-names = 2080 "core_clk", 2081 "bus_aggr_clk", 2082 "iface_clk", 2083 "core_clk_unipro", 2084 "ref_clk", 2085 "tx_lane0_sync_clk", 2086 "rx_lane0_sync_clk", 2087 "rx_lane1_sync_clk", 2088 "ice_core_clk"; 2089 clocks = 2090 <&gcc GCC_UFS_PHY_AXI_CLK>, 2091 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2092 <&gcc GCC_UFS_PHY_AHB_CLK>, 2093 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2094 <&rpmhcc RPMH_CXO_CLK>, 2095 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2096 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2097 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2098 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2099 freq-table-hz = 2100 <37500000 300000000>, 2101 <0 0>, 2102 <0 0>, 2103 <37500000 300000000>, 2104 <0 0>, 2105 <0 0>, 2106 <0 0>, 2107 <0 0>, 2108 <0 300000000>; 2109 2110 status = "disabled"; 2111 }; 2112 2113 ufs_mem_phy: phy@1d87000 { 2114 compatible = "qcom,sm8150-qmp-ufs-phy"; 2115 reg = <0 0x01d87000 0 0x1000>; 2116 2117 clocks = <&rpmhcc RPMH_CXO_CLK>, 2118 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2119 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2120 clock-names = "ref", 2121 "ref_aux", 2122 "qref"; 2123 2124 power-domains = <&gcc UFS_PHY_GDSC>; 2125 2126 resets = <&ufs_mem_hc 0>; 2127 reset-names = "ufsphy"; 2128 2129 #phy-cells = <0>; 2130 2131 status = "disabled"; 2132 }; 2133 2134 cryptobam: dma-controller@1dc4000 { 2135 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2136 reg = <0 0x01dc4000 0 0x24000>; 2137 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2138 #dma-cells = <1>; 2139 qcom,ee = <0>; 2140 qcom,controlled-remotely; 2141 num-channels = <8>; 2142 qcom,num-ees = <2>; 2143 iommus = <&apps_smmu 0x502 0x0641>, 2144 <&apps_smmu 0x504 0x0011>, 2145 <&apps_smmu 0x506 0x0011>, 2146 <&apps_smmu 0x508 0x0011>, 2147 <&apps_smmu 0x512 0x0000>; 2148 }; 2149 2150 crypto: crypto@1dfa000 { 2151 compatible = "qcom,sm8150-qce", "qcom,qce"; 2152 reg = <0 0x01dfa000 0 0x6000>; 2153 dmas = <&cryptobam 4>, <&cryptobam 5>; 2154 dma-names = "rx", "tx"; 2155 iommus = <&apps_smmu 0x502 0x0641>, 2156 <&apps_smmu 0x504 0x0011>, 2157 <&apps_smmu 0x506 0x0011>, 2158 <&apps_smmu 0x508 0x0011>, 2159 <&apps_smmu 0x512 0x0000>; 2160 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2161 interconnect-names = "memory"; 2162 }; 2163 2164 tcsr_mutex: hwlock@1f40000 { 2165 compatible = "qcom,tcsr-mutex"; 2166 reg = <0x0 0x01f40000 0x0 0x20000>; 2167 #hwlock-cells = <1>; 2168 }; 2169 2170 tcsr_regs_1: syscon@1f60000 { 2171 compatible = "qcom,sm8150-tcsr", "syscon"; 2172 reg = <0x0 0x01f60000 0x0 0x20000>; 2173 }; 2174 2175 remoteproc_slpi: remoteproc@2400000 { 2176 compatible = "qcom,sm8150-slpi-pas"; 2177 reg = <0x0 0x02400000 0x0 0x4040>; 2178 2179 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2180 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2181 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2182 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2183 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2184 interrupt-names = "wdog", "fatal", "ready", 2185 "handover", "stop-ack"; 2186 2187 clocks = <&rpmhcc RPMH_CXO_CLK>; 2188 clock-names = "xo"; 2189 2190 power-domains = <&rpmhpd SM8150_LCX>, 2191 <&rpmhpd SM8150_LMX>; 2192 power-domain-names = "lcx", "lmx"; 2193 2194 memory-region = <&slpi_mem>; 2195 2196 qcom,qmp = <&aoss_qmp>; 2197 2198 qcom,smem-states = <&slpi_smp2p_out 0>; 2199 qcom,smem-state-names = "stop"; 2200 2201 status = "disabled"; 2202 2203 glink-edge { 2204 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2205 label = "dsps"; 2206 qcom,remote-pid = <3>; 2207 mboxes = <&apss_shared 24>; 2208 2209 fastrpc { 2210 compatible = "qcom,fastrpc"; 2211 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2212 label = "sdsp"; 2213 qcom,non-secure-domain; 2214 #address-cells = <1>; 2215 #size-cells = <0>; 2216 2217 compute-cb@1 { 2218 compatible = "qcom,fastrpc-compute-cb"; 2219 reg = <1>; 2220 iommus = <&apps_smmu 0x05a1 0x0>; 2221 }; 2222 2223 compute-cb@2 { 2224 compatible = "qcom,fastrpc-compute-cb"; 2225 reg = <2>; 2226 iommus = <&apps_smmu 0x05a2 0x0>; 2227 }; 2228 2229 compute-cb@3 { 2230 compatible = "qcom,fastrpc-compute-cb"; 2231 reg = <3>; 2232 iommus = <&apps_smmu 0x05a3 0x0>; 2233 /* note: shared-cb = <4> in downstream */ 2234 }; 2235 }; 2236 }; 2237 }; 2238 2239 gpu: gpu@2c00000 { 2240 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2241 reg = <0 0x02c00000 0 0x40000>; 2242 reg-names = "kgsl_3d0_reg_memory"; 2243 2244 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2245 2246 iommus = <&adreno_smmu 0 0x401>; 2247 2248 operating-points-v2 = <&gpu_opp_table>; 2249 2250 qcom,gmu = <&gmu>; 2251 2252 nvmem-cells = <&gpu_speed_bin>; 2253 nvmem-cell-names = "speed_bin"; 2254 #cooling-cells = <2>; 2255 2256 status = "disabled"; 2257 2258 zap-shader { 2259 memory-region = <&gpu_mem>; 2260 }; 2261 2262 gpu_opp_table: opp-table { 2263 compatible = "operating-points-v2"; 2264 2265 opp-675000000 { 2266 opp-hz = /bits/ 64 <675000000>; 2267 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2268 opp-supported-hw = <0x2>; 2269 }; 2270 2271 opp-585000000 { 2272 opp-hz = /bits/ 64 <585000000>; 2273 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2274 opp-supported-hw = <0x3>; 2275 }; 2276 2277 opp-499200000 { 2278 opp-hz = /bits/ 64 <499200000>; 2279 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2280 opp-supported-hw = <0x3>; 2281 }; 2282 2283 opp-427000000 { 2284 opp-hz = /bits/ 64 <427000000>; 2285 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2286 opp-supported-hw = <0x3>; 2287 }; 2288 2289 opp-345000000 { 2290 opp-hz = /bits/ 64 <345000000>; 2291 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2292 opp-supported-hw = <0x3>; 2293 }; 2294 2295 opp-257000000 { 2296 opp-hz = /bits/ 64 <257000000>; 2297 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2298 opp-supported-hw = <0x3>; 2299 }; 2300 }; 2301 }; 2302 2303 gmu: gmu@2c6a000 { 2304 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2305 2306 reg = <0 0x02c6a000 0 0x30000>, 2307 <0 0x0b290000 0 0x10000>, 2308 <0 0x0b490000 0 0x10000>; 2309 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2310 2311 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2312 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2313 interrupt-names = "hfi", "gmu"; 2314 2315 clocks = <&gpucc GPU_CC_AHB_CLK>, 2316 <&gpucc GPU_CC_CX_GMU_CLK>, 2317 <&gpucc GPU_CC_CXO_CLK>, 2318 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2319 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2320 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2321 2322 power-domains = <&gpucc GPU_CX_GDSC>, 2323 <&gpucc GPU_GX_GDSC>; 2324 power-domain-names = "cx", "gx"; 2325 2326 iommus = <&adreno_smmu 5 0x400>; 2327 2328 operating-points-v2 = <&gmu_opp_table>; 2329 2330 status = "disabled"; 2331 2332 gmu_opp_table: opp-table { 2333 compatible = "operating-points-v2"; 2334 2335 opp-200000000 { 2336 opp-hz = /bits/ 64 <200000000>; 2337 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2338 }; 2339 }; 2340 }; 2341 2342 gpucc: clock-controller@2c90000 { 2343 compatible = "qcom,sm8150-gpucc"; 2344 reg = <0 0x02c90000 0 0x9000>; 2345 clocks = <&rpmhcc RPMH_CXO_CLK>, 2346 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2347 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2348 clock-names = "bi_tcxo", 2349 "gcc_gpu_gpll0_clk_src", 2350 "gcc_gpu_gpll0_div_clk_src"; 2351 #clock-cells = <1>; 2352 #reset-cells = <1>; 2353 #power-domain-cells = <1>; 2354 }; 2355 2356 adreno_smmu: iommu@2ca0000 { 2357 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2358 "qcom,smmu-500", "arm,mmu-500"; 2359 reg = <0 0x02ca0000 0 0x10000>; 2360 #iommu-cells = <2>; 2361 #global-interrupts = <1>; 2362 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2371 clocks = <&gpucc GPU_CC_AHB_CLK>, 2372 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2373 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2374 clock-names = "ahb", "bus", "iface"; 2375 2376 power-domains = <&gpucc GPU_CX_GDSC>; 2377 }; 2378 2379 tlmm: pinctrl@3100000 { 2380 compatible = "qcom,sm8150-pinctrl"; 2381 reg = <0x0 0x03100000 0x0 0x300000>, 2382 <0x0 0x03500000 0x0 0x300000>, 2383 <0x0 0x03900000 0x0 0x300000>, 2384 <0x0 0x03D00000 0x0 0x300000>; 2385 reg-names = "west", "east", "north", "south"; 2386 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2387 gpio-ranges = <&tlmm 0 0 176>; 2388 gpio-controller; 2389 #gpio-cells = <2>; 2390 interrupt-controller; 2391 #interrupt-cells = <2>; 2392 wakeup-parent = <&pdc>; 2393 2394 qup_i2c0_default: qup-i2c0-default-state { 2395 pins = "gpio0", "gpio1"; 2396 function = "qup0"; 2397 drive-strength = <0x02>; 2398 bias-disable; 2399 }; 2400 2401 qup_spi0_default: qup-spi0-default-state { 2402 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2403 function = "qup0"; 2404 drive-strength = <6>; 2405 bias-disable; 2406 }; 2407 2408 qup_i2c1_default: qup-i2c1-default-state { 2409 pins = "gpio114", "gpio115"; 2410 function = "qup1"; 2411 drive-strength = <2>; 2412 bias-disable; 2413 }; 2414 2415 qup_spi1_default: qup-spi1-default-state { 2416 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2417 function = "qup1"; 2418 drive-strength = <6>; 2419 bias-disable; 2420 }; 2421 2422 qup_i2c2_default: qup-i2c2-default-state { 2423 pins = "gpio126", "gpio127"; 2424 function = "qup2"; 2425 drive-strength = <2>; 2426 bias-disable; 2427 }; 2428 2429 qup_spi2_default: qup-spi2-default-state { 2430 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2431 function = "qup2"; 2432 drive-strength = <6>; 2433 bias-disable; 2434 }; 2435 2436 qup_i2c3_default: qup-i2c3-default-state { 2437 pins = "gpio144", "gpio145"; 2438 function = "qup3"; 2439 drive-strength = <2>; 2440 bias-disable; 2441 }; 2442 2443 qup_spi3_default: qup-spi3-default-state { 2444 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2445 function = "qup3"; 2446 drive-strength = <6>; 2447 bias-disable; 2448 }; 2449 2450 qup_i2c4_default: qup-i2c4-default-state { 2451 pins = "gpio51", "gpio52"; 2452 function = "qup4"; 2453 drive-strength = <2>; 2454 bias-disable; 2455 }; 2456 2457 qup_spi4_default: qup-spi4-default-state { 2458 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2459 function = "qup4"; 2460 drive-strength = <6>; 2461 bias-disable; 2462 }; 2463 2464 qup_i2c5_default: qup-i2c5-default-state { 2465 pins = "gpio121", "gpio122"; 2466 function = "qup5"; 2467 drive-strength = <2>; 2468 bias-disable; 2469 }; 2470 2471 qup_spi5_default: qup-spi5-default-state { 2472 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2473 function = "qup5"; 2474 drive-strength = <6>; 2475 bias-disable; 2476 }; 2477 2478 qup_i2c6_default: qup-i2c6-default-state { 2479 pins = "gpio6", "gpio7"; 2480 function = "qup6"; 2481 drive-strength = <2>; 2482 bias-disable; 2483 }; 2484 2485 qup_spi6_default: qup-spi6-default-state { 2486 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2487 function = "qup6"; 2488 drive-strength = <6>; 2489 bias-disable; 2490 }; 2491 2492 qup_i2c7_default: qup-i2c7-default-state { 2493 pins = "gpio98", "gpio99"; 2494 function = "qup7"; 2495 drive-strength = <2>; 2496 bias-disable; 2497 }; 2498 2499 qup_spi7_default: qup-spi7-default-state { 2500 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2501 function = "qup7"; 2502 drive-strength = <6>; 2503 bias-disable; 2504 }; 2505 2506 qup_i2c8_default: qup-i2c8-default-state { 2507 pins = "gpio88", "gpio89"; 2508 function = "qup8"; 2509 drive-strength = <2>; 2510 bias-disable; 2511 }; 2512 2513 qup_spi8_default: qup-spi8-default-state { 2514 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2515 function = "qup8"; 2516 drive-strength = <6>; 2517 bias-disable; 2518 }; 2519 2520 qup_i2c9_default: qup-i2c9-default-state { 2521 pins = "gpio39", "gpio40"; 2522 function = "qup9"; 2523 drive-strength = <2>; 2524 bias-disable; 2525 }; 2526 2527 qup_spi9_default: qup-spi9-default-state { 2528 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2529 function = "qup9"; 2530 drive-strength = <6>; 2531 bias-disable; 2532 }; 2533 2534 qup_uart9_default: qup-uart9-default-state { 2535 pins = "gpio41", "gpio42"; 2536 function = "qup9"; 2537 drive-strength = <2>; 2538 bias-disable; 2539 }; 2540 2541 qup_i2c10_default: qup-i2c10-default-state { 2542 pins = "gpio9", "gpio10"; 2543 function = "qup10"; 2544 drive-strength = <2>; 2545 bias-disable; 2546 }; 2547 2548 qup_spi10_default: qup-spi10-default-state { 2549 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2550 function = "qup10"; 2551 drive-strength = <6>; 2552 bias-disable; 2553 }; 2554 2555 qup_i2c11_default: qup-i2c11-default-state { 2556 pins = "gpio94", "gpio95"; 2557 function = "qup11"; 2558 drive-strength = <2>; 2559 bias-disable; 2560 }; 2561 2562 qup_spi11_default: qup-spi11-default-state { 2563 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2564 function = "qup11"; 2565 drive-strength = <6>; 2566 bias-disable; 2567 }; 2568 2569 qup_i2c12_default: qup-i2c12-default-state { 2570 pins = "gpio83", "gpio84"; 2571 function = "qup12"; 2572 drive-strength = <2>; 2573 bias-disable; 2574 }; 2575 2576 qup_spi12_default: qup-spi12-default-state { 2577 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2578 function = "qup12"; 2579 drive-strength = <6>; 2580 bias-disable; 2581 }; 2582 2583 qup_i2c13_default: qup-i2c13-default-state { 2584 pins = "gpio43", "gpio44"; 2585 function = "qup13"; 2586 drive-strength = <2>; 2587 bias-disable; 2588 }; 2589 2590 qup_spi13_default: qup-spi13-default-state { 2591 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2592 function = "qup13"; 2593 drive-strength = <6>; 2594 bias-disable; 2595 }; 2596 2597 qup_i2c14_default: qup-i2c14-default-state { 2598 pins = "gpio47", "gpio48"; 2599 function = "qup14"; 2600 drive-strength = <2>; 2601 bias-disable; 2602 }; 2603 2604 qup_spi14_default: qup-spi14-default-state { 2605 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2606 function = "qup14"; 2607 drive-strength = <6>; 2608 bias-disable; 2609 }; 2610 2611 qup_i2c15_default: qup-i2c15-default-state { 2612 pins = "gpio27", "gpio28"; 2613 function = "qup15"; 2614 drive-strength = <2>; 2615 bias-disable; 2616 }; 2617 2618 qup_spi15_default: qup-spi15-default-state { 2619 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2620 function = "qup15"; 2621 drive-strength = <6>; 2622 bias-disable; 2623 }; 2624 2625 qup_i2c16_default: qup-i2c16-default-state { 2626 pins = "gpio86", "gpio85"; 2627 function = "qup16"; 2628 drive-strength = <2>; 2629 bias-disable; 2630 }; 2631 2632 qup_spi16_default: qup-spi16-default-state { 2633 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2634 function = "qup16"; 2635 drive-strength = <6>; 2636 bias-disable; 2637 }; 2638 2639 qup_i2c17_default: qup-i2c17-default-state { 2640 pins = "gpio55", "gpio56"; 2641 function = "qup17"; 2642 drive-strength = <2>; 2643 bias-disable; 2644 }; 2645 2646 qup_spi17_default: qup-spi17-default-state { 2647 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2648 function = "qup17"; 2649 drive-strength = <6>; 2650 bias-disable; 2651 }; 2652 2653 qup_i2c18_default: qup-i2c18-default-state { 2654 pins = "gpio23", "gpio24"; 2655 function = "qup18"; 2656 drive-strength = <2>; 2657 bias-disable; 2658 }; 2659 2660 qup_spi18_default: qup-spi18-default-state { 2661 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2662 function = "qup18"; 2663 drive-strength = <6>; 2664 bias-disable; 2665 }; 2666 2667 qup_i2c19_default: qup-i2c19-default-state { 2668 pins = "gpio57", "gpio58"; 2669 function = "qup19"; 2670 drive-strength = <2>; 2671 bias-disable; 2672 }; 2673 2674 qup_spi19_default: qup-spi19-default-state { 2675 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2676 function = "qup19"; 2677 drive-strength = <6>; 2678 bias-disable; 2679 }; 2680 2681 pcie0_default_state: pcie0-default-state { 2682 perst-pins { 2683 pins = "gpio35"; 2684 function = "gpio"; 2685 drive-strength = <2>; 2686 bias-pull-down; 2687 }; 2688 2689 clkreq-pins { 2690 pins = "gpio36"; 2691 function = "pci_e0"; 2692 drive-strength = <2>; 2693 bias-pull-up; 2694 }; 2695 2696 wake-pins { 2697 pins = "gpio37"; 2698 function = "gpio"; 2699 drive-strength = <2>; 2700 bias-pull-up; 2701 }; 2702 }; 2703 2704 pcie1_default_state: pcie1-default-state { 2705 perst-pins { 2706 pins = "gpio102"; 2707 function = "gpio"; 2708 drive-strength = <2>; 2709 bias-pull-down; 2710 }; 2711 2712 clkreq-pins { 2713 pins = "gpio103"; 2714 function = "pci_e1"; 2715 drive-strength = <2>; 2716 bias-pull-up; 2717 }; 2718 2719 wake-pins { 2720 pins = "gpio104"; 2721 function = "gpio"; 2722 drive-strength = <2>; 2723 bias-pull-up; 2724 }; 2725 }; 2726 }; 2727 2728 remoteproc_mpss: remoteproc@4080000 { 2729 compatible = "qcom,sm8150-mpss-pas"; 2730 reg = <0x0 0x04080000 0x0 0x4040>; 2731 2732 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2733 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2734 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2735 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2736 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2737 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2738 interrupt-names = "wdog", "fatal", "ready", "handover", 2739 "stop-ack", "shutdown-ack"; 2740 2741 clocks = <&rpmhcc RPMH_CXO_CLK>; 2742 clock-names = "xo"; 2743 2744 power-domains = <&rpmhpd SM8150_CX>, 2745 <&rpmhpd SM8150_MSS>; 2746 power-domain-names = "cx", "mss"; 2747 2748 memory-region = <&mpss_mem>; 2749 2750 qcom,qmp = <&aoss_qmp>; 2751 2752 qcom,smem-states = <&modem_smp2p_out 0>; 2753 qcom,smem-state-names = "stop"; 2754 2755 status = "disabled"; 2756 2757 glink-edge { 2758 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2759 label = "modem"; 2760 qcom,remote-pid = <1>; 2761 mboxes = <&apss_shared 12>; 2762 }; 2763 }; 2764 2765 stm@6002000 { 2766 compatible = "arm,coresight-stm", "arm,primecell"; 2767 reg = <0 0x06002000 0 0x1000>, 2768 <0 0x16280000 0 0x180000>; 2769 reg-names = "stm-base", "stm-stimulus-base"; 2770 2771 clocks = <&aoss_qmp>; 2772 clock-names = "apb_pclk"; 2773 2774 out-ports { 2775 port { 2776 stm_out: endpoint { 2777 remote-endpoint = <&funnel0_in7>; 2778 }; 2779 }; 2780 }; 2781 }; 2782 2783 funnel@6041000 { 2784 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2785 reg = <0 0x06041000 0 0x1000>; 2786 2787 clocks = <&aoss_qmp>; 2788 clock-names = "apb_pclk"; 2789 2790 out-ports { 2791 port { 2792 funnel0_out: endpoint { 2793 remote-endpoint = <&merge_funnel_in0>; 2794 }; 2795 }; 2796 }; 2797 2798 in-ports { 2799 #address-cells = <1>; 2800 #size-cells = <0>; 2801 2802 port@7 { 2803 reg = <7>; 2804 funnel0_in7: endpoint { 2805 remote-endpoint = <&stm_out>; 2806 }; 2807 }; 2808 }; 2809 }; 2810 2811 funnel@6042000 { 2812 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2813 reg = <0 0x06042000 0 0x1000>; 2814 2815 clocks = <&aoss_qmp>; 2816 clock-names = "apb_pclk"; 2817 2818 out-ports { 2819 port { 2820 funnel1_out: endpoint { 2821 remote-endpoint = <&merge_funnel_in1>; 2822 }; 2823 }; 2824 }; 2825 2826 in-ports { 2827 #address-cells = <1>; 2828 #size-cells = <0>; 2829 2830 port@4 { 2831 reg = <4>; 2832 funnel1_in4: endpoint { 2833 remote-endpoint = <&swao_replicator_out>; 2834 }; 2835 }; 2836 }; 2837 }; 2838 2839 funnel@6043000 { 2840 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2841 reg = <0 0x06043000 0 0x1000>; 2842 2843 clocks = <&aoss_qmp>; 2844 clock-names = "apb_pclk"; 2845 2846 out-ports { 2847 port { 2848 funnel2_out: endpoint { 2849 remote-endpoint = <&merge_funnel_in2>; 2850 }; 2851 }; 2852 }; 2853 2854 in-ports { 2855 #address-cells = <1>; 2856 #size-cells = <0>; 2857 2858 port@2 { 2859 reg = <2>; 2860 funnel2_in2: endpoint { 2861 remote-endpoint = <&apss_merge_funnel_out>; 2862 }; 2863 }; 2864 }; 2865 }; 2866 2867 funnel@6045000 { 2868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2869 reg = <0 0x06045000 0 0x1000>; 2870 2871 clocks = <&aoss_qmp>; 2872 clock-names = "apb_pclk"; 2873 2874 out-ports { 2875 port { 2876 merge_funnel_out: endpoint { 2877 remote-endpoint = <&etf_in>; 2878 }; 2879 }; 2880 }; 2881 2882 in-ports { 2883 #address-cells = <1>; 2884 #size-cells = <0>; 2885 2886 port@0 { 2887 reg = <0>; 2888 merge_funnel_in0: endpoint { 2889 remote-endpoint = <&funnel0_out>; 2890 }; 2891 }; 2892 2893 port@1 { 2894 reg = <1>; 2895 merge_funnel_in1: endpoint { 2896 remote-endpoint = <&funnel1_out>; 2897 }; 2898 }; 2899 2900 port@2 { 2901 reg = <2>; 2902 merge_funnel_in2: endpoint { 2903 remote-endpoint = <&funnel2_out>; 2904 }; 2905 }; 2906 }; 2907 }; 2908 2909 replicator@6046000 { 2910 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2911 reg = <0 0x06046000 0 0x1000>; 2912 2913 clocks = <&aoss_qmp>; 2914 clock-names = "apb_pclk"; 2915 2916 out-ports { 2917 #address-cells = <1>; 2918 #size-cells = <0>; 2919 2920 port@0 { 2921 reg = <0>; 2922 replicator_out0: endpoint { 2923 remote-endpoint = <&etr_in>; 2924 }; 2925 }; 2926 2927 port@1 { 2928 reg = <1>; 2929 replicator_out1: endpoint { 2930 remote-endpoint = <&replicator1_in>; 2931 }; 2932 }; 2933 }; 2934 2935 in-ports { 2936 port { 2937 replicator_in0: endpoint { 2938 remote-endpoint = <&etf_out>; 2939 }; 2940 }; 2941 }; 2942 }; 2943 2944 etf@6047000 { 2945 compatible = "arm,coresight-tmc", "arm,primecell"; 2946 reg = <0 0x06047000 0 0x1000>; 2947 2948 clocks = <&aoss_qmp>; 2949 clock-names = "apb_pclk"; 2950 2951 out-ports { 2952 port { 2953 etf_out: endpoint { 2954 remote-endpoint = <&replicator_in0>; 2955 }; 2956 }; 2957 }; 2958 2959 in-ports { 2960 port { 2961 etf_in: endpoint { 2962 remote-endpoint = <&merge_funnel_out>; 2963 }; 2964 }; 2965 }; 2966 }; 2967 2968 etr@6048000 { 2969 compatible = "arm,coresight-tmc", "arm,primecell"; 2970 reg = <0 0x06048000 0 0x1000>; 2971 iommus = <&apps_smmu 0x05e0 0x0>; 2972 2973 clocks = <&aoss_qmp>; 2974 clock-names = "apb_pclk"; 2975 arm,scatter-gather; 2976 2977 in-ports { 2978 port { 2979 etr_in: endpoint { 2980 remote-endpoint = <&replicator_out0>; 2981 }; 2982 }; 2983 }; 2984 }; 2985 2986 replicator@604a000 { 2987 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2988 reg = <0 0x0604a000 0 0x1000>; 2989 2990 clocks = <&aoss_qmp>; 2991 clock-names = "apb_pclk"; 2992 2993 out-ports { 2994 #address-cells = <1>; 2995 #size-cells = <0>; 2996 2997 port@1 { 2998 reg = <1>; 2999 replicator1_out: endpoint { 3000 remote-endpoint = <&swao_funnel_in>; 3001 }; 3002 }; 3003 }; 3004 3005 in-ports { 3006 3007 port { 3008 replicator1_in: endpoint { 3009 remote-endpoint = <&replicator_out1>; 3010 }; 3011 }; 3012 }; 3013 }; 3014 3015 funnel@6b08000 { 3016 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3017 reg = <0 0x06b08000 0 0x1000>; 3018 3019 clocks = <&aoss_qmp>; 3020 clock-names = "apb_pclk"; 3021 3022 out-ports { 3023 port { 3024 swao_funnel_out: endpoint { 3025 remote-endpoint = <&swao_etf_in>; 3026 }; 3027 }; 3028 }; 3029 3030 in-ports { 3031 #address-cells = <1>; 3032 #size-cells = <0>; 3033 3034 port@6 { 3035 reg = <6>; 3036 swao_funnel_in: endpoint { 3037 remote-endpoint = <&replicator1_out>; 3038 }; 3039 }; 3040 }; 3041 }; 3042 3043 etf@6b09000 { 3044 compatible = "arm,coresight-tmc", "arm,primecell"; 3045 reg = <0 0x06b09000 0 0x1000>; 3046 3047 clocks = <&aoss_qmp>; 3048 clock-names = "apb_pclk"; 3049 3050 out-ports { 3051 port { 3052 swao_etf_out: endpoint { 3053 remote-endpoint = <&swao_replicator_in>; 3054 }; 3055 }; 3056 }; 3057 3058 in-ports { 3059 port { 3060 swao_etf_in: endpoint { 3061 remote-endpoint = <&swao_funnel_out>; 3062 }; 3063 }; 3064 }; 3065 }; 3066 3067 replicator@6b0a000 { 3068 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3069 reg = <0 0x06b0a000 0 0x1000>; 3070 3071 clocks = <&aoss_qmp>; 3072 clock-names = "apb_pclk"; 3073 qcom,replicator-loses-context; 3074 3075 out-ports { 3076 port { 3077 swao_replicator_out: endpoint { 3078 remote-endpoint = <&funnel1_in4>; 3079 }; 3080 }; 3081 }; 3082 3083 in-ports { 3084 port { 3085 swao_replicator_in: endpoint { 3086 remote-endpoint = <&swao_etf_out>; 3087 }; 3088 }; 3089 }; 3090 }; 3091 3092 etm@7040000 { 3093 compatible = "arm,coresight-etm4x", "arm,primecell"; 3094 reg = <0 0x07040000 0 0x1000>; 3095 3096 cpu = <&cpu0>; 3097 3098 clocks = <&aoss_qmp>; 3099 clock-names = "apb_pclk"; 3100 arm,coresight-loses-context-with-cpu; 3101 qcom,skip-power-up; 3102 3103 out-ports { 3104 port { 3105 etm0_out: endpoint { 3106 remote-endpoint = <&apss_funnel_in0>; 3107 }; 3108 }; 3109 }; 3110 }; 3111 3112 etm@7140000 { 3113 compatible = "arm,coresight-etm4x", "arm,primecell"; 3114 reg = <0 0x07140000 0 0x1000>; 3115 3116 cpu = <&cpu1>; 3117 3118 clocks = <&aoss_qmp>; 3119 clock-names = "apb_pclk"; 3120 arm,coresight-loses-context-with-cpu; 3121 qcom,skip-power-up; 3122 3123 out-ports { 3124 port { 3125 etm1_out: endpoint { 3126 remote-endpoint = <&apss_funnel_in1>; 3127 }; 3128 }; 3129 }; 3130 }; 3131 3132 etm@7240000 { 3133 compatible = "arm,coresight-etm4x", "arm,primecell"; 3134 reg = <0 0x07240000 0 0x1000>; 3135 3136 cpu = <&cpu2>; 3137 3138 clocks = <&aoss_qmp>; 3139 clock-names = "apb_pclk"; 3140 arm,coresight-loses-context-with-cpu; 3141 qcom,skip-power-up; 3142 3143 out-ports { 3144 port { 3145 etm2_out: endpoint { 3146 remote-endpoint = <&apss_funnel_in2>; 3147 }; 3148 }; 3149 }; 3150 }; 3151 3152 etm@7340000 { 3153 compatible = "arm,coresight-etm4x", "arm,primecell"; 3154 reg = <0 0x07340000 0 0x1000>; 3155 3156 cpu = <&cpu3>; 3157 3158 clocks = <&aoss_qmp>; 3159 clock-names = "apb_pclk"; 3160 arm,coresight-loses-context-with-cpu; 3161 qcom,skip-power-up; 3162 3163 out-ports { 3164 port { 3165 etm3_out: endpoint { 3166 remote-endpoint = <&apss_funnel_in3>; 3167 }; 3168 }; 3169 }; 3170 }; 3171 3172 etm@7440000 { 3173 compatible = "arm,coresight-etm4x", "arm,primecell"; 3174 reg = <0 0x07440000 0 0x1000>; 3175 3176 cpu = <&cpu4>; 3177 3178 clocks = <&aoss_qmp>; 3179 clock-names = "apb_pclk"; 3180 arm,coresight-loses-context-with-cpu; 3181 qcom,skip-power-up; 3182 3183 out-ports { 3184 port { 3185 etm4_out: endpoint { 3186 remote-endpoint = <&apss_funnel_in4>; 3187 }; 3188 }; 3189 }; 3190 }; 3191 3192 etm@7540000 { 3193 compatible = "arm,coresight-etm4x", "arm,primecell"; 3194 reg = <0 0x07540000 0 0x1000>; 3195 3196 cpu = <&cpu5>; 3197 3198 clocks = <&aoss_qmp>; 3199 clock-names = "apb_pclk"; 3200 arm,coresight-loses-context-with-cpu; 3201 qcom,skip-power-up; 3202 3203 out-ports { 3204 port { 3205 etm5_out: endpoint { 3206 remote-endpoint = <&apss_funnel_in5>; 3207 }; 3208 }; 3209 }; 3210 }; 3211 3212 etm@7640000 { 3213 compatible = "arm,coresight-etm4x", "arm,primecell"; 3214 reg = <0 0x07640000 0 0x1000>; 3215 3216 cpu = <&cpu6>; 3217 3218 clocks = <&aoss_qmp>; 3219 clock-names = "apb_pclk"; 3220 arm,coresight-loses-context-with-cpu; 3221 qcom,skip-power-up; 3222 3223 out-ports { 3224 port { 3225 etm6_out: endpoint { 3226 remote-endpoint = <&apss_funnel_in6>; 3227 }; 3228 }; 3229 }; 3230 }; 3231 3232 etm@7740000 { 3233 compatible = "arm,coresight-etm4x", "arm,primecell"; 3234 reg = <0 0x07740000 0 0x1000>; 3235 3236 cpu = <&cpu7>; 3237 3238 clocks = <&aoss_qmp>; 3239 clock-names = "apb_pclk"; 3240 arm,coresight-loses-context-with-cpu; 3241 qcom,skip-power-up; 3242 3243 out-ports { 3244 port { 3245 etm7_out: endpoint { 3246 remote-endpoint = <&apss_funnel_in7>; 3247 }; 3248 }; 3249 }; 3250 }; 3251 3252 funnel@7800000 { /* APSS Funnel */ 3253 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3254 reg = <0 0x07800000 0 0x1000>; 3255 3256 clocks = <&aoss_qmp>; 3257 clock-names = "apb_pclk"; 3258 3259 out-ports { 3260 port { 3261 apss_funnel_out: endpoint { 3262 remote-endpoint = <&apss_merge_funnel_in>; 3263 }; 3264 }; 3265 }; 3266 3267 in-ports { 3268 #address-cells = <1>; 3269 #size-cells = <0>; 3270 3271 port@0 { 3272 reg = <0>; 3273 apss_funnel_in0: endpoint { 3274 remote-endpoint = <&etm0_out>; 3275 }; 3276 }; 3277 3278 port@1 { 3279 reg = <1>; 3280 apss_funnel_in1: endpoint { 3281 remote-endpoint = <&etm1_out>; 3282 }; 3283 }; 3284 3285 port@2 { 3286 reg = <2>; 3287 apss_funnel_in2: endpoint { 3288 remote-endpoint = <&etm2_out>; 3289 }; 3290 }; 3291 3292 port@3 { 3293 reg = <3>; 3294 apss_funnel_in3: endpoint { 3295 remote-endpoint = <&etm3_out>; 3296 }; 3297 }; 3298 3299 port@4 { 3300 reg = <4>; 3301 apss_funnel_in4: endpoint { 3302 remote-endpoint = <&etm4_out>; 3303 }; 3304 }; 3305 3306 port@5 { 3307 reg = <5>; 3308 apss_funnel_in5: endpoint { 3309 remote-endpoint = <&etm5_out>; 3310 }; 3311 }; 3312 3313 port@6 { 3314 reg = <6>; 3315 apss_funnel_in6: endpoint { 3316 remote-endpoint = <&etm6_out>; 3317 }; 3318 }; 3319 3320 port@7 { 3321 reg = <7>; 3322 apss_funnel_in7: endpoint { 3323 remote-endpoint = <&etm7_out>; 3324 }; 3325 }; 3326 }; 3327 }; 3328 3329 funnel@7810000 { 3330 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3331 reg = <0 0x07810000 0 0x1000>; 3332 3333 clocks = <&aoss_qmp>; 3334 clock-names = "apb_pclk"; 3335 3336 out-ports { 3337 port { 3338 apss_merge_funnel_out: endpoint { 3339 remote-endpoint = <&funnel2_in2>; 3340 }; 3341 }; 3342 }; 3343 3344 in-ports { 3345 port { 3346 apss_merge_funnel_in: endpoint { 3347 remote-endpoint = <&apss_funnel_out>; 3348 }; 3349 }; 3350 }; 3351 }; 3352 3353 remoteproc_cdsp: remoteproc@8300000 { 3354 compatible = "qcom,sm8150-cdsp-pas"; 3355 reg = <0x0 0x08300000 0x0 0x4040>; 3356 3357 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3358 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3359 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3360 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3361 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3362 interrupt-names = "wdog", "fatal", "ready", 3363 "handover", "stop-ack"; 3364 3365 clocks = <&rpmhcc RPMH_CXO_CLK>; 3366 clock-names = "xo"; 3367 3368 power-domains = <&rpmhpd SM8150_CX>; 3369 3370 memory-region = <&cdsp_mem>; 3371 3372 qcom,qmp = <&aoss_qmp>; 3373 3374 qcom,smem-states = <&cdsp_smp2p_out 0>; 3375 qcom,smem-state-names = "stop"; 3376 3377 status = "disabled"; 3378 3379 glink-edge { 3380 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3381 label = "cdsp"; 3382 qcom,remote-pid = <5>; 3383 mboxes = <&apss_shared 4>; 3384 3385 fastrpc { 3386 compatible = "qcom,fastrpc"; 3387 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3388 label = "cdsp"; 3389 qcom,non-secure-domain; 3390 #address-cells = <1>; 3391 #size-cells = <0>; 3392 3393 compute-cb@1 { 3394 compatible = "qcom,fastrpc-compute-cb"; 3395 reg = <1>; 3396 iommus = <&apps_smmu 0x1001 0x0460>; 3397 }; 3398 3399 compute-cb@2 { 3400 compatible = "qcom,fastrpc-compute-cb"; 3401 reg = <2>; 3402 iommus = <&apps_smmu 0x1002 0x0460>; 3403 }; 3404 3405 compute-cb@3 { 3406 compatible = "qcom,fastrpc-compute-cb"; 3407 reg = <3>; 3408 iommus = <&apps_smmu 0x1003 0x0460>; 3409 }; 3410 3411 compute-cb@4 { 3412 compatible = "qcom,fastrpc-compute-cb"; 3413 reg = <4>; 3414 iommus = <&apps_smmu 0x1004 0x0460>; 3415 }; 3416 3417 compute-cb@5 { 3418 compatible = "qcom,fastrpc-compute-cb"; 3419 reg = <5>; 3420 iommus = <&apps_smmu 0x1005 0x0460>; 3421 }; 3422 3423 compute-cb@6 { 3424 compatible = "qcom,fastrpc-compute-cb"; 3425 reg = <6>; 3426 iommus = <&apps_smmu 0x1006 0x0460>; 3427 }; 3428 3429 compute-cb@7 { 3430 compatible = "qcom,fastrpc-compute-cb"; 3431 reg = <7>; 3432 iommus = <&apps_smmu 0x1007 0x0460>; 3433 }; 3434 3435 compute-cb@8 { 3436 compatible = "qcom,fastrpc-compute-cb"; 3437 reg = <8>; 3438 iommus = <&apps_smmu 0x1008 0x0460>; 3439 }; 3440 3441 /* note: secure cb9 in downstream */ 3442 }; 3443 }; 3444 }; 3445 3446 usb_1_hsphy: phy@88e2000 { 3447 compatible = "qcom,sm8150-usb-hs-phy", 3448 "qcom,usb-snps-hs-7nm-phy"; 3449 reg = <0 0x088e2000 0 0x400>; 3450 status = "disabled"; 3451 #phy-cells = <0>; 3452 3453 clocks = <&rpmhcc RPMH_CXO_CLK>; 3454 clock-names = "ref"; 3455 3456 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3457 }; 3458 3459 usb_2_hsphy: phy@88e3000 { 3460 compatible = "qcom,sm8150-usb-hs-phy", 3461 "qcom,usb-snps-hs-7nm-phy"; 3462 reg = <0 0x088e3000 0 0x400>; 3463 status = "disabled"; 3464 #phy-cells = <0>; 3465 3466 clocks = <&rpmhcc RPMH_CXO_CLK>; 3467 clock-names = "ref"; 3468 3469 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3470 }; 3471 3472 usb_1_qmpphy: phy@88e8000 { 3473 compatible = "qcom,sm8150-qmp-usb3-dp-phy"; 3474 reg = <0 0x088e8000 0 0x3000>; 3475 3476 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3477 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3478 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3479 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3480 clock-names = "aux", 3481 "ref", 3482 "com_aux", 3483 "usb3_pipe"; 3484 3485 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3486 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3487 reset-names = "phy", "common"; 3488 3489 #clock-cells = <1>; 3490 #phy-cells = <1>; 3491 3492 status = "disabled"; 3493 3494 ports { 3495 #address-cells = <1>; 3496 #size-cells = <0>; 3497 3498 port@0 { 3499 reg = <0>; 3500 3501 usb_1_qmpphy_out: endpoint { 3502 }; 3503 }; 3504 3505 port@1 { 3506 reg = <1>; 3507 3508 usb_1_qmpphy_usb_ss_in: endpoint { 3509 remote-endpoint = <&usb_1_dwc3_ss>; 3510 }; 3511 }; 3512 3513 port@2 { 3514 reg = <2>; 3515 3516 usb_1_qmpphy_dp_in: endpoint { 3517 remote-endpoint = <&mdss_dp_out>; 3518 }; 3519 }; 3520 }; 3521 }; 3522 3523 usb_2_qmpphy: phy@88eb000 { 3524 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3525 reg = <0 0x088eb000 0 0x1000>; 3526 3527 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3528 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3529 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3530 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3531 clock-names = "aux", 3532 "ref", 3533 "com_aux", 3534 "pipe"; 3535 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3536 #clock-cells = <0>; 3537 #phy-cells = <0>; 3538 3539 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3540 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3541 reset-names = "phy", 3542 "phy_phy"; 3543 3544 status = "disabled"; 3545 }; 3546 3547 sdhc_2: mmc@8804000 { 3548 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3549 reg = <0 0x08804000 0 0x1000>; 3550 3551 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3553 interrupt-names = "hc_irq", "pwr_irq"; 3554 3555 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3556 <&gcc GCC_SDCC2_APPS_CLK>, 3557 <&rpmhcc RPMH_CXO_CLK>; 3558 clock-names = "iface", "core", "xo"; 3559 iommus = <&apps_smmu 0x6a0 0x0>; 3560 qcom,dll-config = <0x0007642c>; 3561 qcom,ddr-config = <0x80040868>; 3562 power-domains = <&rpmhpd 0>; 3563 operating-points-v2 = <&sdhc2_opp_table>; 3564 3565 status = "disabled"; 3566 3567 sdhc2_opp_table: opp-table { 3568 compatible = "operating-points-v2"; 3569 3570 opp-19200000 { 3571 opp-hz = /bits/ 64 <19200000>; 3572 required-opps = <&rpmhpd_opp_min_svs>; 3573 }; 3574 3575 opp-50000000 { 3576 opp-hz = /bits/ 64 <50000000>; 3577 required-opps = <&rpmhpd_opp_low_svs>; 3578 }; 3579 3580 opp-100000000 { 3581 opp-hz = /bits/ 64 <100000000>; 3582 required-opps = <&rpmhpd_opp_svs>; 3583 }; 3584 3585 opp-202000000 { 3586 opp-hz = /bits/ 64 <202000000>; 3587 required-opps = <&rpmhpd_opp_svs_l1>; 3588 }; 3589 }; 3590 }; 3591 3592 dc_noc: interconnect@9160000 { 3593 compatible = "qcom,sm8150-dc-noc"; 3594 reg = <0 0x09160000 0 0x3200>; 3595 #interconnect-cells = <2>; 3596 qcom,bcm-voters = <&apps_bcm_voter>; 3597 }; 3598 3599 gem_noc: interconnect@9680000 { 3600 compatible = "qcom,sm8150-gem-noc"; 3601 reg = <0 0x09680000 0 0x3e200>; 3602 #interconnect-cells = <2>; 3603 qcom,bcm-voters = <&apps_bcm_voter>; 3604 }; 3605 3606 usb_1: usb@a6f8800 { 3607 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3608 reg = <0 0x0a6f8800 0 0x400>; 3609 status = "disabled"; 3610 #address-cells = <2>; 3611 #size-cells = <2>; 3612 ranges; 3613 dma-ranges; 3614 3615 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3616 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3617 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3618 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3619 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3620 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3621 clock-names = "cfg_noc", 3622 "core", 3623 "iface", 3624 "sleep", 3625 "mock_utmi", 3626 "xo"; 3627 3628 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3629 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3630 assigned-clock-rates = <19200000>, <200000000>; 3631 3632 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3633 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3634 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3635 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3636 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3637 interrupt-names = "pwr_event", 3638 "hs_phy_irq", 3639 "dp_hs_phy_irq", 3640 "dm_hs_phy_irq", 3641 "ss_phy_irq"; 3642 3643 power-domains = <&gcc USB30_PRIM_GDSC>; 3644 3645 resets = <&gcc GCC_USB30_PRIM_BCR>; 3646 3647 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3648 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3649 interconnect-names = "usb-ddr", "apps-usb"; 3650 3651 usb_1_dwc3: usb@a600000 { 3652 compatible = "snps,dwc3"; 3653 reg = <0 0x0a600000 0 0xcd00>; 3654 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3655 iommus = <&apps_smmu 0x140 0>; 3656 snps,dis_u2_susphy_quirk; 3657 snps,dis_u3_susphy_quirk; 3658 snps,dis_enblslpm_quirk; 3659 snps,dis-u1-entry-quirk; 3660 snps,dis-u2-entry-quirk; 3661 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3662 phy-names = "usb2-phy", "usb3-phy"; 3663 3664 ports { 3665 #address-cells = <1>; 3666 #size-cells = <0>; 3667 3668 port@0 { 3669 reg = <0>; 3670 3671 usb_1_dwc3_hs: endpoint { 3672 }; 3673 }; 3674 3675 port@1 { 3676 reg = <1>; 3677 3678 usb_1_dwc3_ss: endpoint { 3679 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3680 }; 3681 }; 3682 }; 3683 }; 3684 }; 3685 3686 usb_2: usb@a8f8800 { 3687 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3688 reg = <0 0x0a8f8800 0 0x400>; 3689 status = "disabled"; 3690 #address-cells = <2>; 3691 #size-cells = <2>; 3692 ranges; 3693 dma-ranges; 3694 3695 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3696 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3697 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3698 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3699 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3700 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3701 clock-names = "cfg_noc", 3702 "core", 3703 "iface", 3704 "sleep", 3705 "mock_utmi", 3706 "xo"; 3707 3708 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3709 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3710 assigned-clock-rates = <19200000>, <200000000>; 3711 3712 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3713 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3714 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 3715 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3716 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>; 3717 interrupt-names = "pwr_event", 3718 "hs_phy_irq", 3719 "dp_hs_phy_irq", 3720 "dm_hs_phy_irq", 3721 "ss_phy_irq"; 3722 3723 power-domains = <&gcc USB30_SEC_GDSC>; 3724 3725 resets = <&gcc GCC_USB30_SEC_BCR>; 3726 3727 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3728 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3729 interconnect-names = "usb-ddr", "apps-usb"; 3730 3731 usb_2_dwc3: usb@a800000 { 3732 compatible = "snps,dwc3"; 3733 reg = <0 0x0a800000 0 0xcd00>; 3734 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3735 iommus = <&apps_smmu 0x160 0>; 3736 snps,dis_u2_susphy_quirk; 3737 snps,dis_u3_susphy_quirk; 3738 snps,dis_enblslpm_quirk; 3739 snps,dis-u1-entry-quirk; 3740 snps,dis-u2-entry-quirk; 3741 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 3742 phy-names = "usb2-phy", "usb3-phy"; 3743 }; 3744 }; 3745 3746 videocc: clock-controller@ab00000 { 3747 compatible = "qcom,sm8150-videocc"; 3748 reg = <0 0x0ab00000 0 0x10000>; 3749 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3750 <&rpmhcc RPMH_CXO_CLK>; 3751 clock-names = "iface", "bi_tcxo"; 3752 power-domains = <&rpmhpd SM8150_MMCX>; 3753 required-opps = <&rpmhpd_opp_low_svs>; 3754 #clock-cells = <1>; 3755 #reset-cells = <1>; 3756 #power-domain-cells = <1>; 3757 }; 3758 3759 camnoc_virt: interconnect@ac00000 { 3760 compatible = "qcom,sm8150-camnoc-virt"; 3761 reg = <0 0x0ac00000 0 0x1000>; 3762 #interconnect-cells = <2>; 3763 qcom,bcm-voters = <&apps_bcm_voter>; 3764 }; 3765 3766 camcc: clock-controller@ad00000 { 3767 compatible = "qcom,sm8150-camcc"; 3768 reg = <0 0x0ad00000 0 0x10000>; 3769 clocks = <&rpmhcc RPMH_CXO_CLK>, 3770 <&gcc GCC_CAMERA_AHB_CLK>; 3771 power-domains = <&rpmhpd SM8150_MMCX>; 3772 required-opps = <&rpmhpd_opp_low_svs>; 3773 #clock-cells = <1>; 3774 #reset-cells = <1>; 3775 #power-domain-cells = <1>; 3776 }; 3777 3778 mdss: display-subsystem@ae00000 { 3779 compatible = "qcom,sm8150-mdss"; 3780 reg = <0 0x0ae00000 0 0x1000>; 3781 reg-names = "mdss"; 3782 3783 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 3784 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 3785 interconnect-names = "mdp0-mem", "mdp1-mem"; 3786 3787 power-domains = <&dispcc MDSS_GDSC>; 3788 3789 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3790 <&gcc GCC_DISP_HF_AXI_CLK>, 3791 <&gcc GCC_DISP_SF_AXI_CLK>, 3792 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3793 clock-names = "iface", "bus", "nrt_bus", "core"; 3794 3795 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3796 interrupt-controller; 3797 #interrupt-cells = <1>; 3798 3799 iommus = <&apps_smmu 0x800 0x420>; 3800 3801 status = "disabled"; 3802 3803 #address-cells = <2>; 3804 #size-cells = <2>; 3805 ranges; 3806 3807 mdss_mdp: display-controller@ae01000 { 3808 compatible = "qcom,sm8150-dpu"; 3809 reg = <0 0x0ae01000 0 0x8f000>, 3810 <0 0x0aeb0000 0 0x3000>; 3811 reg-names = "mdp", "vbif"; 3812 3813 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3814 <&gcc GCC_DISP_HF_AXI_CLK>, 3815 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3816 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3817 clock-names = "iface", "bus", "core", "vsync"; 3818 3819 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3820 assigned-clock-rates = <19200000>; 3821 3822 operating-points-v2 = <&mdp_opp_table>; 3823 power-domains = <&rpmhpd SM8150_MMCX>; 3824 3825 interrupt-parent = <&mdss>; 3826 interrupts = <0>; 3827 3828 ports { 3829 #address-cells = <1>; 3830 #size-cells = <0>; 3831 3832 port@0 { 3833 reg = <0>; 3834 dpu_intf1_out: endpoint { 3835 remote-endpoint = <&mdss_dsi0_in>; 3836 }; 3837 }; 3838 3839 port@1 { 3840 reg = <1>; 3841 dpu_intf2_out: endpoint { 3842 remote-endpoint = <&mdss_dsi1_in>; 3843 }; 3844 }; 3845 3846 port@2 { 3847 reg = <2>; 3848 dpu_intf0_out: endpoint { 3849 remote-endpoint = <&mdss_dp_in>; 3850 }; 3851 }; 3852 }; 3853 3854 mdp_opp_table: opp-table { 3855 compatible = "operating-points-v2"; 3856 3857 opp-171428571 { 3858 opp-hz = /bits/ 64 <171428571>; 3859 required-opps = <&rpmhpd_opp_low_svs>; 3860 }; 3861 3862 opp-300000000 { 3863 opp-hz = /bits/ 64 <300000000>; 3864 required-opps = <&rpmhpd_opp_svs>; 3865 }; 3866 3867 opp-345000000 { 3868 opp-hz = /bits/ 64 <345000000>; 3869 required-opps = <&rpmhpd_opp_svs_l1>; 3870 }; 3871 3872 opp-460000000 { 3873 opp-hz = /bits/ 64 <460000000>; 3874 required-opps = <&rpmhpd_opp_nom>; 3875 }; 3876 }; 3877 }; 3878 3879 mdss_dp: displayport-controller@ae90000 { 3880 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp"; 3881 reg = <0 0xae90000 0 0x200>, 3882 <0 0xae90200 0 0x200>, 3883 <0 0xae90400 0 0x600>, 3884 <0 0x0ae90a00 0 0x600>, 3885 <0 0x0ae91000 0 0x600>; 3886 3887 interrupt-parent = <&mdss>; 3888 interrupts = <12>; 3889 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3890 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3891 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3892 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3893 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3894 clock-names = "core_iface", 3895 "core_aux", 3896 "ctrl_link", 3897 "ctrl_link_iface", 3898 "stream_pixel"; 3899 3900 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3901 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3902 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3903 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3904 3905 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3906 phy-names = "dp"; 3907 3908 #sound-dai-cells = <0>; 3909 3910 operating-points-v2 = <&dp_opp_table>; 3911 power-domains = <&rpmhpd SM8250_MMCX>; 3912 3913 status = "disabled"; 3914 3915 ports { 3916 #address-cells = <1>; 3917 #size-cells = <0>; 3918 3919 port@0 { 3920 reg = <0>; 3921 mdss_dp_in: endpoint { 3922 remote-endpoint = <&dpu_intf0_out>; 3923 }; 3924 }; 3925 3926 port@1 { 3927 reg = <1>; 3928 3929 mdss_dp_out: endpoint { 3930 remote-endpoint = <&usb_1_qmpphy_dp_in>; 3931 }; 3932 }; 3933 }; 3934 3935 dp_opp_table: opp-table { 3936 compatible = "operating-points-v2"; 3937 3938 opp-160000000 { 3939 opp-hz = /bits/ 64 <160000000>; 3940 required-opps = <&rpmhpd_opp_low_svs>; 3941 }; 3942 3943 opp-270000000 { 3944 opp-hz = /bits/ 64 <270000000>; 3945 required-opps = <&rpmhpd_opp_svs>; 3946 }; 3947 3948 opp-540000000 { 3949 opp-hz = /bits/ 64 <540000000>; 3950 required-opps = <&rpmhpd_opp_svs_l1>; 3951 }; 3952 3953 opp-810000000 { 3954 opp-hz = /bits/ 64 <810000000>; 3955 required-opps = <&rpmhpd_opp_nom>; 3956 }; 3957 }; 3958 }; 3959 3960 mdss_dsi0: dsi@ae94000 { 3961 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3962 reg = <0 0x0ae94000 0 0x400>; 3963 reg-names = "dsi_ctrl"; 3964 3965 interrupt-parent = <&mdss>; 3966 interrupts = <4>; 3967 3968 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3969 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3970 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3971 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3972 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3973 <&gcc GCC_DISP_HF_AXI_CLK>; 3974 clock-names = "byte", 3975 "byte_intf", 3976 "pixel", 3977 "core", 3978 "iface", 3979 "bus"; 3980 3981 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3982 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3983 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3984 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3985 3986 operating-points-v2 = <&dsi_opp_table>; 3987 power-domains = <&rpmhpd SM8150_MMCX>; 3988 3989 phys = <&mdss_dsi0_phy>; 3990 3991 status = "disabled"; 3992 3993 #address-cells = <1>; 3994 #size-cells = <0>; 3995 3996 ports { 3997 #address-cells = <1>; 3998 #size-cells = <0>; 3999 4000 port@0 { 4001 reg = <0>; 4002 mdss_dsi0_in: endpoint { 4003 remote-endpoint = <&dpu_intf1_out>; 4004 }; 4005 }; 4006 4007 port@1 { 4008 reg = <1>; 4009 mdss_dsi0_out: endpoint { 4010 }; 4011 }; 4012 }; 4013 4014 dsi_opp_table: opp-table { 4015 compatible = "operating-points-v2"; 4016 4017 opp-187500000 { 4018 opp-hz = /bits/ 64 <187500000>; 4019 required-opps = <&rpmhpd_opp_low_svs>; 4020 }; 4021 4022 opp-300000000 { 4023 opp-hz = /bits/ 64 <300000000>; 4024 required-opps = <&rpmhpd_opp_svs>; 4025 }; 4026 4027 opp-358000000 { 4028 opp-hz = /bits/ 64 <358000000>; 4029 required-opps = <&rpmhpd_opp_svs_l1>; 4030 }; 4031 }; 4032 }; 4033 4034 mdss_dsi0_phy: phy@ae94400 { 4035 compatible = "qcom,dsi-phy-7nm-8150"; 4036 reg = <0 0x0ae94400 0 0x200>, 4037 <0 0x0ae94600 0 0x280>, 4038 <0 0x0ae94900 0 0x260>; 4039 reg-names = "dsi_phy", 4040 "dsi_phy_lane", 4041 "dsi_pll"; 4042 4043 #clock-cells = <1>; 4044 #phy-cells = <0>; 4045 4046 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4047 <&rpmhcc RPMH_CXO_CLK>; 4048 clock-names = "iface", "ref"; 4049 4050 status = "disabled"; 4051 }; 4052 4053 mdss_dsi1: dsi@ae96000 { 4054 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4055 reg = <0 0x0ae96000 0 0x400>; 4056 reg-names = "dsi_ctrl"; 4057 4058 interrupt-parent = <&mdss>; 4059 interrupts = <5>; 4060 4061 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4062 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4063 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4064 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4065 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4066 <&gcc GCC_DISP_HF_AXI_CLK>; 4067 clock-names = "byte", 4068 "byte_intf", 4069 "pixel", 4070 "core", 4071 "iface", 4072 "bus"; 4073 4074 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4075 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4076 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4077 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4078 4079 operating-points-v2 = <&dsi_opp_table>; 4080 power-domains = <&rpmhpd SM8150_MMCX>; 4081 4082 phys = <&mdss_dsi1_phy>; 4083 4084 status = "disabled"; 4085 4086 #address-cells = <1>; 4087 #size-cells = <0>; 4088 4089 ports { 4090 #address-cells = <1>; 4091 #size-cells = <0>; 4092 4093 port@0 { 4094 reg = <0>; 4095 mdss_dsi1_in: endpoint { 4096 remote-endpoint = <&dpu_intf2_out>; 4097 }; 4098 }; 4099 4100 port@1 { 4101 reg = <1>; 4102 mdss_dsi1_out: endpoint { 4103 }; 4104 }; 4105 }; 4106 }; 4107 4108 mdss_dsi1_phy: phy@ae96400 { 4109 compatible = "qcom,dsi-phy-7nm-8150"; 4110 reg = <0 0x0ae96400 0 0x200>, 4111 <0 0x0ae96600 0 0x280>, 4112 <0 0x0ae96900 0 0x260>; 4113 reg-names = "dsi_phy", 4114 "dsi_phy_lane", 4115 "dsi_pll"; 4116 4117 #clock-cells = <1>; 4118 #phy-cells = <0>; 4119 4120 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4121 <&rpmhcc RPMH_CXO_CLK>; 4122 clock-names = "iface", "ref"; 4123 4124 status = "disabled"; 4125 }; 4126 }; 4127 4128 dispcc: clock-controller@af00000 { 4129 compatible = "qcom,sm8150-dispcc"; 4130 reg = <0 0x0af00000 0 0x10000>; 4131 clocks = <&rpmhcc RPMH_CXO_CLK>, 4132 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4133 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4134 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4135 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 4136 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4137 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4138 clock-names = "bi_tcxo", 4139 "dsi0_phy_pll_out_byteclk", 4140 "dsi0_phy_pll_out_dsiclk", 4141 "dsi1_phy_pll_out_byteclk", 4142 "dsi1_phy_pll_out_dsiclk", 4143 "dp_phy_pll_link_clk", 4144 "dp_phy_pll_vco_div_clk"; 4145 power-domains = <&rpmhpd SM8150_MMCX>; 4146 required-opps = <&rpmhpd_opp_low_svs>; 4147 #clock-cells = <1>; 4148 #reset-cells = <1>; 4149 #power-domain-cells = <1>; 4150 }; 4151 4152 pdc: interrupt-controller@b220000 { 4153 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 4154 reg = <0 0x0b220000 0 0x30000>; 4155 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4156 <125 63 1>; 4157 #interrupt-cells = <2>; 4158 interrupt-parent = <&intc>; 4159 interrupt-controller; 4160 }; 4161 4162 aoss_qmp: power-management@c300000 { 4163 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 4164 reg = <0x0 0x0c300000 0x0 0x400>; 4165 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4166 mboxes = <&apss_shared 0>; 4167 4168 #clock-cells = <0>; 4169 }; 4170 4171 sram@c3f0000 { 4172 compatible = "qcom,rpmh-stats"; 4173 reg = <0 0x0c3f0000 0 0x400>; 4174 }; 4175 4176 tsens0: thermal-sensor@c263000 { 4177 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4178 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4179 <0 0x0c222000 0 0x1ff>; /* SROT */ 4180 #qcom,sensors = <16>; 4181 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4183 interrupt-names = "uplow", "critical"; 4184 #thermal-sensor-cells = <1>; 4185 }; 4186 4187 tsens1: thermal-sensor@c265000 { 4188 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4189 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4190 <0 0x0c223000 0 0x1ff>; /* SROT */ 4191 #qcom,sensors = <8>; 4192 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4194 interrupt-names = "uplow", "critical"; 4195 #thermal-sensor-cells = <1>; 4196 }; 4197 4198 spmi_bus: spmi@c440000 { 4199 compatible = "qcom,spmi-pmic-arb"; 4200 reg = <0x0 0x0c440000 0x0 0x0001100>, 4201 <0x0 0x0c600000 0x0 0x2000000>, 4202 <0x0 0x0e600000 0x0 0x0100000>, 4203 <0x0 0x0e700000 0x0 0x00a0000>, 4204 <0x0 0x0c40a000 0x0 0x0026000>; 4205 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4206 interrupt-names = "periph_irq"; 4207 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4208 qcom,ee = <0>; 4209 qcom,channel = <0>; 4210 #address-cells = <2>; 4211 #size-cells = <0>; 4212 interrupt-controller; 4213 #interrupt-cells = <4>; 4214 }; 4215 4216 apps_smmu: iommu@15000000 { 4217 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4218 reg = <0 0x15000000 0 0x100000>; 4219 #iommu-cells = <2>; 4220 #global-interrupts = <1>; 4221 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4280 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4281 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4282 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4283 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4284 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4285 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4286 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4287 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4288 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4289 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4302 dma-coherent; 4303 }; 4304 4305 remoteproc_adsp: remoteproc@17300000 { 4306 compatible = "qcom,sm8150-adsp-pas"; 4307 reg = <0x0 0x17300000 0x0 0x4040>; 4308 4309 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4310 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4311 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4312 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4313 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4314 interrupt-names = "wdog", "fatal", "ready", 4315 "handover", "stop-ack"; 4316 4317 clocks = <&rpmhcc RPMH_CXO_CLK>; 4318 clock-names = "xo"; 4319 4320 power-domains = <&rpmhpd SM8150_CX>; 4321 4322 memory-region = <&adsp_mem>; 4323 4324 qcom,qmp = <&aoss_qmp>; 4325 4326 qcom,smem-states = <&adsp_smp2p_out 0>; 4327 qcom,smem-state-names = "stop"; 4328 4329 status = "disabled"; 4330 4331 glink-edge { 4332 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4333 label = "lpass"; 4334 qcom,remote-pid = <2>; 4335 mboxes = <&apss_shared 8>; 4336 4337 fastrpc { 4338 compatible = "qcom,fastrpc"; 4339 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4340 label = "adsp"; 4341 qcom,non-secure-domain; 4342 #address-cells = <1>; 4343 #size-cells = <0>; 4344 4345 compute-cb@3 { 4346 compatible = "qcom,fastrpc-compute-cb"; 4347 reg = <3>; 4348 iommus = <&apps_smmu 0x1b23 0x0>; 4349 }; 4350 4351 compute-cb@4 { 4352 compatible = "qcom,fastrpc-compute-cb"; 4353 reg = <4>; 4354 iommus = <&apps_smmu 0x1b24 0x0>; 4355 }; 4356 4357 compute-cb@5 { 4358 compatible = "qcom,fastrpc-compute-cb"; 4359 reg = <5>; 4360 iommus = <&apps_smmu 0x1b25 0x0>; 4361 }; 4362 }; 4363 }; 4364 }; 4365 4366 intc: interrupt-controller@17a00000 { 4367 compatible = "arm,gic-v3"; 4368 interrupt-controller; 4369 #interrupt-cells = <3>; 4370 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4371 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4372 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4373 }; 4374 4375 apss_shared: mailbox@17c00000 { 4376 compatible = "qcom,sm8150-apss-shared", 4377 "qcom,sdm845-apss-shared"; 4378 reg = <0x0 0x17c00000 0x0 0x1000>; 4379 #mbox-cells = <1>; 4380 }; 4381 4382 watchdog@17c10000 { 4383 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4384 reg = <0 0x17c10000 0 0x1000>; 4385 clocks = <&sleep_clk>; 4386 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4387 }; 4388 4389 timer@17c20000 { 4390 #address-cells = <1>; 4391 #size-cells = <1>; 4392 ranges = <0 0 0 0x20000000>; 4393 compatible = "arm,armv7-timer-mem"; 4394 reg = <0x0 0x17c20000 0x0 0x1000>; 4395 clock-frequency = <19200000>; 4396 4397 frame@17c21000 { 4398 frame-number = <0>; 4399 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4401 reg = <0x17c21000 0x1000>, 4402 <0x17c22000 0x1000>; 4403 }; 4404 4405 frame@17c23000 { 4406 frame-number = <1>; 4407 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4408 reg = <0x17c23000 0x1000>; 4409 status = "disabled"; 4410 }; 4411 4412 frame@17c25000 { 4413 frame-number = <2>; 4414 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4415 reg = <0x17c25000 0x1000>; 4416 status = "disabled"; 4417 }; 4418 4419 frame@17c27000 { 4420 frame-number = <3>; 4421 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4422 reg = <0x17c26000 0x1000>; 4423 status = "disabled"; 4424 }; 4425 4426 frame@17c29000 { 4427 frame-number = <4>; 4428 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4429 reg = <0x17c29000 0x1000>; 4430 status = "disabled"; 4431 }; 4432 4433 frame@17c2b000 { 4434 frame-number = <5>; 4435 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4436 reg = <0x17c2b000 0x1000>; 4437 status = "disabled"; 4438 }; 4439 4440 frame@17c2d000 { 4441 frame-number = <6>; 4442 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4443 reg = <0x17c2d000 0x1000>; 4444 status = "disabled"; 4445 }; 4446 }; 4447 4448 apps_rsc: rsc@18200000 { 4449 label = "apps_rsc"; 4450 compatible = "qcom,rpmh-rsc"; 4451 reg = <0x0 0x18200000 0x0 0x10000>, 4452 <0x0 0x18210000 0x0 0x10000>, 4453 <0x0 0x18220000 0x0 0x10000>; 4454 reg-names = "drv-0", "drv-1", "drv-2"; 4455 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4456 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4457 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4458 qcom,tcs-offset = <0xd00>; 4459 qcom,drv-id = <2>; 4460 qcom,tcs-config = <ACTIVE_TCS 2>, 4461 <SLEEP_TCS 3>, 4462 <WAKE_TCS 3>, 4463 <CONTROL_TCS 1>; 4464 power-domains = <&cluster_pd>; 4465 4466 rpmhcc: clock-controller { 4467 compatible = "qcom,sm8150-rpmh-clk"; 4468 #clock-cells = <1>; 4469 clock-names = "xo"; 4470 clocks = <&xo_board>; 4471 }; 4472 4473 rpmhpd: power-controller { 4474 compatible = "qcom,sm8150-rpmhpd"; 4475 #power-domain-cells = <1>; 4476 operating-points-v2 = <&rpmhpd_opp_table>; 4477 4478 rpmhpd_opp_table: opp-table { 4479 compatible = "operating-points-v2"; 4480 4481 rpmhpd_opp_ret: opp1 { 4482 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4483 }; 4484 4485 rpmhpd_opp_min_svs: opp2 { 4486 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4487 }; 4488 4489 rpmhpd_opp_low_svs: opp3 { 4490 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4491 }; 4492 4493 rpmhpd_opp_svs: opp4 { 4494 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4495 }; 4496 4497 rpmhpd_opp_svs_l1: opp5 { 4498 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4499 }; 4500 4501 rpmhpd_opp_svs_l2: opp6 { 4502 opp-level = <224>; 4503 }; 4504 4505 rpmhpd_opp_nom: opp7 { 4506 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4507 }; 4508 4509 rpmhpd_opp_nom_l1: opp8 { 4510 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4511 }; 4512 4513 rpmhpd_opp_nom_l2: opp9 { 4514 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4515 }; 4516 4517 rpmhpd_opp_turbo: opp10 { 4518 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4519 }; 4520 4521 rpmhpd_opp_turbo_l1: opp11 { 4522 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4523 }; 4524 }; 4525 }; 4526 4527 apps_bcm_voter: bcm-voter { 4528 compatible = "qcom,bcm-voter"; 4529 }; 4530 }; 4531 4532 osm_l3: interconnect@18321000 { 4533 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4534 reg = <0 0x18321000 0 0x1400>; 4535 4536 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4537 clock-names = "xo", "alternate"; 4538 4539 #interconnect-cells = <1>; 4540 }; 4541 4542 cpufreq_hw: cpufreq@18323000 { 4543 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4544 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4545 <0 0x18327800 0 0x1400>; 4546 reg-names = "freq-domain0", "freq-domain1", 4547 "freq-domain2"; 4548 4549 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4550 clock-names = "xo", "alternate"; 4551 4552 #freq-domain-cells = <1>; 4553 #clock-cells = <1>; 4554 }; 4555 4556 lmh_cluster1: lmh@18350800 { 4557 compatible = "qcom,sm8150-lmh"; 4558 reg = <0 0x18350800 0 0x400>; 4559 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4560 cpus = <&cpu4>; 4561 qcom,lmh-temp-arm-millicelsius = <60000>; 4562 qcom,lmh-temp-low-millicelsius = <84500>; 4563 qcom,lmh-temp-high-millicelsius = <85000>; 4564 interrupt-controller; 4565 #interrupt-cells = <1>; 4566 }; 4567 4568 lmh_cluster0: lmh@18358800 { 4569 compatible = "qcom,sm8150-lmh"; 4570 reg = <0 0x18358800 0 0x400>; 4571 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4572 cpus = <&cpu0>; 4573 qcom,lmh-temp-arm-millicelsius = <60000>; 4574 qcom,lmh-temp-low-millicelsius = <84500>; 4575 qcom,lmh-temp-high-millicelsius = <85000>; 4576 interrupt-controller; 4577 #interrupt-cells = <1>; 4578 }; 4579 4580 wifi: wifi@18800000 { 4581 compatible = "qcom,wcn3990-wifi"; 4582 reg = <0 0x18800000 0 0x800000>; 4583 reg-names = "membase"; 4584 memory-region = <&wlan_mem>; 4585 clock-names = "cxo_ref_clk_pin", "qdss"; 4586 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4587 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4588 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4589 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4590 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4591 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4592 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4594 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4595 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4596 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4598 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4599 iommus = <&apps_smmu 0x0640 0x1>; 4600 status = "disabled"; 4601 }; 4602 }; 4603 4604 timer { 4605 compatible = "arm,armv8-timer"; 4606 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4607 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4608 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4609 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4610 }; 4611 4612 thermal-zones { 4613 cpu0-thermal { 4614 polling-delay-passive = <250>; 4615 4616 thermal-sensors = <&tsens0 1>; 4617 4618 trips { 4619 cpu0_alert0: trip-point0 { 4620 temperature = <90000>; 4621 hysteresis = <2000>; 4622 type = "passive"; 4623 }; 4624 4625 cpu0_alert1: trip-point1 { 4626 temperature = <95000>; 4627 hysteresis = <2000>; 4628 type = "passive"; 4629 }; 4630 4631 cpu0_crit: cpu-crit { 4632 temperature = <110000>; 4633 hysteresis = <1000>; 4634 type = "critical"; 4635 }; 4636 }; 4637 4638 cooling-maps { 4639 map0 { 4640 trip = <&cpu0_alert0>; 4641 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4642 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4644 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4645 }; 4646 map1 { 4647 trip = <&cpu0_alert1>; 4648 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4649 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4650 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4651 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4652 }; 4653 }; 4654 }; 4655 4656 cpu1-thermal { 4657 polling-delay-passive = <250>; 4658 4659 thermal-sensors = <&tsens0 2>; 4660 4661 trips { 4662 cpu1_alert0: trip-point0 { 4663 temperature = <90000>; 4664 hysteresis = <2000>; 4665 type = "passive"; 4666 }; 4667 4668 cpu1_alert1: trip-point1 { 4669 temperature = <95000>; 4670 hysteresis = <2000>; 4671 type = "passive"; 4672 }; 4673 4674 cpu1_crit: cpu-crit { 4675 temperature = <110000>; 4676 hysteresis = <1000>; 4677 type = "critical"; 4678 }; 4679 }; 4680 4681 cooling-maps { 4682 map0 { 4683 trip = <&cpu1_alert0>; 4684 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4686 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4687 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4688 }; 4689 map1 { 4690 trip = <&cpu1_alert1>; 4691 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4692 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4693 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4694 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4695 }; 4696 }; 4697 }; 4698 4699 cpu2-thermal { 4700 polling-delay-passive = <250>; 4701 4702 thermal-sensors = <&tsens0 3>; 4703 4704 trips { 4705 cpu2_alert0: trip-point0 { 4706 temperature = <90000>; 4707 hysteresis = <2000>; 4708 type = "passive"; 4709 }; 4710 4711 cpu2_alert1: trip-point1 { 4712 temperature = <95000>; 4713 hysteresis = <2000>; 4714 type = "passive"; 4715 }; 4716 4717 cpu2_crit: cpu-crit { 4718 temperature = <110000>; 4719 hysteresis = <1000>; 4720 type = "critical"; 4721 }; 4722 }; 4723 4724 cooling-maps { 4725 map0 { 4726 trip = <&cpu2_alert0>; 4727 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4728 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4729 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4730 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4731 }; 4732 map1 { 4733 trip = <&cpu2_alert1>; 4734 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4735 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4736 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4737 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4738 }; 4739 }; 4740 }; 4741 4742 cpu3-thermal { 4743 polling-delay-passive = <250>; 4744 4745 thermal-sensors = <&tsens0 4>; 4746 4747 trips { 4748 cpu3_alert0: trip-point0 { 4749 temperature = <90000>; 4750 hysteresis = <2000>; 4751 type = "passive"; 4752 }; 4753 4754 cpu3_alert1: trip-point1 { 4755 temperature = <95000>; 4756 hysteresis = <2000>; 4757 type = "passive"; 4758 }; 4759 4760 cpu3_crit: cpu-crit { 4761 temperature = <110000>; 4762 hysteresis = <1000>; 4763 type = "critical"; 4764 }; 4765 }; 4766 4767 cooling-maps { 4768 map0 { 4769 trip = <&cpu3_alert0>; 4770 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4771 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4772 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4773 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4774 }; 4775 map1 { 4776 trip = <&cpu3_alert1>; 4777 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4778 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4779 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4780 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4781 }; 4782 }; 4783 }; 4784 4785 cpu4-top-thermal { 4786 polling-delay-passive = <250>; 4787 4788 thermal-sensors = <&tsens0 7>; 4789 4790 trips { 4791 cpu4_top_alert0: trip-point0 { 4792 temperature = <90000>; 4793 hysteresis = <2000>; 4794 type = "passive"; 4795 }; 4796 4797 cpu4_top_alert1: trip-point1 { 4798 temperature = <95000>; 4799 hysteresis = <2000>; 4800 type = "passive"; 4801 }; 4802 4803 cpu4_top_crit: cpu-crit { 4804 temperature = <110000>; 4805 hysteresis = <1000>; 4806 type = "critical"; 4807 }; 4808 }; 4809 4810 cooling-maps { 4811 map0 { 4812 trip = <&cpu4_top_alert0>; 4813 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4816 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4817 }; 4818 map1 { 4819 trip = <&cpu4_top_alert1>; 4820 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4821 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4822 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4823 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4824 }; 4825 }; 4826 }; 4827 4828 cpu5-top-thermal { 4829 polling-delay-passive = <250>; 4830 4831 thermal-sensors = <&tsens0 8>; 4832 4833 trips { 4834 cpu5_top_alert0: trip-point0 { 4835 temperature = <90000>; 4836 hysteresis = <2000>; 4837 type = "passive"; 4838 }; 4839 4840 cpu5_top_alert1: trip-point1 { 4841 temperature = <95000>; 4842 hysteresis = <2000>; 4843 type = "passive"; 4844 }; 4845 4846 cpu5_top_crit: cpu-crit { 4847 temperature = <110000>; 4848 hysteresis = <1000>; 4849 type = "critical"; 4850 }; 4851 }; 4852 4853 cooling-maps { 4854 map0 { 4855 trip = <&cpu5_top_alert0>; 4856 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4857 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4859 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4860 }; 4861 map1 { 4862 trip = <&cpu5_top_alert1>; 4863 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4864 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4865 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4866 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4867 }; 4868 }; 4869 }; 4870 4871 cpu6-top-thermal { 4872 polling-delay-passive = <250>; 4873 4874 thermal-sensors = <&tsens0 9>; 4875 4876 trips { 4877 cpu6_top_alert0: trip-point0 { 4878 temperature = <90000>; 4879 hysteresis = <2000>; 4880 type = "passive"; 4881 }; 4882 4883 cpu6_top_alert1: trip-point1 { 4884 temperature = <95000>; 4885 hysteresis = <2000>; 4886 type = "passive"; 4887 }; 4888 4889 cpu6_top_crit: cpu-crit { 4890 temperature = <110000>; 4891 hysteresis = <1000>; 4892 type = "critical"; 4893 }; 4894 }; 4895 4896 cooling-maps { 4897 map0 { 4898 trip = <&cpu6_top_alert0>; 4899 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4900 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4901 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4902 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4903 }; 4904 map1 { 4905 trip = <&cpu6_top_alert1>; 4906 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4907 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4908 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4909 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4910 }; 4911 }; 4912 }; 4913 4914 cpu7-top-thermal { 4915 polling-delay-passive = <250>; 4916 4917 thermal-sensors = <&tsens0 10>; 4918 4919 trips { 4920 cpu7_top_alert0: trip-point0 { 4921 temperature = <90000>; 4922 hysteresis = <2000>; 4923 type = "passive"; 4924 }; 4925 4926 cpu7_top_alert1: trip-point1 { 4927 temperature = <95000>; 4928 hysteresis = <2000>; 4929 type = "passive"; 4930 }; 4931 4932 cpu7_top_crit: cpu-crit { 4933 temperature = <110000>; 4934 hysteresis = <1000>; 4935 type = "critical"; 4936 }; 4937 }; 4938 4939 cooling-maps { 4940 map0 { 4941 trip = <&cpu7_top_alert0>; 4942 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4943 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4944 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4945 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4946 }; 4947 map1 { 4948 trip = <&cpu7_top_alert1>; 4949 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4950 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4951 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4952 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4953 }; 4954 }; 4955 }; 4956 4957 cpu4-bottom-thermal { 4958 polling-delay-passive = <250>; 4959 4960 thermal-sensors = <&tsens0 11>; 4961 4962 trips { 4963 cpu4_bottom_alert0: trip-point0 { 4964 temperature = <90000>; 4965 hysteresis = <2000>; 4966 type = "passive"; 4967 }; 4968 4969 cpu4_bottom_alert1: trip-point1 { 4970 temperature = <95000>; 4971 hysteresis = <2000>; 4972 type = "passive"; 4973 }; 4974 4975 cpu4_bottom_crit: cpu-crit { 4976 temperature = <110000>; 4977 hysteresis = <1000>; 4978 type = "critical"; 4979 }; 4980 }; 4981 4982 cooling-maps { 4983 map0 { 4984 trip = <&cpu4_bottom_alert0>; 4985 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4986 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4987 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4988 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4989 }; 4990 map1 { 4991 trip = <&cpu4_bottom_alert1>; 4992 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4993 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4994 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4995 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4996 }; 4997 }; 4998 }; 4999 5000 cpu5-bottom-thermal { 5001 polling-delay-passive = <250>; 5002 5003 thermal-sensors = <&tsens0 12>; 5004 5005 trips { 5006 cpu5_bottom_alert0: trip-point0 { 5007 temperature = <90000>; 5008 hysteresis = <2000>; 5009 type = "passive"; 5010 }; 5011 5012 cpu5_bottom_alert1: trip-point1 { 5013 temperature = <95000>; 5014 hysteresis = <2000>; 5015 type = "passive"; 5016 }; 5017 5018 cpu5_bottom_crit: cpu-crit { 5019 temperature = <110000>; 5020 hysteresis = <1000>; 5021 type = "critical"; 5022 }; 5023 }; 5024 5025 cooling-maps { 5026 map0 { 5027 trip = <&cpu5_bottom_alert0>; 5028 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5029 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5030 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5031 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5032 }; 5033 map1 { 5034 trip = <&cpu5_bottom_alert1>; 5035 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5036 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5037 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5038 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5039 }; 5040 }; 5041 }; 5042 5043 cpu6-bottom-thermal { 5044 polling-delay-passive = <250>; 5045 5046 thermal-sensors = <&tsens0 13>; 5047 5048 trips { 5049 cpu6_bottom_alert0: trip-point0 { 5050 temperature = <90000>; 5051 hysteresis = <2000>; 5052 type = "passive"; 5053 }; 5054 5055 cpu6_bottom_alert1: trip-point1 { 5056 temperature = <95000>; 5057 hysteresis = <2000>; 5058 type = "passive"; 5059 }; 5060 5061 cpu6_bottom_crit: cpu-crit { 5062 temperature = <110000>; 5063 hysteresis = <1000>; 5064 type = "critical"; 5065 }; 5066 }; 5067 5068 cooling-maps { 5069 map0 { 5070 trip = <&cpu6_bottom_alert0>; 5071 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5072 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5073 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5074 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5075 }; 5076 map1 { 5077 trip = <&cpu6_bottom_alert1>; 5078 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5079 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5080 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5081 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5082 }; 5083 }; 5084 }; 5085 5086 cpu7-bottom-thermal { 5087 polling-delay-passive = <250>; 5088 5089 thermal-sensors = <&tsens0 14>; 5090 5091 trips { 5092 cpu7_bottom_alert0: trip-point0 { 5093 temperature = <90000>; 5094 hysteresis = <2000>; 5095 type = "passive"; 5096 }; 5097 5098 cpu7_bottom_alert1: trip-point1 { 5099 temperature = <95000>; 5100 hysteresis = <2000>; 5101 type = "passive"; 5102 }; 5103 5104 cpu7_bottom_crit: cpu-crit { 5105 temperature = <110000>; 5106 hysteresis = <1000>; 5107 type = "critical"; 5108 }; 5109 }; 5110 5111 cooling-maps { 5112 map0 { 5113 trip = <&cpu7_bottom_alert0>; 5114 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5115 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5116 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5117 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5118 }; 5119 map1 { 5120 trip = <&cpu7_bottom_alert1>; 5121 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5122 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5123 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5124 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5125 }; 5126 }; 5127 }; 5128 5129 aoss0-thermal { 5130 polling-delay-passive = <250>; 5131 5132 thermal-sensors = <&tsens0 0>; 5133 5134 trips { 5135 aoss0_alert0: trip-point0 { 5136 temperature = <90000>; 5137 hysteresis = <2000>; 5138 type = "hot"; 5139 }; 5140 }; 5141 }; 5142 5143 cluster0-thermal { 5144 polling-delay-passive = <250>; 5145 5146 thermal-sensors = <&tsens0 5>; 5147 5148 trips { 5149 cluster0_alert0: trip-point0 { 5150 temperature = <90000>; 5151 hysteresis = <2000>; 5152 type = "hot"; 5153 }; 5154 cluster0_crit: cluster0-crit { 5155 temperature = <110000>; 5156 hysteresis = <2000>; 5157 type = "critical"; 5158 }; 5159 }; 5160 }; 5161 5162 cluster1-thermal { 5163 polling-delay-passive = <250>; 5164 5165 thermal-sensors = <&tsens0 6>; 5166 5167 trips { 5168 cluster1_alert0: trip-point0 { 5169 temperature = <90000>; 5170 hysteresis = <2000>; 5171 type = "hot"; 5172 }; 5173 cluster1_crit: cluster1-crit { 5174 temperature = <110000>; 5175 hysteresis = <2000>; 5176 type = "critical"; 5177 }; 5178 }; 5179 }; 5180 5181 gpu-top-thermal { 5182 polling-delay-passive = <250>; 5183 5184 thermal-sensors = <&tsens0 15>; 5185 5186 cooling-maps { 5187 map0 { 5188 trip = <&gpu_top_alert0>; 5189 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5190 }; 5191 }; 5192 5193 trips { 5194 gpu_top_alert0: trip-point0 { 5195 temperature = <85000>; 5196 hysteresis = <1000>; 5197 type = "passive"; 5198 }; 5199 5200 trip-point1 { 5201 temperature = <90000>; 5202 hysteresis = <1000>; 5203 type = "hot"; 5204 }; 5205 5206 trip-point2 { 5207 temperature = <110000>; 5208 hysteresis = <1000>; 5209 type = "critical"; 5210 }; 5211 }; 5212 }; 5213 5214 aoss1-thermal { 5215 polling-delay-passive = <250>; 5216 5217 thermal-sensors = <&tsens1 0>; 5218 5219 trips { 5220 aoss1_alert0: trip-point0 { 5221 temperature = <90000>; 5222 hysteresis = <2000>; 5223 type = "hot"; 5224 }; 5225 }; 5226 }; 5227 5228 wlan-thermal { 5229 polling-delay-passive = <250>; 5230 5231 thermal-sensors = <&tsens1 1>; 5232 5233 trips { 5234 wlan_alert0: trip-point0 { 5235 temperature = <90000>; 5236 hysteresis = <2000>; 5237 type = "hot"; 5238 }; 5239 }; 5240 }; 5241 5242 video-thermal { 5243 polling-delay-passive = <250>; 5244 5245 thermal-sensors = <&tsens1 2>; 5246 5247 trips { 5248 video_alert0: trip-point0 { 5249 temperature = <90000>; 5250 hysteresis = <2000>; 5251 type = "hot"; 5252 }; 5253 }; 5254 }; 5255 5256 mem-thermal { 5257 polling-delay-passive = <250>; 5258 5259 thermal-sensors = <&tsens1 3>; 5260 5261 trips { 5262 mem_alert0: trip-point0 { 5263 temperature = <90000>; 5264 hysteresis = <2000>; 5265 type = "hot"; 5266 }; 5267 }; 5268 }; 5269 5270 q6-hvx-thermal { 5271 polling-delay-passive = <250>; 5272 5273 thermal-sensors = <&tsens1 4>; 5274 5275 trips { 5276 q6_hvx_alert0: trip-point0 { 5277 temperature = <90000>; 5278 hysteresis = <2000>; 5279 type = "hot"; 5280 }; 5281 }; 5282 }; 5283 5284 camera-thermal { 5285 polling-delay-passive = <250>; 5286 5287 thermal-sensors = <&tsens1 5>; 5288 5289 trips { 5290 camera_alert0: trip-point0 { 5291 temperature = <90000>; 5292 hysteresis = <2000>; 5293 type = "hot"; 5294 }; 5295 }; 5296 }; 5297 5298 compute-thermal { 5299 polling-delay-passive = <250>; 5300 5301 thermal-sensors = <&tsens1 6>; 5302 5303 trips { 5304 compute_alert0: trip-point0 { 5305 temperature = <90000>; 5306 hysteresis = <2000>; 5307 type = "hot"; 5308 }; 5309 }; 5310 }; 5311 5312 modem-thermal { 5313 polling-delay-passive = <250>; 5314 5315 thermal-sensors = <&tsens1 7>; 5316 5317 trips { 5318 modem_alert0: trip-point0 { 5319 temperature = <90000>; 5320 hysteresis = <2000>; 5321 type = "hot"; 5322 }; 5323 }; 5324 }; 5325 5326 npu-thermal { 5327 polling-delay-passive = <250>; 5328 5329 thermal-sensors = <&tsens1 8>; 5330 5331 trips { 5332 npu_alert0: trip-point0 { 5333 temperature = <90000>; 5334 hysteresis = <2000>; 5335 type = "hot"; 5336 }; 5337 }; 5338 }; 5339 5340 modem-vec-thermal { 5341 polling-delay-passive = <250>; 5342 5343 thermal-sensors = <&tsens1 9>; 5344 5345 trips { 5346 modem_vec_alert0: trip-point0 { 5347 temperature = <90000>; 5348 hysteresis = <2000>; 5349 type = "hot"; 5350 }; 5351 }; 5352 }; 5353 5354 modem-scl-thermal { 5355 polling-delay-passive = <250>; 5356 5357 thermal-sensors = <&tsens1 10>; 5358 5359 trips { 5360 modem_scl_alert0: trip-point0 { 5361 temperature = <90000>; 5362 hysteresis = <2000>; 5363 type = "hot"; 5364 }; 5365 }; 5366 }; 5367 5368 gpu-bottom-thermal { 5369 polling-delay-passive = <250>; 5370 5371 thermal-sensors = <&tsens1 11>; 5372 5373 cooling-maps { 5374 map0 { 5375 trip = <&gpu_bottom_alert0>; 5376 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5377 }; 5378 }; 5379 5380 trips { 5381 gpu_bottom_alert0: trip-point0 { 5382 temperature = <85000>; 5383 hysteresis = <1000>; 5384 type = "passive"; 5385 }; 5386 5387 trip-point1 { 5388 temperature = <90000>; 5389 hysteresis = <1000>; 5390 type = "hot"; 5391 }; 5392 5393 trip-point2 { 5394 temperature = <110000>; 5395 hysteresis = <1000>; 5396 type = "critical"; 5397 }; 5398 }; 5399 }; 5400 }; 5401}; 5402