1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 11#include <dt-bindings/clock/qcom,gcc-sdm845.h> 12#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 13#include <dt-bindings/clock/qcom,lpass-sdm845.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sdm845.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sdm845.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/phy/phy-qcom-qusb2.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/clock/qcom,gcc-sdm845.h> 31#include <dt-bindings/thermal/thermal.h> 32 33/ { 34 interrupt-parent = <&intc>; 35 36 #address-cells = <2>; 37 #size-cells = <2>; 38 39 aliases { 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 i2c9 = &i2c9; 50 i2c10 = &i2c10; 51 i2c11 = &i2c11; 52 i2c12 = &i2c12; 53 i2c13 = &i2c13; 54 i2c14 = &i2c14; 55 i2c15 = &i2c15; 56 spi0 = &spi0; 57 spi1 = &spi1; 58 spi2 = &spi2; 59 spi3 = &spi3; 60 spi4 = &spi4; 61 spi5 = &spi5; 62 spi6 = &spi6; 63 spi7 = &spi7; 64 spi8 = &spi8; 65 spi9 = &spi9; 66 spi10 = &spi10; 67 spi11 = &spi11; 68 spi12 = &spi12; 69 spi13 = &spi13; 70 spi14 = &spi14; 71 spi15 = &spi15; 72 }; 73 74 chosen { }; 75 76 clocks { 77 xo_board: xo-board { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <38400000>; 81 clock-output-names = "xo_board"; 82 }; 83 84 sleep_clk: sleep-clk { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <32764>; 88 }; 89 }; 90 91 cpus: cpus { 92 #address-cells = <2>; 93 #size-cells = <0>; 94 95 cpu0: cpu@0 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo385"; 98 reg = <0x0 0x0>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <611>; 102 dynamic-power-coefficient = <154>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 operating-points-v2 = <&cpu0_opp_table>; 105 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 106 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 107 power-domains = <&cpu_pd0>; 108 power-domain-names = "psci"; 109 #cooling-cells = <2>; 110 next-level-cache = <&l2_0>; 111 l2_0: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&l3_0>; 116 l3_0: l3-cache { 117 compatible = "cache"; 118 cache-level = <3>; 119 cache-unified; 120 }; 121 }; 122 }; 123 124 cpu1: cpu@100 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo385"; 127 reg = <0x0 0x100>; 128 clocks = <&cpufreq_hw 0>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <611>; 131 dynamic-power-coefficient = <154>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 operating-points-v2 = <&cpu0_opp_table>; 134 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 135 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 136 power-domains = <&cpu_pd1>; 137 power-domain-names = "psci"; 138 #cooling-cells = <2>; 139 next-level-cache = <&l2_100>; 140 l2_100: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu2: cpu@200 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo385"; 151 reg = <0x0 0x200>; 152 clocks = <&cpufreq_hw 0>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <611>; 155 dynamic-power-coefficient = <154>; 156 qcom,freq-domain = <&cpufreq_hw 0>; 157 operating-points-v2 = <&cpu0_opp_table>; 158 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 159 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 160 power-domains = <&cpu_pd2>; 161 power-domain-names = "psci"; 162 #cooling-cells = <2>; 163 next-level-cache = <&l2_200>; 164 l2_200: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_0>; 169 }; 170 }; 171 172 cpu3: cpu@300 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo385"; 175 reg = <0x0 0x300>; 176 clocks = <&cpufreq_hw 0>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <611>; 179 dynamic-power-coefficient = <154>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 operating-points-v2 = <&cpu0_opp_table>; 182 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 183 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 184 #cooling-cells = <2>; 185 power-domains = <&cpu_pd3>; 186 power-domain-names = "psci"; 187 next-level-cache = <&l2_300>; 188 l2_300: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 cache-unified; 192 next-level-cache = <&l3_0>; 193 }; 194 }; 195 196 cpu4: cpu@400 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo385"; 199 reg = <0x0 0x400>; 200 clocks = <&cpufreq_hw 1>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <442>; 204 qcom,freq-domain = <&cpufreq_hw 1>; 205 operating-points-v2 = <&cpu4_opp_table>; 206 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 power-domains = <&cpu_pd4>; 209 power-domain-names = "psci"; 210 #cooling-cells = <2>; 211 next-level-cache = <&l2_400>; 212 l2_400: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&l3_0>; 217 }; 218 }; 219 220 cpu5: cpu@500 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo385"; 223 reg = <0x0 0x500>; 224 clocks = <&cpufreq_hw 1>; 225 enable-method = "psci"; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <442>; 228 qcom,freq-domain = <&cpufreq_hw 1>; 229 operating-points-v2 = <&cpu4_opp_table>; 230 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 232 power-domains = <&cpu_pd5>; 233 power-domain-names = "psci"; 234 #cooling-cells = <2>; 235 next-level-cache = <&l2_500>; 236 l2_500: l2-cache { 237 compatible = "cache"; 238 cache-level = <2>; 239 cache-unified; 240 next-level-cache = <&l3_0>; 241 }; 242 }; 243 244 cpu6: cpu@600 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo385"; 247 reg = <0x0 0x600>; 248 clocks = <&cpufreq_hw 1>; 249 enable-method = "psci"; 250 capacity-dmips-mhz = <1024>; 251 dynamic-power-coefficient = <442>; 252 qcom,freq-domain = <&cpufreq_hw 1>; 253 operating-points-v2 = <&cpu4_opp_table>; 254 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 255 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 256 power-domains = <&cpu_pd6>; 257 power-domain-names = "psci"; 258 #cooling-cells = <2>; 259 next-level-cache = <&l2_600>; 260 l2_600: l2-cache { 261 compatible = "cache"; 262 cache-level = <2>; 263 cache-unified; 264 next-level-cache = <&l3_0>; 265 }; 266 }; 267 268 cpu7: cpu@700 { 269 device_type = "cpu"; 270 compatible = "qcom,kryo385"; 271 reg = <0x0 0x700>; 272 clocks = <&cpufreq_hw 1>; 273 enable-method = "psci"; 274 capacity-dmips-mhz = <1024>; 275 dynamic-power-coefficient = <442>; 276 qcom,freq-domain = <&cpufreq_hw 1>; 277 operating-points-v2 = <&cpu4_opp_table>; 278 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 280 power-domains = <&cpu_pd7>; 281 power-domain-names = "psci"; 282 #cooling-cells = <2>; 283 next-level-cache = <&l2_700>; 284 l2_700: l2-cache { 285 compatible = "cache"; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_0>; 289 }; 290 }; 291 292 cpu-map { 293 cluster0 { 294 core0 { 295 cpu = <&cpu0>; 296 }; 297 298 core1 { 299 cpu = <&cpu1>; 300 }; 301 302 core2 { 303 cpu = <&cpu2>; 304 }; 305 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 310 core4 { 311 cpu = <&cpu4>; 312 }; 313 314 core5 { 315 cpu = <&cpu5>; 316 }; 317 318 core6 { 319 cpu = <&cpu6>; 320 }; 321 322 core7 { 323 cpu = <&cpu7>; 324 }; 325 }; 326 }; 327 328 cpu_idle_states: idle-states { 329 entry-method = "psci"; 330 331 little_cpu_sleep_0: cpu-sleep-0-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "little-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <350>; 336 exit-latency-us = <461>; 337 min-residency-us = <1890>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_0: cpu-sleep-1-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "big-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <264>; 346 exit-latency-us = <621>; 347 min-residency-us = <952>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 cluster_sleep_0: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x4100c244>; 356 entry-latency-us = <3263>; 357 exit-latency-us = <6562>; 358 min-residency-us = <9987>; 359 }; 360 }; 361 }; 362 363 firmware { 364 scm { 365 compatible = "qcom,scm-sdm845", "qcom,scm"; 366 }; 367 }; 368 369 memory@80000000 { 370 device_type = "memory"; 371 /* We expect the bootloader to fill in the size */ 372 reg = <0 0x80000000 0 0>; 373 }; 374 375 cpu0_opp_table: opp-table-cpu0 { 376 compatible = "operating-points-v2"; 377 opp-shared; 378 379 cpu0_opp1: opp-300000000 { 380 opp-hz = /bits/ 64 <300000000>; 381 opp-peak-kBps = <800000 4800000>; 382 }; 383 384 cpu0_opp2: opp-403200000 { 385 opp-hz = /bits/ 64 <403200000>; 386 opp-peak-kBps = <800000 4800000>; 387 }; 388 389 cpu0_opp3: opp-480000000 { 390 opp-hz = /bits/ 64 <480000000>; 391 opp-peak-kBps = <800000 6451200>; 392 }; 393 394 cpu0_opp4: opp-576000000 { 395 opp-hz = /bits/ 64 <576000000>; 396 opp-peak-kBps = <800000 6451200>; 397 }; 398 399 cpu0_opp5: opp-652800000 { 400 opp-hz = /bits/ 64 <652800000>; 401 opp-peak-kBps = <800000 7680000>; 402 }; 403 404 cpu0_opp6: opp-748800000 { 405 opp-hz = /bits/ 64 <748800000>; 406 opp-peak-kBps = <1804000 9216000>; 407 }; 408 409 cpu0_opp7: opp-825600000 { 410 opp-hz = /bits/ 64 <825600000>; 411 opp-peak-kBps = <1804000 9216000>; 412 }; 413 414 cpu0_opp8: opp-902400000 { 415 opp-hz = /bits/ 64 <902400000>; 416 opp-peak-kBps = <1804000 10444800>; 417 }; 418 419 cpu0_opp9: opp-979200000 { 420 opp-hz = /bits/ 64 <979200000>; 421 opp-peak-kBps = <1804000 11980800>; 422 }; 423 424 cpu0_opp10: opp-1056000000 { 425 opp-hz = /bits/ 64 <1056000000>; 426 opp-peak-kBps = <1804000 11980800>; 427 }; 428 429 cpu0_opp11: opp-1132800000 { 430 opp-hz = /bits/ 64 <1132800000>; 431 opp-peak-kBps = <2188000 13516800>; 432 }; 433 434 cpu0_opp12: opp-1228800000 { 435 opp-hz = /bits/ 64 <1228800000>; 436 opp-peak-kBps = <2188000 15052800>; 437 }; 438 439 cpu0_opp13: opp-1324800000 { 440 opp-hz = /bits/ 64 <1324800000>; 441 opp-peak-kBps = <2188000 16588800>; 442 }; 443 444 cpu0_opp14: opp-1420800000 { 445 opp-hz = /bits/ 64 <1420800000>; 446 opp-peak-kBps = <3072000 18124800>; 447 }; 448 449 cpu0_opp15: opp-1516800000 { 450 opp-hz = /bits/ 64 <1516800000>; 451 opp-peak-kBps = <3072000 19353600>; 452 }; 453 454 cpu0_opp16: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <4068000 19353600>; 457 }; 458 459 cpu0_opp17: opp-1689600000 { 460 opp-hz = /bits/ 64 <1689600000>; 461 opp-peak-kBps = <4068000 20889600>; 462 }; 463 464 cpu0_opp18: opp-1766400000 { 465 opp-hz = /bits/ 64 <1766400000>; 466 opp-peak-kBps = <4068000 22425600>; 467 }; 468 }; 469 470 cpu4_opp_table: opp-table-cpu4 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 cpu4_opp1: opp-300000000 { 475 opp-hz = /bits/ 64 <300000000>; 476 opp-peak-kBps = <800000 4800000>; 477 }; 478 479 cpu4_opp2: opp-403200000 { 480 opp-hz = /bits/ 64 <403200000>; 481 opp-peak-kBps = <800000 4800000>; 482 }; 483 484 cpu4_opp3: opp-480000000 { 485 opp-hz = /bits/ 64 <480000000>; 486 opp-peak-kBps = <1804000 4800000>; 487 }; 488 489 cpu4_opp4: opp-576000000 { 490 opp-hz = /bits/ 64 <576000000>; 491 opp-peak-kBps = <1804000 4800000>; 492 }; 493 494 cpu4_opp5: opp-652800000 { 495 opp-hz = /bits/ 64 <652800000>; 496 opp-peak-kBps = <1804000 4800000>; 497 }; 498 499 cpu4_opp6: opp-748800000 { 500 opp-hz = /bits/ 64 <748800000>; 501 opp-peak-kBps = <1804000 4800000>; 502 }; 503 504 cpu4_opp7: opp-825600000 { 505 opp-hz = /bits/ 64 <825600000>; 506 opp-peak-kBps = <2188000 9216000>; 507 }; 508 509 cpu4_opp8: opp-902400000 { 510 opp-hz = /bits/ 64 <902400000>; 511 opp-peak-kBps = <2188000 9216000>; 512 }; 513 514 cpu4_opp9: opp-979200000 { 515 opp-hz = /bits/ 64 <979200000>; 516 opp-peak-kBps = <2188000 9216000>; 517 }; 518 519 cpu4_opp10: opp-1056000000 { 520 opp-hz = /bits/ 64 <1056000000>; 521 opp-peak-kBps = <3072000 9216000>; 522 }; 523 524 cpu4_opp11: opp-1132800000 { 525 opp-hz = /bits/ 64 <1132800000>; 526 opp-peak-kBps = <3072000 11980800>; 527 }; 528 529 cpu4_opp12: opp-1209600000 { 530 opp-hz = /bits/ 64 <1209600000>; 531 opp-peak-kBps = <4068000 11980800>; 532 }; 533 534 cpu4_opp13: opp-1286400000 { 535 opp-hz = /bits/ 64 <1286400000>; 536 opp-peak-kBps = <4068000 11980800>; 537 }; 538 539 cpu4_opp14: opp-1363200000 { 540 opp-hz = /bits/ 64 <1363200000>; 541 opp-peak-kBps = <4068000 15052800>; 542 }; 543 544 cpu4_opp15: opp-1459200000 { 545 opp-hz = /bits/ 64 <1459200000>; 546 opp-peak-kBps = <4068000 15052800>; 547 }; 548 549 cpu4_opp16: opp-1536000000 { 550 opp-hz = /bits/ 64 <1536000000>; 551 opp-peak-kBps = <5412000 15052800>; 552 }; 553 554 cpu4_opp17: opp-1612800000 { 555 opp-hz = /bits/ 64 <1612800000>; 556 opp-peak-kBps = <5412000 15052800>; 557 }; 558 559 cpu4_opp18: opp-1689600000 { 560 opp-hz = /bits/ 64 <1689600000>; 561 opp-peak-kBps = <5412000 19353600>; 562 }; 563 564 cpu4_opp19: opp-1766400000 { 565 opp-hz = /bits/ 64 <1766400000>; 566 opp-peak-kBps = <6220000 19353600>; 567 }; 568 569 cpu4_opp20: opp-1843200000 { 570 opp-hz = /bits/ 64 <1843200000>; 571 opp-peak-kBps = <6220000 19353600>; 572 }; 573 574 cpu4_opp21: opp-1920000000 { 575 opp-hz = /bits/ 64 <1920000000>; 576 opp-peak-kBps = <7216000 19353600>; 577 }; 578 579 cpu4_opp22: opp-1996800000 { 580 opp-hz = /bits/ 64 <1996800000>; 581 opp-peak-kBps = <7216000 20889600>; 582 }; 583 584 cpu4_opp23: opp-2092800000 { 585 opp-hz = /bits/ 64 <2092800000>; 586 opp-peak-kBps = <7216000 20889600>; 587 }; 588 589 cpu4_opp24: opp-2169600000 { 590 opp-hz = /bits/ 64 <2169600000>; 591 opp-peak-kBps = <7216000 20889600>; 592 }; 593 594 cpu4_opp25: opp-2246400000 { 595 opp-hz = /bits/ 64 <2246400000>; 596 opp-peak-kBps = <7216000 20889600>; 597 }; 598 599 cpu4_opp26: opp-2323200000 { 600 opp-hz = /bits/ 64 <2323200000>; 601 opp-peak-kBps = <7216000 20889600>; 602 }; 603 604 cpu4_opp27: opp-2400000000 { 605 opp-hz = /bits/ 64 <2400000000>; 606 opp-peak-kBps = <7216000 22425600>; 607 }; 608 609 cpu4_opp28: opp-2476800000 { 610 opp-hz = /bits/ 64 <2476800000>; 611 opp-peak-kBps = <7216000 22425600>; 612 }; 613 614 cpu4_opp29: opp-2553600000 { 615 opp-hz = /bits/ 64 <2553600000>; 616 opp-peak-kBps = <7216000 22425600>; 617 }; 618 619 cpu4_opp30: opp-2649600000 { 620 opp-hz = /bits/ 64 <2649600000>; 621 opp-peak-kBps = <7216000 22425600>; 622 }; 623 624 cpu4_opp31: opp-2745600000 { 625 opp-hz = /bits/ 64 <2745600000>; 626 opp-peak-kBps = <7216000 25497600>; 627 }; 628 629 cpu4_opp32: opp-2803200000 { 630 opp-hz = /bits/ 64 <2803200000>; 631 opp-peak-kBps = <7216000 25497600>; 632 }; 633 }; 634 635 dsi_opp_table: opp-table-dsi { 636 compatible = "operating-points-v2"; 637 638 opp-19200000 { 639 opp-hz = /bits/ 64 <19200000>; 640 required-opps = <&rpmhpd_opp_min_svs>; 641 }; 642 643 opp-180000000 { 644 opp-hz = /bits/ 64 <180000000>; 645 required-opps = <&rpmhpd_opp_low_svs>; 646 }; 647 648 opp-275000000 { 649 opp-hz = /bits/ 64 <275000000>; 650 required-opps = <&rpmhpd_opp_svs>; 651 }; 652 653 opp-328580000 { 654 opp-hz = /bits/ 64 <328580000>; 655 required-opps = <&rpmhpd_opp_svs_l1>; 656 }; 657 658 opp-358000000 { 659 opp-hz = /bits/ 64 <358000000>; 660 required-opps = <&rpmhpd_opp_nom>; 661 }; 662 }; 663 664 qspi_opp_table: opp-table-qspi { 665 compatible = "operating-points-v2"; 666 667 opp-19200000 { 668 opp-hz = /bits/ 64 <19200000>; 669 required-opps = <&rpmhpd_opp_min_svs>; 670 }; 671 672 opp-100000000 { 673 opp-hz = /bits/ 64 <100000000>; 674 required-opps = <&rpmhpd_opp_low_svs>; 675 }; 676 677 opp-150000000 { 678 opp-hz = /bits/ 64 <150000000>; 679 required-opps = <&rpmhpd_opp_svs>; 680 }; 681 682 opp-300000000 { 683 opp-hz = /bits/ 64 <300000000>; 684 required-opps = <&rpmhpd_opp_nom>; 685 }; 686 }; 687 688 qup_opp_table: opp-table-qup { 689 compatible = "operating-points-v2"; 690 691 opp-50000000 { 692 opp-hz = /bits/ 64 <50000000>; 693 required-opps = <&rpmhpd_opp_min_svs>; 694 }; 695 696 opp-75000000 { 697 opp-hz = /bits/ 64 <75000000>; 698 required-opps = <&rpmhpd_opp_low_svs>; 699 }; 700 701 opp-100000000 { 702 opp-hz = /bits/ 64 <100000000>; 703 required-opps = <&rpmhpd_opp_svs>; 704 }; 705 706 opp-128000000 { 707 opp-hz = /bits/ 64 <128000000>; 708 required-opps = <&rpmhpd_opp_nom>; 709 }; 710 }; 711 712 pmu { 713 compatible = "arm,armv8-pmuv3"; 714 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 715 }; 716 717 psci: psci { 718 compatible = "arm,psci-1.0"; 719 method = "smc"; 720 721 cpu_pd0: power-domain-cpu0 { 722 #power-domain-cells = <0>; 723 power-domains = <&cluster_pd>; 724 domain-idle-states = <&little_cpu_sleep_0>; 725 }; 726 727 cpu_pd1: power-domain-cpu1 { 728 #power-domain-cells = <0>; 729 power-domains = <&cluster_pd>; 730 domain-idle-states = <&little_cpu_sleep_0>; 731 }; 732 733 cpu_pd2: power-domain-cpu2 { 734 #power-domain-cells = <0>; 735 power-domains = <&cluster_pd>; 736 domain-idle-states = <&little_cpu_sleep_0>; 737 }; 738 739 cpu_pd3: power-domain-cpu3 { 740 #power-domain-cells = <0>; 741 power-domains = <&cluster_pd>; 742 domain-idle-states = <&little_cpu_sleep_0>; 743 }; 744 745 cpu_pd4: power-domain-cpu4 { 746 #power-domain-cells = <0>; 747 power-domains = <&cluster_pd>; 748 domain-idle-states = <&big_cpu_sleep_0>; 749 }; 750 751 cpu_pd5: power-domain-cpu5 { 752 #power-domain-cells = <0>; 753 power-domains = <&cluster_pd>; 754 domain-idle-states = <&big_cpu_sleep_0>; 755 }; 756 757 cpu_pd6: power-domain-cpu6 { 758 #power-domain-cells = <0>; 759 power-domains = <&cluster_pd>; 760 domain-idle-states = <&big_cpu_sleep_0>; 761 }; 762 763 cpu_pd7: power-domain-cpu7 { 764 #power-domain-cells = <0>; 765 power-domains = <&cluster_pd>; 766 domain-idle-states = <&big_cpu_sleep_0>; 767 }; 768 769 cluster_pd: power-domain-cluster { 770 #power-domain-cells = <0>; 771 domain-idle-states = <&cluster_sleep_0>; 772 }; 773 }; 774 775 reserved-memory { 776 #address-cells = <2>; 777 #size-cells = <2>; 778 ranges; 779 780 hyp_mem: hyp-mem@85700000 { 781 reg = <0 0x85700000 0 0x600000>; 782 no-map; 783 }; 784 785 xbl_mem: xbl-mem@85e00000 { 786 reg = <0 0x85e00000 0 0x100000>; 787 no-map; 788 }; 789 790 aop_mem: aop-mem@85fc0000 { 791 reg = <0 0x85fc0000 0 0x20000>; 792 no-map; 793 }; 794 795 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 796 compatible = "qcom,cmd-db"; 797 reg = <0x0 0x85fe0000 0 0x20000>; 798 no-map; 799 }; 800 801 smem@86000000 { 802 compatible = "qcom,smem"; 803 reg = <0x0 0x86000000 0 0x200000>; 804 no-map; 805 hwlocks = <&tcsr_mutex 3>; 806 }; 807 808 tz_mem: tz@86200000 { 809 reg = <0 0x86200000 0 0x2d00000>; 810 no-map; 811 }; 812 813 rmtfs_mem: rmtfs@88f00000 { 814 compatible = "qcom,rmtfs-mem"; 815 reg = <0 0x88f00000 0 0x200000>; 816 no-map; 817 818 qcom,client-id = <1>; 819 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 820 }; 821 822 qseecom_mem: qseecom@8ab00000 { 823 reg = <0 0x8ab00000 0 0x1400000>; 824 no-map; 825 }; 826 827 camera_mem: camera-mem@8bf00000 { 828 reg = <0 0x8bf00000 0 0x500000>; 829 no-map; 830 }; 831 832 ipa_fw_mem: ipa-fw@8c400000 { 833 reg = <0 0x8c400000 0 0x10000>; 834 no-map; 835 }; 836 837 ipa_gsi_mem: ipa-gsi@8c410000 { 838 reg = <0 0x8c410000 0 0x5000>; 839 no-map; 840 }; 841 842 gpu_mem: gpu@8c415000 { 843 reg = <0 0x8c415000 0 0x2000>; 844 no-map; 845 }; 846 847 adsp_mem: adsp@8c500000 { 848 reg = <0 0x8c500000 0 0x1a00000>; 849 no-map; 850 }; 851 852 wlan_msa_mem: wlan-msa@8df00000 { 853 reg = <0 0x8df00000 0 0x100000>; 854 no-map; 855 }; 856 857 mpss_region: mpss@8e000000 { 858 reg = <0 0x8e000000 0 0x7800000>; 859 no-map; 860 }; 861 862 venus_mem: venus@95800000 { 863 reg = <0 0x95800000 0 0x500000>; 864 no-map; 865 }; 866 867 cdsp_mem: cdsp@95d00000 { 868 reg = <0 0x95d00000 0 0x800000>; 869 no-map; 870 }; 871 872 mba_region: mba@96500000 { 873 reg = <0 0x96500000 0 0x200000>; 874 no-map; 875 }; 876 877 slpi_mem: slpi@96700000 { 878 reg = <0 0x96700000 0 0x1400000>; 879 no-map; 880 }; 881 882 spss_mem: spss@97b00000 { 883 reg = <0 0x97b00000 0 0x100000>; 884 no-map; 885 }; 886 887 mdata_mem: mpss-metadata { 888 alloc-ranges = <0 0xa0000000 0 0x20000000>; 889 size = <0 0x4000>; 890 no-map; 891 }; 892 893 fastrpc_mem: fastrpc { 894 compatible = "shared-dma-pool"; 895 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 896 alignment = <0x0 0x400000>; 897 size = <0x0 0x1000000>; 898 reusable; 899 }; 900 }; 901 902 adsp_pas: remoteproc-adsp { 903 compatible = "qcom,sdm845-adsp-pas"; 904 905 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 906 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 907 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 908 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 909 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 910 interrupt-names = "wdog", "fatal", "ready", 911 "handover", "stop-ack"; 912 913 clocks = <&rpmhcc RPMH_CXO_CLK>; 914 clock-names = "xo"; 915 916 memory-region = <&adsp_mem>; 917 918 qcom,qmp = <&aoss_qmp>; 919 920 qcom,smem-states = <&adsp_smp2p_out 0>; 921 qcom,smem-state-names = "stop"; 922 923 status = "disabled"; 924 925 glink-edge { 926 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 927 label = "lpass"; 928 qcom,remote-pid = <2>; 929 mboxes = <&apss_shared 8>; 930 931 apr { 932 compatible = "qcom,apr-v2"; 933 qcom,glink-channels = "apr_audio_svc"; 934 qcom,domain = <APR_DOMAIN_ADSP>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 qcom,intents = <512 20>; 938 939 service@3 { 940 reg = <APR_SVC_ADSP_CORE>; 941 compatible = "qcom,q6core"; 942 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 943 }; 944 945 q6afe: service@4 { 946 compatible = "qcom,q6afe"; 947 reg = <APR_SVC_AFE>; 948 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 949 q6afedai: dais { 950 compatible = "qcom,q6afe-dais"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 #sound-dai-cells = <1>; 954 }; 955 }; 956 957 q6asm: service@7 { 958 compatible = "qcom,q6asm"; 959 reg = <APR_SVC_ASM>; 960 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 961 q6asmdai: dais { 962 compatible = "qcom,q6asm-dais"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 #sound-dai-cells = <1>; 966 iommus = <&apps_smmu 0x1821 0x0>; 967 }; 968 }; 969 970 q6adm: service@8 { 971 compatible = "qcom,q6adm"; 972 reg = <APR_SVC_ADM>; 973 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 974 q6routing: routing { 975 compatible = "qcom,q6adm-routing"; 976 #sound-dai-cells = <0>; 977 }; 978 }; 979 }; 980 981 fastrpc { 982 compatible = "qcom,fastrpc"; 983 qcom,glink-channels = "fastrpcglink-apps-dsp"; 984 label = "adsp"; 985 qcom,non-secure-domain; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 989 compute-cb@3 { 990 compatible = "qcom,fastrpc-compute-cb"; 991 reg = <3>; 992 iommus = <&apps_smmu 0x1823 0x0>; 993 }; 994 995 compute-cb@4 { 996 compatible = "qcom,fastrpc-compute-cb"; 997 reg = <4>; 998 iommus = <&apps_smmu 0x1824 0x0>; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 cdsp_pas: remoteproc-cdsp { 1005 compatible = "qcom,sdm845-cdsp-pas"; 1006 1007 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1008 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1009 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1010 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1011 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1012 interrupt-names = "wdog", "fatal", "ready", 1013 "handover", "stop-ack"; 1014 1015 clocks = <&rpmhcc RPMH_CXO_CLK>; 1016 clock-names = "xo"; 1017 1018 memory-region = <&cdsp_mem>; 1019 1020 qcom,qmp = <&aoss_qmp>; 1021 1022 qcom,smem-states = <&cdsp_smp2p_out 0>; 1023 qcom,smem-state-names = "stop"; 1024 1025 status = "disabled"; 1026 1027 glink-edge { 1028 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1029 label = "turing"; 1030 qcom,remote-pid = <5>; 1031 mboxes = <&apss_shared 4>; 1032 fastrpc { 1033 compatible = "qcom,fastrpc"; 1034 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1035 label = "cdsp"; 1036 qcom,non-secure-domain; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 compute-cb@1 { 1041 compatible = "qcom,fastrpc-compute-cb"; 1042 reg = <1>; 1043 iommus = <&apps_smmu 0x1401 0x30>; 1044 }; 1045 1046 compute-cb@2 { 1047 compatible = "qcom,fastrpc-compute-cb"; 1048 reg = <2>; 1049 iommus = <&apps_smmu 0x1402 0x30>; 1050 }; 1051 1052 compute-cb@3 { 1053 compatible = "qcom,fastrpc-compute-cb"; 1054 reg = <3>; 1055 iommus = <&apps_smmu 0x1403 0x30>; 1056 }; 1057 1058 compute-cb@4 { 1059 compatible = "qcom,fastrpc-compute-cb"; 1060 reg = <4>; 1061 iommus = <&apps_smmu 0x1404 0x30>; 1062 }; 1063 1064 compute-cb@5 { 1065 compatible = "qcom,fastrpc-compute-cb"; 1066 reg = <5>; 1067 iommus = <&apps_smmu 0x1405 0x30>; 1068 }; 1069 1070 compute-cb@6 { 1071 compatible = "qcom,fastrpc-compute-cb"; 1072 reg = <6>; 1073 iommus = <&apps_smmu 0x1406 0x30>; 1074 }; 1075 1076 compute-cb@7 { 1077 compatible = "qcom,fastrpc-compute-cb"; 1078 reg = <7>; 1079 iommus = <&apps_smmu 0x1407 0x30>; 1080 }; 1081 1082 compute-cb@8 { 1083 compatible = "qcom,fastrpc-compute-cb"; 1084 reg = <8>; 1085 iommus = <&apps_smmu 0x1408 0x30>; 1086 }; 1087 }; 1088 }; 1089 }; 1090 1091 smp2p-cdsp { 1092 compatible = "qcom,smp2p"; 1093 qcom,smem = <94>, <432>; 1094 1095 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1096 1097 mboxes = <&apss_shared 6>; 1098 1099 qcom,local-pid = <0>; 1100 qcom,remote-pid = <5>; 1101 1102 cdsp_smp2p_out: master-kernel { 1103 qcom,entry-name = "master-kernel"; 1104 #qcom,smem-state-cells = <1>; 1105 }; 1106 1107 cdsp_smp2p_in: slave-kernel { 1108 qcom,entry-name = "slave-kernel"; 1109 1110 interrupt-controller; 1111 #interrupt-cells = <2>; 1112 }; 1113 }; 1114 1115 smp2p-lpass { 1116 compatible = "qcom,smp2p"; 1117 qcom,smem = <443>, <429>; 1118 1119 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1120 1121 mboxes = <&apss_shared 10>; 1122 1123 qcom,local-pid = <0>; 1124 qcom,remote-pid = <2>; 1125 1126 adsp_smp2p_out: master-kernel { 1127 qcom,entry-name = "master-kernel"; 1128 #qcom,smem-state-cells = <1>; 1129 }; 1130 1131 adsp_smp2p_in: slave-kernel { 1132 qcom,entry-name = "slave-kernel"; 1133 1134 interrupt-controller; 1135 #interrupt-cells = <2>; 1136 }; 1137 }; 1138 1139 smp2p-mpss { 1140 compatible = "qcom,smp2p"; 1141 qcom,smem = <435>, <428>; 1142 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1143 mboxes = <&apss_shared 14>; 1144 qcom,local-pid = <0>; 1145 qcom,remote-pid = <1>; 1146 1147 modem_smp2p_out: master-kernel { 1148 qcom,entry-name = "master-kernel"; 1149 #qcom,smem-state-cells = <1>; 1150 }; 1151 1152 modem_smp2p_in: slave-kernel { 1153 qcom,entry-name = "slave-kernel"; 1154 interrupt-controller; 1155 #interrupt-cells = <2>; 1156 }; 1157 1158 ipa_smp2p_out: ipa-ap-to-modem { 1159 qcom,entry-name = "ipa"; 1160 #qcom,smem-state-cells = <1>; 1161 }; 1162 1163 ipa_smp2p_in: ipa-modem-to-ap { 1164 qcom,entry-name = "ipa"; 1165 interrupt-controller; 1166 #interrupt-cells = <2>; 1167 }; 1168 }; 1169 1170 smp2p-slpi { 1171 compatible = "qcom,smp2p"; 1172 qcom,smem = <481>, <430>; 1173 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1174 mboxes = <&apss_shared 26>; 1175 qcom,local-pid = <0>; 1176 qcom,remote-pid = <3>; 1177 1178 slpi_smp2p_out: master-kernel { 1179 qcom,entry-name = "master-kernel"; 1180 #qcom,smem-state-cells = <1>; 1181 }; 1182 1183 slpi_smp2p_in: slave-kernel { 1184 qcom,entry-name = "slave-kernel"; 1185 interrupt-controller; 1186 #interrupt-cells = <2>; 1187 }; 1188 }; 1189 1190 soc: soc@0 { 1191 #address-cells = <2>; 1192 #size-cells = <2>; 1193 ranges = <0 0 0 0 0x10 0>; 1194 dma-ranges = <0 0 0 0 0x10 0>; 1195 compatible = "simple-bus"; 1196 1197 gcc: clock-controller@100000 { 1198 compatible = "qcom,gcc-sdm845"; 1199 reg = <0 0x00100000 0 0x1f0000>; 1200 clocks = <&rpmhcc RPMH_CXO_CLK>, 1201 <&rpmhcc RPMH_CXO_CLK_A>, 1202 <&sleep_clk>, 1203 <&pcie0_phy>, 1204 <&pcie1_phy>; 1205 clock-names = "bi_tcxo", 1206 "bi_tcxo_ao", 1207 "sleep_clk", 1208 "pcie_0_pipe_clk", 1209 "pcie_1_pipe_clk"; 1210 #clock-cells = <1>; 1211 #reset-cells = <1>; 1212 #power-domain-cells = <1>; 1213 power-domains = <&rpmhpd SDM845_CX>; 1214 }; 1215 1216 qfprom@784000 { 1217 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1218 reg = <0 0x00784000 0 0x8ff>; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 1222 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1223 reg = <0x1eb 0x1>; 1224 bits = <1 4>; 1225 }; 1226 1227 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1228 reg = <0x1eb 0x2>; 1229 bits = <6 4>; 1230 }; 1231 }; 1232 1233 rng: rng@793000 { 1234 compatible = "qcom,prng-ee"; 1235 reg = <0 0x00793000 0 0x1000>; 1236 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1237 clock-names = "core"; 1238 }; 1239 1240 gpi_dma0: dma-controller@800000 { 1241 #dma-cells = <3>; 1242 compatible = "qcom,sdm845-gpi-dma"; 1243 reg = <0 0x00800000 0 0x60000>; 1244 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1257 dma-channels = <13>; 1258 dma-channel-mask = <0xfa>; 1259 iommus = <&apps_smmu 0x0016 0x0>; 1260 status = "disabled"; 1261 }; 1262 1263 qupv3_id_0: geniqup@8c0000 { 1264 compatible = "qcom,geni-se-qup"; 1265 reg = <0 0x008c0000 0 0x6000>; 1266 clock-names = "m-ahb", "s-ahb"; 1267 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1268 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1269 iommus = <&apps_smmu 0x3 0x0>; 1270 #address-cells = <2>; 1271 #size-cells = <2>; 1272 ranges; 1273 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1274 interconnect-names = "qup-core"; 1275 status = "disabled"; 1276 1277 i2c0: i2c@880000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0 0x00880000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c0_default>; 1284 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 power-domains = <&rpmhpd SDM845_CX>; 1288 operating-points-v2 = <&qup_opp_table>; 1289 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1290 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1291 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1292 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1293 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1294 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1295 dma-names = "tx", "rx"; 1296 status = "disabled"; 1297 }; 1298 1299 spi0: spi@880000 { 1300 compatible = "qcom,geni-spi"; 1301 reg = <0 0x00880000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_spi0_default>; 1306 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1310 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1311 interconnect-names = "qup-core", "qup-config"; 1312 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1313 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1314 dma-names = "tx", "rx"; 1315 status = "disabled"; 1316 }; 1317 1318 uart0: serial@880000 { 1319 compatible = "qcom,geni-uart"; 1320 reg = <0 0x00880000 0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&qup_uart0_default>; 1325 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1326 power-domains = <&rpmhpd SDM845_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1329 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1330 interconnect-names = "qup-core", "qup-config"; 1331 status = "disabled"; 1332 }; 1333 1334 i2c1: i2c@884000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x00884000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c1_default>; 1341 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 power-domains = <&rpmhpd SDM845_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1347 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1348 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1351 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1352 dma-names = "tx", "rx"; 1353 status = "disabled"; 1354 }; 1355 1356 spi1: spi@884000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0 0x00884000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_spi1_default>; 1363 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1367 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1368 interconnect-names = "qup-core", "qup-config"; 1369 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1370 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1371 dma-names = "tx", "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 uart1: serial@884000 { 1376 compatible = "qcom,geni-uart"; 1377 reg = <0 0x00884000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_uart1_default>; 1382 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1383 power-domains = <&rpmhpd SDM845_CX>; 1384 operating-points-v2 = <&qup_opp_table>; 1385 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1386 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1387 interconnect-names = "qup-core", "qup-config"; 1388 status = "disabled"; 1389 }; 1390 1391 i2c2: i2c@888000 { 1392 compatible = "qcom,geni-i2c"; 1393 reg = <0 0x00888000 0 0x4000>; 1394 clock-names = "se"; 1395 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_i2c2_default>; 1398 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 power-domains = <&rpmhpd SDM845_CX>; 1402 operating-points-v2 = <&qup_opp_table>; 1403 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1404 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1405 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1406 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1407 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1408 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1409 dma-names = "tx", "rx"; 1410 status = "disabled"; 1411 }; 1412 1413 spi2: spi@888000 { 1414 compatible = "qcom,geni-spi"; 1415 reg = <0 0x00888000 0 0x4000>; 1416 clock-names = "se"; 1417 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_spi2_default>; 1420 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1424 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1425 interconnect-names = "qup-core", "qup-config"; 1426 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1427 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1428 dma-names = "tx", "rx"; 1429 status = "disabled"; 1430 }; 1431 1432 uart2: serial@888000 { 1433 compatible = "qcom,geni-uart"; 1434 reg = <0 0x00888000 0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_uart2_default>; 1439 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd SDM845_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1443 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 i2c3: i2c@88c000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x0088c000 0 0x4000>; 1451 clock-names = "se"; 1452 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_i2c3_default>; 1455 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 power-domains = <&rpmhpd SDM845_CX>; 1459 operating-points-v2 = <&qup_opp_table>; 1460 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1461 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1462 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1463 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1464 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1465 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1466 dma-names = "tx", "rx"; 1467 status = "disabled"; 1468 }; 1469 1470 spi3: spi@88c000 { 1471 compatible = "qcom,geni-spi"; 1472 reg = <0 0x0088c000 0 0x4000>; 1473 clock-names = "se"; 1474 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1475 pinctrl-names = "default"; 1476 pinctrl-0 = <&qup_spi3_default>; 1477 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1481 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1482 interconnect-names = "qup-core", "qup-config"; 1483 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1484 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1485 dma-names = "tx", "rx"; 1486 status = "disabled"; 1487 }; 1488 1489 uart3: serial@88c000 { 1490 compatible = "qcom,geni-uart"; 1491 reg = <0 0x0088c000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_uart3_default>; 1496 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1497 power-domains = <&rpmhpd SDM845_CX>; 1498 operating-points-v2 = <&qup_opp_table>; 1499 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1500 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1501 interconnect-names = "qup-core", "qup-config"; 1502 status = "disabled"; 1503 }; 1504 1505 i2c4: i2c@890000 { 1506 compatible = "qcom,geni-i2c"; 1507 reg = <0 0x00890000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_i2c4_default>; 1512 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 power-domains = <&rpmhpd SDM845_CX>; 1516 operating-points-v2 = <&qup_opp_table>; 1517 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1518 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1519 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1521 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1522 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1523 dma-names = "tx", "rx"; 1524 status = "disabled"; 1525 }; 1526 1527 spi4: spi@890000 { 1528 compatible = "qcom,geni-spi"; 1529 reg = <0 0x00890000 0 0x4000>; 1530 clock-names = "se"; 1531 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_spi4_default>; 1534 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1538 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1539 interconnect-names = "qup-core", "qup-config"; 1540 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1541 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1542 dma-names = "tx", "rx"; 1543 status = "disabled"; 1544 }; 1545 1546 uart4: serial@890000 { 1547 compatible = "qcom,geni-uart"; 1548 reg = <0 0x00890000 0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_uart4_default>; 1553 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1554 power-domains = <&rpmhpd SDM845_CX>; 1555 operating-points-v2 = <&qup_opp_table>; 1556 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1557 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1558 interconnect-names = "qup-core", "qup-config"; 1559 status = "disabled"; 1560 }; 1561 1562 i2c5: i2c@894000 { 1563 compatible = "qcom,geni-i2c"; 1564 reg = <0 0x00894000 0 0x4000>; 1565 clock-names = "se"; 1566 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&qup_i2c5_default>; 1569 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 power-domains = <&rpmhpd SDM845_CX>; 1573 operating-points-v2 = <&qup_opp_table>; 1574 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1575 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1576 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1578 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1579 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1580 dma-names = "tx", "rx"; 1581 status = "disabled"; 1582 }; 1583 1584 spi5: spi@894000 { 1585 compatible = "qcom,geni-spi"; 1586 reg = <0 0x00894000 0 0x4000>; 1587 clock-names = "se"; 1588 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1589 pinctrl-names = "default"; 1590 pinctrl-0 = <&qup_spi5_default>; 1591 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1595 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1596 interconnect-names = "qup-core", "qup-config"; 1597 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1598 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1599 dma-names = "tx", "rx"; 1600 status = "disabled"; 1601 }; 1602 1603 uart5: serial@894000 { 1604 compatible = "qcom,geni-uart"; 1605 reg = <0 0x00894000 0 0x4000>; 1606 clock-names = "se"; 1607 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_uart5_default>; 1610 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1611 power-domains = <&rpmhpd SDM845_CX>; 1612 operating-points-v2 = <&qup_opp_table>; 1613 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1615 interconnect-names = "qup-core", "qup-config"; 1616 status = "disabled"; 1617 }; 1618 1619 i2c6: i2c@898000 { 1620 compatible = "qcom,geni-i2c"; 1621 reg = <0 0x00898000 0 0x4000>; 1622 clock-names = "se"; 1623 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1624 pinctrl-names = "default"; 1625 pinctrl-0 = <&qup_i2c6_default>; 1626 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 power-domains = <&rpmhpd SDM845_CX>; 1630 operating-points-v2 = <&qup_opp_table>; 1631 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1632 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1633 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1634 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1635 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1636 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1637 dma-names = "tx", "rx"; 1638 status = "disabled"; 1639 }; 1640 1641 spi6: spi@898000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00898000 0 0x4000>; 1644 clock-names = "se"; 1645 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&qup_spi6_default>; 1648 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1652 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1653 interconnect-names = "qup-core", "qup-config"; 1654 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1655 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1656 dma-names = "tx", "rx"; 1657 status = "disabled"; 1658 }; 1659 1660 uart6: serial@898000 { 1661 compatible = "qcom,geni-uart"; 1662 reg = <0 0x00898000 0 0x4000>; 1663 clock-names = "se"; 1664 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1665 pinctrl-names = "default"; 1666 pinctrl-0 = <&qup_uart6_default>; 1667 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SDM845_CX>; 1669 operating-points-v2 = <&qup_opp_table>; 1670 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1671 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1672 interconnect-names = "qup-core", "qup-config"; 1673 status = "disabled"; 1674 }; 1675 1676 i2c7: i2c@89c000 { 1677 compatible = "qcom,geni-i2c"; 1678 reg = <0 0x0089c000 0 0x4000>; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1681 pinctrl-names = "default"; 1682 pinctrl-0 = <&qup_i2c7_default>; 1683 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 power-domains = <&rpmhpd SDM845_CX>; 1687 operating-points-v2 = <&qup_opp_table>; 1688 status = "disabled"; 1689 }; 1690 1691 spi7: spi@89c000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0 0x0089c000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1696 pinctrl-names = "default"; 1697 pinctrl-0 = <&qup_spi7_default>; 1698 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1702 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1703 interconnect-names = "qup-core", "qup-config"; 1704 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1705 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 status = "disabled"; 1708 }; 1709 1710 uart7: serial@89c000 { 1711 compatible = "qcom,geni-uart"; 1712 reg = <0 0x0089c000 0 0x4000>; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_uart7_default>; 1717 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1718 power-domains = <&rpmhpd SDM845_CX>; 1719 operating-points-v2 = <&qup_opp_table>; 1720 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1721 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1722 interconnect-names = "qup-core", "qup-config"; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 gpi_dma1: dma-controller@a00000 { 1728 #dma-cells = <3>; 1729 compatible = "qcom,sdm845-gpi-dma"; 1730 reg = <0 0x00a00000 0 0x60000>; 1731 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1744 dma-channels = <13>; 1745 dma-channel-mask = <0xfa>; 1746 iommus = <&apps_smmu 0x06d6 0x0>; 1747 status = "disabled"; 1748 }; 1749 1750 qupv3_id_1: geniqup@ac0000 { 1751 compatible = "qcom,geni-se-qup"; 1752 reg = <0 0x00ac0000 0 0x6000>; 1753 clock-names = "m-ahb", "s-ahb"; 1754 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1755 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1756 iommus = <&apps_smmu 0x6c3 0x0>; 1757 #address-cells = <2>; 1758 #size-cells = <2>; 1759 ranges; 1760 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1761 interconnect-names = "qup-core"; 1762 status = "disabled"; 1763 1764 i2c8: i2c@a80000 { 1765 compatible = "qcom,geni-i2c"; 1766 reg = <0 0x00a80000 0 0x4000>; 1767 clock-names = "se"; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1769 pinctrl-names = "default"; 1770 pinctrl-0 = <&qup_i2c8_default>; 1771 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 power-domains = <&rpmhpd SDM845_CX>; 1775 operating-points-v2 = <&qup_opp_table>; 1776 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1777 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1778 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1779 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1780 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1781 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1782 dma-names = "tx", "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 spi8: spi@a80000 { 1787 compatible = "qcom,geni-spi"; 1788 reg = <0 0x00a80000 0 0x4000>; 1789 clock-names = "se"; 1790 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1791 pinctrl-names = "default"; 1792 pinctrl-0 = <&qup_spi8_default>; 1793 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1797 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1798 interconnect-names = "qup-core", "qup-config"; 1799 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1800 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1801 dma-names = "tx", "rx"; 1802 status = "disabled"; 1803 }; 1804 1805 uart8: serial@a80000 { 1806 compatible = "qcom,geni-uart"; 1807 reg = <0 0x00a80000 0 0x4000>; 1808 clock-names = "se"; 1809 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1810 pinctrl-names = "default"; 1811 pinctrl-0 = <&qup_uart8_default>; 1812 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1813 power-domains = <&rpmhpd SDM845_CX>; 1814 operating-points-v2 = <&qup_opp_table>; 1815 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1816 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1817 interconnect-names = "qup-core", "qup-config"; 1818 status = "disabled"; 1819 }; 1820 1821 i2c9: i2c@a84000 { 1822 compatible = "qcom,geni-i2c"; 1823 reg = <0 0x00a84000 0 0x4000>; 1824 clock-names = "se"; 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_i2c9_default>; 1828 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SDM845_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1834 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1835 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1836 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1837 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1838 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1839 dma-names = "tx", "rx"; 1840 status = "disabled"; 1841 }; 1842 1843 spi9: spi@a84000 { 1844 compatible = "qcom,geni-spi"; 1845 reg = <0 0x00a84000 0 0x4000>; 1846 clock-names = "se"; 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&qup_spi9_default>; 1850 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1854 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1855 interconnect-names = "qup-core", "qup-config"; 1856 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 status = "disabled"; 1860 }; 1861 1862 uart9: serial@a84000 { 1863 compatible = "qcom,geni-debug-uart"; 1864 reg = <0 0x00a84000 0 0x4000>; 1865 clock-names = "se"; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_uart9_default>; 1869 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1870 power-domains = <&rpmhpd SDM845_CX>; 1871 operating-points-v2 = <&qup_opp_table>; 1872 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1873 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 status = "disabled"; 1876 }; 1877 1878 i2c10: i2c@a88000 { 1879 compatible = "qcom,geni-i2c"; 1880 reg = <0 0x00a88000 0 0x4000>; 1881 clock-names = "se"; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1883 pinctrl-names = "default"; 1884 pinctrl-0 = <&qup_i2c10_default>; 1885 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 power-domains = <&rpmhpd SDM845_CX>; 1889 operating-points-v2 = <&qup_opp_table>; 1890 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1891 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1892 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1893 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1894 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1895 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1896 dma-names = "tx", "rx"; 1897 status = "disabled"; 1898 }; 1899 1900 spi10: spi@a88000 { 1901 compatible = "qcom,geni-spi"; 1902 reg = <0 0x00a88000 0 0x4000>; 1903 clock-names = "se"; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_spi10_default>; 1907 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1911 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1914 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1915 dma-names = "tx", "rx"; 1916 status = "disabled"; 1917 }; 1918 1919 uart10: serial@a88000 { 1920 compatible = "qcom,geni-uart"; 1921 reg = <0 0x00a88000 0 0x4000>; 1922 clock-names = "se"; 1923 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1924 pinctrl-names = "default"; 1925 pinctrl-0 = <&qup_uart10_default>; 1926 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1927 power-domains = <&rpmhpd SDM845_CX>; 1928 operating-points-v2 = <&qup_opp_table>; 1929 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1930 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1931 interconnect-names = "qup-core", "qup-config"; 1932 status = "disabled"; 1933 }; 1934 1935 i2c11: i2c@a8c000 { 1936 compatible = "qcom,geni-i2c"; 1937 reg = <0 0x00a8c000 0 0x4000>; 1938 clock-names = "se"; 1939 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1940 pinctrl-names = "default"; 1941 pinctrl-0 = <&qup_i2c11_default>; 1942 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 power-domains = <&rpmhpd SDM845_CX>; 1946 operating-points-v2 = <&qup_opp_table>; 1947 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1948 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1949 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1950 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1951 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1952 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1953 dma-names = "tx", "rx"; 1954 status = "disabled"; 1955 }; 1956 1957 spi11: spi@a8c000 { 1958 compatible = "qcom,geni-spi"; 1959 reg = <0 0x00a8c000 0 0x4000>; 1960 clock-names = "se"; 1961 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1962 pinctrl-names = "default"; 1963 pinctrl-0 = <&qup_spi11_default>; 1964 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1965 #address-cells = <1>; 1966 #size-cells = <0>; 1967 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1968 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1969 interconnect-names = "qup-core", "qup-config"; 1970 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1971 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1972 dma-names = "tx", "rx"; 1973 status = "disabled"; 1974 }; 1975 1976 uart11: serial@a8c000 { 1977 compatible = "qcom,geni-uart"; 1978 reg = <0 0x00a8c000 0 0x4000>; 1979 clock-names = "se"; 1980 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1981 pinctrl-names = "default"; 1982 pinctrl-0 = <&qup_uart11_default>; 1983 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1984 power-domains = <&rpmhpd SDM845_CX>; 1985 operating-points-v2 = <&qup_opp_table>; 1986 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1987 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1988 interconnect-names = "qup-core", "qup-config"; 1989 status = "disabled"; 1990 }; 1991 1992 i2c12: i2c@a90000 { 1993 compatible = "qcom,geni-i2c"; 1994 reg = <0 0x00a90000 0 0x4000>; 1995 clock-names = "se"; 1996 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1997 pinctrl-names = "default"; 1998 pinctrl-0 = <&qup_i2c12_default>; 1999 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 power-domains = <&rpmhpd SDM845_CX>; 2003 operating-points-v2 = <&qup_opp_table>; 2004 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2005 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2006 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2007 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2008 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2009 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2010 dma-names = "tx", "rx"; 2011 status = "disabled"; 2012 }; 2013 2014 spi12: spi@a90000 { 2015 compatible = "qcom,geni-spi"; 2016 reg = <0 0x00a90000 0 0x4000>; 2017 clock-names = "se"; 2018 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2019 pinctrl-names = "default"; 2020 pinctrl-0 = <&qup_spi12_default>; 2021 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2022 #address-cells = <1>; 2023 #size-cells = <0>; 2024 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2025 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2026 interconnect-names = "qup-core", "qup-config"; 2027 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2028 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2029 dma-names = "tx", "rx"; 2030 status = "disabled"; 2031 }; 2032 2033 uart12: serial@a90000 { 2034 compatible = "qcom,geni-uart"; 2035 reg = <0 0x00a90000 0 0x4000>; 2036 clock-names = "se"; 2037 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2038 pinctrl-names = "default"; 2039 pinctrl-0 = <&qup_uart12_default>; 2040 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2041 power-domains = <&rpmhpd SDM845_CX>; 2042 operating-points-v2 = <&qup_opp_table>; 2043 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2044 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2045 interconnect-names = "qup-core", "qup-config"; 2046 status = "disabled"; 2047 }; 2048 2049 i2c13: i2c@a94000 { 2050 compatible = "qcom,geni-i2c"; 2051 reg = <0 0x00a94000 0 0x4000>; 2052 clock-names = "se"; 2053 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2054 pinctrl-names = "default"; 2055 pinctrl-0 = <&qup_i2c13_default>; 2056 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 power-domains = <&rpmhpd SDM845_CX>; 2060 operating-points-v2 = <&qup_opp_table>; 2061 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2062 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2063 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2064 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2065 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2066 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2067 dma-names = "tx", "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 spi13: spi@a94000 { 2072 compatible = "qcom,geni-spi"; 2073 reg = <0 0x00a94000 0 0x4000>; 2074 clock-names = "se"; 2075 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2076 pinctrl-names = "default"; 2077 pinctrl-0 = <&qup_spi13_default>; 2078 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2082 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2083 interconnect-names = "qup-core", "qup-config"; 2084 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2085 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2086 dma-names = "tx", "rx"; 2087 status = "disabled"; 2088 }; 2089 2090 uart13: serial@a94000 { 2091 compatible = "qcom,geni-uart"; 2092 reg = <0 0x00a94000 0 0x4000>; 2093 clock-names = "se"; 2094 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2095 pinctrl-names = "default"; 2096 pinctrl-0 = <&qup_uart13_default>; 2097 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2098 power-domains = <&rpmhpd SDM845_CX>; 2099 operating-points-v2 = <&qup_opp_table>; 2100 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2101 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2102 interconnect-names = "qup-core", "qup-config"; 2103 status = "disabled"; 2104 }; 2105 2106 i2c14: i2c@a98000 { 2107 compatible = "qcom,geni-i2c"; 2108 reg = <0 0x00a98000 0 0x4000>; 2109 clock-names = "se"; 2110 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2111 pinctrl-names = "default"; 2112 pinctrl-0 = <&qup_i2c14_default>; 2113 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2114 #address-cells = <1>; 2115 #size-cells = <0>; 2116 power-domains = <&rpmhpd SDM845_CX>; 2117 operating-points-v2 = <&qup_opp_table>; 2118 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2119 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2120 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2121 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2122 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2123 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2124 dma-names = "tx", "rx"; 2125 status = "disabled"; 2126 }; 2127 2128 spi14: spi@a98000 { 2129 compatible = "qcom,geni-spi"; 2130 reg = <0 0x00a98000 0 0x4000>; 2131 clock-names = "se"; 2132 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2133 pinctrl-names = "default"; 2134 pinctrl-0 = <&qup_spi14_default>; 2135 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2139 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2140 interconnect-names = "qup-core", "qup-config"; 2141 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2142 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2143 dma-names = "tx", "rx"; 2144 status = "disabled"; 2145 }; 2146 2147 uart14: serial@a98000 { 2148 compatible = "qcom,geni-uart"; 2149 reg = <0 0x00a98000 0 0x4000>; 2150 clock-names = "se"; 2151 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2152 pinctrl-names = "default"; 2153 pinctrl-0 = <&qup_uart14_default>; 2154 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2155 power-domains = <&rpmhpd SDM845_CX>; 2156 operating-points-v2 = <&qup_opp_table>; 2157 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2158 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2159 interconnect-names = "qup-core", "qup-config"; 2160 status = "disabled"; 2161 }; 2162 2163 i2c15: i2c@a9c000 { 2164 compatible = "qcom,geni-i2c"; 2165 reg = <0 0x00a9c000 0 0x4000>; 2166 clock-names = "se"; 2167 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2168 pinctrl-names = "default"; 2169 pinctrl-0 = <&qup_i2c15_default>; 2170 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 power-domains = <&rpmhpd SDM845_CX>; 2174 operating-points-v2 = <&qup_opp_table>; 2175 status = "disabled"; 2176 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2177 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2178 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2179 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2180 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2181 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2182 dma-names = "tx", "rx"; 2183 }; 2184 2185 spi15: spi@a9c000 { 2186 compatible = "qcom,geni-spi"; 2187 reg = <0 0x00a9c000 0 0x4000>; 2188 clock-names = "se"; 2189 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2190 pinctrl-names = "default"; 2191 pinctrl-0 = <&qup_spi15_default>; 2192 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2196 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2197 interconnect-names = "qup-core", "qup-config"; 2198 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2199 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2200 dma-names = "tx", "rx"; 2201 status = "disabled"; 2202 }; 2203 2204 uart15: serial@a9c000 { 2205 compatible = "qcom,geni-uart"; 2206 reg = <0 0x00a9c000 0 0x4000>; 2207 clock-names = "se"; 2208 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2209 pinctrl-names = "default"; 2210 pinctrl-0 = <&qup_uart15_default>; 2211 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2212 power-domains = <&rpmhpd SDM845_CX>; 2213 operating-points-v2 = <&qup_opp_table>; 2214 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2215 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2216 interconnect-names = "qup-core", "qup-config"; 2217 status = "disabled"; 2218 }; 2219 }; 2220 2221 llcc: system-cache-controller@1100000 { 2222 compatible = "qcom,sdm845-llcc"; 2223 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2224 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2225 <0 0x01300000 0 0x50000>; 2226 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2227 "llcc3_base", "llcc_broadcast_base"; 2228 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2229 }; 2230 2231 dma@10a2000 { 2232 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2233 reg = <0x0 0x010a2000 0x0 0x1000>, 2234 <0x0 0x010ae000 0x0 0x2000>; 2235 }; 2236 2237 pmu@114a000 { 2238 compatible = "qcom,sdm845-llcc-bwmon"; 2239 reg = <0 0x0114a000 0 0x1000>; 2240 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2241 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2242 2243 operating-points-v2 = <&llcc_bwmon_opp_table>; 2244 2245 llcc_bwmon_opp_table: opp-table { 2246 compatible = "operating-points-v2"; 2247 2248 /* 2249 * The interconnect path bandwidth taken from 2250 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2251 * interconnect. This also matches the 2252 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2253 * bus width: 4 bytes) from msm-4.9 downstream 2254 * kernel. 2255 */ 2256 opp-0 { 2257 opp-peak-kBps = <800000>; 2258 }; 2259 opp-1 { 2260 opp-peak-kBps = <1804000>; 2261 }; 2262 opp-2 { 2263 opp-peak-kBps = <3072000>; 2264 }; 2265 opp-3 { 2266 opp-peak-kBps = <5412000>; 2267 }; 2268 opp-4 { 2269 opp-peak-kBps = <7216000>; 2270 }; 2271 }; 2272 }; 2273 2274 pmu@1436400 { 2275 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2276 reg = <0 0x01436400 0 0x600>; 2277 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2278 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2279 2280 operating-points-v2 = <&cpu_bwmon_opp_table>; 2281 2282 cpu_bwmon_opp_table: opp-table { 2283 compatible = "operating-points-v2"; 2284 2285 /* 2286 * The interconnect path bandwidth taken from 2287 * cpu4_opp_table bandwidth for OSM L3 2288 * interconnect. This also matches the OSM L3 2289 * from bandwidth table of qcom,cpu4-l3lat-mon 2290 * (qcom,core-dev-table, bus width: 16 bytes) 2291 * from msm-4.9 downstream kernel. 2292 */ 2293 opp-0 { 2294 opp-peak-kBps = <4800000>; 2295 }; 2296 opp-1 { 2297 opp-peak-kBps = <9216000>; 2298 }; 2299 opp-2 { 2300 opp-peak-kBps = <15052800>; 2301 }; 2302 opp-3 { 2303 opp-peak-kBps = <20889600>; 2304 }; 2305 opp-4 { 2306 opp-peak-kBps = <25497600>; 2307 }; 2308 }; 2309 }; 2310 2311 pcie0: pcie@1c00000 { 2312 compatible = "qcom,pcie-sdm845"; 2313 reg = <0 0x01c00000 0 0x2000>, 2314 <0 0x60000000 0 0xf1d>, 2315 <0 0x60000f20 0 0xa8>, 2316 <0 0x60100000 0 0x100000>, 2317 <0 0x01c07000 0 0x1000>; 2318 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2319 device_type = "pci"; 2320 linux,pci-domain = <0>; 2321 bus-range = <0x00 0xff>; 2322 num-lanes = <1>; 2323 2324 #address-cells = <3>; 2325 #size-cells = <2>; 2326 2327 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2328 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2329 2330 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2331 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2332 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2333 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2339 interrupt-names = "msi0", 2340 "msi1", 2341 "msi2", 2342 "msi3", 2343 "msi4", 2344 "msi5", 2345 "msi6", 2346 "msi7", 2347 "global"; 2348 #interrupt-cells = <1>; 2349 interrupt-map-mask = <0 0 0 0x7>; 2350 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2351 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2352 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2353 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2354 2355 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2356 <&gcc GCC_PCIE_0_AUX_CLK>, 2357 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2358 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2359 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2360 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2361 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2362 clock-names = "pipe", 2363 "aux", 2364 "cfg", 2365 "bus_master", 2366 "bus_slave", 2367 "slave_q2a", 2368 "tbu"; 2369 2370 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2371 <0x100 &apps_smmu 0x1c11 0x1>, 2372 <0x200 &apps_smmu 0x1c12 0x1>, 2373 <0x300 &apps_smmu 0x1c13 0x1>, 2374 <0x400 &apps_smmu 0x1c14 0x1>, 2375 <0x500 &apps_smmu 0x1c15 0x1>, 2376 <0x600 &apps_smmu 0x1c16 0x1>, 2377 <0x700 &apps_smmu 0x1c17 0x1>, 2378 <0x800 &apps_smmu 0x1c18 0x1>, 2379 <0x900 &apps_smmu 0x1c19 0x1>, 2380 <0xa00 &apps_smmu 0x1c1a 0x1>, 2381 <0xb00 &apps_smmu 0x1c1b 0x1>, 2382 <0xc00 &apps_smmu 0x1c1c 0x1>, 2383 <0xd00 &apps_smmu 0x1c1d 0x1>, 2384 <0xe00 &apps_smmu 0x1c1e 0x1>, 2385 <0xf00 &apps_smmu 0x1c1f 0x1>; 2386 2387 resets = <&gcc GCC_PCIE_0_BCR>; 2388 reset-names = "pci"; 2389 2390 power-domains = <&gcc PCIE_0_GDSC>; 2391 2392 phys = <&pcie0_phy>; 2393 phy-names = "pciephy"; 2394 2395 status = "disabled"; 2396 2397 pcie@0 { 2398 device_type = "pci"; 2399 reg = <0x0 0x0 0x0 0x0 0x0>; 2400 bus-range = <0x01 0xff>; 2401 2402 #address-cells = <3>; 2403 #size-cells = <2>; 2404 ranges; 2405 }; 2406 }; 2407 2408 pcie0_phy: phy@1c06000 { 2409 compatible = "qcom,sdm845-qmp-pcie-phy"; 2410 reg = <0 0x01c06000 0 0x1000>; 2411 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2412 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2413 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2414 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2415 <&gcc GCC_PCIE_0_PIPE_CLK>; 2416 clock-names = "aux", 2417 "cfg_ahb", 2418 "ref", 2419 "refgen", 2420 "pipe"; 2421 2422 clock-output-names = "pcie_0_pipe_clk"; 2423 #clock-cells = <0>; 2424 2425 #phy-cells = <0>; 2426 2427 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2428 reset-names = "phy"; 2429 2430 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2431 assigned-clock-rates = <100000000>; 2432 2433 status = "disabled"; 2434 }; 2435 2436 pcie1: pcie@1c08000 { 2437 compatible = "qcom,pcie-sdm845"; 2438 reg = <0 0x01c08000 0 0x2000>, 2439 <0 0x40000000 0 0xf1d>, 2440 <0 0x40000f20 0 0xa8>, 2441 <0 0x40100000 0 0x100000>, 2442 <0 0x01c0c000 0 0x1000>; 2443 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2444 device_type = "pci"; 2445 linux,pci-domain = <1>; 2446 bus-range = <0x00 0xff>; 2447 num-lanes = <1>; 2448 2449 #address-cells = <3>; 2450 #size-cells = <2>; 2451 2452 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2453 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2454 2455 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2459 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2460 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2464 interrupt-names = "msi0", 2465 "msi1", 2466 "msi2", 2467 "msi3", 2468 "msi4", 2469 "msi5", 2470 "msi6", 2471 "msi7", 2472 "global"; 2473 #interrupt-cells = <1>; 2474 interrupt-map-mask = <0 0 0 0x7>; 2475 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2476 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2477 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2478 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2479 2480 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2481 <&gcc GCC_PCIE_1_AUX_CLK>, 2482 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2483 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2484 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2485 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2486 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2487 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2488 clock-names = "pipe", 2489 "aux", 2490 "cfg", 2491 "bus_master", 2492 "bus_slave", 2493 "slave_q2a", 2494 "ref", 2495 "tbu"; 2496 2497 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2498 assigned-clock-rates = <19200000>; 2499 2500 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2501 <0x100 &apps_smmu 0x1c01 0x1>, 2502 <0x200 &apps_smmu 0x1c02 0x1>, 2503 <0x300 &apps_smmu 0x1c03 0x1>, 2504 <0x400 &apps_smmu 0x1c04 0x1>, 2505 <0x500 &apps_smmu 0x1c05 0x1>, 2506 <0x600 &apps_smmu 0x1c06 0x1>, 2507 <0x700 &apps_smmu 0x1c07 0x1>, 2508 <0x800 &apps_smmu 0x1c08 0x1>, 2509 <0x900 &apps_smmu 0x1c09 0x1>, 2510 <0xa00 &apps_smmu 0x1c0a 0x1>, 2511 <0xb00 &apps_smmu 0x1c0b 0x1>, 2512 <0xc00 &apps_smmu 0x1c0c 0x1>, 2513 <0xd00 &apps_smmu 0x1c0d 0x1>, 2514 <0xe00 &apps_smmu 0x1c0e 0x1>, 2515 <0xf00 &apps_smmu 0x1c0f 0x1>; 2516 2517 resets = <&gcc GCC_PCIE_1_BCR>; 2518 reset-names = "pci"; 2519 2520 power-domains = <&gcc PCIE_1_GDSC>; 2521 2522 phys = <&pcie1_phy>; 2523 phy-names = "pciephy"; 2524 2525 status = "disabled"; 2526 2527 pcie@0 { 2528 device_type = "pci"; 2529 reg = <0x0 0x0 0x0 0x0 0x0>; 2530 bus-range = <0x01 0xff>; 2531 2532 #address-cells = <3>; 2533 #size-cells = <2>; 2534 ranges; 2535 }; 2536 }; 2537 2538 pcie1_phy: phy@1c0a000 { 2539 compatible = "qcom,sdm845-qhp-pcie-phy"; 2540 reg = <0 0x01c0a000 0 0x2000>; 2541 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2542 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2543 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2544 <&gcc GCC_PCIE_PHY_REFGEN_CLK>, 2545 <&gcc GCC_PCIE_1_PIPE_CLK>; 2546 clock-names = "aux", 2547 "cfg_ahb", 2548 "ref", 2549 "refgen", 2550 "pipe"; 2551 2552 clock-output-names = "pcie_1_pipe_clk"; 2553 #clock-cells = <0>; 2554 2555 #phy-cells = <0>; 2556 2557 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2558 reset-names = "phy"; 2559 2560 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2561 assigned-clock-rates = <100000000>; 2562 2563 status = "disabled"; 2564 }; 2565 2566 mem_noc: interconnect@1380000 { 2567 compatible = "qcom,sdm845-mem-noc"; 2568 reg = <0 0x01380000 0 0x27200>; 2569 #interconnect-cells = <2>; 2570 qcom,bcm-voters = <&apps_bcm_voter>; 2571 }; 2572 2573 dc_noc: interconnect@14e0000 { 2574 compatible = "qcom,sdm845-dc-noc"; 2575 reg = <0 0x014e0000 0 0x400>; 2576 #interconnect-cells = <2>; 2577 qcom,bcm-voters = <&apps_bcm_voter>; 2578 }; 2579 2580 config_noc: interconnect@1500000 { 2581 compatible = "qcom,sdm845-config-noc"; 2582 reg = <0 0x01500000 0 0x5080>; 2583 #interconnect-cells = <2>; 2584 qcom,bcm-voters = <&apps_bcm_voter>; 2585 }; 2586 2587 system_noc: interconnect@1620000 { 2588 compatible = "qcom,sdm845-system-noc"; 2589 reg = <0 0x01620000 0 0x18080>; 2590 #interconnect-cells = <2>; 2591 qcom,bcm-voters = <&apps_bcm_voter>; 2592 }; 2593 2594 aggre1_noc: interconnect@16e0000 { 2595 compatible = "qcom,sdm845-aggre1-noc"; 2596 reg = <0 0x016e0000 0 0x15080>; 2597 #interconnect-cells = <2>; 2598 qcom,bcm-voters = <&apps_bcm_voter>; 2599 }; 2600 2601 aggre2_noc: interconnect@1700000 { 2602 compatible = "qcom,sdm845-aggre2-noc"; 2603 reg = <0 0x01700000 0 0x1f300>; 2604 #interconnect-cells = <2>; 2605 qcom,bcm-voters = <&apps_bcm_voter>; 2606 }; 2607 2608 mmss_noc: interconnect@1740000 { 2609 compatible = "qcom,sdm845-mmss-noc"; 2610 reg = <0 0x01740000 0 0x1c100>; 2611 #interconnect-cells = <2>; 2612 qcom,bcm-voters = <&apps_bcm_voter>; 2613 }; 2614 2615 ufs_mem_hc: ufshc@1d84000 { 2616 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2617 "jedec,ufs-2.0"; 2618 reg = <0 0x01d84000 0 0x2500>, 2619 <0 0x01d90000 0 0x8000>; 2620 reg-names = "std", "ice"; 2621 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2622 phys = <&ufs_mem_phy>; 2623 phy-names = "ufsphy"; 2624 lanes-per-direction = <2>; 2625 power-domains = <&gcc UFS_PHY_GDSC>; 2626 #reset-cells = <1>; 2627 resets = <&gcc GCC_UFS_PHY_BCR>; 2628 reset-names = "rst"; 2629 2630 iommus = <&apps_smmu 0x100 0xf>; 2631 2632 clock-names = 2633 "core_clk", 2634 "bus_aggr_clk", 2635 "iface_clk", 2636 "core_clk_unipro", 2637 "ref_clk", 2638 "tx_lane0_sync_clk", 2639 "rx_lane0_sync_clk", 2640 "rx_lane1_sync_clk", 2641 "ice_core_clk"; 2642 clocks = 2643 <&gcc GCC_UFS_PHY_AXI_CLK>, 2644 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2645 <&gcc GCC_UFS_PHY_AHB_CLK>, 2646 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2647 <&rpmhcc RPMH_CXO_CLK>, 2648 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2649 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2650 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2651 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2652 2653 operating-points-v2 = <&ufs_opp_table>; 2654 2655 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, 2656 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2657 interconnect-names = "ufs-ddr", "cpu-ufs"; 2658 2659 status = "disabled"; 2660 2661 ufs_opp_table: opp-table { 2662 compatible = "operating-points-v2"; 2663 2664 opp-50000000 { 2665 opp-hz = /bits/ 64 <50000000>, 2666 /bits/ 64 <0>, 2667 /bits/ 64 <0>, 2668 /bits/ 64 <37500000>, 2669 /bits/ 64 <0>, 2670 /bits/ 64 <0>, 2671 /bits/ 64 <0>, 2672 /bits/ 64 <0>, 2673 /bits/ 64 <75000000>; 2674 required-opps = <&rpmhpd_opp_low_svs>; 2675 }; 2676 2677 opp-200000000 { 2678 opp-hz = /bits/ 64 <200000000>, 2679 /bits/ 64 <0>, 2680 /bits/ 64 <0>, 2681 /bits/ 64 <150000000>, 2682 /bits/ 64 <0>, 2683 /bits/ 64 <0>, 2684 /bits/ 64 <0>, 2685 /bits/ 64 <0>, 2686 /bits/ 64 <300000000>; 2687 required-opps = <&rpmhpd_opp_nom>; 2688 }; 2689 }; 2690 }; 2691 2692 ufs_mem_phy: phy@1d87000 { 2693 compatible = "qcom,sdm845-qmp-ufs-phy"; 2694 reg = <0 0x01d87000 0 0x1000>; 2695 2696 clocks = <&rpmhcc RPMH_CXO_CLK>, 2697 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2698 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2699 clock-names = "ref", 2700 "ref_aux", 2701 "qref"; 2702 2703 power-domains = <&gcc UFS_PHY_GDSC>; 2704 2705 resets = <&ufs_mem_hc 0>; 2706 reset-names = "ufsphy"; 2707 2708 #phy-cells = <0>; 2709 status = "disabled"; 2710 }; 2711 2712 cryptobam: dma-controller@1dc4000 { 2713 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2714 reg = <0 0x01dc4000 0 0x24000>; 2715 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2716 clocks = <&rpmhcc RPMH_CE_CLK>; 2717 clock-names = "bam_clk"; 2718 #dma-cells = <1>; 2719 qcom,ee = <0>; 2720 qcom,controlled-remotely; 2721 iommus = <&apps_smmu 0x704 0x1>, 2722 <&apps_smmu 0x706 0x1>, 2723 <&apps_smmu 0x714 0x1>, 2724 <&apps_smmu 0x716 0x1>; 2725 }; 2726 2727 crypto: crypto@1dfa000 { 2728 compatible = "qcom,crypto-v5.4"; 2729 reg = <0 0x01dfa000 0 0x6000>; 2730 clocks = <&gcc GCC_CE1_AHB_CLK>, 2731 <&gcc GCC_CE1_AXI_CLK>, 2732 <&rpmhcc RPMH_CE_CLK>; 2733 clock-names = "iface", "bus", "core"; 2734 dmas = <&cryptobam 6>, <&cryptobam 7>; 2735 dma-names = "rx", "tx"; 2736 iommus = <&apps_smmu 0x704 0x1>, 2737 <&apps_smmu 0x706 0x1>, 2738 <&apps_smmu 0x714 0x1>, 2739 <&apps_smmu 0x716 0x1>; 2740 }; 2741 2742 ipa: ipa@1e40000 { 2743 compatible = "qcom,sdm845-ipa"; 2744 2745 iommus = <&apps_smmu 0x720 0x0>, 2746 <&apps_smmu 0x722 0x0>; 2747 reg = <0 0x01e40000 0 0x7000>, 2748 <0 0x01e47000 0 0x2000>, 2749 <0 0x01e04000 0 0x2c000>; 2750 reg-names = "ipa-reg", 2751 "ipa-shared", 2752 "gsi"; 2753 2754 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2755 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2756 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2757 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2758 interrupt-names = "ipa", 2759 "gsi", 2760 "ipa-clock-query", 2761 "ipa-setup-ready"; 2762 2763 clocks = <&rpmhcc RPMH_IPA_CLK>; 2764 clock-names = "core"; 2765 2766 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2767 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2768 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2769 interconnect-names = "memory", 2770 "imem", 2771 "config"; 2772 2773 qcom,smem-states = <&ipa_smp2p_out 0>, 2774 <&ipa_smp2p_out 1>; 2775 qcom,smem-state-names = "ipa-clock-enabled-valid", 2776 "ipa-clock-enabled"; 2777 2778 status = "disabled"; 2779 }; 2780 2781 tcsr_mutex: hwlock@1f40000 { 2782 compatible = "qcom,tcsr-mutex"; 2783 reg = <0 0x01f40000 0 0x20000>; 2784 #hwlock-cells = <1>; 2785 }; 2786 2787 tcsr_regs_1: syscon@1f60000 { 2788 compatible = "qcom,sdm845-tcsr", "syscon"; 2789 reg = <0 0x01f60000 0 0x20000>; 2790 }; 2791 2792 tlmm: pinctrl@3400000 { 2793 compatible = "qcom,sdm845-pinctrl"; 2794 reg = <0 0x03400000 0 0xc00000>; 2795 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2796 gpio-controller; 2797 #gpio-cells = <2>; 2798 interrupt-controller; 2799 #interrupt-cells = <2>; 2800 gpio-ranges = <&tlmm 0 0 151>; 2801 wakeup-parent = <&pdc_intc>; 2802 2803 cci0_default: cci0-default-state { 2804 /* SDA, SCL */ 2805 pins = "gpio17", "gpio18"; 2806 function = "cci_i2c"; 2807 2808 bias-pull-up; 2809 drive-strength = <2>; /* 2 mA */ 2810 }; 2811 2812 cci0_sleep: cci0-sleep-state { 2813 /* SDA, SCL */ 2814 pins = "gpio17", "gpio18"; 2815 function = "cci_i2c"; 2816 2817 drive-strength = <2>; /* 2 mA */ 2818 bias-pull-down; 2819 }; 2820 2821 cci1_default: cci1-default-state { 2822 /* SDA, SCL */ 2823 pins = "gpio19", "gpio20"; 2824 function = "cci_i2c"; 2825 2826 bias-pull-up; 2827 drive-strength = <2>; /* 2 mA */ 2828 }; 2829 2830 cci1_sleep: cci1-sleep-state { 2831 /* SDA, SCL */ 2832 pins = "gpio19", "gpio20"; 2833 function = "cci_i2c"; 2834 2835 drive-strength = <2>; /* 2 mA */ 2836 bias-pull-down; 2837 }; 2838 2839 qspi_clk: qspi-clk-state { 2840 pins = "gpio95"; 2841 function = "qspi_clk"; 2842 }; 2843 2844 qspi_cs0: qspi-cs0-state { 2845 pins = "gpio90"; 2846 function = "qspi_cs"; 2847 }; 2848 2849 qspi_cs1: qspi-cs1-state { 2850 pins = "gpio89"; 2851 function = "qspi_cs"; 2852 }; 2853 2854 qspi_data0: qspi-data0-state { 2855 pins = "gpio91"; 2856 function = "qspi_data"; 2857 }; 2858 2859 qspi_data1: qspi-data1-state { 2860 pins = "gpio92"; 2861 function = "qspi_data"; 2862 }; 2863 2864 qspi_data23: qspi-data23-state { 2865 pins = "gpio93", "gpio94"; 2866 function = "qspi_data"; 2867 }; 2868 2869 qup_i2c0_default: qup-i2c0-default-state { 2870 pins = "gpio0", "gpio1"; 2871 function = "qup0"; 2872 }; 2873 2874 qup_i2c1_default: qup-i2c1-default-state { 2875 pins = "gpio17", "gpio18"; 2876 function = "qup1"; 2877 }; 2878 2879 qup_i2c2_default: qup-i2c2-default-state { 2880 pins = "gpio27", "gpio28"; 2881 function = "qup2"; 2882 }; 2883 2884 qup_i2c3_default: qup-i2c3-default-state { 2885 pins = "gpio41", "gpio42"; 2886 function = "qup3"; 2887 }; 2888 2889 qup_i2c4_default: qup-i2c4-default-state { 2890 pins = "gpio89", "gpio90"; 2891 function = "qup4"; 2892 }; 2893 2894 qup_i2c5_default: qup-i2c5-default-state { 2895 pins = "gpio85", "gpio86"; 2896 function = "qup5"; 2897 }; 2898 2899 qup_i2c6_default: qup-i2c6-default-state { 2900 pins = "gpio45", "gpio46"; 2901 function = "qup6"; 2902 }; 2903 2904 qup_i2c7_default: qup-i2c7-default-state { 2905 pins = "gpio93", "gpio94"; 2906 function = "qup7"; 2907 }; 2908 2909 qup_i2c8_default: qup-i2c8-default-state { 2910 pins = "gpio65", "gpio66"; 2911 function = "qup8"; 2912 }; 2913 2914 qup_i2c9_default: qup-i2c9-default-state { 2915 pins = "gpio6", "gpio7"; 2916 function = "qup9"; 2917 }; 2918 2919 qup_i2c10_default: qup-i2c10-default-state { 2920 pins = "gpio55", "gpio56"; 2921 function = "qup10"; 2922 }; 2923 2924 qup_i2c11_default: qup-i2c11-default-state { 2925 pins = "gpio31", "gpio32"; 2926 function = "qup11"; 2927 }; 2928 2929 qup_i2c12_default: qup-i2c12-default-state { 2930 pins = "gpio49", "gpio50"; 2931 function = "qup12"; 2932 }; 2933 2934 qup_i2c13_default: qup-i2c13-default-state { 2935 pins = "gpio105", "gpio106"; 2936 function = "qup13"; 2937 }; 2938 2939 qup_i2c14_default: qup-i2c14-default-state { 2940 pins = "gpio33", "gpio34"; 2941 function = "qup14"; 2942 }; 2943 2944 qup_i2c15_default: qup-i2c15-default-state { 2945 pins = "gpio81", "gpio82"; 2946 function = "qup15"; 2947 }; 2948 2949 qup_spi0_default: qup-spi0-default-state { 2950 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2951 function = "qup0"; 2952 }; 2953 2954 qup_spi1_default: qup-spi1-default-state { 2955 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2956 function = "qup1"; 2957 }; 2958 2959 qup_spi2_default: qup-spi2-default-state { 2960 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2961 function = "qup2"; 2962 }; 2963 2964 qup_spi3_default: qup-spi3-default-state { 2965 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2966 function = "qup3"; 2967 }; 2968 2969 qup_spi4_default: qup-spi4-default-state { 2970 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2971 function = "qup4"; 2972 }; 2973 2974 qup_spi5_default: qup-spi5-default-state { 2975 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2976 function = "qup5"; 2977 }; 2978 2979 qup_spi6_default: qup-spi6-default-state { 2980 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2981 function = "qup6"; 2982 }; 2983 2984 qup_spi7_default: qup-spi7-default-state { 2985 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2986 function = "qup7"; 2987 }; 2988 2989 qup_spi8_default: qup-spi8-default-state { 2990 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2991 function = "qup8"; 2992 }; 2993 2994 qup_spi9_default: qup-spi9-default-state { 2995 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 2996 function = "qup9"; 2997 }; 2998 2999 qup_spi10_default: qup-spi10-default-state { 3000 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 3001 function = "qup10"; 3002 }; 3003 3004 qup_spi11_default: qup-spi11-default-state { 3005 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 3006 function = "qup11"; 3007 }; 3008 3009 qup_spi12_default: qup-spi12-default-state { 3010 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 3011 function = "qup12"; 3012 }; 3013 3014 qup_spi13_default: qup-spi13-default-state { 3015 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 3016 function = "qup13"; 3017 }; 3018 3019 qup_spi14_default: qup-spi14-default-state { 3020 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 3021 function = "qup14"; 3022 }; 3023 3024 qup_spi15_default: qup-spi15-default-state { 3025 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 3026 function = "qup15"; 3027 }; 3028 3029 qup_uart0_default: qup-uart0-default-state { 3030 qup_uart0_tx: tx-pins { 3031 pins = "gpio2"; 3032 function = "qup0"; 3033 }; 3034 3035 qup_uart0_rx: rx-pins { 3036 pins = "gpio3"; 3037 function = "qup0"; 3038 }; 3039 }; 3040 3041 qup_uart1_default: qup-uart1-default-state { 3042 qup_uart1_tx: tx-pins { 3043 pins = "gpio19"; 3044 function = "qup1"; 3045 }; 3046 3047 qup_uart1_rx: rx-pins { 3048 pins = "gpio20"; 3049 function = "qup1"; 3050 }; 3051 }; 3052 3053 qup_uart2_default: qup-uart2-default-state { 3054 qup_uart2_tx: tx-pins { 3055 pins = "gpio29"; 3056 function = "qup2"; 3057 }; 3058 3059 qup_uart2_rx: rx-pins { 3060 pins = "gpio30"; 3061 function = "qup2"; 3062 }; 3063 }; 3064 3065 qup_uart3_default: qup-uart3-default-state { 3066 qup_uart3_tx: tx-pins { 3067 pins = "gpio43"; 3068 function = "qup3"; 3069 }; 3070 3071 qup_uart3_rx: rx-pins { 3072 pins = "gpio44"; 3073 function = "qup3"; 3074 }; 3075 }; 3076 3077 qup_uart3_4pin: qup-uart3-4pin-state { 3078 qup_uart3_4pin_cts: cts-pins { 3079 pins = "gpio41"; 3080 function = "qup3"; 3081 }; 3082 3083 qup_uart3_4pin_rts_tx: rts-tx-pins { 3084 pins = "gpio42", "gpio43"; 3085 function = "qup3"; 3086 }; 3087 3088 qup_uart3_4pin_rx: rx-pins { 3089 pins = "gpio44"; 3090 function = "qup3"; 3091 }; 3092 }; 3093 3094 qup_uart4_default: qup-uart4-default-state { 3095 qup_uart4_tx: tx-pins { 3096 pins = "gpio91"; 3097 function = "qup4"; 3098 }; 3099 3100 qup_uart4_rx: rx-pins { 3101 pins = "gpio92"; 3102 function = "qup4"; 3103 }; 3104 }; 3105 3106 qup_uart5_default: qup-uart5-default-state { 3107 qup_uart5_tx: tx-pins { 3108 pins = "gpio87"; 3109 function = "qup5"; 3110 }; 3111 3112 qup_uart5_rx: rx-pins { 3113 pins = "gpio88"; 3114 function = "qup5"; 3115 }; 3116 }; 3117 3118 qup_uart6_default: qup-uart6-default-state { 3119 qup_uart6_tx: tx-pins { 3120 pins = "gpio47"; 3121 function = "qup6"; 3122 }; 3123 3124 qup_uart6_rx: rx-pins { 3125 pins = "gpio48"; 3126 function = "qup6"; 3127 }; 3128 }; 3129 3130 qup_uart6_4pin: qup-uart6-4pin-state { 3131 qup_uart6_4pin_cts: cts-pins { 3132 pins = "gpio45"; 3133 function = "qup6"; 3134 bias-pull-down; 3135 }; 3136 3137 qup_uart6_4pin_rts_tx: rts-tx-pins { 3138 pins = "gpio46", "gpio47"; 3139 function = "qup6"; 3140 drive-strength = <2>; 3141 bias-disable; 3142 }; 3143 3144 qup_uart6_4pin_rx: rx-pins { 3145 pins = "gpio48"; 3146 function = "qup6"; 3147 bias-pull-up; 3148 }; 3149 }; 3150 3151 qup_uart7_default: qup-uart7-default-state { 3152 qup_uart7_tx: tx-pins { 3153 pins = "gpio95"; 3154 function = "qup7"; 3155 }; 3156 3157 qup_uart7_rx: rx-pins { 3158 pins = "gpio96"; 3159 function = "qup7"; 3160 }; 3161 }; 3162 3163 qup_uart8_default: qup-uart8-default-state { 3164 qup_uart8_tx: tx-pins { 3165 pins = "gpio67"; 3166 function = "qup8"; 3167 }; 3168 3169 qup_uart8_rx: rx-pins { 3170 pins = "gpio68"; 3171 function = "qup8"; 3172 }; 3173 }; 3174 3175 qup_uart9_default: qup-uart9-default-state { 3176 qup_uart9_tx: tx-pins { 3177 pins = "gpio4"; 3178 function = "qup9"; 3179 }; 3180 3181 qup_uart9_rx: rx-pins { 3182 pins = "gpio5"; 3183 function = "qup9"; 3184 }; 3185 }; 3186 3187 qup_uart10_default: qup-uart10-default-state { 3188 qup_uart10_tx: tx-pins { 3189 pins = "gpio53"; 3190 function = "qup10"; 3191 }; 3192 3193 qup_uart10_rx: rx-pins { 3194 pins = "gpio54"; 3195 function = "qup10"; 3196 }; 3197 }; 3198 3199 qup_uart11_default: qup-uart11-default-state { 3200 qup_uart11_tx: tx-pins { 3201 pins = "gpio33"; 3202 function = "qup11"; 3203 }; 3204 3205 qup_uart11_rx: rx-pins { 3206 pins = "gpio34"; 3207 function = "qup11"; 3208 }; 3209 }; 3210 3211 qup_uart12_default: qup-uart12-default-state { 3212 qup_uart12_tx: tx-pins { 3213 pins = "gpio51"; 3214 function = "qup0"; 3215 }; 3216 3217 qup_uart12_rx: rx-pins { 3218 pins = "gpio52"; 3219 function = "qup0"; 3220 }; 3221 }; 3222 3223 qup_uart13_default: qup-uart13-default-state { 3224 qup_uart13_tx: tx-pins { 3225 pins = "gpio107"; 3226 function = "qup13"; 3227 }; 3228 3229 qup_uart13_rx: rx-pins { 3230 pins = "gpio108"; 3231 function = "qup13"; 3232 }; 3233 }; 3234 3235 qup_uart14_default: qup-uart14-default-state { 3236 qup_uart14_tx: tx-pins { 3237 pins = "gpio31"; 3238 function = "qup14"; 3239 }; 3240 3241 qup_uart14_rx: rx-pins { 3242 pins = "gpio32"; 3243 function = "qup14"; 3244 }; 3245 }; 3246 3247 qup_uart15_default: qup-uart15-default-state { 3248 qup_uart15_tx: tx-pins { 3249 pins = "gpio83"; 3250 function = "qup15"; 3251 }; 3252 3253 qup_uart15_rx: rx-pins { 3254 pins = "gpio84"; 3255 function = "qup15"; 3256 }; 3257 }; 3258 3259 quat_mi2s_sleep: quat-mi2s-sleep-state { 3260 pins = "gpio58", "gpio59"; 3261 function = "gpio"; 3262 drive-strength = <2>; 3263 bias-pull-down; 3264 }; 3265 3266 quat_mi2s_active: quat-mi2s-active-state { 3267 pins = "gpio58", "gpio59"; 3268 function = "qua_mi2s"; 3269 drive-strength = <8>; 3270 bias-disable; 3271 output-high; 3272 }; 3273 3274 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3275 pins = "gpio60"; 3276 function = "gpio"; 3277 drive-strength = <2>; 3278 bias-pull-down; 3279 }; 3280 3281 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3282 pins = "gpio60"; 3283 function = "qua_mi2s"; 3284 drive-strength = <8>; 3285 bias-disable; 3286 }; 3287 3288 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3289 pins = "gpio61"; 3290 function = "gpio"; 3291 drive-strength = <2>; 3292 bias-pull-down; 3293 }; 3294 3295 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3296 pins = "gpio61"; 3297 function = "qua_mi2s"; 3298 drive-strength = <8>; 3299 bias-disable; 3300 }; 3301 3302 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3303 pins = "gpio62"; 3304 function = "gpio"; 3305 drive-strength = <2>; 3306 bias-pull-down; 3307 }; 3308 3309 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3310 pins = "gpio62"; 3311 function = "qua_mi2s"; 3312 drive-strength = <8>; 3313 bias-disable; 3314 }; 3315 3316 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3317 pins = "gpio63"; 3318 function = "gpio"; 3319 drive-strength = <2>; 3320 bias-pull-down; 3321 }; 3322 3323 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3324 pins = "gpio63"; 3325 function = "qua_mi2s"; 3326 drive-strength = <8>; 3327 bias-disable; 3328 }; 3329 }; 3330 3331 mss_pil: remoteproc@4080000 { 3332 compatible = "qcom,sdm845-mss-pil"; 3333 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3334 reg-names = "qdsp6", "rmb"; 3335 3336 interrupts-extended = 3337 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3338 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3339 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3340 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3341 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3342 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3343 interrupt-names = "wdog", "fatal", "ready", 3344 "handover", "stop-ack", 3345 "shutdown-ack"; 3346 3347 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3348 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3349 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3350 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3351 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3352 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3353 <&gcc GCC_PRNG_AHB_CLK>, 3354 <&rpmhcc RPMH_CXO_CLK>; 3355 clock-names = "iface", "bus", "mem", "gpll0_mss", 3356 "snoc_axi", "mnoc_axi", "prng", "xo"; 3357 3358 qcom,qmp = <&aoss_qmp>; 3359 3360 qcom,smem-states = <&modem_smp2p_out 0>; 3361 qcom,smem-state-names = "stop"; 3362 3363 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3364 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3365 reset-names = "mss_restart", "pdc_reset"; 3366 3367 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3368 3369 power-domains = <&rpmhpd SDM845_CX>, 3370 <&rpmhpd SDM845_MX>, 3371 <&rpmhpd SDM845_MSS>; 3372 power-domain-names = "cx", "mx", "mss"; 3373 3374 status = "disabled"; 3375 3376 mba { 3377 memory-region = <&mba_region>; 3378 }; 3379 3380 mpss { 3381 memory-region = <&mpss_region>; 3382 }; 3383 3384 metadata { 3385 memory-region = <&mdata_mem>; 3386 }; 3387 3388 glink-edge { 3389 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3390 label = "modem"; 3391 qcom,remote-pid = <1>; 3392 mboxes = <&apss_shared 12>; 3393 }; 3394 }; 3395 3396 gpucc: clock-controller@5090000 { 3397 compatible = "qcom,sdm845-gpucc"; 3398 reg = <0 0x05090000 0 0x9000>; 3399 #clock-cells = <1>; 3400 #reset-cells = <1>; 3401 #power-domain-cells = <1>; 3402 clocks = <&rpmhcc RPMH_CXO_CLK>, 3403 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3404 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3405 clock-names = "bi_tcxo", 3406 "gcc_gpu_gpll0_clk_src", 3407 "gcc_gpu_gpll0_div_clk_src"; 3408 }; 3409 3410 slpi_pas: remoteproc@5c00000 { 3411 compatible = "qcom,sdm845-slpi-pas"; 3412 reg = <0 0x5c00000 0 0x4000>; 3413 3414 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3415 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3416 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3417 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3418 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3419 interrupt-names = "wdog", "fatal", "ready", 3420 "handover", "stop-ack"; 3421 3422 clocks = <&rpmhcc RPMH_CXO_CLK>; 3423 clock-names = "xo"; 3424 3425 qcom,qmp = <&aoss_qmp>; 3426 3427 power-domains = <&rpmhpd SDM845_LCX>, 3428 <&rpmhpd SDM845_LMX>; 3429 power-domain-names = "lcx", "lmx"; 3430 3431 memory-region = <&slpi_mem>; 3432 3433 qcom,smem-states = <&slpi_smp2p_out 0>; 3434 qcom,smem-state-names = "stop"; 3435 3436 status = "disabled"; 3437 3438 glink-edge { 3439 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3440 label = "dsps"; 3441 qcom,remote-pid = <3>; 3442 mboxes = <&apss_shared 24>; 3443 3444 fastrpc { 3445 compatible = "qcom,fastrpc"; 3446 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3447 label = "sdsp"; 3448 qcom,non-secure-domain; 3449 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3450 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3451 memory-region = <&fastrpc_mem>; 3452 #address-cells = <1>; 3453 #size-cells = <0>; 3454 3455 compute-cb@0 { 3456 compatible = "qcom,fastrpc-compute-cb"; 3457 reg = <0>; 3458 }; 3459 }; 3460 }; 3461 }; 3462 3463 stm@6002000 { 3464 compatible = "arm,coresight-stm", "arm,primecell"; 3465 reg = <0 0x06002000 0 0x1000>, 3466 <0 0x16280000 0 0x180000>; 3467 reg-names = "stm-base", "stm-stimulus-base"; 3468 3469 clocks = <&aoss_qmp>; 3470 clock-names = "apb_pclk"; 3471 3472 out-ports { 3473 port { 3474 stm_out: endpoint { 3475 remote-endpoint = 3476 <&funnel0_in7>; 3477 }; 3478 }; 3479 }; 3480 }; 3481 3482 funnel@6041000 { 3483 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3484 reg = <0 0x06041000 0 0x1000>; 3485 3486 clocks = <&aoss_qmp>; 3487 clock-names = "apb_pclk"; 3488 3489 out-ports { 3490 port { 3491 funnel0_out: endpoint { 3492 remote-endpoint = 3493 <&merge_funnel_in0>; 3494 }; 3495 }; 3496 }; 3497 3498 in-ports { 3499 #address-cells = <1>; 3500 #size-cells = <0>; 3501 3502 port@7 { 3503 reg = <7>; 3504 funnel0_in7: endpoint { 3505 remote-endpoint = <&stm_out>; 3506 }; 3507 }; 3508 }; 3509 }; 3510 3511 funnel@6043000 { 3512 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3513 reg = <0 0x06043000 0 0x1000>; 3514 3515 clocks = <&aoss_qmp>; 3516 clock-names = "apb_pclk"; 3517 3518 out-ports { 3519 port { 3520 funnel2_out: endpoint { 3521 remote-endpoint = 3522 <&merge_funnel_in2>; 3523 }; 3524 }; 3525 }; 3526 3527 in-ports { 3528 #address-cells = <1>; 3529 #size-cells = <0>; 3530 3531 port@5 { 3532 reg = <5>; 3533 funnel2_in5: endpoint { 3534 remote-endpoint = 3535 <&apss_merge_funnel_out>; 3536 }; 3537 }; 3538 }; 3539 }; 3540 3541 funnel@6045000 { 3542 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3543 reg = <0 0x06045000 0 0x1000>; 3544 3545 clocks = <&aoss_qmp>; 3546 clock-names = "apb_pclk"; 3547 3548 out-ports { 3549 port { 3550 merge_funnel_out: endpoint { 3551 remote-endpoint = <&etf_in>; 3552 }; 3553 }; 3554 }; 3555 3556 in-ports { 3557 #address-cells = <1>; 3558 #size-cells = <0>; 3559 3560 port@0 { 3561 reg = <0>; 3562 merge_funnel_in0: endpoint { 3563 remote-endpoint = 3564 <&funnel0_out>; 3565 }; 3566 }; 3567 3568 port@2 { 3569 reg = <2>; 3570 merge_funnel_in2: endpoint { 3571 remote-endpoint = 3572 <&funnel2_out>; 3573 }; 3574 }; 3575 }; 3576 }; 3577 3578 replicator@6046000 { 3579 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3580 reg = <0 0x06046000 0 0x1000>; 3581 3582 clocks = <&aoss_qmp>; 3583 clock-names = "apb_pclk"; 3584 3585 out-ports { 3586 port { 3587 replicator_out: endpoint { 3588 remote-endpoint = <&etr_in>; 3589 }; 3590 }; 3591 }; 3592 3593 in-ports { 3594 port { 3595 replicator_in: endpoint { 3596 remote-endpoint = <&etf_out>; 3597 }; 3598 }; 3599 }; 3600 }; 3601 3602 etf@6047000 { 3603 compatible = "arm,coresight-tmc", "arm,primecell"; 3604 reg = <0 0x06047000 0 0x1000>; 3605 3606 clocks = <&aoss_qmp>; 3607 clock-names = "apb_pclk"; 3608 3609 out-ports { 3610 port { 3611 etf_out: endpoint { 3612 remote-endpoint = 3613 <&replicator_in>; 3614 }; 3615 }; 3616 }; 3617 3618 in-ports { 3619 3620 port { 3621 etf_in: endpoint { 3622 remote-endpoint = 3623 <&merge_funnel_out>; 3624 }; 3625 }; 3626 }; 3627 }; 3628 3629 etr@6048000 { 3630 compatible = "arm,coresight-tmc", "arm,primecell"; 3631 reg = <0 0x06048000 0 0x1000>; 3632 3633 clocks = <&aoss_qmp>; 3634 clock-names = "apb_pclk"; 3635 arm,scatter-gather; 3636 3637 in-ports { 3638 port { 3639 etr_in: endpoint { 3640 remote-endpoint = 3641 <&replicator_out>; 3642 }; 3643 }; 3644 }; 3645 }; 3646 3647 etm@7040000 { 3648 compatible = "arm,coresight-etm4x", "arm,primecell"; 3649 reg = <0 0x07040000 0 0x1000>; 3650 3651 cpu = <&cpu0>; 3652 3653 clocks = <&aoss_qmp>; 3654 clock-names = "apb_pclk"; 3655 arm,coresight-loses-context-with-cpu; 3656 3657 out-ports { 3658 port { 3659 etm0_out: endpoint { 3660 remote-endpoint = 3661 <&apss_funnel_in0>; 3662 }; 3663 }; 3664 }; 3665 }; 3666 3667 etm@7140000 { 3668 compatible = "arm,coresight-etm4x", "arm,primecell"; 3669 reg = <0 0x07140000 0 0x1000>; 3670 3671 cpu = <&cpu1>; 3672 3673 clocks = <&aoss_qmp>; 3674 clock-names = "apb_pclk"; 3675 arm,coresight-loses-context-with-cpu; 3676 3677 out-ports { 3678 port { 3679 etm1_out: endpoint { 3680 remote-endpoint = 3681 <&apss_funnel_in1>; 3682 }; 3683 }; 3684 }; 3685 }; 3686 3687 etm@7240000 { 3688 compatible = "arm,coresight-etm4x", "arm,primecell"; 3689 reg = <0 0x07240000 0 0x1000>; 3690 3691 cpu = <&cpu2>; 3692 3693 clocks = <&aoss_qmp>; 3694 clock-names = "apb_pclk"; 3695 arm,coresight-loses-context-with-cpu; 3696 3697 out-ports { 3698 port { 3699 etm2_out: endpoint { 3700 remote-endpoint = 3701 <&apss_funnel_in2>; 3702 }; 3703 }; 3704 }; 3705 }; 3706 3707 etm@7340000 { 3708 compatible = "arm,coresight-etm4x", "arm,primecell"; 3709 reg = <0 0x07340000 0 0x1000>; 3710 3711 cpu = <&cpu3>; 3712 3713 clocks = <&aoss_qmp>; 3714 clock-names = "apb_pclk"; 3715 arm,coresight-loses-context-with-cpu; 3716 3717 out-ports { 3718 port { 3719 etm3_out: endpoint { 3720 remote-endpoint = 3721 <&apss_funnel_in3>; 3722 }; 3723 }; 3724 }; 3725 }; 3726 3727 etm@7440000 { 3728 compatible = "arm,coresight-etm4x", "arm,primecell"; 3729 reg = <0 0x07440000 0 0x1000>; 3730 3731 cpu = <&cpu4>; 3732 3733 clocks = <&aoss_qmp>; 3734 clock-names = "apb_pclk"; 3735 arm,coresight-loses-context-with-cpu; 3736 3737 out-ports { 3738 port { 3739 etm4_out: endpoint { 3740 remote-endpoint = 3741 <&apss_funnel_in4>; 3742 }; 3743 }; 3744 }; 3745 }; 3746 3747 etm@7540000 { 3748 compatible = "arm,coresight-etm4x", "arm,primecell"; 3749 reg = <0 0x07540000 0 0x1000>; 3750 3751 cpu = <&cpu5>; 3752 3753 clocks = <&aoss_qmp>; 3754 clock-names = "apb_pclk"; 3755 arm,coresight-loses-context-with-cpu; 3756 3757 out-ports { 3758 port { 3759 etm5_out: endpoint { 3760 remote-endpoint = 3761 <&apss_funnel_in5>; 3762 }; 3763 }; 3764 }; 3765 }; 3766 3767 etm@7640000 { 3768 compatible = "arm,coresight-etm4x", "arm,primecell"; 3769 reg = <0 0x07640000 0 0x1000>; 3770 3771 cpu = <&cpu6>; 3772 3773 clocks = <&aoss_qmp>; 3774 clock-names = "apb_pclk"; 3775 arm,coresight-loses-context-with-cpu; 3776 3777 out-ports { 3778 port { 3779 etm6_out: endpoint { 3780 remote-endpoint = 3781 <&apss_funnel_in6>; 3782 }; 3783 }; 3784 }; 3785 }; 3786 3787 etm@7740000 { 3788 compatible = "arm,coresight-etm4x", "arm,primecell"; 3789 reg = <0 0x07740000 0 0x1000>; 3790 3791 cpu = <&cpu7>; 3792 3793 clocks = <&aoss_qmp>; 3794 clock-names = "apb_pclk"; 3795 arm,coresight-loses-context-with-cpu; 3796 3797 out-ports { 3798 port { 3799 etm7_out: endpoint { 3800 remote-endpoint = 3801 <&apss_funnel_in7>; 3802 }; 3803 }; 3804 }; 3805 }; 3806 3807 funnel@7800000 { /* APSS Funnel */ 3808 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3809 reg = <0 0x07800000 0 0x1000>; 3810 3811 clocks = <&aoss_qmp>; 3812 clock-names = "apb_pclk"; 3813 3814 out-ports { 3815 port { 3816 apss_funnel_out: endpoint { 3817 remote-endpoint = 3818 <&apss_merge_funnel_in>; 3819 }; 3820 }; 3821 }; 3822 3823 in-ports { 3824 #address-cells = <1>; 3825 #size-cells = <0>; 3826 3827 port@0 { 3828 reg = <0>; 3829 apss_funnel_in0: endpoint { 3830 remote-endpoint = 3831 <&etm0_out>; 3832 }; 3833 }; 3834 3835 port@1 { 3836 reg = <1>; 3837 apss_funnel_in1: endpoint { 3838 remote-endpoint = 3839 <&etm1_out>; 3840 }; 3841 }; 3842 3843 port@2 { 3844 reg = <2>; 3845 apss_funnel_in2: endpoint { 3846 remote-endpoint = 3847 <&etm2_out>; 3848 }; 3849 }; 3850 3851 port@3 { 3852 reg = <3>; 3853 apss_funnel_in3: endpoint { 3854 remote-endpoint = 3855 <&etm3_out>; 3856 }; 3857 }; 3858 3859 port@4 { 3860 reg = <4>; 3861 apss_funnel_in4: endpoint { 3862 remote-endpoint = 3863 <&etm4_out>; 3864 }; 3865 }; 3866 3867 port@5 { 3868 reg = <5>; 3869 apss_funnel_in5: endpoint { 3870 remote-endpoint = 3871 <&etm5_out>; 3872 }; 3873 }; 3874 3875 port@6 { 3876 reg = <6>; 3877 apss_funnel_in6: endpoint { 3878 remote-endpoint = 3879 <&etm6_out>; 3880 }; 3881 }; 3882 3883 port@7 { 3884 reg = <7>; 3885 apss_funnel_in7: endpoint { 3886 remote-endpoint = 3887 <&etm7_out>; 3888 }; 3889 }; 3890 }; 3891 }; 3892 3893 funnel@7810000 { 3894 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3895 reg = <0 0x07810000 0 0x1000>; 3896 3897 clocks = <&aoss_qmp>; 3898 clock-names = "apb_pclk"; 3899 3900 out-ports { 3901 port { 3902 apss_merge_funnel_out: endpoint { 3903 remote-endpoint = 3904 <&funnel2_in5>; 3905 }; 3906 }; 3907 }; 3908 3909 in-ports { 3910 port { 3911 apss_merge_funnel_in: endpoint { 3912 remote-endpoint = 3913 <&apss_funnel_out>; 3914 }; 3915 }; 3916 }; 3917 }; 3918 3919 sdhc_2: mmc@8804000 { 3920 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3921 reg = <0 0x08804000 0 0x1000>; 3922 3923 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3925 interrupt-names = "hc_irq", "pwr_irq"; 3926 3927 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3928 <&gcc GCC_SDCC2_APPS_CLK>, 3929 <&rpmhcc RPMH_CXO_CLK>; 3930 clock-names = "iface", "core", "xo"; 3931 iommus = <&apps_smmu 0xa0 0xf>; 3932 power-domains = <&rpmhpd SDM845_CX>; 3933 operating-points-v2 = <&sdhc2_opp_table>; 3934 3935 status = "disabled"; 3936 3937 sdhc2_opp_table: opp-table { 3938 compatible = "operating-points-v2"; 3939 3940 opp-9600000 { 3941 opp-hz = /bits/ 64 <9600000>; 3942 required-opps = <&rpmhpd_opp_min_svs>; 3943 }; 3944 3945 opp-19200000 { 3946 opp-hz = /bits/ 64 <19200000>; 3947 required-opps = <&rpmhpd_opp_low_svs>; 3948 }; 3949 3950 opp-100000000 { 3951 opp-hz = /bits/ 64 <100000000>; 3952 required-opps = <&rpmhpd_opp_svs>; 3953 }; 3954 3955 opp-201500000 { 3956 opp-hz = /bits/ 64 <201500000>; 3957 required-opps = <&rpmhpd_opp_svs_l1>; 3958 }; 3959 }; 3960 }; 3961 3962 qspi: spi@88df000 { 3963 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3964 reg = <0 0x088df000 0 0x600>; 3965 iommus = <&apps_smmu 0x160 0x0>; 3966 #address-cells = <1>; 3967 #size-cells = <0>; 3968 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3969 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3970 <&gcc GCC_QSPI_CORE_CLK>; 3971 clock-names = "iface", "core"; 3972 power-domains = <&rpmhpd SDM845_CX>; 3973 operating-points-v2 = <&qspi_opp_table>; 3974 status = "disabled"; 3975 }; 3976 3977 slim: slim-ngd@171c0000 { 3978 compatible = "qcom,slim-ngd-v2.1.0"; 3979 reg = <0 0x171c0000 0 0x2c000>; 3980 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3981 3982 dmas = <&slimbam 3>, <&slimbam 4>; 3983 dma-names = "rx", "tx"; 3984 3985 iommus = <&apps_smmu 0x1806 0x0>; 3986 #address-cells = <1>; 3987 #size-cells = <0>; 3988 status = "disabled"; 3989 }; 3990 3991 lmh_cluster1: lmh@17d70800 { 3992 compatible = "qcom,sdm845-lmh"; 3993 reg = <0 0x17d70800 0 0x400>; 3994 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3995 cpus = <&cpu4>; 3996 qcom,lmh-temp-arm-millicelsius = <65000>; 3997 qcom,lmh-temp-low-millicelsius = <94500>; 3998 qcom,lmh-temp-high-millicelsius = <95000>; 3999 interrupt-controller; 4000 #interrupt-cells = <1>; 4001 }; 4002 4003 lmh_cluster0: lmh@17d78800 { 4004 compatible = "qcom,sdm845-lmh"; 4005 reg = <0 0x17d78800 0 0x400>; 4006 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4007 cpus = <&cpu0>; 4008 qcom,lmh-temp-arm-millicelsius = <65000>; 4009 qcom,lmh-temp-low-millicelsius = <94500>; 4010 qcom,lmh-temp-high-millicelsius = <95000>; 4011 interrupt-controller; 4012 #interrupt-cells = <1>; 4013 }; 4014 4015 usb_1_hsphy: phy@88e2000 { 4016 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 4017 reg = <0 0x088e2000 0 0x400>; 4018 status = "disabled"; 4019 #phy-cells = <0>; 4020 4021 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4022 <&rpmhcc RPMH_CXO_CLK>; 4023 clock-names = "cfg_ahb", "ref"; 4024 4025 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4026 4027 nvmem-cells = <&qusb2p_hstx_trim>; 4028 }; 4029 4030 usb_2_hsphy: phy@88e3000 { 4031 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 4032 reg = <0 0x088e3000 0 0x400>; 4033 status = "disabled"; 4034 #phy-cells = <0>; 4035 4036 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4037 <&rpmhcc RPMH_CXO_CLK>; 4038 clock-names = "cfg_ahb", "ref"; 4039 4040 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4041 4042 nvmem-cells = <&qusb2s_hstx_trim>; 4043 }; 4044 4045 usb_1_qmpphy: phy@88e8000 { 4046 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 4047 reg = <0 0x088e8000 0 0x3000>; 4048 status = "disabled"; 4049 4050 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4051 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4052 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4053 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 4054 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 4055 clock-names = "aux", 4056 "ref", 4057 "com_aux", 4058 "usb3_pipe", 4059 "cfg_ahb"; 4060 4061 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4062 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4063 reset-names = "phy", "common"; 4064 4065 #clock-cells = <1>; 4066 #phy-cells = <1>; 4067 orientation-switch; 4068 4069 ports { 4070 #address-cells = <1>; 4071 #size-cells = <0>; 4072 4073 port@0 { 4074 reg = <0>; 4075 4076 usb_1_qmpphy_out: endpoint { 4077 }; 4078 }; 4079 4080 port@1 { 4081 reg = <1>; 4082 4083 usb_1_qmpphy_usb_ss_in: endpoint { 4084 remote-endpoint = <&usb_1_dwc3_ss>; 4085 }; 4086 }; 4087 4088 port@2 { 4089 reg = <2>; 4090 4091 usb_1_qmpphy_dp_in: endpoint { 4092 remote-endpoint = <&dp_out>; 4093 }; 4094 }; 4095 }; 4096 }; 4097 4098 usb_2_qmpphy: phy@88eb000 { 4099 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4100 reg = <0 0x088eb000 0 0x1000>; 4101 4102 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4103 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4104 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4105 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4106 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4107 clock-names = "aux", 4108 "cfg_ahb", 4109 "ref", 4110 "com_aux", 4111 "pipe"; 4112 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4113 #clock-cells = <0>; 4114 #phy-cells = <0>; 4115 4116 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4117 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4118 reset-names = "phy", 4119 "phy_phy"; 4120 4121 status = "disabled"; 4122 }; 4123 4124 usb_1: usb@a6f8800 { 4125 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4126 reg = <0 0x0a6f8800 0 0x400>; 4127 status = "disabled"; 4128 #address-cells = <2>; 4129 #size-cells = <2>; 4130 ranges; 4131 dma-ranges; 4132 4133 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4134 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4135 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4136 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4137 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4138 clock-names = "cfg_noc", 4139 "core", 4140 "iface", 4141 "sleep", 4142 "mock_utmi"; 4143 4144 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4145 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4146 assigned-clock-rates = <19200000>, <150000000>; 4147 4148 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4149 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4150 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, 4151 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 4152 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; 4153 interrupt-names = "pwr_event", 4154 "hs_phy_irq", 4155 "dp_hs_phy_irq", 4156 "dm_hs_phy_irq", 4157 "ss_phy_irq"; 4158 4159 power-domains = <&gcc USB30_PRIM_GDSC>; 4160 4161 resets = <&gcc GCC_USB30_PRIM_BCR>; 4162 4163 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4164 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4165 interconnect-names = "usb-ddr", "apps-usb"; 4166 4167 usb_1_dwc3: usb@a600000 { 4168 compatible = "snps,dwc3"; 4169 reg = <0 0x0a600000 0 0xcd00>; 4170 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4171 iommus = <&apps_smmu 0x740 0>; 4172 snps,dis_u2_susphy_quirk; 4173 snps,dis_enblslpm_quirk; 4174 snps,parkmode-disable-ss-quirk; 4175 snps,dis-u1-entry-quirk; 4176 snps,dis-u2-entry-quirk; 4177 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4178 phy-names = "usb2-phy", "usb3-phy"; 4179 4180 ports { 4181 #address-cells = <1>; 4182 #size-cells = <0>; 4183 4184 port@0 { 4185 reg = <0>; 4186 4187 usb_1_dwc3_hs: endpoint { 4188 }; 4189 }; 4190 4191 port@1 { 4192 reg = <1>; 4193 4194 usb_1_dwc3_ss: endpoint { 4195 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4196 }; 4197 }; 4198 }; 4199 }; 4200 }; 4201 4202 usb_2: usb@a8f8800 { 4203 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4204 reg = <0 0x0a8f8800 0 0x400>; 4205 status = "disabled"; 4206 #address-cells = <2>; 4207 #size-cells = <2>; 4208 ranges; 4209 dma-ranges; 4210 4211 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4212 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4213 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4214 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4215 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4216 clock-names = "cfg_noc", 4217 "core", 4218 "iface", 4219 "sleep", 4220 "mock_utmi"; 4221 4222 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4223 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4224 assigned-clock-rates = <19200000>, <150000000>; 4225 4226 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4227 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4228 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, 4229 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 4230 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; 4231 interrupt-names = "pwr_event", 4232 "hs_phy_irq", 4233 "dp_hs_phy_irq", 4234 "dm_hs_phy_irq", 4235 "ss_phy_irq"; 4236 4237 power-domains = <&gcc USB30_SEC_GDSC>; 4238 4239 resets = <&gcc GCC_USB30_SEC_BCR>; 4240 4241 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4242 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4243 interconnect-names = "usb-ddr", "apps-usb"; 4244 4245 usb_2_dwc3: usb@a800000 { 4246 compatible = "snps,dwc3"; 4247 reg = <0 0x0a800000 0 0xcd00>; 4248 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4249 iommus = <&apps_smmu 0x760 0>; 4250 snps,dis_u2_susphy_quirk; 4251 snps,dis_enblslpm_quirk; 4252 snps,parkmode-disable-ss-quirk; 4253 snps,dis-u1-entry-quirk; 4254 snps,dis-u2-entry-quirk; 4255 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4256 phy-names = "usb2-phy", "usb3-phy"; 4257 }; 4258 }; 4259 4260 venus: video-codec@aa00000 { 4261 compatible = "qcom,sdm845-venus-v2"; 4262 reg = <0 0x0aa00000 0 0xff000>; 4263 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4264 power-domains = <&videocc VENUS_GDSC>, 4265 <&videocc VCODEC0_GDSC>, 4266 <&videocc VCODEC1_GDSC>, 4267 <&rpmhpd SDM845_CX>; 4268 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4269 operating-points-v2 = <&venus_opp_table>; 4270 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4271 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4272 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4273 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4274 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4275 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4276 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4277 clock-names = "core", "iface", "bus", 4278 "vcodec0_core", "vcodec0_bus", 4279 "vcodec1_core", "vcodec1_bus"; 4280 iommus = <&apps_smmu 0x10a0 0x8>, 4281 <&apps_smmu 0x10b0 0x0>; 4282 memory-region = <&venus_mem>; 4283 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4284 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4285 interconnect-names = "video-mem", "cpu-cfg"; 4286 4287 status = "disabled"; 4288 4289 video-core0 { 4290 compatible = "venus-decoder"; 4291 }; 4292 4293 video-core1 { 4294 compatible = "venus-encoder"; 4295 }; 4296 4297 venus_opp_table: opp-table { 4298 compatible = "operating-points-v2"; 4299 4300 opp-100000000 { 4301 opp-hz = /bits/ 64 <100000000>; 4302 required-opps = <&rpmhpd_opp_min_svs>; 4303 }; 4304 4305 opp-200000000 { 4306 opp-hz = /bits/ 64 <200000000>; 4307 required-opps = <&rpmhpd_opp_low_svs>; 4308 }; 4309 4310 opp-320000000 { 4311 opp-hz = /bits/ 64 <320000000>; 4312 required-opps = <&rpmhpd_opp_svs>; 4313 }; 4314 4315 opp-380000000 { 4316 opp-hz = /bits/ 64 <380000000>; 4317 required-opps = <&rpmhpd_opp_svs_l1>; 4318 }; 4319 4320 opp-444000000 { 4321 opp-hz = /bits/ 64 <444000000>; 4322 required-opps = <&rpmhpd_opp_nom>; 4323 }; 4324 4325 opp-533000097 { 4326 opp-hz = /bits/ 64 <533000097>; 4327 required-opps = <&rpmhpd_opp_turbo>; 4328 }; 4329 }; 4330 }; 4331 4332 videocc: clock-controller@ab00000 { 4333 compatible = "qcom,sdm845-videocc"; 4334 reg = <0 0x0ab00000 0 0x10000>; 4335 clocks = <&rpmhcc RPMH_CXO_CLK>; 4336 clock-names = "bi_tcxo"; 4337 #clock-cells = <1>; 4338 #power-domain-cells = <1>; 4339 #reset-cells = <1>; 4340 }; 4341 4342 camss: camss@acb3000 { 4343 compatible = "qcom,sdm845-camss"; 4344 4345 reg = <0 0x0acb3000 0 0x1000>, 4346 <0 0x0acba000 0 0x1000>, 4347 <0 0x0acc8000 0 0x1000>, 4348 <0 0x0ac65000 0 0x1000>, 4349 <0 0x0ac66000 0 0x1000>, 4350 <0 0x0ac67000 0 0x1000>, 4351 <0 0x0ac68000 0 0x1000>, 4352 <0 0x0acaf000 0 0x4000>, 4353 <0 0x0acb6000 0 0x4000>, 4354 <0 0x0acc4000 0 0x4000>; 4355 reg-names = "csid0", 4356 "csid1", 4357 "csid2", 4358 "csiphy0", 4359 "csiphy1", 4360 "csiphy2", 4361 "csiphy3", 4362 "vfe0", 4363 "vfe1", 4364 "vfe_lite"; 4365 4366 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4367 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4368 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4369 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4370 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4371 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4372 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4373 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4374 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4375 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; 4376 interrupt-names = "csid0", 4377 "csid1", 4378 "csid2", 4379 "csiphy0", 4380 "csiphy1", 4381 "csiphy2", 4382 "csiphy3", 4383 "vfe0", 4384 "vfe1", 4385 "vfe_lite"; 4386 4387 power-domains = <&clock_camcc IFE_0_GDSC>, 4388 <&clock_camcc IFE_1_GDSC>, 4389 <&clock_camcc TITAN_TOP_GDSC>; 4390 4391 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4392 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4393 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4394 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4395 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4396 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4397 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4398 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4399 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4400 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4401 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4402 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4403 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4404 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4405 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4406 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4407 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4408 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4409 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4410 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4411 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4412 <&gcc GCC_CAMERA_AHB_CLK>, 4413 <&gcc GCC_CAMERA_AXI_CLK>, 4414 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4415 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4416 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4417 <&clock_camcc CAM_CC_IFE_0_CLK>, 4418 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4419 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4420 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4421 <&clock_camcc CAM_CC_IFE_1_CLK>, 4422 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4423 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4424 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4425 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4426 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4427 clock-names = "camnoc_axi", 4428 "cpas_ahb", 4429 "cphy_rx_src", 4430 "csi0", 4431 "csi0_src", 4432 "csi1", 4433 "csi1_src", 4434 "csi2", 4435 "csi2_src", 4436 "csiphy0", 4437 "csiphy0_timer", 4438 "csiphy0_timer_src", 4439 "csiphy1", 4440 "csiphy1_timer", 4441 "csiphy1_timer_src", 4442 "csiphy2", 4443 "csiphy2_timer", 4444 "csiphy2_timer_src", 4445 "csiphy3", 4446 "csiphy3_timer", 4447 "csiphy3_timer_src", 4448 "gcc_camera_ahb", 4449 "gcc_camera_axi", 4450 "slow_ahb_src", 4451 "soc_ahb", 4452 "vfe0_axi", 4453 "vfe0", 4454 "vfe0_cphy_rx", 4455 "vfe0_src", 4456 "vfe1_axi", 4457 "vfe1", 4458 "vfe1_cphy_rx", 4459 "vfe1_src", 4460 "vfe_lite", 4461 "vfe_lite_cphy_rx", 4462 "vfe_lite_src"; 4463 4464 iommus = <&apps_smmu 0x0808 0x0>, 4465 <&apps_smmu 0x0810 0x8>, 4466 <&apps_smmu 0x0c08 0x0>, 4467 <&apps_smmu 0x0c10 0x8>; 4468 4469 status = "disabled"; 4470 4471 ports { 4472 #address-cells = <1>; 4473 #size-cells = <0>; 4474 4475 port@0 { 4476 reg = <0>; 4477 }; 4478 4479 port@1 { 4480 reg = <1>; 4481 }; 4482 4483 port@2 { 4484 reg = <2>; 4485 }; 4486 4487 port@3 { 4488 reg = <3>; 4489 }; 4490 }; 4491 }; 4492 4493 cci: cci@ac4a000 { 4494 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4495 #address-cells = <1>; 4496 #size-cells = <0>; 4497 4498 reg = <0 0x0ac4a000 0 0x4000>; 4499 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4500 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4501 4502 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4503 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4504 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4505 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4506 <&clock_camcc CAM_CC_CCI_CLK>, 4507 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4508 clock-names = "camnoc_axi", 4509 "soc_ahb", 4510 "slow_ahb_src", 4511 "cpas_ahb", 4512 "cci", 4513 "cci_src"; 4514 4515 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4516 <&clock_camcc CAM_CC_CCI_CLK>; 4517 assigned-clock-rates = <80000000>, <37500000>; 4518 4519 pinctrl-names = "default", "sleep"; 4520 pinctrl-0 = <&cci0_default &cci1_default>; 4521 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4522 4523 status = "disabled"; 4524 4525 cci_i2c0: i2c-bus@0 { 4526 reg = <0>; 4527 clock-frequency = <1000000>; 4528 #address-cells = <1>; 4529 #size-cells = <0>; 4530 }; 4531 4532 cci_i2c1: i2c-bus@1 { 4533 reg = <1>; 4534 clock-frequency = <1000000>; 4535 #address-cells = <1>; 4536 #size-cells = <0>; 4537 }; 4538 }; 4539 4540 clock_camcc: clock-controller@ad00000 { 4541 compatible = "qcom,sdm845-camcc"; 4542 reg = <0 0x0ad00000 0 0x10000>; 4543 #clock-cells = <1>; 4544 #reset-cells = <1>; 4545 #power-domain-cells = <1>; 4546 clocks = <&rpmhcc RPMH_CXO_CLK>; 4547 clock-names = "bi_tcxo"; 4548 }; 4549 4550 mdss: display-subsystem@ae00000 { 4551 compatible = "qcom,sdm845-mdss"; 4552 reg = <0 0x0ae00000 0 0x1000>; 4553 reg-names = "mdss"; 4554 4555 power-domains = <&dispcc MDSS_GDSC>; 4556 4557 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4558 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4559 clock-names = "iface", "core"; 4560 4561 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4562 interrupt-controller; 4563 #interrupt-cells = <1>; 4564 4565 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4566 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4567 interconnect-names = "mdp0-mem", "mdp1-mem"; 4568 4569 iommus = <&apps_smmu 0x880 0x8>, 4570 <&apps_smmu 0xc80 0x8>; 4571 4572 status = "disabled"; 4573 4574 #address-cells = <2>; 4575 #size-cells = <2>; 4576 ranges; 4577 4578 mdss_mdp: display-controller@ae01000 { 4579 compatible = "qcom,sdm845-dpu"; 4580 reg = <0 0x0ae01000 0 0x8f000>, 4581 <0 0x0aeb0000 0 0x3000>; 4582 reg-names = "mdp", "vbif"; 4583 4584 clocks = <&gcc GCC_DISP_AXI_CLK>, 4585 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4586 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4587 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4588 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4589 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4590 4591 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4592 assigned-clock-rates = <19200000>; 4593 operating-points-v2 = <&mdp_opp_table>; 4594 power-domains = <&rpmhpd SDM845_CX>; 4595 4596 interrupt-parent = <&mdss>; 4597 interrupts = <0>; 4598 4599 ports { 4600 #address-cells = <1>; 4601 #size-cells = <0>; 4602 4603 port@0 { 4604 reg = <0>; 4605 dpu_intf0_out: endpoint { 4606 remote-endpoint = <&dp_in>; 4607 }; 4608 }; 4609 4610 port@1 { 4611 reg = <1>; 4612 dpu_intf1_out: endpoint { 4613 remote-endpoint = <&mdss_dsi0_in>; 4614 }; 4615 }; 4616 4617 port@2 { 4618 reg = <2>; 4619 dpu_intf2_out: endpoint { 4620 remote-endpoint = <&mdss_dsi1_in>; 4621 }; 4622 }; 4623 }; 4624 4625 mdp_opp_table: opp-table { 4626 compatible = "operating-points-v2"; 4627 4628 opp-19200000 { 4629 opp-hz = /bits/ 64 <19200000>; 4630 required-opps = <&rpmhpd_opp_min_svs>; 4631 }; 4632 4633 opp-171428571 { 4634 opp-hz = /bits/ 64 <171428571>; 4635 required-opps = <&rpmhpd_opp_low_svs>; 4636 }; 4637 4638 opp-344000000 { 4639 opp-hz = /bits/ 64 <344000000>; 4640 required-opps = <&rpmhpd_opp_svs_l1>; 4641 }; 4642 4643 opp-430000000 { 4644 opp-hz = /bits/ 64 <430000000>; 4645 required-opps = <&rpmhpd_opp_nom>; 4646 }; 4647 }; 4648 }; 4649 4650 mdss_dp: displayport-controller@ae90000 { 4651 status = "disabled"; 4652 compatible = "qcom,sdm845-dp"; 4653 4654 reg = <0 0x0ae90000 0 0x200>, 4655 <0 0x0ae90200 0 0x200>, 4656 <0 0x0ae90400 0 0x600>, 4657 <0 0x0ae90a00 0 0x600>, 4658 <0 0x0ae91000 0 0x600>; 4659 4660 interrupt-parent = <&mdss>; 4661 interrupts = <12>; 4662 4663 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4664 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4665 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4666 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4667 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4668 clock-names = "core_iface", "core_aux", "ctrl_link", 4669 "ctrl_link_iface", "stream_pixel"; 4670 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4671 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4672 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4673 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4674 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4675 phy-names = "dp"; 4676 4677 operating-points-v2 = <&dp_opp_table>; 4678 power-domains = <&rpmhpd SDM845_CX>; 4679 4680 ports { 4681 #address-cells = <1>; 4682 #size-cells = <0>; 4683 port@0 { 4684 reg = <0>; 4685 dp_in: endpoint { 4686 remote-endpoint = <&dpu_intf0_out>; 4687 }; 4688 }; 4689 4690 port@1 { 4691 reg = <1>; 4692 dp_out: endpoint { 4693 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4694 }; 4695 }; 4696 }; 4697 4698 dp_opp_table: opp-table { 4699 compatible = "operating-points-v2"; 4700 4701 opp-162000000 { 4702 opp-hz = /bits/ 64 <162000000>; 4703 required-opps = <&rpmhpd_opp_low_svs>; 4704 }; 4705 4706 opp-270000000 { 4707 opp-hz = /bits/ 64 <270000000>; 4708 required-opps = <&rpmhpd_opp_svs>; 4709 }; 4710 4711 opp-540000000 { 4712 opp-hz = /bits/ 64 <540000000>; 4713 required-opps = <&rpmhpd_opp_svs_l1>; 4714 }; 4715 4716 opp-810000000 { 4717 opp-hz = /bits/ 64 <810000000>; 4718 required-opps = <&rpmhpd_opp_nom>; 4719 }; 4720 }; 4721 }; 4722 4723 mdss_dsi0: dsi@ae94000 { 4724 compatible = "qcom,sdm845-dsi-ctrl", 4725 "qcom,mdss-dsi-ctrl"; 4726 reg = <0 0x0ae94000 0 0x400>; 4727 reg-names = "dsi_ctrl"; 4728 4729 interrupt-parent = <&mdss>; 4730 interrupts = <4>; 4731 4732 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4733 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4734 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4735 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4736 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4737 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4738 clock-names = "byte", 4739 "byte_intf", 4740 "pixel", 4741 "core", 4742 "iface", 4743 "bus"; 4744 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4745 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4746 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4747 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4748 4749 operating-points-v2 = <&dsi_opp_table>; 4750 power-domains = <&rpmhpd SDM845_CX>; 4751 4752 phys = <&mdss_dsi0_phy>; 4753 4754 status = "disabled"; 4755 4756 #address-cells = <1>; 4757 #size-cells = <0>; 4758 4759 ports { 4760 #address-cells = <1>; 4761 #size-cells = <0>; 4762 4763 port@0 { 4764 reg = <0>; 4765 mdss_dsi0_in: endpoint { 4766 remote-endpoint = <&dpu_intf1_out>; 4767 }; 4768 }; 4769 4770 port@1 { 4771 reg = <1>; 4772 mdss_dsi0_out: endpoint { 4773 }; 4774 }; 4775 }; 4776 }; 4777 4778 mdss_dsi0_phy: phy@ae94400 { 4779 compatible = "qcom,dsi-phy-10nm"; 4780 reg = <0 0x0ae94400 0 0x200>, 4781 <0 0x0ae94600 0 0x280>, 4782 <0 0x0ae94a00 0 0x1e0>; 4783 reg-names = "dsi_phy", 4784 "dsi_phy_lane", 4785 "dsi_pll"; 4786 4787 #clock-cells = <1>; 4788 #phy-cells = <0>; 4789 4790 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4791 <&rpmhcc RPMH_CXO_CLK>; 4792 clock-names = "iface", "ref"; 4793 4794 status = "disabled"; 4795 }; 4796 4797 mdss_dsi1: dsi@ae96000 { 4798 compatible = "qcom,sdm845-dsi-ctrl", 4799 "qcom,mdss-dsi-ctrl"; 4800 reg = <0 0x0ae96000 0 0x400>; 4801 reg-names = "dsi_ctrl"; 4802 4803 interrupt-parent = <&mdss>; 4804 interrupts = <5>; 4805 4806 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4807 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4808 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4809 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4810 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4811 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4812 clock-names = "byte", 4813 "byte_intf", 4814 "pixel", 4815 "core", 4816 "iface", 4817 "bus"; 4818 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4819 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4820 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4821 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4822 4823 operating-points-v2 = <&dsi_opp_table>; 4824 power-domains = <&rpmhpd SDM845_CX>; 4825 4826 phys = <&mdss_dsi1_phy>; 4827 4828 status = "disabled"; 4829 4830 #address-cells = <1>; 4831 #size-cells = <0>; 4832 4833 ports { 4834 #address-cells = <1>; 4835 #size-cells = <0>; 4836 4837 port@0 { 4838 reg = <0>; 4839 mdss_dsi1_in: endpoint { 4840 remote-endpoint = <&dpu_intf2_out>; 4841 }; 4842 }; 4843 4844 port@1 { 4845 reg = <1>; 4846 mdss_dsi1_out: endpoint { 4847 }; 4848 }; 4849 }; 4850 }; 4851 4852 mdss_dsi1_phy: phy@ae96400 { 4853 compatible = "qcom,dsi-phy-10nm"; 4854 reg = <0 0x0ae96400 0 0x200>, 4855 <0 0x0ae96600 0 0x280>, 4856 <0 0x0ae96a00 0 0x10e>; 4857 reg-names = "dsi_phy", 4858 "dsi_phy_lane", 4859 "dsi_pll"; 4860 4861 #clock-cells = <1>; 4862 #phy-cells = <0>; 4863 4864 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4865 <&rpmhcc RPMH_CXO_CLK>; 4866 clock-names = "iface", "ref"; 4867 4868 status = "disabled"; 4869 }; 4870 }; 4871 4872 gpu: gpu@5000000 { 4873 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4874 4875 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4876 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4877 4878 /* 4879 * Look ma, no clocks! The GPU clocks and power are 4880 * controlled entirely by the GMU 4881 */ 4882 4883 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4884 4885 iommus = <&adreno_smmu 0>; 4886 4887 operating-points-v2 = <&gpu_opp_table>; 4888 4889 qcom,gmu = <&gmu>; 4890 #cooling-cells = <2>; 4891 4892 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4893 interconnect-names = "gfx-mem"; 4894 4895 status = "disabled"; 4896 4897 gpu_opp_table: opp-table { 4898 compatible = "operating-points-v2"; 4899 4900 opp-710000000 { 4901 opp-hz = /bits/ 64 <710000000>; 4902 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4903 opp-peak-kBps = <7216000>; 4904 }; 4905 4906 opp-675000000 { 4907 opp-hz = /bits/ 64 <675000000>; 4908 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4909 opp-peak-kBps = <7216000>; 4910 }; 4911 4912 opp-596000000 { 4913 opp-hz = /bits/ 64 <596000000>; 4914 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4915 opp-peak-kBps = <6220000>; 4916 }; 4917 4918 opp-520000000 { 4919 opp-hz = /bits/ 64 <520000000>; 4920 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4921 opp-peak-kBps = <6220000>; 4922 }; 4923 4924 opp-414000000 { 4925 opp-hz = /bits/ 64 <414000000>; 4926 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4927 opp-peak-kBps = <4068000>; 4928 }; 4929 4930 opp-342000000 { 4931 opp-hz = /bits/ 64 <342000000>; 4932 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4933 opp-peak-kBps = <2724000>; 4934 }; 4935 4936 opp-257000000 { 4937 opp-hz = /bits/ 64 <257000000>; 4938 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4939 opp-peak-kBps = <1648000>; 4940 }; 4941 }; 4942 }; 4943 4944 adreno_smmu: iommu@5040000 { 4945 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4946 reg = <0 0x05040000 0 0x10000>; 4947 #iommu-cells = <1>; 4948 #global-interrupts = <2>; 4949 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4950 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4951 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4952 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4953 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4954 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4955 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4956 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4957 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4958 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4959 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4960 <&gcc GCC_GPU_CFG_AHB_CLK>; 4961 clock-names = "bus", "iface"; 4962 4963 power-domains = <&gpucc GPU_CX_GDSC>; 4964 }; 4965 4966 gmu: gmu@506a000 { 4967 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4968 4969 reg = <0 0x0506a000 0 0x30000>, 4970 <0 0x0b280000 0 0x10000>, 4971 <0 0x0b480000 0 0x10000>; 4972 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4973 4974 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4976 interrupt-names = "hfi", "gmu"; 4977 4978 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4979 <&gpucc GPU_CC_CXO_CLK>, 4980 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4981 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4982 clock-names = "gmu", "cxo", "axi", "memnoc"; 4983 4984 power-domains = <&gpucc GPU_CX_GDSC>, 4985 <&gpucc GPU_GX_GDSC>; 4986 power-domain-names = "cx", "gx"; 4987 4988 iommus = <&adreno_smmu 5>; 4989 4990 operating-points-v2 = <&gmu_opp_table>; 4991 4992 gmu_opp_table: opp-table { 4993 compatible = "operating-points-v2"; 4994 4995 opp-400000000 { 4996 opp-hz = /bits/ 64 <400000000>; 4997 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4998 }; 4999 5000 opp-200000000 { 5001 opp-hz = /bits/ 64 <200000000>; 5002 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5003 }; 5004 }; 5005 }; 5006 5007 dispcc: clock-controller@af00000 { 5008 compatible = "qcom,sdm845-dispcc"; 5009 reg = <0 0x0af00000 0 0x10000>; 5010 clocks = <&rpmhcc RPMH_CXO_CLK>, 5011 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 5012 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 5013 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5014 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5015 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5016 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5017 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5018 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5019 clock-names = "bi_tcxo", 5020 "gcc_disp_gpll0_clk_src", 5021 "gcc_disp_gpll0_div_clk_src", 5022 "dsi0_phy_pll_out_byteclk", 5023 "dsi0_phy_pll_out_dsiclk", 5024 "dsi1_phy_pll_out_byteclk", 5025 "dsi1_phy_pll_out_dsiclk", 5026 "dp_link_clk_divsel_ten", 5027 "dp_vco_divided_clk_src_mux"; 5028 #clock-cells = <1>; 5029 #reset-cells = <1>; 5030 #power-domain-cells = <1>; 5031 }; 5032 5033 pdc_intc: interrupt-controller@b220000 { 5034 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 5035 reg = <0 0x0b220000 0 0x30000>; 5036 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 5037 #interrupt-cells = <2>; 5038 interrupt-parent = <&intc>; 5039 interrupt-controller; 5040 }; 5041 5042 pdc_reset: reset-controller@b2e0000 { 5043 compatible = "qcom,sdm845-pdc-global"; 5044 reg = <0 0x0b2e0000 0 0x20000>; 5045 #reset-cells = <1>; 5046 }; 5047 5048 tsens0: thermal-sensor@c263000 { 5049 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 5050 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5051 <0 0x0c222000 0 0x1ff>; /* SROT */ 5052 #qcom,sensors = <13>; 5053 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5055 interrupt-names = "uplow", "critical"; 5056 #thermal-sensor-cells = <1>; 5057 }; 5058 5059 tsens1: thermal-sensor@c265000 { 5060 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 5061 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5062 <0 0x0c223000 0 0x1ff>; /* SROT */ 5063 #qcom,sensors = <8>; 5064 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5066 interrupt-names = "uplow", "critical"; 5067 #thermal-sensor-cells = <1>; 5068 }; 5069 5070 aoss_reset: reset-controller@c2a0000 { 5071 compatible = "qcom,sdm845-aoss-cc"; 5072 reg = <0 0x0c2a0000 0 0x31000>; 5073 #reset-cells = <1>; 5074 }; 5075 5076 aoss_qmp: power-management@c300000 { 5077 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 5078 reg = <0 0x0c300000 0 0x400>; 5079 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 5080 mboxes = <&apss_shared 0>; 5081 5082 #clock-cells = <0>; 5083 5084 cx_cdev: cx { 5085 #cooling-cells = <2>; 5086 }; 5087 5088 ebi_cdev: ebi { 5089 #cooling-cells = <2>; 5090 }; 5091 }; 5092 5093 sram@c3f0000 { 5094 compatible = "qcom,sdm845-rpmh-stats"; 5095 reg = <0 0x0c3f0000 0 0x400>; 5096 }; 5097 5098 spmi_bus: spmi@c440000 { 5099 compatible = "qcom,spmi-pmic-arb"; 5100 reg = <0 0x0c440000 0 0x1100>, 5101 <0 0x0c600000 0 0x2000000>, 5102 <0 0x0e600000 0 0x100000>, 5103 <0 0x0e700000 0 0xa0000>, 5104 <0 0x0c40a000 0 0x26000>; 5105 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5106 interrupt-names = "periph_irq"; 5107 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 5108 qcom,ee = <0>; 5109 qcom,channel = <0>; 5110 #address-cells = <2>; 5111 #size-cells = <0>; 5112 interrupt-controller; 5113 #interrupt-cells = <4>; 5114 }; 5115 5116 sram@14680000 { 5117 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5118 reg = <0 0x14680000 0 0x40000>; 5119 5120 #address-cells = <1>; 5121 #size-cells = <1>; 5122 5123 ranges = <0 0 0x14680000 0x40000>; 5124 5125 pil-reloc@3f94c { 5126 compatible = "qcom,pil-reloc-info"; 5127 reg = <0x3f94c 0xc8>; 5128 }; 5129 }; 5130 5131 apps_smmu: iommu@15000000 { 5132 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5133 reg = <0 0x15000000 0 0x80000>; 5134 #iommu-cells = <2>; 5135 #global-interrupts = <1>; 5136 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5195 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5196 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5197 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5198 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5199 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5200 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5201 }; 5202 5203 anoc_1_tbu: tbu@150c5000 { 5204 compatible = "qcom,sdm845-tbu"; 5205 reg = <0x0 0x150c5000 0x0 0x1000>; 5206 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5207 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5208 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; 5209 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 5210 }; 5211 5212 anoc_2_tbu: tbu@150c9000 { 5213 compatible = "qcom,sdm845-tbu"; 5214 reg = <0x0 0x150c9000 0x0 0x1000>; 5215 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5216 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5217 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; 5218 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 5219 }; 5220 5221 mnoc_hf_0_tbu: tbu@150cd000 { 5222 compatible = "qcom,sdm845-tbu"; 5223 reg = <0x0 0x150cd000 0x0 0x1000>; 5224 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5225 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5226 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 5227 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 5228 }; 5229 5230 mnoc_hf_1_tbu: tbu@150d1000 { 5231 compatible = "qcom,sdm845-tbu"; 5232 reg = <0x0 0x150d1000 0x0 0x1000>; 5233 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5234 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5235 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 5236 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 5237 }; 5238 5239 mnoc_sf_0_tbu: tbu@150d5000 { 5240 compatible = "qcom,sdm845-tbu"; 5241 reg = <0x0 0x150d5000 0x0 0x1000>; 5242 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 5243 &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; 5244 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; 5245 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 5246 }; 5247 5248 compute_dsp_tbu: tbu@150d9000 { 5249 compatible = "qcom,sdm845-tbu"; 5250 reg = <0x0 0x150d9000 0x0 0x1000>; 5251 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5252 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5253 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 5254 }; 5255 5256 adsp_tbu: tbu@150dd000 { 5257 compatible = "qcom,sdm845-tbu"; 5258 reg = <0x0 0x150dd000 0x0 0x1000>; 5259 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5260 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5261 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; 5262 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 5263 }; 5264 5265 anoc_1_pcie_tbu: tbu@150e1000 { 5266 compatible = "qcom,sdm845-tbu"; 5267 reg = <0x0 0x150e1000 0x0 0x1000>; 5268 clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 5269 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 5270 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5271 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; 5272 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 5273 }; 5274 5275 lpasscc: clock-controller@17014000 { 5276 compatible = "qcom,sdm845-lpasscc"; 5277 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5278 reg-names = "cc", "qdsp6ss"; 5279 #clock-cells = <1>; 5280 status = "disabled"; 5281 }; 5282 5283 gladiator_noc: interconnect@17900000 { 5284 compatible = "qcom,sdm845-gladiator-noc"; 5285 reg = <0 0x17900000 0 0xd080>; 5286 #interconnect-cells = <2>; 5287 qcom,bcm-voters = <&apps_bcm_voter>; 5288 }; 5289 5290 watchdog@17980000 { 5291 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5292 reg = <0 0x17980000 0 0x1000>; 5293 clocks = <&sleep_clk>; 5294 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5295 }; 5296 5297 apss_shared: mailbox@17990000 { 5298 compatible = "qcom,sdm845-apss-shared"; 5299 reg = <0 0x17990000 0 0x1000>; 5300 #mbox-cells = <1>; 5301 }; 5302 5303 apps_rsc: rsc@179c0000 { 5304 compatible = "qcom,sdm845-rpmh-apps-rsc", "qcom,rpmh-rsc"; 5305 label = "apps_rsc"; 5306 reg = <0 0x179c0000 0 0x10000>, 5307 <0 0x179d0000 0 0x10000>, 5308 <0 0x179e0000 0 0x10000>; 5309 reg-names = "drv-0", "drv-1", "drv-2"; 5310 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5311 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5312 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5313 qcom,tcs-offset = <0xd00>; 5314 qcom,drv-id = <2>; 5315 qcom,tcs-config = <ACTIVE_TCS 2>, 5316 <SLEEP_TCS 3>, 5317 <WAKE_TCS 3>, 5318 <CONTROL_TCS 1>; 5319 power-domains = <&cluster_pd>; 5320 5321 apps_bcm_voter: bcm-voter { 5322 compatible = "qcom,bcm-voter"; 5323 }; 5324 5325 rpmhcc: clock-controller { 5326 compatible = "qcom,sdm845-rpmh-clk"; 5327 #clock-cells = <1>; 5328 clock-names = "xo"; 5329 clocks = <&xo_board>; 5330 }; 5331 5332 rpmhpd: power-controller { 5333 compatible = "qcom,sdm845-rpmhpd"; 5334 #power-domain-cells = <1>; 5335 operating-points-v2 = <&rpmhpd_opp_table>; 5336 5337 rpmhpd_opp_table: opp-table { 5338 compatible = "operating-points-v2"; 5339 5340 rpmhpd_opp_ret: opp1 { 5341 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5342 }; 5343 5344 rpmhpd_opp_min_svs: opp2 { 5345 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5346 }; 5347 5348 rpmhpd_opp_low_svs: opp3 { 5349 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5350 }; 5351 5352 rpmhpd_opp_svs: opp4 { 5353 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5354 }; 5355 5356 rpmhpd_opp_svs_l1: opp5 { 5357 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5358 }; 5359 5360 rpmhpd_opp_nom: opp6 { 5361 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5362 }; 5363 5364 rpmhpd_opp_nom_l1: opp7 { 5365 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5366 }; 5367 5368 rpmhpd_opp_nom_l2: opp8 { 5369 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5370 }; 5371 5372 rpmhpd_opp_turbo: opp9 { 5373 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5374 }; 5375 5376 rpmhpd_opp_turbo_l1: opp10 { 5377 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5378 }; 5379 }; 5380 }; 5381 }; 5382 5383 intc: interrupt-controller@17a00000 { 5384 compatible = "arm,gic-v3"; 5385 #address-cells = <2>; 5386 #size-cells = <2>; 5387 ranges; 5388 #interrupt-cells = <3>; 5389 interrupt-controller; 5390 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5391 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5392 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5393 5394 msi-controller@17a40000 { 5395 compatible = "arm,gic-v3-its"; 5396 msi-controller; 5397 #msi-cells = <1>; 5398 reg = <0 0x17a40000 0 0x20000>; 5399 status = "disabled"; 5400 }; 5401 }; 5402 5403 slimbam: dma-controller@17184000 { 5404 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5405 qcom,controlled-remotely; 5406 reg = <0 0x17184000 0 0x2a000>; 5407 num-channels = <31>; 5408 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5409 #dma-cells = <1>; 5410 qcom,ee = <1>; 5411 qcom,num-ees = <2>; 5412 iommus = <&apps_smmu 0x1806 0x0>; 5413 }; 5414 5415 timer@17c90000 { 5416 #address-cells = <1>; 5417 #size-cells = <1>; 5418 ranges = <0 0 0 0x20000000>; 5419 compatible = "arm,armv7-timer-mem"; 5420 reg = <0 0x17c90000 0 0x1000>; 5421 5422 frame@17ca0000 { 5423 frame-number = <0>; 5424 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5425 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5426 reg = <0x17ca0000 0x1000>, 5427 <0x17cb0000 0x1000>; 5428 }; 5429 5430 frame@17cc0000 { 5431 frame-number = <1>; 5432 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5433 reg = <0x17cc0000 0x1000>; 5434 status = "disabled"; 5435 }; 5436 5437 frame@17cd0000 { 5438 frame-number = <2>; 5439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5440 reg = <0x17cd0000 0x1000>; 5441 status = "disabled"; 5442 }; 5443 5444 frame@17ce0000 { 5445 frame-number = <3>; 5446 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5447 reg = <0x17ce0000 0x1000>; 5448 status = "disabled"; 5449 }; 5450 5451 frame@17cf0000 { 5452 frame-number = <4>; 5453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5454 reg = <0x17cf0000 0x1000>; 5455 status = "disabled"; 5456 }; 5457 5458 frame@17d00000 { 5459 frame-number = <5>; 5460 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5461 reg = <0x17d00000 0x1000>; 5462 status = "disabled"; 5463 }; 5464 5465 frame@17d10000 { 5466 frame-number = <6>; 5467 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5468 reg = <0x17d10000 0x1000>; 5469 status = "disabled"; 5470 }; 5471 }; 5472 5473 osm_l3: interconnect@17d41000 { 5474 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5475 reg = <0 0x17d41000 0 0x1400>; 5476 5477 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5478 clock-names = "xo", "alternate"; 5479 5480 #interconnect-cells = <1>; 5481 }; 5482 5483 cpufreq_hw: cpufreq@17d43000 { 5484 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5485 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5486 reg-names = "freq-domain0", "freq-domain1"; 5487 5488 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5489 5490 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5491 clock-names = "xo", "alternate"; 5492 5493 #freq-domain-cells = <1>; 5494 #clock-cells = <1>; 5495 }; 5496 5497 wifi: wifi@18800000 { 5498 compatible = "qcom,wcn3990-wifi"; 5499 status = "disabled"; 5500 reg = <0 0x18800000 0 0x800000>; 5501 reg-names = "membase"; 5502 memory-region = <&wlan_msa_mem>; 5503 clock-names = "cxo_ref_clk_pin"; 5504 clocks = <&rpmhcc RPMH_RF_CLK2>; 5505 interrupts = 5506 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5507 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5508 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5509 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5510 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5511 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5512 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5513 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5514 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5515 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5516 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5517 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5518 iommus = <&apps_smmu 0x0040 0x1>; 5519 }; 5520 }; 5521 5522 sound: sound { 5523 }; 5524 5525 thermal-zones { 5526 cpu0-thermal { 5527 polling-delay-passive = <250>; 5528 5529 thermal-sensors = <&tsens0 1>; 5530 5531 trips { 5532 cpu0_alert0: trip-point0 { 5533 temperature = <90000>; 5534 hysteresis = <2000>; 5535 type = "passive"; 5536 }; 5537 5538 cpu0_alert1: trip-point1 { 5539 temperature = <95000>; 5540 hysteresis = <2000>; 5541 type = "passive"; 5542 }; 5543 5544 cpu0_crit: cpu-crit { 5545 temperature = <110000>; 5546 hysteresis = <1000>; 5547 type = "critical"; 5548 }; 5549 }; 5550 }; 5551 5552 cpu1-thermal { 5553 polling-delay-passive = <250>; 5554 5555 thermal-sensors = <&tsens0 2>; 5556 5557 trips { 5558 cpu1_alert0: trip-point0 { 5559 temperature = <90000>; 5560 hysteresis = <2000>; 5561 type = "passive"; 5562 }; 5563 5564 cpu1_alert1: trip-point1 { 5565 temperature = <95000>; 5566 hysteresis = <2000>; 5567 type = "passive"; 5568 }; 5569 5570 cpu1_crit: cpu-crit { 5571 temperature = <110000>; 5572 hysteresis = <1000>; 5573 type = "critical"; 5574 }; 5575 }; 5576 }; 5577 5578 cpu2-thermal { 5579 polling-delay-passive = <250>; 5580 5581 thermal-sensors = <&tsens0 3>; 5582 5583 trips { 5584 cpu2_alert0: trip-point0 { 5585 temperature = <90000>; 5586 hysteresis = <2000>; 5587 type = "passive"; 5588 }; 5589 5590 cpu2_alert1: trip-point1 { 5591 temperature = <95000>; 5592 hysteresis = <2000>; 5593 type = "passive"; 5594 }; 5595 5596 cpu2_crit: cpu-crit { 5597 temperature = <110000>; 5598 hysteresis = <1000>; 5599 type = "critical"; 5600 }; 5601 }; 5602 }; 5603 5604 cpu3-thermal { 5605 polling-delay-passive = <250>; 5606 5607 thermal-sensors = <&tsens0 4>; 5608 5609 trips { 5610 cpu3_alert0: trip-point0 { 5611 temperature = <90000>; 5612 hysteresis = <2000>; 5613 type = "passive"; 5614 }; 5615 5616 cpu3_alert1: trip-point1 { 5617 temperature = <95000>; 5618 hysteresis = <2000>; 5619 type = "passive"; 5620 }; 5621 5622 cpu3_crit: cpu-crit { 5623 temperature = <110000>; 5624 hysteresis = <1000>; 5625 type = "critical"; 5626 }; 5627 }; 5628 }; 5629 5630 cpu4-thermal { 5631 polling-delay-passive = <250>; 5632 5633 thermal-sensors = <&tsens0 7>; 5634 5635 trips { 5636 cpu4_alert0: trip-point0 { 5637 temperature = <90000>; 5638 hysteresis = <2000>; 5639 type = "passive"; 5640 }; 5641 5642 cpu4_alert1: trip-point1 { 5643 temperature = <95000>; 5644 hysteresis = <2000>; 5645 type = "passive"; 5646 }; 5647 5648 cpu4_crit: cpu-crit { 5649 temperature = <110000>; 5650 hysteresis = <1000>; 5651 type = "critical"; 5652 }; 5653 }; 5654 }; 5655 5656 cpu5-thermal { 5657 polling-delay-passive = <250>; 5658 5659 thermal-sensors = <&tsens0 8>; 5660 5661 trips { 5662 cpu5_alert0: trip-point0 { 5663 temperature = <90000>; 5664 hysteresis = <2000>; 5665 type = "passive"; 5666 }; 5667 5668 cpu5_alert1: trip-point1 { 5669 temperature = <95000>; 5670 hysteresis = <2000>; 5671 type = "passive"; 5672 }; 5673 5674 cpu5_crit: cpu-crit { 5675 temperature = <110000>; 5676 hysteresis = <1000>; 5677 type = "critical"; 5678 }; 5679 }; 5680 }; 5681 5682 cpu6-thermal { 5683 polling-delay-passive = <250>; 5684 5685 thermal-sensors = <&tsens0 9>; 5686 5687 trips { 5688 cpu6_alert0: trip-point0 { 5689 temperature = <90000>; 5690 hysteresis = <2000>; 5691 type = "passive"; 5692 }; 5693 5694 cpu6_alert1: trip-point1 { 5695 temperature = <95000>; 5696 hysteresis = <2000>; 5697 type = "passive"; 5698 }; 5699 5700 cpu6_crit: cpu-crit { 5701 temperature = <110000>; 5702 hysteresis = <1000>; 5703 type = "critical"; 5704 }; 5705 }; 5706 }; 5707 5708 cpu7-thermal { 5709 polling-delay-passive = <250>; 5710 5711 thermal-sensors = <&tsens0 10>; 5712 5713 trips { 5714 cpu7_alert0: trip-point0 { 5715 temperature = <90000>; 5716 hysteresis = <2000>; 5717 type = "passive"; 5718 }; 5719 5720 cpu7_alert1: trip-point1 { 5721 temperature = <95000>; 5722 hysteresis = <2000>; 5723 type = "passive"; 5724 }; 5725 5726 cpu7_crit: cpu-crit { 5727 temperature = <110000>; 5728 hysteresis = <1000>; 5729 type = "critical"; 5730 }; 5731 }; 5732 }; 5733 5734 aoss0-thermal { 5735 polling-delay-passive = <250>; 5736 5737 thermal-sensors = <&tsens0 0>; 5738 5739 trips { 5740 aoss0_alert0: trip-point0 { 5741 temperature = <90000>; 5742 hysteresis = <2000>; 5743 type = "hot"; 5744 }; 5745 }; 5746 }; 5747 5748 cluster0-thermal { 5749 polling-delay-passive = <250>; 5750 5751 thermal-sensors = <&tsens0 5>; 5752 5753 trips { 5754 cluster0_alert0: trip-point0 { 5755 temperature = <90000>; 5756 hysteresis = <2000>; 5757 type = "hot"; 5758 }; 5759 cluster0_crit: cluster0-crit { 5760 temperature = <110000>; 5761 hysteresis = <2000>; 5762 type = "critical"; 5763 }; 5764 }; 5765 }; 5766 5767 cluster1-thermal { 5768 polling-delay-passive = <250>; 5769 5770 thermal-sensors = <&tsens0 6>; 5771 5772 trips { 5773 cluster1_alert0: trip-point0 { 5774 temperature = <90000>; 5775 hysteresis = <2000>; 5776 type = "hot"; 5777 }; 5778 cluster1_crit: cluster1-crit { 5779 temperature = <110000>; 5780 hysteresis = <2000>; 5781 type = "critical"; 5782 }; 5783 }; 5784 }; 5785 5786 gpu-top-thermal { 5787 polling-delay-passive = <250>; 5788 5789 thermal-sensors = <&tsens0 11>; 5790 5791 cooling-maps { 5792 map0 { 5793 trip = <&gpu_top_alert0>; 5794 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5795 }; 5796 }; 5797 5798 trips { 5799 gpu_top_alert0: trip-point0 { 5800 temperature = <85000>; 5801 hysteresis = <1000>; 5802 type = "passive"; 5803 }; 5804 5805 trip-point1 { 5806 temperature = <90000>; 5807 hysteresis = <1000>; 5808 type = "hot"; 5809 }; 5810 5811 trip-point2 { 5812 temperature = <110000>; 5813 hysteresis = <1000>; 5814 type = "critical"; 5815 }; 5816 }; 5817 }; 5818 5819 gpu-bottom-thermal { 5820 polling-delay-passive = <250>; 5821 5822 thermal-sensors = <&tsens0 12>; 5823 5824 cooling-maps { 5825 map0 { 5826 trip = <&gpu_bottom_alert0>; 5827 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5828 }; 5829 }; 5830 5831 trips { 5832 gpu_bottom_alert0: trip-point0 { 5833 temperature = <85000>; 5834 hysteresis = <1000>; 5835 type = "passive"; 5836 }; 5837 5838 trip-point1 { 5839 temperature = <90000>; 5840 hysteresis = <1000>; 5841 type = "hot"; 5842 }; 5843 5844 trip-point2 { 5845 temperature = <110000>; 5846 hysteresis = <1000>; 5847 type = "critical"; 5848 }; 5849 }; 5850 }; 5851 5852 aoss1-thermal { 5853 polling-delay-passive = <250>; 5854 5855 thermal-sensors = <&tsens1 0>; 5856 5857 trips { 5858 aoss1_alert0: trip-point0 { 5859 temperature = <90000>; 5860 hysteresis = <2000>; 5861 type = "hot"; 5862 }; 5863 }; 5864 }; 5865 5866 q6-modem-thermal { 5867 polling-delay-passive = <250>; 5868 5869 thermal-sensors = <&tsens1 1>; 5870 5871 trips { 5872 q6_modem_alert0: trip-point0 { 5873 temperature = <90000>; 5874 hysteresis = <2000>; 5875 type = "hot"; 5876 }; 5877 }; 5878 }; 5879 5880 mem-thermal { 5881 polling-delay-passive = <250>; 5882 5883 thermal-sensors = <&tsens1 2>; 5884 5885 trips { 5886 mem_alert0: trip-point0 { 5887 temperature = <90000>; 5888 hysteresis = <2000>; 5889 type = "hot"; 5890 }; 5891 }; 5892 }; 5893 5894 wlan-thermal { 5895 polling-delay-passive = <250>; 5896 5897 thermal-sensors = <&tsens1 3>; 5898 5899 trips { 5900 wlan_alert0: trip-point0 { 5901 temperature = <90000>; 5902 hysteresis = <2000>; 5903 type = "hot"; 5904 }; 5905 }; 5906 }; 5907 5908 q6-hvx-thermal { 5909 polling-delay-passive = <250>; 5910 5911 thermal-sensors = <&tsens1 4>; 5912 5913 trips { 5914 q6_hvx_alert0: trip-point0 { 5915 temperature = <90000>; 5916 hysteresis = <2000>; 5917 type = "hot"; 5918 }; 5919 }; 5920 }; 5921 5922 camera-thermal { 5923 polling-delay-passive = <250>; 5924 5925 thermal-sensors = <&tsens1 5>; 5926 5927 trips { 5928 camera_alert0: trip-point0 { 5929 temperature = <90000>; 5930 hysteresis = <2000>; 5931 type = "hot"; 5932 }; 5933 }; 5934 }; 5935 5936 video-thermal { 5937 polling-delay-passive = <250>; 5938 5939 thermal-sensors = <&tsens1 6>; 5940 5941 trips { 5942 video_alert0: trip-point0 { 5943 temperature = <90000>; 5944 hysteresis = <2000>; 5945 type = "hot"; 5946 }; 5947 }; 5948 }; 5949 5950 modem-thermal { 5951 polling-delay-passive = <250>; 5952 5953 thermal-sensors = <&tsens1 7>; 5954 5955 trips { 5956 modem_alert0: trip-point0 { 5957 temperature = <90000>; 5958 hysteresis = <2000>; 5959 type = "hot"; 5960 }; 5961 }; 5962 }; 5963 }; 5964 5965 timer { 5966 compatible = "arm,armv8-timer"; 5967 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5968 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5969 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5970 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5971 }; 5972}; 5973