1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Richard Acayan. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,camcc-sdm845.h> 10#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 11#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 12#include <dt-bindings/clock/qcom,gcc-sdm845.h> 13#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/phy/phy-qcom-qusb2.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { }; 31 32 chosen { }; 33 34 clocks { 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 }; 40 41 xo_board: xo-board { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <38400000>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "qcom,kryo360"; 55 reg = <0x0 0x0>; 56 enable-method = "psci"; 57 capacity-dmips-mhz = <610>; 58 dynamic-power-coefficient = <203>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 62 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 63 power-domains = <&cpu_pd0>; 64 power-domain-names = "psci"; 65 next-level-cache = <&l2_0>; 66 l2_0: l2-cache { 67 compatible = "cache"; 68 next-level-cache = <&l3_0>; 69 cache-level = <2>; 70 cache-unified; 71 l3_0: l3-cache { 72 compatible = "cache"; 73 cache-level = <3>; 74 cache-unified; 75 }; 76 }; 77 }; 78 79 cpu1: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo360"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 capacity-dmips-mhz = <610>; 85 dynamic-power-coefficient = <203>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 89 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 90 power-domains = <&cpu_pd1>; 91 power-domain-names = "psci"; 92 next-level-cache = <&l2_100>; 93 l2_100: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&l3_0>; 98 }; 99 }; 100 101 cpu2: cpu@200 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo360"; 104 reg = <0x0 0x200>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <610>; 107 dynamic-power-coefficient = <203>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 operating-points-v2 = <&cpu0_opp_table>; 110 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 111 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 112 power-domains = <&cpu_pd2>; 113 power-domain-names = "psci"; 114 next-level-cache = <&l2_200>; 115 l2_200: l2-cache { 116 compatible = "cache"; 117 cache-level = <2>; 118 cache-unified; 119 next-level-cache = <&l3_0>; 120 }; 121 }; 122 123 cpu3: cpu@300 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo360"; 126 reg = <0x0 0x300>; 127 enable-method = "psci"; 128 capacity-dmips-mhz = <610>; 129 dynamic-power-coefficient = <203>; 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 operating-points-v2 = <&cpu0_opp_table>; 132 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 133 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 134 power-domains = <&cpu_pd3>; 135 power-domain-names = "psci"; 136 next-level-cache = <&l2_300>; 137 l2_300: l2-cache { 138 compatible = "cache"; 139 cache-level = <2>; 140 cache-unified; 141 next-level-cache = <&l3_0>; 142 }; 143 }; 144 145 cpu4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo360"; 148 reg = <0x0 0x400>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <610>; 151 dynamic-power-coefficient = <203>; 152 qcom,freq-domain = <&cpufreq_hw 0>; 153 operating-points-v2 = <&cpu0_opp_table>; 154 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156 power-domains = <&cpu_pd4>; 157 power-domain-names = "psci"; 158 next-level-cache = <&l2_400>; 159 l2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 next-level-cache = <&l3_0>; 164 }; 165 }; 166 167 cpu5: cpu@500 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo360"; 170 reg = <0x0 0x500>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <610>; 173 dynamic-power-coefficient = <203>; 174 qcom,freq-domain = <&cpufreq_hw 0>; 175 operating-points-v2 = <&cpu0_opp_table>; 176 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 177 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 178 power-domains = <&cpu_pd5>; 179 power-domain-names = "psci"; 180 next-level-cache = <&l2_500>; 181 l2_500: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&l3_0>; 186 }; 187 }; 188 189 cpu6: cpu@600 { 190 device_type = "cpu"; 191 compatible = "qcom,kryo360"; 192 reg = <0x0 0x600>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 dynamic-power-coefficient = <393>; 196 qcom,freq-domain = <&cpufreq_hw 1>; 197 operating-points-v2 = <&cpu6_opp_table>; 198 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 199 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 200 power-domains = <&cpu_pd6>; 201 power-domain-names = "psci"; 202 next-level-cache = <&l2_600>; 203 l2_600: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&l3_0>; 208 }; 209 }; 210 211 cpu7: cpu@700 { 212 device_type = "cpu"; 213 compatible = "qcom,kryo360"; 214 reg = <0x0 0x700>; 215 enable-method = "psci"; 216 capacity-dmips-mhz = <1024>; 217 dynamic-power-coefficient = <393>; 218 qcom,freq-domain = <&cpufreq_hw 1>; 219 operating-points-v2 = <&cpu6_opp_table>; 220 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 221 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 222 power-domains = <&cpu_pd7>; 223 power-domain-names = "psci"; 224 next-level-cache = <&l2_700>; 225 l2_700: l2-cache { 226 compatible = "cache"; 227 cache-level = <2>; 228 cache-unified; 229 next-level-cache = <&l3_0>; 230 }; 231 }; 232 233 cpu-map { 234 cluster0 { 235 core0 { 236 cpu = <&cpu0>; 237 }; 238 239 core1 { 240 cpu = <&cpu1>; 241 }; 242 243 core2 { 244 cpu = <&cpu2>; 245 }; 246 247 core3 { 248 cpu = <&cpu3>; 249 }; 250 251 core4 { 252 cpu = <&cpu4>; 253 }; 254 255 core5 { 256 cpu = <&cpu5>; 257 }; 258 259 core6 { 260 cpu = <&cpu6>; 261 }; 262 263 core7 { 264 cpu = <&cpu7>; 265 }; 266 }; 267 }; 268 269 idle-states { 270 entry-method = "psci"; 271 272 little_cpu_sleep_0: cpu-sleep-0-0 { 273 compatible = "arm,idle-state"; 274 idle-state-name = "little-rail-power-collapse"; 275 arm,psci-suspend-param = <0x40000004>; 276 entry-latency-us = <702>; 277 exit-latency-us = <915>; 278 min-residency-us = <1617>; 279 local-timer-stop; 280 }; 281 282 big_cpu_sleep_0: cpu-sleep-1-0 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "big-rail-power-collapse"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <526>; 287 exit-latency-us = <1854>; 288 min-residency-us = <2380>; 289 local-timer-stop; 290 }; 291 }; 292 293 domain-idle-states { 294 cluster_sleep_0: cluster-sleep-0 { 295 compatible = "domain-idle-state"; 296 arm,psci-suspend-param = <0x4100c244>; 297 entry-latency-us = <3263>; 298 exit-latency-us = <6562>; 299 min-residency-us = <9825>; 300 }; 301 }; 302 }; 303 304 firmware { 305 scm { 306 compatible = "qcom,scm-sdm670", "qcom,scm"; 307 }; 308 }; 309 310 memory@80000000 { 311 device_type = "memory"; 312 /* We expect the bootloader to fill in the size */ 313 reg = <0x0 0x80000000 0x0 0x0>; 314 }; 315 316 cpu0_opp_table: opp-table-cpu0 { 317 compatible = "operating-points-v2"; 318 opp-shared; 319 320 cpu0_opp1: opp-300000000 { 321 opp-hz = /bits/ 64 <300000000>; 322 opp-peak-kBps = <400000 4800000>; 323 }; 324 325 cpu0_opp2: opp-576000000 { 326 opp-hz = /bits/ 64 <576000000>; 327 opp-peak-kBps = <400000 4800000>; 328 }; 329 330 cpu0_opp3: opp-748800000 { 331 opp-hz = /bits/ 64 <748800000>; 332 opp-peak-kBps = <1200000 4800000>; 333 }; 334 335 cpu0_opp4: opp-998400000 { 336 opp-hz = /bits/ 64 <998400000>; 337 opp-peak-kBps = <1804000 8908800>; 338 }; 339 340 cpu0_opp5: opp-1209600000 { 341 opp-hz = /bits/ 64 <1209600000>; 342 opp-peak-kBps = <2188000 8908800>; 343 }; 344 345 cpu0_opp6: opp-1324800000 { 346 opp-hz = /bits/ 64 <1324800000>; 347 opp-peak-kBps = <2188000 13516800>; 348 }; 349 350 cpu0_opp7: opp-1516800000 { 351 opp-hz = /bits/ 64 <1516800000>; 352 opp-peak-kBps = <3072000 15052800>; 353 }; 354 355 cpu0_opp8: opp-1612800000 { 356 opp-hz = /bits/ 64 <1612800000>; 357 opp-peak-kBps = <3072000 22118400>; 358 }; 359 360 cpu0_opp9: opp-1708800000 { 361 opp-hz = /bits/ 64 <1708800000>; 362 opp-peak-kBps = <4068000 23040000>; 363 }; 364 }; 365 366 cpu6_opp_table: opp-table-cpu6 { 367 compatible = "operating-points-v2"; 368 opp-shared; 369 370 cpu6_opp1: opp-300000000 { 371 opp-hz = /bits/ 64 <300000000>; 372 opp-peak-kBps = <400000 4800000>; 373 }; 374 375 cpu6_opp2: opp-652800000 { 376 opp-hz = /bits/ 64 <652800000>; 377 opp-peak-kBps = <400000 4800000>; 378 }; 379 380 cpu6_opp3: opp-825600000 { 381 opp-hz = /bits/ 64 <825600000>; 382 opp-peak-kBps = <1200000 4800000>; 383 }; 384 385 cpu6_opp4: opp-979200000 { 386 opp-hz = /bits/ 64 <979200000>; 387 opp-peak-kBps = <1200000 4800000>; 388 }; 389 390 cpu6_opp5: opp-1132800000 { 391 opp-hz = /bits/ 64 <1132800000>; 392 opp-peak-kBps = <2188000 8908800>; 393 }; 394 395 cpu6_opp6: opp-1363200000 { 396 opp-hz = /bits/ 64 <1363200000>; 397 opp-peak-kBps = <4068000 12902400>; 398 }; 399 400 cpu6_opp7: opp-1536000000 { 401 opp-hz = /bits/ 64 <1536000000>; 402 opp-peak-kBps = <4068000 12902400>; 403 }; 404 405 cpu6_opp8: opp-1747200000 { 406 opp-hz = /bits/ 64 <1747200000>; 407 opp-peak-kBps = <4068000 15052800>; 408 }; 409 410 cpu6_opp9: opp-1843200000 { 411 opp-hz = /bits/ 64 <1843200000>; 412 opp-peak-kBps = <4068000 15052800>; 413 }; 414 415 cpu6_opp10: opp-1996800000 { 416 opp-hz = /bits/ 64 <1996800000>; 417 opp-peak-kBps = <6220000 19046400>; 418 }; 419 }; 420 421 dsi_opp_table: opp-table-dsi { 422 compatible = "operating-points-v2"; 423 424 opp-19200000 { 425 opp-hz = /bits/ 64 <19200000>; 426 required-opps = <&rpmhpd_opp_min_svs>; 427 }; 428 429 opp-180000000 { 430 opp-hz = /bits/ 64 <180000000>; 431 required-opps = <&rpmhpd_opp_low_svs>; 432 }; 433 434 opp-275000000 { 435 opp-hz = /bits/ 64 <275000000>; 436 required-opps = <&rpmhpd_opp_svs>; 437 }; 438 439 opp-358000000 { 440 opp-hz = /bits/ 64 <358000000>; 441 required-opps = <&rpmhpd_opp_svs_l1>; 442 }; 443 }; 444 445 psci { 446 compatible = "arm,psci-1.0"; 447 method = "smc"; 448 449 cpu_pd0: power-domain-cpu0 { 450 #power-domain-cells = <0>; 451 power-domains = <&cluster_pd>; 452 domain-idle-states = <&little_cpu_sleep_0>; 453 }; 454 455 cpu_pd1: power-domain-cpu1 { 456 #power-domain-cells = <0>; 457 power-domains = <&cluster_pd>; 458 domain-idle-states = <&little_cpu_sleep_0>; 459 }; 460 461 cpu_pd2: power-domain-cpu2 { 462 #power-domain-cells = <0>; 463 power-domains = <&cluster_pd>; 464 domain-idle-states = <&little_cpu_sleep_0>; 465 }; 466 467 cpu_pd3: power-domain-cpu3 { 468 #power-domain-cells = <0>; 469 power-domains = <&cluster_pd>; 470 domain-idle-states = <&little_cpu_sleep_0>; 471 }; 472 473 cpu_pd4: power-domain-cpu4 { 474 #power-domain-cells = <0>; 475 power-domains = <&cluster_pd>; 476 domain-idle-states = <&little_cpu_sleep_0>; 477 }; 478 479 cpu_pd5: power-domain-cpu5 { 480 #power-domain-cells = <0>; 481 power-domains = <&cluster_pd>; 482 domain-idle-states = <&little_cpu_sleep_0>; 483 }; 484 485 cpu_pd6: power-domain-cpu6 { 486 #power-domain-cells = <0>; 487 power-domains = <&cluster_pd>; 488 domain-idle-states = <&big_cpu_sleep_0>; 489 }; 490 491 cpu_pd7: power-domain-cpu7 { 492 #power-domain-cells = <0>; 493 power-domains = <&cluster_pd>; 494 domain-idle-states = <&big_cpu_sleep_0>; 495 }; 496 497 cluster_pd: power-domain-cluster { 498 #power-domain-cells = <0>; 499 domain-idle-states = <&cluster_sleep_0>; 500 }; 501 }; 502 503 reserved-memory { 504 #address-cells = <2>; 505 #size-cells = <2>; 506 ranges; 507 508 hyp_mem: hyp-mem@85700000 { 509 reg = <0 0x85700000 0 0x600000>; 510 no-map; 511 }; 512 513 xbl_mem: xbl-mem@85e00000 { 514 reg = <0 0x85e00000 0 0x100000>; 515 no-map; 516 }; 517 518 aop_mem: aop-mem@85fc0000 { 519 reg = <0 0x85fc0000 0 0x20000>; 520 no-map; 521 }; 522 523 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 524 compatible = "qcom,cmd-db"; 525 reg = <0 0x85fe0000 0 0x20000>; 526 no-map; 527 }; 528 529 smem@86000000 { 530 compatible = "qcom,smem"; 531 reg = <0 0x86000000 0 0x200000>; 532 no-map; 533 hwlocks = <&tcsr_mutex 3>; 534 }; 535 536 tz_mem: tz@86200000 { 537 reg = <0 0x86200000 0 0x2d00000>; 538 no-map; 539 }; 540 541 camera_mem: camera-mem@8ab00000 { 542 reg = <0 0x8ab00000 0 0x500000>; 543 no-map; 544 }; 545 546 mpss_region: mpss@8b000000 { 547 reg = <0 0x8b000000 0 0x7e00000>; 548 no-map; 549 }; 550 551 venus_mem: venus@92e00000 { 552 reg = <0 0x92e00000 0 0x500000>; 553 no-map; 554 }; 555 556 wlan_msa_mem: wlan-msa@93300000 { 557 reg = <0 0x93300000 0 0x100000>; 558 no-map; 559 }; 560 561 cdsp_mem: cdsp@93400000 { 562 reg = <0 0x93400000 0 0x800000>; 563 no-map; 564 }; 565 566 mba_region: mba@93c00000 { 567 reg = <0 0x93c00000 0 0x200000>; 568 no-map; 569 }; 570 571 adsp_mem: adsp@93e00000 { 572 reg = <0 0x93e00000 0 0x1e00000>; 573 no-map; 574 }; 575 576 ipa_fw_mem: ipa-fw@95c00000 { 577 reg = <0 0x95c00000 0 0x10000>; 578 no-map; 579 }; 580 581 ipa_gsi_mem: ipa-gsi@95c10000 { 582 reg = <0 0x95c10000 0 0x5000>; 583 no-map; 584 }; 585 586 gpu_mem: gpu@95c15000 { 587 reg = <0 0x95c15000 0 0x2000>; 588 no-map; 589 }; 590 591 spss_mem: spss@97b00000 { 592 reg = <0 0x97b00000 0 0x100000>; 593 no-map; 594 }; 595 596 qseecom_mem: qseecom@9e400000 { 597 reg = <0 0x9e400000 0 0x1400000>; 598 no-map; 599 }; 600 }; 601 602 timer { 603 compatible = "arm,armv8-timer"; 604 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 605 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 606 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 607 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 608 }; 609 610 soc: soc@0 { 611 #address-cells = <2>; 612 #size-cells = <2>; 613 ranges = <0 0 0 0 0x10 0>; 614 dma-ranges = <0 0 0 0 0x10 0>; 615 compatible = "simple-bus"; 616 617 gcc: clock-controller@100000 { 618 compatible = "qcom,gcc-sdm670"; 619 reg = <0 0x00100000 0 0x1f0000>; 620 clocks = <&rpmhcc RPMH_CXO_CLK>, 621 <&rpmhcc RPMH_CXO_CLK_A>, 622 <&sleep_clk>; 623 clock-names = "bi_tcxo", 624 "bi_tcxo_ao", 625 "sleep_clk"; 626 #clock-cells = <1>; 627 #reset-cells = <1>; 628 #power-domain-cells = <1>; 629 }; 630 631 qfprom: qfprom@784000 { 632 compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; 633 reg = <0 0x00784000 0 0x1000>; 634 #address-cells = <1>; 635 #size-cells = <1>; 636 637 gpu_speed_bin: gpu_speed_bin@1a2 { 638 reg = <0x1a2 0x2>; 639 bits = <5 8>; 640 }; 641 642 qusb2_hstx_trim: hstx-trim@1eb { 643 reg = <0x1eb 0x1>; 644 bits = <1 4>; 645 }; 646 }; 647 648 sdhc_1: mmc@7c4000 { 649 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; 650 reg = <0 0x007c4000 0 0x1000>, 651 <0 0x007c5000 0 0x1000>, 652 <0 0x007c8000 0 0x8000>; 653 reg-names = "hc", "cqhci", "ice"; 654 655 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 657 interrupt-names = "hc_irq", "pwr_irq"; 658 659 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 660 <&gcc GCC_SDCC1_APPS_CLK>, 661 <&rpmhcc RPMH_CXO_CLK>, 662 <&gcc GCC_SDCC1_ICE_CORE_CLK>, 663 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 664 clock-names = "iface", "core", "xo", "ice", "bus"; 665 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, 666 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; 667 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 668 operating-points-v2 = <&sdhc1_opp_table>; 669 670 iommus = <&apps_smmu 0x140 0xf>; 671 672 pinctrl-names = "default", "sleep"; 673 pinctrl-0 = <&sdc1_state_on>; 674 pinctrl-1 = <&sdc1_state_off>; 675 power-domains = <&rpmhpd SDM670_CX>; 676 677 bus-width = <8>; 678 non-removable; 679 680 status = "disabled"; 681 682 sdhc1_opp_table: opp-table { 683 compatible = "operating-points-v2"; 684 685 opp-20000000 { 686 opp-hz = /bits/ 64 <20000000>; 687 required-opps = <&rpmhpd_opp_min_svs>; 688 opp-peak-kBps = <80000 80000>; 689 opp-avg-kBps = <52286 80000>; 690 }; 691 692 opp-50000000 { 693 opp-hz = /bits/ 64 <50000000>; 694 required-opps = <&rpmhpd_opp_low_svs>; 695 opp-peak-kBps = <200000 100000>; 696 opp-avg-kBps = <130718 100000>; 697 }; 698 699 opp-100000000 { 700 opp-hz = /bits/ 64 <100000000>; 701 required-opps = <&rpmhpd_opp_svs>; 702 opp-peak-kBps = <200000 130000>; 703 opp-avg-kBps = <130718 130000>; 704 }; 705 706 opp-384000000 { 707 opp-hz = /bits/ 64 <384000000>; 708 required-opps = <&rpmhpd_opp_nom>; 709 opp-peak-kBps = <4096000 4096000>; 710 opp-avg-kBps = <1338562 1338562>; 711 }; 712 }; 713 }; 714 715 gpi_dma0: dma-controller@800000 { 716 #dma-cells = <3>; 717 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 718 reg = <0 0x00800000 0 0x60000>; 719 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 732 dma-channels = <13>; 733 dma-channel-mask = <0xfa>; 734 iommus = <&apps_smmu 0x16 0x0>; 735 status = "disabled"; 736 }; 737 738 qupv3_id_0: geniqup@8c0000 { 739 compatible = "qcom,geni-se-qup"; 740 reg = <0 0x008c0000 0 0x6000>; 741 clock-names = "m-ahb", "s-ahb"; 742 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 743 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 744 iommus = <&apps_smmu 0x3 0x0>; 745 #address-cells = <2>; 746 #size-cells = <2>; 747 ranges; 748 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; 749 interconnect-names = "qup-core"; 750 status = "disabled"; 751 752 i2c0: i2c@880000 { 753 compatible = "qcom,geni-i2c"; 754 reg = <0 0x00880000 0 0x4000>; 755 clock-names = "se"; 756 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&qup_i2c0_default>; 759 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 power-domains = <&rpmhpd SDM670_CX>; 763 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 764 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 765 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 766 interconnect-names = "qup-core", "qup-config", "qup-memory"; 767 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 768 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 769 dma-names = "tx", "rx"; 770 status = "disabled"; 771 }; 772 773 i2c1: i2c@884000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0 0x00884000 0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&qup_i2c1_default>; 780 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 power-domains = <&rpmhpd SDM670_CX>; 784 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 785 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 786 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 787 interconnect-names = "qup-core", "qup-config", "qup-memory"; 788 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 789 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 790 dma-names = "tx", "rx"; 791 status = "disabled"; 792 }; 793 794 i2c2: i2c@888000 { 795 compatible = "qcom,geni-i2c"; 796 reg = <0 0x00888000 0 0x4000>; 797 clock-names = "se"; 798 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&qup_i2c2_default>; 801 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 power-domains = <&rpmhpd SDM670_CX>; 805 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 806 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 807 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 808 interconnect-names = "qup-core", "qup-config", "qup-memory"; 809 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 810 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 811 dma-names = "tx", "rx"; 812 status = "disabled"; 813 }; 814 815 i2c3: i2c@88c000 { 816 compatible = "qcom,geni-i2c"; 817 reg = <0 0x0088c000 0 0x4000>; 818 clock-names = "se"; 819 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&qup_i2c3_default>; 822 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 power-domains = <&rpmhpd SDM670_CX>; 826 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 827 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 828 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 829 interconnect-names = "qup-core", "qup-config", "qup-memory"; 830 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 831 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 832 dma-names = "tx", "rx"; 833 status = "disabled"; 834 }; 835 836 i2c4: i2c@890000 { 837 compatible = "qcom,geni-i2c"; 838 reg = <0 0x00890000 0 0x4000>; 839 clock-names = "se"; 840 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&qup_i2c4_default>; 843 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 power-domains = <&rpmhpd SDM670_CX>; 847 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 848 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 849 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 850 interconnect-names = "qup-core", "qup-config", "qup-memory"; 851 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 852 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 853 dma-names = "tx", "rx"; 854 status = "disabled"; 855 }; 856 857 i2c5: i2c@894000 { 858 compatible = "qcom,geni-i2c"; 859 reg = <0 0x00894000 0 0x4000>; 860 clock-names = "se"; 861 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_i2c5_default>; 864 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 power-domains = <&rpmhpd SDM670_CX>; 868 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 869 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 870 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 871 interconnect-names = "qup-core", "qup-config", "qup-memory"; 872 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 873 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 874 dma-names = "tx", "rx"; 875 status = "disabled"; 876 }; 877 878 i2c6: i2c@898000 { 879 compatible = "qcom,geni-i2c"; 880 reg = <0 0x00898000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_i2c6_default>; 885 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 power-domains = <&rpmhpd SDM670_CX>; 889 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 890 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 891 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 892 interconnect-names = "qup-core", "qup-config", "qup-memory"; 893 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 894 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 895 dma-names = "tx", "rx"; 896 status = "disabled"; 897 }; 898 899 i2c7: i2c@89c000 { 900 compatible = "qcom,geni-i2c"; 901 reg = <0 0x0089c000 0 0x4000>; 902 clock-names = "se"; 903 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&qup_i2c7_default>; 906 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 power-domains = <&rpmhpd SDM670_CX>; 910 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 911 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 912 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 913 interconnect-names = "qup-core", "qup-config", "qup-memory"; 914 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 915 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 916 dma-names = "tx", "rx"; 917 status = "disabled"; 918 }; 919 }; 920 921 gpi_dma1: dma-controller@a00000 { 922 #dma-cells = <3>; 923 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 924 reg = <0 0x00a00000 0 0x60000>; 925 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 938 dma-channels = <13>; 939 dma-channel-mask = <0xfa>; 940 iommus = <&apps_smmu 0x6d6 0x0>; 941 status = "disabled"; 942 }; 943 944 qupv3_id_1: geniqup@ac0000 { 945 compatible = "qcom,geni-se-qup"; 946 reg = <0 0x00ac0000 0 0x6000>; 947 clock-names = "m-ahb", "s-ahb"; 948 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 949 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 950 iommus = <&apps_smmu 0x6c3 0x0>; 951 #address-cells = <2>; 952 #size-cells = <2>; 953 ranges; 954 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; 955 interconnect-names = "qup-core"; 956 status = "disabled"; 957 958 i2c8: i2c@a80000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00a80000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c8_default>; 965 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 power-domains = <&rpmhpd SDM670_CX>; 969 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 970 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 971 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 972 interconnect-names = "qup-core", "qup-config", "qup-memory"; 973 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 974 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 975 dma-names = "tx", "rx"; 976 status = "disabled"; 977 }; 978 979 i2c9: i2c@a84000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0 0x00a84000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_i2c9_default>; 986 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 power-domains = <&rpmhpd SDM670_CX>; 990 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 991 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 992 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 993 interconnect-names = "qup-core", "qup-config", "qup-memory"; 994 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 995 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 996 dma-names = "tx", "rx"; 997 status = "disabled"; 998 }; 999 1000 i2c10: i2c@a88000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0 0x00a88000 0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c10_default>; 1007 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 power-domains = <&rpmhpd SDM670_CX>; 1011 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1012 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1013 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1014 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1015 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1016 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1017 dma-names = "tx", "rx"; 1018 status = "disabled"; 1019 }; 1020 1021 i2c11: i2c@a8c000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0 0x00a8c000 0 0x4000>; 1024 clock-names = "se"; 1025 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&qup_i2c11_default>; 1028 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 power-domains = <&rpmhpd SDM670_CX>; 1032 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1033 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1034 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1035 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1036 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1037 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1038 dma-names = "tx", "rx"; 1039 status = "disabled"; 1040 }; 1041 1042 i2c12: i2c@a90000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00a90000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c12_default>; 1049 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 power-domains = <&rpmhpd SDM670_CX>; 1053 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1054 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1055 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1056 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1057 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1058 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1059 dma-names = "tx", "rx"; 1060 status = "disabled"; 1061 }; 1062 1063 i2c13: i2c@a94000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x00a94000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_i2c13_default>; 1070 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 power-domains = <&rpmhpd SDM670_CX>; 1074 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1075 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1076 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1077 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1078 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1079 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1080 dma-names = "tx", "rx"; 1081 status = "disabled"; 1082 }; 1083 1084 i2c14: i2c@a98000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00a98000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_i2c14_default>; 1091 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 power-domains = <&rpmhpd SDM670_CX>; 1095 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1096 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1097 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1098 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1099 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1100 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1101 dma-names = "tx", "rx"; 1102 status = "disabled"; 1103 }; 1104 1105 i2c15: i2c@a9c000 { 1106 compatible = "qcom,geni-i2c"; 1107 reg = <0 0x00a9c000 0 0x4000>; 1108 clock-names = "se"; 1109 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_i2c15_default>; 1112 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 power-domains = <&rpmhpd SDM670_CX>; 1116 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1117 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1118 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1119 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1120 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1121 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1122 dma-names = "tx", "rx"; 1123 status = "disabled"; 1124 }; 1125 }; 1126 1127 mem_noc: interconnect@1380000 { 1128 compatible = "qcom,sdm670-mem-noc"; 1129 reg = <0 0x01380000 0 0x27200>; 1130 #interconnect-cells = <2>; 1131 qcom,bcm-voters = <&apps_bcm_voter>; 1132 }; 1133 1134 dc_noc: interconnect@14e0000 { 1135 compatible = "qcom,sdm670-dc-noc"; 1136 reg = <0 0x014e0000 0 0x400>; 1137 #interconnect-cells = <2>; 1138 qcom,bcm-voters = <&apps_bcm_voter>; 1139 }; 1140 1141 config_noc: interconnect@1500000 { 1142 compatible = "qcom,sdm670-config-noc"; 1143 reg = <0 0x01500000 0 0x5080>; 1144 #interconnect-cells = <2>; 1145 qcom,bcm-voters = <&apps_bcm_voter>; 1146 }; 1147 1148 system_noc: interconnect@1620000 { 1149 compatible = "qcom,sdm670-system-noc"; 1150 reg = <0 0x01620000 0 0x18080>; 1151 #interconnect-cells = <2>; 1152 qcom,bcm-voters = <&apps_bcm_voter>; 1153 }; 1154 1155 aggre1_noc: interconnect@16e0000 { 1156 compatible = "qcom,sdm670-aggre1-noc"; 1157 reg = <0 0x016e0000 0 0x15080>; 1158 #interconnect-cells = <2>; 1159 qcom,bcm-voters = <&apps_bcm_voter>; 1160 }; 1161 1162 aggre2_noc: interconnect@1700000 { 1163 compatible = "qcom,sdm670-aggre2-noc"; 1164 reg = <0 0x01700000 0 0x1f300>; 1165 #interconnect-cells = <2>; 1166 qcom,bcm-voters = <&apps_bcm_voter>; 1167 }; 1168 1169 mmss_noc: interconnect@1740000 { 1170 compatible = "qcom,sdm670-mmss-noc"; 1171 reg = <0 0x01740000 0 0x1c100>; 1172 #interconnect-cells = <2>; 1173 qcom,bcm-voters = <&apps_bcm_voter>; 1174 }; 1175 1176 tcsr_mutex: hwlock@1f40000 { 1177 compatible = "qcom,tcsr-mutex"; 1178 reg = <0 0x01f40000 0 0x20000>; 1179 #hwlock-cells = <1>; 1180 }; 1181 1182 tlmm: pinctrl@3400000 { 1183 compatible = "qcom,sdm670-tlmm"; 1184 reg = <0 0x03400000 0 0xc00000>; 1185 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1186 gpio-controller; 1187 #gpio-cells = <2>; 1188 interrupt-controller; 1189 #interrupt-cells = <2>; 1190 gpio-ranges = <&tlmm 0 0 151>; 1191 wakeup-parent = <&pdc>; 1192 1193 cci0_default: cci0-default-state { 1194 pins = "gpio17", "gpio18"; 1195 function = "cci_i2c"; 1196 drive-strength = <2>; 1197 bias-pull-up; 1198 }; 1199 1200 cci0_sleep: cci0-sleep-state { 1201 pins = "gpio17", "gpio18"; 1202 function = "cci_i2c"; 1203 drive-strength = <2>; 1204 bias-pull-down; 1205 }; 1206 1207 cci1_default: cci1-default-state { 1208 pins = "gpio19", "gpio20"; 1209 function = "cci_i2c"; 1210 drive-strength = <2>; 1211 bias-pull-up; 1212 }; 1213 1214 cci1_sleep: cci1-sleep-state { 1215 pins = "gpio19", "gpio20"; 1216 function = "cci_i2c"; 1217 drive-strength = <2>; 1218 bias-pull-down; 1219 }; 1220 1221 qup_i2c0_default: qup-i2c0-default-state { 1222 pins = "gpio0", "gpio1"; 1223 function = "qup0"; 1224 }; 1225 1226 qup_i2c1_default: qup-i2c1-default-state { 1227 pins = "gpio17", "gpio18"; 1228 function = "qup1"; 1229 }; 1230 1231 qup_i2c2_default: qup-i2c2-default-state { 1232 pins = "gpio27", "gpio28"; 1233 function = "qup2"; 1234 }; 1235 1236 qup_i2c3_default: qup-i2c3-default-state { 1237 pins = "gpio41", "gpio42"; 1238 function = "qup3"; 1239 }; 1240 1241 qup_i2c4_default: qup-i2c4-default-state { 1242 pins = "gpio89", "gpio90"; 1243 function = "qup4"; 1244 }; 1245 1246 qup_i2c5_default: qup-i2c5-default-state { 1247 pins = "gpio85", "gpio86"; 1248 function = "qup5"; 1249 }; 1250 1251 qup_i2c6_default: qup-i2c6-default-state { 1252 pins = "gpio45", "gpio46"; 1253 function = "qup6"; 1254 }; 1255 1256 qup_i2c7_default: qup-i2c7-default-state { 1257 pins = "gpio93", "gpio94"; 1258 function = "qup7"; 1259 }; 1260 1261 qup_i2c8_default: qup-i2c8-default-state { 1262 pins = "gpio65", "gpio66"; 1263 function = "qup8"; 1264 }; 1265 1266 qup_i2c9_default: qup-i2c9-default-state { 1267 pins = "gpio6", "gpio7"; 1268 function = "qup9"; 1269 }; 1270 1271 qup_i2c10_default: qup-i2c10-default-state { 1272 pins = "gpio55", "gpio56"; 1273 function = "qup10"; 1274 }; 1275 1276 qup_i2c11_default: qup-i2c11-default-state { 1277 pins = "gpio31", "gpio32"; 1278 function = "qup11"; 1279 }; 1280 1281 qup_i2c12_default: qup-i2c12-default-state { 1282 pins = "gpio49", "gpio50"; 1283 function = "qup12"; 1284 }; 1285 1286 qup_i2c13_default: qup-i2c13-default-state { 1287 pins = "gpio105", "gpio106"; 1288 function = "qup13"; 1289 }; 1290 1291 qup_i2c14_default: qup-i2c14-default-state { 1292 pins = "gpio33", "gpio34"; 1293 function = "qup14"; 1294 }; 1295 1296 qup_i2c15_default: qup-i2c15-default-state { 1297 pins = "gpio81", "gpio82"; 1298 function = "qup15"; 1299 }; 1300 1301 sdc1_state_on: sdc1-on-state { 1302 clk-pins { 1303 pins = "sdc1_clk"; 1304 bias-disable; 1305 drive-strength = <16>; 1306 }; 1307 1308 cmd-pins { 1309 pins = "sdc1_cmd"; 1310 bias-pull-up; 1311 drive-strength = <10>; 1312 }; 1313 1314 data-pins { 1315 pins = "sdc1_data"; 1316 bias-pull-up; 1317 drive-strength = <10>; 1318 }; 1319 1320 rclk-pins { 1321 pins = "sdc1_rclk"; 1322 bias-pull-down; 1323 }; 1324 }; 1325 1326 sdc1_state_off: sdc1-off-state { 1327 clk-pins { 1328 pins = "sdc1_clk"; 1329 bias-disable; 1330 drive-strength = <2>; 1331 }; 1332 1333 cmd-pins { 1334 pins = "sdc1_cmd"; 1335 bias-pull-up; 1336 drive-strength = <2>; 1337 }; 1338 1339 data-pins { 1340 pins = "sdc1_data"; 1341 bias-pull-up; 1342 drive-strength = <2>; 1343 }; 1344 1345 rclk-pins { 1346 pins = "sdc1_rclk"; 1347 bias-pull-down; 1348 }; 1349 }; 1350 }; 1351 1352 gpu: gpu@5000000 { 1353 compatible = "qcom,adreno-615.0", "qcom,adreno"; 1354 1355 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>; 1356 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 1357 1358 /* 1359 * Look ma, no clocks! The GPU clocks and power are 1360 * controlled entirely by the GMU 1361 */ 1362 1363 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1364 1365 iommus = <&adreno_smmu 0>; 1366 1367 operating-points-v2 = <&gpu_opp_table>; 1368 1369 qcom,gmu = <&gmu>; 1370 1371 interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>; 1372 interconnect-names = "gfx-mem"; 1373 1374 nvmem-cells = <&gpu_speed_bin>; 1375 nvmem-cell-names = "speed_bin"; 1376 1377 status = "disabled"; 1378 1379 gpu_opp_table: opp-table { 1380 compatible = "operating-points-v2"; 1381 1382 opp-780000000 { 1383 opp-hz = /bits/ 64 <780000000>; 1384 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1385 opp-peak-kBps = <7216000>; 1386 opp-supported-hw = <0x8>; 1387 }; 1388 1389 opp-750000000 { 1390 opp-hz = /bits/ 64 <750000000>; 1391 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1392 opp-peak-kBps = <7216000>; 1393 opp-supported-hw = <0x8>; 1394 }; 1395 1396 opp-700000000 { 1397 opp-hz = /bits/ 64 <700000000>; 1398 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1399 opp-peak-kBps = <7216000>; 1400 opp-supported-hw = <0x4>; 1401 }; 1402 1403 opp-650000000 { 1404 opp-hz = /bits/ 64 <650000000>; 1405 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1406 opp-peak-kBps = <7216000>; 1407 opp-supported-hw = <0xc>; 1408 }; 1409 1410 opp-565000000 { 1411 opp-hz = /bits/ 64 <565000000>; 1412 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1413 opp-peak-kBps = <7216000>; 1414 opp-supported-hw = <0xc>; 1415 }; 1416 1417 opp-504000000 { 1418 opp-hz = /bits/ 64 <504000000>; 1419 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1420 opp-peak-kBps = <7216000>; 1421 opp-supported-hw = <0x2>; 1422 }; 1423 1424 opp-430000000 { 1425 opp-hz = /bits/ 64 <430000000>; 1426 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1427 opp-peak-kBps = <7216000>; 1428 opp-supported-hw = <0xf>; 1429 }; 1430 1431 opp-355000000 { 1432 opp-hz = /bits/ 64 <355000000>; 1433 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1434 opp-peak-kBps = <6220000>; 1435 opp-supported-hw = <0xf>; 1436 }; 1437 1438 opp-267000000 { 1439 opp-hz = /bits/ 64 <267000000>; 1440 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1441 opp-peak-kBps = <4068000>; 1442 opp-supported-hw = <0xf>; 1443 }; 1444 1445 opp-180000000 { 1446 opp-hz = /bits/ 64 <180000000>; 1447 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1448 opp-peak-kBps = <1804000>; 1449 opp-supported-hw = <0xf>; 1450 }; 1451 }; 1452 }; 1453 1454 adreno_smmu: iommu@5040000 { 1455 compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1456 reg = <0 0x05040000 0 0x10000>; 1457 #iommu-cells = <1>; 1458 #global-interrupts = <2>; 1459 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 1462 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 1463 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 1464 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 1465 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 1466 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 1467 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 1468 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 1469 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1470 <&gcc GCC_GPU_CFG_AHB_CLK>; 1471 clock-names = "bus", "iface"; 1472 1473 power-domains = <&gpucc GPU_CX_GDSC>; 1474 }; 1475 1476 gmu: gmu@506a000 { 1477 compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu"; 1478 1479 reg = <0 0x0506a000 0 0x30000>, 1480 <0 0x0b280000 0 0x10000>, 1481 <0 0x0b480000 0 0x10000>; 1482 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1483 1484 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1486 interrupt-names = "hfi", "gmu"; 1487 1488 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1489 <&gpucc GPU_CC_CXO_CLK>, 1490 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1491 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1492 clock-names = "gmu", "cxo", "axi", "memnoc"; 1493 1494 power-domains = <&gpucc GPU_CX_GDSC>, 1495 <&gpucc GPU_GX_GDSC>; 1496 power-domain-names = "cx", "gx"; 1497 1498 iommus = <&adreno_smmu 5>; 1499 1500 operating-points-v2 = <&gmu_opp_table>; 1501 1502 gmu_opp_table: opp-table { 1503 compatible = "operating-points-v2"; 1504 1505 opp-200000000 { 1506 opp-hz = /bits/ 64 <200000000>; 1507 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1508 }; 1509 }; 1510 }; 1511 1512 gpucc: clock-controller@5090000 { 1513 compatible = "qcom,sdm845-gpucc"; 1514 reg = <0 0x05090000 0 0x9000>; 1515 #clock-cells = <1>; 1516 #reset-cells = <1>; 1517 #power-domain-cells = <1>; 1518 clocks = <&rpmhcc RPMH_CXO_CLK>, 1519 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1520 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1521 clock-names = "bi_tcxo", 1522 "gcc_gpu_gpll0_clk_src", 1523 "gcc_gpu_gpll0_div_clk_src"; 1524 }; 1525 1526 usb_1_hsphy: phy@88e2000 { 1527 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; 1528 reg = <0 0x088e2000 0 0x400>; 1529 #phy-cells = <0>; 1530 1531 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1532 <&rpmhcc RPMH_CXO_CLK>; 1533 clock-names = "cfg_ahb", "ref"; 1534 1535 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1536 1537 nvmem-cells = <&qusb2_hstx_trim>; 1538 1539 status = "disabled"; 1540 }; 1541 1542 usb_1: usb@a6f8800 { 1543 compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; 1544 reg = <0 0x0a6f8800 0 0x400>; 1545 #address-cells = <2>; 1546 #size-cells = <2>; 1547 ranges; 1548 dma-ranges; 1549 1550 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1551 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1552 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1553 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1554 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1555 clock-names = "cfg_noc", 1556 "core", 1557 "iface", 1558 "sleep", 1559 "mock_utmi"; 1560 1561 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1562 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1563 assigned-clock-rates = <19200000>, <150000000>; 1564 1565 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1566 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1567 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 1568 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 1569 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 1570 interrupt-names = "pwr_event", 1571 "hs_phy_irq", 1572 "dp_hs_phy_irq", 1573 "dm_hs_phy_irq", 1574 "ss_phy_irq"; 1575 1576 power-domains = <&gcc USB30_PRIM_GDSC>; 1577 1578 resets = <&gcc GCC_USB30_PRIM_BCR>; 1579 1580 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, 1581 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1582 interconnect-names = "usb-ddr", "apps-usb"; 1583 1584 status = "disabled"; 1585 1586 usb_1_dwc3: usb@a600000 { 1587 compatible = "snps,dwc3"; 1588 reg = <0 0x0a600000 0 0xcd00>; 1589 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1590 iommus = <&apps_smmu 0x740 0>; 1591 snps,dis_u2_susphy_quirk; 1592 snps,dis_enblslpm_quirk; 1593 phys = <&usb_1_hsphy>; 1594 phy-names = "usb2-phy"; 1595 }; 1596 }; 1597 1598 pdc: interrupt-controller@b220000 { 1599 compatible = "qcom,sdm670-pdc", "qcom,pdc"; 1600 reg = <0 0x0b220000 0 0x30000>; 1601 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>, 1602 <54 534 24>, <79 559 15>, <94 609 15>, 1603 <115 630 7>; 1604 #interrupt-cells = <2>; 1605 interrupt-parent = <&intc>; 1606 interrupt-controller; 1607 }; 1608 1609 spmi_bus: spmi@c440000 { 1610 compatible = "qcom,spmi-pmic-arb"; 1611 reg = <0 0x0c440000 0 0x1100>, 1612 <0 0x0c600000 0 0x2000000>, 1613 <0 0x0e600000 0 0x100000>, 1614 <0 0x0e700000 0 0xa0000>, 1615 <0 0x0c40a000 0 0x26000>; 1616 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1617 interrupt-names = "periph_irq"; 1618 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1619 qcom,ee = <0>; 1620 qcom,channel = <0>; 1621 #address-cells = <2>; 1622 #size-cells = <0>; 1623 interrupt-controller; 1624 #interrupt-cells = <4>; 1625 }; 1626 1627 cci: cci@ac4a000 { 1628 compatible = "qcom,sdm670-cci", "qcom,msm8996-cci"; 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 1632 reg = <0 0x0ac4a000 0 0x4000>; 1633 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 1634 power-domains = <&camcc TITAN_TOP_GDSC>; 1635 1636 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 1637 <&camcc CAM_CC_SOC_AHB_CLK>, 1638 <&camcc CAM_CC_CPAS_AHB_CLK>, 1639 <&camcc CAM_CC_CCI_CLK>; 1640 clock-names = "camnoc_axi", 1641 "soc_ahb", 1642 "cpas_ahb", 1643 "cci"; 1644 1645 pinctrl-names = "default", "sleep"; 1646 pinctrl-0 = <&cci0_default &cci1_default>; 1647 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1648 1649 status = "disabled"; 1650 1651 cci_i2c0: i2c-bus@0 { 1652 reg = <0>; 1653 clock-frequency = <1000000>; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 }; 1657 1658 cci_i2c1: i2c-bus@1 { 1659 reg = <1>; 1660 clock-frequency = <1000000>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 }; 1664 }; 1665 1666 camss: isp@acb3000 { 1667 compatible = "qcom,sdm670-camss"; 1668 reg = <0 0x0acb3000 0 0x1000>, 1669 <0 0x0acba000 0 0x1000>, 1670 <0 0x0acc8000 0 0x1000>, 1671 <0 0x0ac65000 0 0x1000>, 1672 <0 0x0ac66000 0 0x1000>, 1673 <0 0x0ac67000 0 0x1000>, 1674 <0 0x0acaf000 0 0x4000>, 1675 <0 0x0acb6000 0 0x4000>, 1676 <0 0x0acc4000 0 0x4000>; 1677 reg-names = "csid0", 1678 "csid1", 1679 "csid2", 1680 "csiphy0", 1681 "csiphy1", 1682 "csiphy2", 1683 "vfe0", 1684 "vfe1", 1685 "vfe_lite"; 1686 1687 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 1688 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 1689 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 1690 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 1691 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 1692 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 1693 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 1694 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 1695 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; 1696 interrupt-names = "csid0", 1697 "csid1", 1698 "csid2", 1699 "csiphy0", 1700 "csiphy1", 1701 "csiphy2", 1702 "vfe0", 1703 "vfe1", 1704 "vfe_lite"; 1705 1706 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 1707 <&camcc CAM_CC_CPAS_AHB_CLK>, 1708 <&camcc CAM_CC_IFE_0_CSID_CLK>, 1709 <&camcc CAM_CC_IFE_1_CSID_CLK>, 1710 <&camcc CAM_CC_IFE_LITE_CSID_CLK>, 1711 <&camcc CAM_CC_CSIPHY0_CLK>, 1712 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 1713 <&camcc CAM_CC_CSIPHY1_CLK>, 1714 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 1715 <&camcc CAM_CC_CSIPHY2_CLK>, 1716 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 1717 <&gcc GCC_CAMERA_AHB_CLK>, 1718 <&gcc GCC_CAMERA_AXI_CLK>, 1719 <&camcc CAM_CC_SOC_AHB_CLK>, 1720 <&camcc CAM_CC_IFE_0_CLK>, 1721 <&camcc CAM_CC_IFE_0_AXI_CLK>, 1722 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 1723 <&camcc CAM_CC_IFE_1_CLK>, 1724 <&camcc CAM_CC_IFE_1_AXI_CLK>, 1725 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 1726 <&camcc CAM_CC_IFE_LITE_CLK>, 1727 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; 1728 clock-names = "camnoc_axi", 1729 "cpas_ahb", 1730 "csi0", 1731 "csi1", 1732 "csi2", 1733 "csiphy0", 1734 "csiphy0_timer", 1735 "csiphy1", 1736 "csiphy1_timer", 1737 "csiphy2", 1738 "csiphy2_timer", 1739 "gcc_camera_ahb", 1740 "gcc_camera_axi", 1741 "soc_ahb", 1742 "vfe0", 1743 "vfe0_axi", 1744 "vfe0_cphy_rx", 1745 "vfe1", 1746 "vfe1_axi", 1747 "vfe1_cphy_rx", 1748 "vfe_lite", 1749 "vfe_lite_cphy_rx"; 1750 1751 iommus = <&apps_smmu 0x808 0x0>, 1752 <&apps_smmu 0x810 0x8>, 1753 <&apps_smmu 0xc08 0x0>, 1754 <&apps_smmu 0xc10 0x8>; 1755 1756 power-domains = <&camcc IFE_0_GDSC>, 1757 <&camcc IFE_1_GDSC>, 1758 <&camcc TITAN_TOP_GDSC>; 1759 power-domain-names = "ife0", 1760 "ife1", 1761 "top"; 1762 1763 status = "disabled"; 1764 1765 ports { 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 1769 port@0 { 1770 reg = <0>; 1771 1772 camss_endpoint0: endpoint { 1773 status = "disabled"; 1774 }; 1775 }; 1776 1777 port@1 { 1778 reg = <1>; 1779 1780 camss_endpoint1: endpoint { 1781 status = "disabled"; 1782 }; 1783 }; 1784 1785 port@2 { 1786 reg = <2>; 1787 1788 camss_endpoint2: endpoint { 1789 status = "disabled"; 1790 }; 1791 }; 1792 }; 1793 }; 1794 1795 camcc: clock-controller@ad00000 { 1796 compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc"; 1797 reg = <0 0x0ad00000 0 0x10000>; 1798 clocks = <&rpmhcc RPMH_CXO_CLK>; 1799 clock-names = "bi_tcxo"; 1800 #clock-cells = <1>; 1801 #reset-cells = <1>; 1802 #power-domain-cells = <1>; 1803 }; 1804 1805 mdss: display-subsystem@ae00000 { 1806 compatible = "qcom,sdm670-mdss"; 1807 reg = <0 0x0ae00000 0 0x1000>; 1808 reg-names = "mdss"; 1809 1810 power-domains = <&dispcc MDSS_GDSC>; 1811 1812 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1813 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1814 clock-names = "iface", "core"; 1815 1816 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1817 interrupt-controller; 1818 #interrupt-cells = <1>; 1819 1820 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, 1821 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; 1822 interconnect-names = "mdp0-mem", "mdp1-mem"; 1823 1824 iommus = <&apps_smmu 0x880 0x8>, 1825 <&apps_smmu 0xc80 0x8>; 1826 1827 #address-cells = <2>; 1828 #size-cells = <2>; 1829 ranges; 1830 1831 status = "disabled"; 1832 1833 mdss_mdp: display-controller@ae01000 { 1834 compatible = "qcom,sdm670-dpu"; 1835 reg = <0 0x0ae01000 0 0x8f000>, 1836 <0 0x0aeb0000 0 0x3000>; 1837 reg-names = "mdp", "vbif"; 1838 1839 clocks = <&gcc GCC_DISP_AXI_CLK>, 1840 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1841 <&dispcc DISP_CC_MDSS_AXI_CLK>, 1842 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1843 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1844 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 1845 1846 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1847 assigned-clock-rates = <19200000>; 1848 operating-points-v2 = <&mdp_opp_table>; 1849 power-domains = <&rpmhpd SDM670_CX>; 1850 1851 interrupt-parent = <&mdss>; 1852 interrupts = <0>; 1853 1854 ports { 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 1858 port@0 { 1859 reg = <0>; 1860 dpu_intf0_out: endpoint { 1861 remote-endpoint = <&mdss_dsi0_in>; 1862 }; 1863 }; 1864 1865 port@1 { 1866 reg = <1>; 1867 dpu_intf1_out: endpoint { 1868 remote-endpoint = <&mdss_dsi1_in>; 1869 }; 1870 }; 1871 }; 1872 1873 mdp_opp_table: opp-table { 1874 compatible = "operating-points-v2"; 1875 1876 opp-19200000 { 1877 opp-hz = /bits/ 64 <19200000>; 1878 required-opps = <&rpmhpd_opp_min_svs>; 1879 }; 1880 1881 opp-171428571 { 1882 opp-hz = /bits/ 64 <171428571>; 1883 required-opps = <&rpmhpd_opp_low_svs>; 1884 }; 1885 1886 opp-358000000 { 1887 opp-hz = /bits/ 64 <358000000>; 1888 required-opps = <&rpmhpd_opp_svs_l1>; 1889 }; 1890 1891 opp-430000000 { 1892 opp-hz = /bits/ 64 <430000000>; 1893 required-opps = <&rpmhpd_opp_nom>; 1894 }; 1895 }; 1896 }; 1897 1898 mdss_dsi0: dsi@ae94000 { 1899 compatible = "qcom,sdm670-dsi-ctrl", 1900 "qcom,mdss-dsi-ctrl"; 1901 reg = <0 0x0ae94000 0 0x400>; 1902 reg-names = "dsi_ctrl"; 1903 1904 interrupt-parent = <&mdss>; 1905 interrupts = <4>; 1906 1907 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1908 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1909 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1910 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1911 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1912 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1913 clock-names = "byte", 1914 "byte_intf", 1915 "pixel", 1916 "core", 1917 "iface", 1918 "bus"; 1919 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1920 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1921 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1922 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1923 1924 operating-points-v2 = <&dsi_opp_table>; 1925 power-domains = <&rpmhpd SDM670_CX>; 1926 1927 phys = <&mdss_dsi0_phy>; 1928 1929 #address-cells = <1>; 1930 #size-cells = <0>; 1931 1932 status = "disabled"; 1933 1934 ports { 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 1938 port@0 { 1939 reg = <0>; 1940 mdss_dsi0_in: endpoint { 1941 remote-endpoint = <&dpu_intf0_out>; 1942 }; 1943 }; 1944 1945 port@1 { 1946 reg = <1>; 1947 mdss_dsi0_out: endpoint { 1948 }; 1949 }; 1950 }; 1951 }; 1952 1953 mdss_dsi0_phy: phy@ae94400 { 1954 compatible = "qcom,dsi-phy-10nm"; 1955 reg = <0 0x0ae94400 0 0x200>, 1956 <0 0x0ae94600 0 0x280>, 1957 <0 0x0ae94a00 0 0x1e0>; 1958 reg-names = "dsi_phy", 1959 "dsi_phy_lane", 1960 "dsi_pll"; 1961 1962 #clock-cells = <1>; 1963 #phy-cells = <0>; 1964 1965 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1966 <&rpmhcc RPMH_CXO_CLK>; 1967 clock-names = "iface", "ref"; 1968 1969 status = "disabled"; 1970 }; 1971 1972 mdss_dsi1: dsi@ae96000 { 1973 compatible = "qcom,sdm670-dsi-ctrl", 1974 "qcom,mdss-dsi-ctrl"; 1975 reg = <0 0x0ae96000 0 0x400>; 1976 reg-names = "dsi_ctrl"; 1977 1978 interrupt-parent = <&mdss>; 1979 interrupts = <5>; 1980 1981 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 1982 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 1983 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 1984 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 1985 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1986 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1987 clock-names = "byte", 1988 "byte_intf", 1989 "pixel", 1990 "core", 1991 "iface", 1992 "bus"; 1993 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 1994 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 1995 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1996 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 1997 1998 operating-points-v2 = <&dsi_opp_table>; 1999 power-domains = <&rpmhpd SDM670_CX>; 2000 2001 phys = <&mdss_dsi1_phy>; 2002 2003 #address-cells = <1>; 2004 #size-cells = <0>; 2005 2006 status = "disabled"; 2007 2008 ports { 2009 #address-cells = <1>; 2010 #size-cells = <0>; 2011 2012 port@0 { 2013 reg = <0>; 2014 mdss_dsi1_in: endpoint { 2015 remote-endpoint = <&dpu_intf1_out>; 2016 }; 2017 }; 2018 2019 port@1 { 2020 reg = <1>; 2021 mdss_dsi1_out: endpoint { 2022 }; 2023 }; 2024 }; 2025 }; 2026 2027 mdss_dsi1_phy: phy@ae96400 { 2028 compatible = "qcom,dsi-phy-10nm"; 2029 reg = <0 0x0ae96400 0 0x200>, 2030 <0 0x0ae96600 0 0x280>, 2031 <0 0x0ae96a00 0 0x10e>; 2032 reg-names = "dsi_phy", 2033 "dsi_phy_lane", 2034 "dsi_pll"; 2035 2036 #clock-cells = <1>; 2037 #phy-cells = <0>; 2038 2039 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2040 <&rpmhcc RPMH_CXO_CLK>; 2041 clock-names = "iface", "ref"; 2042 2043 status = "disabled"; 2044 }; 2045 }; 2046 2047 dispcc: clock-controller@af00000 { 2048 compatible = "qcom,sdm845-dispcc"; 2049 reg = <0 0x0af00000 0 0x10000>; 2050 clocks = <&rpmhcc RPMH_CXO_CLK>, 2051 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2052 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 2053 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2054 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2055 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2056 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 2057 <0>, 2058 <0>; 2059 clock-names = "bi_tcxo", 2060 "gcc_disp_gpll0_clk_src", 2061 "gcc_disp_gpll0_div_clk_src", 2062 "dsi0_phy_pll_out_byteclk", 2063 "dsi0_phy_pll_out_dsiclk", 2064 "dsi1_phy_pll_out_byteclk", 2065 "dsi1_phy_pll_out_dsiclk", 2066 "dp_link_clk_divsel_ten", 2067 "dp_vco_divided_clk_src_mux"; 2068 #clock-cells = <1>; 2069 #reset-cells = <1>; 2070 #power-domain-cells = <1>; 2071 }; 2072 2073 apps_smmu: iommu@15000000 { 2074 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2075 reg = <0 0x15000000 0 0x80000>; 2076 #iommu-cells = <2>; 2077 #global-interrupts = <1>; 2078 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 2143 dma-coherent; 2144 }; 2145 2146 gladiator_noc: interconnect@17900000 { 2147 compatible = "qcom,sdm670-gladiator-noc"; 2148 reg = <0 0x17900000 0 0xd080>; 2149 #interconnect-cells = <2>; 2150 qcom,bcm-voters = <&apps_bcm_voter>; 2151 }; 2152 2153 apps_rsc: rsc@179c0000 { 2154 compatible = "qcom,rpmh-rsc"; 2155 reg = <0 0x179c0000 0 0x10000>, 2156 <0 0x179d0000 0 0x10000>, 2157 <0 0x179e0000 0 0x10000>; 2158 reg-names = "drv-0", "drv-1", "drv-2"; 2159 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2162 label = "apps_rsc"; 2163 qcom,tcs-offset = <0xd00>; 2164 qcom,drv-id = <2>; 2165 qcom,tcs-config = <ACTIVE_TCS 2>, 2166 <SLEEP_TCS 3>, 2167 <WAKE_TCS 3>, 2168 <CONTROL_TCS 1>; 2169 power-domains = <&cluster_pd>; 2170 2171 apps_bcm_voter: bcm-voter { 2172 compatible = "qcom,bcm-voter"; 2173 }; 2174 2175 rpmhcc: clock-controller { 2176 compatible = "qcom,sdm670-rpmh-clk"; 2177 #clock-cells = <1>; 2178 clock-names = "xo"; 2179 clocks = <&xo_board>; 2180 }; 2181 2182 rpmhpd: power-controller { 2183 compatible = "qcom,sdm670-rpmhpd"; 2184 #power-domain-cells = <1>; 2185 operating-points-v2 = <&rpmhpd_opp_table>; 2186 2187 rpmhpd_opp_table: opp-table { 2188 compatible = "operating-points-v2"; 2189 2190 rpmhpd_opp_ret: opp1 { 2191 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2192 }; 2193 2194 rpmhpd_opp_min_svs: opp2 { 2195 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2196 }; 2197 2198 rpmhpd_opp_low_svs: opp3 { 2199 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2200 }; 2201 2202 rpmhpd_opp_svs: opp4 { 2203 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2204 }; 2205 2206 rpmhpd_opp_svs_l1: opp5 { 2207 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2208 }; 2209 2210 rpmhpd_opp_nom: opp6 { 2211 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2212 }; 2213 2214 rpmhpd_opp_nom_l1: opp7 { 2215 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2216 }; 2217 2218 rpmhpd_opp_nom_l2: opp8 { 2219 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2220 }; 2221 2222 rpmhpd_opp_turbo: opp9 { 2223 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2224 }; 2225 2226 rpmhpd_opp_turbo_l1: opp10 { 2227 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2228 }; 2229 }; 2230 }; 2231 }; 2232 2233 intc: interrupt-controller@17a00000 { 2234 compatible = "arm,gic-v3"; 2235 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2236 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2237 interrupt-controller; 2238 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2239 #interrupt-cells = <3>; 2240 }; 2241 2242 osm_l3: interconnect@17d41000 { 2243 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3"; 2244 reg = <0 0x17d41000 0 0x1400>; 2245 2246 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2247 clock-names = "xo", "alternate"; 2248 2249 #interconnect-cells = <1>; 2250 }; 2251 2252 cpufreq_hw: cpufreq@17d43000 { 2253 compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw"; 2254 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 2255 reg-names = "freq-domain0", "freq-domain1"; 2256 2257 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2258 clock-names = "xo", "alternate"; 2259 2260 #freq-domain-cells = <1>; 2261 }; 2262 }; 2263}; 2264