1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 12#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sc8280xp.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32764>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a78c"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <981>; 54 dynamic-power-coefficient = <549>; 55 next-level-cache = <&l2_0>; 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 61 #cooling-cells = <2>; 62 l2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&l3_0>; 67 l3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a78c"; 78 reg = <0x0 0x100>; 79 clocks = <&cpufreq_hw 0>; 80 enable-method = "psci"; 81 capacity-dmips-mhz = <981>; 82 dynamic-power-coefficient = <549>; 83 next-level-cache = <&l2_100>; 84 power-domains = <&cpu_pd1>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 89 #cooling-cells = <2>; 90 l2_100: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 }; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a78c"; 101 reg = <0x0 0x200>; 102 clocks = <&cpufreq_hw 0>; 103 enable-method = "psci"; 104 capacity-dmips-mhz = <981>; 105 dynamic-power-coefficient = <549>; 106 next-level-cache = <&l2_200>; 107 power-domains = <&cpu_pd2>; 108 power-domain-names = "psci"; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 112 #cooling-cells = <2>; 113 l2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&l3_0>; 118 }; 119 }; 120 121 cpu3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a78c"; 124 reg = <0x0 0x300>; 125 clocks = <&cpufreq_hw 0>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <981>; 128 dynamic-power-coefficient = <549>; 129 next-level-cache = <&l2_300>; 130 power-domains = <&cpu_pd3>; 131 power-domain-names = "psci"; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 operating-points-v2 = <&cpu0_opp_table>; 134 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 135 #cooling-cells = <2>; 136 l2_300: l2-cache { 137 compatible = "cache"; 138 cache-level = <2>; 139 cache-unified; 140 next-level-cache = <&l3_0>; 141 }; 142 }; 143 144 cpu4: cpu@400 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-x1c"; 147 reg = <0x0 0x400>; 148 clocks = <&cpufreq_hw 1>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <1024>; 151 dynamic-power-coefficient = <590>; 152 next-level-cache = <&l2_400>; 153 power-domains = <&cpu_pd4>; 154 power-domain-names = "psci"; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 operating-points-v2 = <&cpu4_opp_table>; 157 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 158 #cooling-cells = <2>; 159 l2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 next-level-cache = <&l3_0>; 164 }; 165 }; 166 167 cpu5: cpu@500 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-x1c"; 170 reg = <0x0 0x500>; 171 clocks = <&cpufreq_hw 1>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 dynamic-power-coefficient = <590>; 175 next-level-cache = <&l2_500>; 176 power-domains = <&cpu_pd5>; 177 power-domain-names = "psci"; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 operating-points-v2 = <&cpu4_opp_table>; 180 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 181 #cooling-cells = <2>; 182 l2_500: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&l3_0>; 187 }; 188 }; 189 190 cpu6: cpu@600 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-x1c"; 193 reg = <0x0 0x600>; 194 clocks = <&cpufreq_hw 1>; 195 enable-method = "psci"; 196 capacity-dmips-mhz = <1024>; 197 dynamic-power-coefficient = <590>; 198 next-level-cache = <&l2_600>; 199 power-domains = <&cpu_pd6>; 200 power-domain-names = "psci"; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu4_opp_table>; 203 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 204 #cooling-cells = <2>; 205 l2_600: l2-cache { 206 compatible = "cache"; 207 cache-level = <2>; 208 cache-unified; 209 next-level-cache = <&l3_0>; 210 }; 211 }; 212 213 cpu7: cpu@700 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-x1c"; 216 reg = <0x0 0x700>; 217 clocks = <&cpufreq_hw 1>; 218 enable-method = "psci"; 219 capacity-dmips-mhz = <1024>; 220 dynamic-power-coefficient = <590>; 221 next-level-cache = <&l2_700>; 222 power-domains = <&cpu_pd7>; 223 power-domain-names = "psci"; 224 qcom,freq-domain = <&cpufreq_hw 1>; 225 operating-points-v2 = <&cpu4_opp_table>; 226 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 227 #cooling-cells = <2>; 228 l2_700: l2-cache { 229 compatible = "cache"; 230 cache-level = <2>; 231 cache-unified; 232 next-level-cache = <&l3_0>; 233 }; 234 }; 235 236 cpu-map { 237 cluster0 { 238 core0 { 239 cpu = <&cpu0>; 240 }; 241 242 core1 { 243 cpu = <&cpu1>; 244 }; 245 246 core2 { 247 cpu = <&cpu2>; 248 }; 249 250 core3 { 251 cpu = <&cpu3>; 252 }; 253 254 core4 { 255 cpu = <&cpu4>; 256 }; 257 258 core5 { 259 cpu = <&cpu5>; 260 }; 261 262 core6 { 263 cpu = <&cpu6>; 264 }; 265 266 core7 { 267 cpu = <&cpu7>; 268 }; 269 }; 270 }; 271 272 idle-states { 273 entry-method = "psci"; 274 275 little_cpu_sleep_0: cpu-sleep-0-0 { 276 compatible = "arm,idle-state"; 277 idle-state-name = "little-rail-power-collapse"; 278 arm,psci-suspend-param = <0x40000004>; 279 entry-latency-us = <355>; 280 exit-latency-us = <909>; 281 min-residency-us = <3934>; 282 local-timer-stop; 283 }; 284 285 big_cpu_sleep_0: cpu-sleep-1-0 { 286 compatible = "arm,idle-state"; 287 idle-state-name = "big-rail-power-collapse"; 288 arm,psci-suspend-param = <0x40000004>; 289 entry-latency-us = <241>; 290 exit-latency-us = <1461>; 291 min-residency-us = <4488>; 292 local-timer-stop; 293 }; 294 }; 295 296 domain-idle-states { 297 cluster_sleep_0: cluster-sleep-0 { 298 compatible = "domain-idle-state"; 299 arm,psci-suspend-param = <0x4100c344>; 300 entry-latency-us = <3263>; 301 exit-latency-us = <6562>; 302 min-residency-us = <9987>; 303 }; 304 }; 305 }; 306 307 firmware { 308 scm: scm { 309 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 310 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 311 qcom,dload-mode = <&tcsr 0x13000>; 312 }; 313 }; 314 315 aggre1_noc: interconnect-aggre1-noc { 316 compatible = "qcom,sc8280xp-aggre1-noc"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 aggre2_noc: interconnect-aggre2-noc { 322 compatible = "qcom,sc8280xp-aggre2-noc"; 323 #interconnect-cells = <2>; 324 qcom,bcm-voters = <&apps_bcm_voter>; 325 }; 326 327 clk_virt: interconnect-clk-virt { 328 compatible = "qcom,sc8280xp-clk-virt"; 329 #interconnect-cells = <2>; 330 qcom,bcm-voters = <&apps_bcm_voter>; 331 }; 332 333 config_noc: interconnect-config-noc { 334 compatible = "qcom,sc8280xp-config-noc"; 335 #interconnect-cells = <2>; 336 qcom,bcm-voters = <&apps_bcm_voter>; 337 }; 338 339 dc_noc: interconnect-dc-noc { 340 compatible = "qcom,sc8280xp-dc-noc"; 341 #interconnect-cells = <2>; 342 qcom,bcm-voters = <&apps_bcm_voter>; 343 }; 344 345 gem_noc: interconnect-gem-noc { 346 compatible = "qcom,sc8280xp-gem-noc"; 347 #interconnect-cells = <2>; 348 qcom,bcm-voters = <&apps_bcm_voter>; 349 }; 350 351 lpass_noc: interconnect-lpass-ag-noc { 352 compatible = "qcom,sc8280xp-lpass-ag-noc"; 353 #interconnect-cells = <2>; 354 qcom,bcm-voters = <&apps_bcm_voter>; 355 }; 356 357 mc_virt: interconnect-mc-virt { 358 compatible = "qcom,sc8280xp-mc-virt"; 359 #interconnect-cells = <2>; 360 qcom,bcm-voters = <&apps_bcm_voter>; 361 }; 362 363 mmss_noc: interconnect-mmss-noc { 364 compatible = "qcom,sc8280xp-mmss-noc"; 365 #interconnect-cells = <2>; 366 qcom,bcm-voters = <&apps_bcm_voter>; 367 }; 368 369 nspa_noc: interconnect-nspa-noc { 370 compatible = "qcom,sc8280xp-nspa-noc"; 371 #interconnect-cells = <2>; 372 qcom,bcm-voters = <&apps_bcm_voter>; 373 }; 374 375 nspb_noc: interconnect-nspb-noc { 376 compatible = "qcom,sc8280xp-nspb-noc"; 377 #interconnect-cells = <2>; 378 qcom,bcm-voters = <&apps_bcm_voter>; 379 }; 380 381 system_noc: interconnect-system-noc { 382 compatible = "qcom,sc8280xp-system-noc"; 383 #interconnect-cells = <2>; 384 qcom,bcm-voters = <&apps_bcm_voter>; 385 }; 386 387 memory@80000000 { 388 device_type = "memory"; 389 /* We expect the bootloader to fill in the size */ 390 reg = <0x0 0x80000000 0x0 0x0>; 391 }; 392 393 cpu0_opp_table: opp-table-cpu0 { 394 compatible = "operating-points-v2"; 395 opp-shared; 396 397 opp-300000000 { 398 opp-hz = /bits/ 64 <300000000>; 399 opp-peak-kBps = <(300000 * 32)>; 400 }; 401 opp-403200000 { 402 opp-hz = /bits/ 64 <403200000>; 403 opp-peak-kBps = <(384000 * 32)>; 404 }; 405 opp-499200000 { 406 opp-hz = /bits/ 64 <499200000>; 407 opp-peak-kBps = <(480000 * 32)>; 408 }; 409 opp-595200000 { 410 opp-hz = /bits/ 64 <595200000>; 411 opp-peak-kBps = <(576000 * 32)>; 412 }; 413 opp-691200000 { 414 opp-hz = /bits/ 64 <691200000>; 415 opp-peak-kBps = <(672000 * 32)>; 416 }; 417 opp-806400000 { 418 opp-hz = /bits/ 64 <806400000>; 419 opp-peak-kBps = <(768000 * 32)>; 420 }; 421 opp-902400000 { 422 opp-hz = /bits/ 64 <902400000>; 423 opp-peak-kBps = <(864000 * 32)>; 424 }; 425 opp-1017600000 { 426 opp-hz = /bits/ 64 <1017600000>; 427 opp-peak-kBps = <(960000 * 32)>; 428 }; 429 opp-1113600000 { 430 opp-hz = /bits/ 64 <1113600000>; 431 opp-peak-kBps = <(1075200 * 32)>; 432 }; 433 opp-1209600000 { 434 opp-hz = /bits/ 64 <1209600000>; 435 opp-peak-kBps = <(1171200 * 32)>; 436 }; 437 opp-1324800000 { 438 opp-hz = /bits/ 64 <1324800000>; 439 opp-peak-kBps = <(1267200 * 32)>; 440 }; 441 opp-1440000000 { 442 opp-hz = /bits/ 64 <1440000000>; 443 opp-peak-kBps = <(1363200 * 32)>; 444 }; 445 opp-1555200000 { 446 opp-hz = /bits/ 64 <1555200000>; 447 opp-peak-kBps = <(1536000 * 32)>; 448 }; 449 opp-1670400000 { 450 opp-hz = /bits/ 64 <1670400000>; 451 opp-peak-kBps = <(1612800 * 32)>; 452 }; 453 opp-1785600000 { 454 opp-hz = /bits/ 64 <1785600000>; 455 opp-peak-kBps = <(1689600 * 32)>; 456 }; 457 opp-1881600000 { 458 opp-hz = /bits/ 64 <1881600000>; 459 opp-peak-kBps = <(1689600 * 32)>; 460 }; 461 opp-1996800000 { 462 opp-hz = /bits/ 64 <1996800000>; 463 opp-peak-kBps = <(1689600 * 32)>; 464 }; 465 opp-2112000000 { 466 opp-hz = /bits/ 64 <2112000000>; 467 opp-peak-kBps = <(1689600 * 32)>; 468 }; 469 opp-2227200000 { 470 opp-hz = /bits/ 64 <2227200000>; 471 opp-peak-kBps = <(1689600 * 32)>; 472 }; 473 opp-2342400000 { 474 opp-hz = /bits/ 64 <2342400000>; 475 opp-peak-kBps = <(1689600 * 32)>; 476 }; 477 opp-2438400000 { 478 opp-hz = /bits/ 64 <2438400000>; 479 opp-peak-kBps = <(1689600 * 32)>; 480 }; 481 }; 482 483 cpu4_opp_table: opp-table-cpu4 { 484 compatible = "operating-points-v2"; 485 opp-shared; 486 487 opp-825600000 { 488 opp-hz = /bits/ 64 <825600000>; 489 opp-peak-kBps = <(768000 * 32)>; 490 }; 491 opp-940800000 { 492 opp-hz = /bits/ 64 <940800000>; 493 opp-peak-kBps = <(864000 * 32)>; 494 }; 495 opp-1056000000 { 496 opp-hz = /bits/ 64 <1056000000>; 497 opp-peak-kBps = <(960000 * 32)>; 498 }; 499 opp-1171200000 { 500 opp-hz = /bits/ 64 <1171200000>; 501 opp-peak-kBps = <(1171200 * 32)>; 502 }; 503 opp-1286400000 { 504 opp-hz = /bits/ 64 <1286400000>; 505 opp-peak-kBps = <(1267200 * 32)>; 506 }; 507 opp-1401600000 { 508 opp-hz = /bits/ 64 <1401600000>; 509 opp-peak-kBps = <(1363200 * 32)>; 510 }; 511 opp-1516800000 { 512 opp-hz = /bits/ 64 <1516800000>; 513 opp-peak-kBps = <(1459200 * 32)>; 514 }; 515 opp-1632000000 { 516 opp-hz = /bits/ 64 <1632000000>; 517 opp-peak-kBps = <(1612800 * 32)>; 518 }; 519 opp-1747200000 { 520 opp-hz = /bits/ 64 <1747200000>; 521 opp-peak-kBps = <(1689600 * 32)>; 522 }; 523 opp-1862400000 { 524 opp-hz = /bits/ 64 <1862400000>; 525 opp-peak-kBps = <(1689600 * 32)>; 526 }; 527 opp-1977600000 { 528 opp-hz = /bits/ 64 <1977600000>; 529 opp-peak-kBps = <(1689600 * 32)>; 530 }; 531 opp-2073600000 { 532 opp-hz = /bits/ 64 <2073600000>; 533 opp-peak-kBps = <(1689600 * 32)>; 534 }; 535 opp-2169600000 { 536 opp-hz = /bits/ 64 <2169600000>; 537 opp-peak-kBps = <(1689600 * 32)>; 538 }; 539 opp-2284800000 { 540 opp-hz = /bits/ 64 <2284800000>; 541 opp-peak-kBps = <(1689600 * 32)>; 542 }; 543 opp-2400000000 { 544 opp-hz = /bits/ 64 <2400000000>; 545 opp-peak-kBps = <(1689600 * 32)>; 546 }; 547 opp-2496000000 { 548 opp-hz = /bits/ 64 <2496000000>; 549 opp-peak-kBps = <(1689600 * 32)>; 550 }; 551 opp-2592000000 { 552 opp-hz = /bits/ 64 <2592000000>; 553 opp-peak-kBps = <(1689600 * 32)>; 554 }; 555 opp-2688000000 { 556 opp-hz = /bits/ 64 <2688000000>; 557 opp-peak-kBps = <(1689600 * 32)>; 558 }; 559 opp-2803200000 { 560 opp-hz = /bits/ 64 <2803200000>; 561 opp-peak-kBps = <(1689600 * 32)>; 562 }; 563 opp-2899200000 { 564 opp-hz = /bits/ 64 <2899200000>; 565 opp-peak-kBps = <(1689600 * 32)>; 566 }; 567 opp-2995200000 { 568 opp-hz = /bits/ 64 <2995200000>; 569 opp-peak-kBps = <(1689600 * 32)>; 570 }; 571 }; 572 573 qup_opp_table_100mhz: opp-table-qup100mhz { 574 compatible = "operating-points-v2"; 575 576 opp-75000000 { 577 opp-hz = /bits/ 64 <75000000>; 578 required-opps = <&rpmhpd_opp_low_svs>; 579 }; 580 581 opp-100000000 { 582 opp-hz = /bits/ 64 <100000000>; 583 required-opps = <&rpmhpd_opp_svs>; 584 }; 585 }; 586 587 pmu { 588 compatible = "arm,armv8-pmuv3"; 589 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 590 }; 591 592 psci { 593 compatible = "arm,psci-1.0"; 594 method = "smc"; 595 596 cpu_pd0: power-domain-cpu0 { 597 #power-domain-cells = <0>; 598 power-domains = <&cluster_pd>; 599 domain-idle-states = <&little_cpu_sleep_0>; 600 }; 601 602 cpu_pd1: power-domain-cpu1 { 603 #power-domain-cells = <0>; 604 power-domains = <&cluster_pd>; 605 domain-idle-states = <&little_cpu_sleep_0>; 606 }; 607 608 cpu_pd2: power-domain-cpu2 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_pd>; 611 domain-idle-states = <&little_cpu_sleep_0>; 612 }; 613 614 cpu_pd3: power-domain-cpu3 { 615 #power-domain-cells = <0>; 616 power-domains = <&cluster_pd>; 617 domain-idle-states = <&little_cpu_sleep_0>; 618 }; 619 620 cpu_pd4: power-domain-cpu4 { 621 #power-domain-cells = <0>; 622 power-domains = <&cluster_pd>; 623 domain-idle-states = <&big_cpu_sleep_0>; 624 }; 625 626 cpu_pd5: power-domain-cpu5 { 627 #power-domain-cells = <0>; 628 power-domains = <&cluster_pd>; 629 domain-idle-states = <&big_cpu_sleep_0>; 630 }; 631 632 cpu_pd6: power-domain-cpu6 { 633 #power-domain-cells = <0>; 634 power-domains = <&cluster_pd>; 635 domain-idle-states = <&big_cpu_sleep_0>; 636 }; 637 638 cpu_pd7: power-domain-cpu7 { 639 #power-domain-cells = <0>; 640 power-domains = <&cluster_pd>; 641 domain-idle-states = <&big_cpu_sleep_0>; 642 }; 643 644 cluster_pd: power-domain-cpu-cluster0 { 645 #power-domain-cells = <0>; 646 domain-idle-states = <&cluster_sleep_0>; 647 }; 648 }; 649 650 reserved-memory { 651 #address-cells = <2>; 652 #size-cells = <2>; 653 ranges; 654 655 reserved-region@80000000 { 656 reg = <0 0x80000000 0 0x860000>; 657 no-map; 658 }; 659 660 cmd_db: cmd-db-region@80860000 { 661 compatible = "qcom,cmd-db"; 662 reg = <0 0x80860000 0 0x20000>; 663 no-map; 664 }; 665 666 reserved-region@80880000 { 667 reg = <0 0x80880000 0 0x80000>; 668 no-map; 669 }; 670 671 smem_mem: smem-region@80900000 { 672 compatible = "qcom,smem"; 673 reg = <0 0x80900000 0 0x200000>; 674 no-map; 675 hwlocks = <&tcsr_mutex 3>; 676 }; 677 678 reserved-region@80b00000 { 679 reg = <0 0x80b00000 0 0x100000>; 680 no-map; 681 }; 682 683 reserved-region@83b00000 { 684 reg = <0 0x83b00000 0 0x1700000>; 685 no-map; 686 }; 687 688 reserved-region@85b00000 { 689 reg = <0 0x85b00000 0 0xc00000>; 690 no-map; 691 }; 692 693 pil_adsp_mem: adsp-region@86c00000 { 694 reg = <0 0x86c00000 0 0x2000000>; 695 no-map; 696 }; 697 698 pil_slpi_mem: slpi-region@88c00000 { 699 reg = <0 0x88c00000 0 0x1500000>; 700 no-map; 701 }; 702 703 pil_nsp0_mem: cdsp0-region@8a100000 { 704 reg = <0 0x8a100000 0 0x1e00000>; 705 no-map; 706 }; 707 708 pil_nsp1_mem: cdsp1-region@8c600000 { 709 reg = <0 0x8c600000 0 0x1e00000>; 710 no-map; 711 }; 712 713 reserved-region@aeb00000 { 714 reg = <0 0xaeb00000 0 0x16600000>; 715 no-map; 716 }; 717 }; 718 719 smp2p-adsp { 720 compatible = "qcom,smp2p"; 721 qcom,smem = <443>, <429>; 722 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 723 IPCC_MPROC_SIGNAL_SMP2P 724 IRQ_TYPE_EDGE_RISING>; 725 mboxes = <&ipcc IPCC_CLIENT_LPASS 726 IPCC_MPROC_SIGNAL_SMP2P>; 727 728 qcom,local-pid = <0>; 729 qcom,remote-pid = <2>; 730 731 smp2p_adsp_out: master-kernel { 732 qcom,entry-name = "master-kernel"; 733 #qcom,smem-state-cells = <1>; 734 }; 735 736 smp2p_adsp_in: slave-kernel { 737 qcom,entry-name = "slave-kernel"; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 }; 741 }; 742 743 smp2p-nsp0 { 744 compatible = "qcom,smp2p"; 745 qcom,smem = <94>, <432>; 746 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 747 IPCC_MPROC_SIGNAL_SMP2P 748 IRQ_TYPE_EDGE_RISING>; 749 mboxes = <&ipcc IPCC_CLIENT_CDSP 750 IPCC_MPROC_SIGNAL_SMP2P>; 751 752 qcom,local-pid = <0>; 753 qcom,remote-pid = <5>; 754 755 smp2p_nsp0_out: master-kernel { 756 qcom,entry-name = "master-kernel"; 757 #qcom,smem-state-cells = <1>; 758 }; 759 760 smp2p_nsp0_in: slave-kernel { 761 qcom,entry-name = "slave-kernel"; 762 interrupt-controller; 763 #interrupt-cells = <2>; 764 }; 765 }; 766 767 smp2p-nsp1 { 768 compatible = "qcom,smp2p"; 769 qcom,smem = <617>, <616>; 770 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 771 IPCC_MPROC_SIGNAL_SMP2P 772 IRQ_TYPE_EDGE_RISING>; 773 mboxes = <&ipcc IPCC_CLIENT_NSP1 774 IPCC_MPROC_SIGNAL_SMP2P>; 775 776 qcom,local-pid = <0>; 777 qcom,remote-pid = <12>; 778 779 smp2p_nsp1_out: master-kernel { 780 qcom,entry-name = "master-kernel"; 781 #qcom,smem-state-cells = <1>; 782 }; 783 784 smp2p_nsp1_in: slave-kernel { 785 qcom,entry-name = "slave-kernel"; 786 interrupt-controller; 787 #interrupt-cells = <2>; 788 }; 789 }; 790 791 smp2p-slpi { 792 compatible = "qcom,smp2p"; 793 qcom,smem = <481>, <430>; 794 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 795 IPCC_MPROC_SIGNAL_SMP2P 796 IRQ_TYPE_EDGE_RISING>; 797 mboxes = <&ipcc IPCC_CLIENT_SLPI 798 IPCC_MPROC_SIGNAL_SMP2P>; 799 800 qcom,local-pid = <0>; 801 qcom,remote-pid = <3>; 802 803 smp2p_slpi_out: master-kernel { 804 qcom,entry-name = "master-kernel"; 805 #qcom,smem-state-cells = <1>; 806 }; 807 808 smp2p_slpi_in: slave-kernel { 809 qcom,entry-name = "slave-kernel"; 810 interrupt-controller; 811 #interrupt-cells = <2>; 812 }; 813 }; 814 815 soc: soc@0 { 816 compatible = "simple-bus"; 817 #address-cells = <2>; 818 #size-cells = <2>; 819 ranges = <0 0 0 0 0x10 0>; 820 dma-ranges = <0 0 0 0 0x10 0>; 821 822 ethernet0: ethernet@20000 { 823 compatible = "qcom,sc8280xp-ethqos"; 824 reg = <0x0 0x00020000 0x0 0x10000>, 825 <0x0 0x00036000 0x0 0x100>; 826 reg-names = "stmmaceth", "rgmii"; 827 828 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 829 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 830 <&gcc GCC_EMAC0_PTP_CLK>, 831 <&gcc GCC_EMAC0_RGMII_CLK>; 832 clock-names = "stmmaceth", 833 "pclk", 834 "ptp_ref", 835 "rgmii"; 836 837 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "macirq", "eth_lpi"; 840 841 iommus = <&apps_smmu 0x4c0 0xf>; 842 power-domains = <&gcc EMAC_0_GDSC>; 843 844 snps,tso; 845 snps,pbl = <32>; 846 rx-fifo-depth = <4096>; 847 tx-fifo-depth = <4096>; 848 849 status = "disabled"; 850 }; 851 852 gcc: clock-controller@100000 { 853 compatible = "qcom,gcc-sc8280xp"; 854 reg = <0x0 0x00100000 0x0 0x1f0000>; 855 #clock-cells = <1>; 856 #reset-cells = <1>; 857 #power-domain-cells = <1>; 858 clocks = <&rpmhcc RPMH_CXO_CLK>, 859 <&sleep_clk>, 860 <0>, 861 <0>, 862 <0>, 863 <0>, 864 <0>, 865 <0>, 866 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 867 <0>, 868 <0>, 869 <0>, 870 <0>, 871 <0>, 872 <0>, 873 <0>, 874 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 875 <0>, 876 <0>, 877 <0>, 878 <0>, 879 <0>, 880 <0>, 881 <0>, 882 <0>, 883 <0>, 884 <&pcie2a_phy>, 885 <&pcie2b_phy>, 886 <&pcie3a_phy>, 887 <&pcie3b_phy>, 888 <&pcie4_phy>, 889 <0>, 890 <0>; 891 power-domains = <&rpmhpd SC8280XP_CX>; 892 }; 893 894 ipcc: mailbox@408000 { 895 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 896 reg = <0 0x00408000 0 0x1000>; 897 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 898 interrupt-controller; 899 #interrupt-cells = <3>; 900 #mbox-cells = <2>; 901 }; 902 903 qfprom: efuse@784000 { 904 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; 905 reg = <0 0x00784000 0 0x3000>; 906 #address-cells = <1>; 907 #size-cells = <1>; 908 909 gpu_speed_bin: gpu-speed-bin@18b { 910 reg = <0x18b 0x1>; 911 bits = <5 3>; 912 }; 913 }; 914 915 qup2: geniqup@8c0000 { 916 compatible = "qcom,geni-se-qup"; 917 reg = <0 0x008c0000 0 0x2000>; 918 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 919 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 920 clock-names = "m-ahb", "s-ahb"; 921 iommus = <&apps_smmu 0xa3 0>; 922 923 #address-cells = <2>; 924 #size-cells = <2>; 925 ranges; 926 927 status = "disabled"; 928 929 i2c16: i2c@880000 { 930 compatible = "qcom,geni-i2c"; 931 reg = <0 0x00880000 0 0x4000>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 935 clock-names = "se"; 936 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 937 power-domains = <&rpmhpd SC8280XP_CX>; 938 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 939 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 940 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 941 interconnect-names = "qup-core", "qup-config", "qup-memory"; 942 status = "disabled"; 943 }; 944 945 spi16: spi@880000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x00880000 0 0x4000>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 951 clock-names = "se"; 952 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 953 power-domains = <&rpmhpd SC8280XP_CX>; 954 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 956 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 957 interconnect-names = "qup-core", "qup-config", "qup-memory"; 958 status = "disabled"; 959 }; 960 961 i2c17: i2c@884000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0 0x00884000 0 0x4000>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 967 clock-names = "se"; 968 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 969 power-domains = <&rpmhpd SC8280XP_CX>; 970 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 972 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 973 interconnect-names = "qup-core", "qup-config", "qup-memory"; 974 status = "disabled"; 975 }; 976 977 spi17: spi@884000 { 978 compatible = "qcom,geni-spi"; 979 reg = <0 0x00884000 0 0x4000>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 983 clock-names = "se"; 984 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 985 power-domains = <&rpmhpd SC8280XP_CX>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 988 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 989 interconnect-names = "qup-core", "qup-config", "qup-memory"; 990 status = "disabled"; 991 }; 992 993 uart17: serial@884000 { 994 compatible = "qcom,geni-uart"; 995 reg = <0 0x00884000 0 0x4000>; 996 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 997 clock-names = "se"; 998 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 999 operating-points-v2 = <&qup_opp_table_100mhz>; 1000 power-domains = <&rpmhpd SC8280XP_CX>; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1003 interconnect-names = "qup-core", "qup-config"; 1004 status = "disabled"; 1005 }; 1006 1007 i2c18: i2c@888000 { 1008 compatible = "qcom,geni-i2c"; 1009 reg = <0 0x00888000 0 0x4000>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1013 clock-names = "se"; 1014 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1015 power-domains = <&rpmhpd SC8280XP_CX>; 1016 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1018 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1019 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1020 status = "disabled"; 1021 }; 1022 1023 spi18: spi@888000 { 1024 compatible = "qcom,geni-spi"; 1025 reg = <0 0x00888000 0 0x4000>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1029 clock-names = "se"; 1030 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1031 power-domains = <&rpmhpd SC8280XP_CX>; 1032 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1033 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1034 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1035 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1036 status = "disabled"; 1037 }; 1038 1039 uart18: serial@888000 { 1040 compatible = "qcom,geni-uart"; 1041 reg = <0 0x00888000 0 0x4000>; 1042 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1043 clock-names = "se"; 1044 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1045 operating-points-v2 = <&qup_opp_table_100mhz>; 1046 power-domains = <&rpmhpd SC8280XP_CX>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1048 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1049 interconnect-names = "qup-core", "qup-config"; 1050 1051 pinctrl-0 = <&qup_uart18_default>; 1052 pinctrl-names = "default"; 1053 1054 status = "disabled"; 1055 }; 1056 1057 i2c19: i2c@88c000 { 1058 compatible = "qcom,geni-i2c"; 1059 reg = <0 0x0088c000 0 0x4000>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1063 clock-names = "se"; 1064 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1065 power-domains = <&rpmhpd SC8280XP_CX>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1067 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1068 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1069 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1070 status = "disabled"; 1071 }; 1072 1073 spi19: spi@88c000 { 1074 compatible = "qcom,geni-spi"; 1075 reg = <0 0x0088c000 0 0x4000>; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1079 clock-names = "se"; 1080 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1081 power-domains = <&rpmhpd SC8280XP_CX>; 1082 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1083 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1084 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1085 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1086 status = "disabled"; 1087 }; 1088 1089 i2c20: i2c@890000 { 1090 compatible = "qcom,geni-i2c"; 1091 reg = <0 0x00890000 0 0x4000>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1095 clock-names = "se"; 1096 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1097 power-domains = <&rpmhpd SC8280XP_CX>; 1098 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1099 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1100 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1101 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1102 status = "disabled"; 1103 }; 1104 1105 spi20: spi@890000 { 1106 compatible = "qcom,geni-spi"; 1107 reg = <0 0x00890000 0 0x4000>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1111 clock-names = "se"; 1112 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1113 power-domains = <&rpmhpd SC8280XP_CX>; 1114 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1116 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1117 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1118 status = "disabled"; 1119 }; 1120 1121 i2c21: i2c@894000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0 0x00894000 0 0x4000>; 1124 clock-names = "se"; 1125 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1126 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 power-domains = <&rpmhpd SC8280XP_CX>; 1130 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1132 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1133 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1134 status = "disabled"; 1135 }; 1136 1137 spi21: spi@894000 { 1138 compatible = "qcom,geni-spi"; 1139 reg = <0 0x00894000 0 0x4000>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1143 clock-names = "se"; 1144 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1145 power-domains = <&rpmhpd SC8280XP_CX>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1148 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1149 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1150 status = "disabled"; 1151 }; 1152 1153 i2c22: i2c@898000 { 1154 compatible = "qcom,geni-i2c"; 1155 reg = <0 0x00898000 0 0x4000>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1160 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1161 power-domains = <&rpmhpd SC8280XP_CX>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1164 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1166 status = "disabled"; 1167 }; 1168 1169 spi22: spi@898000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x00898000 0 0x4000>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1175 clock-names = "se"; 1176 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1177 power-domains = <&rpmhpd SC8280XP_CX>; 1178 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1179 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1180 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1181 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1182 status = "disabled"; 1183 }; 1184 1185 i2c23: i2c@89c000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0 0x0089c000 0 0x4000>; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1192 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1193 power-domains = <&rpmhpd SC8280XP_CX>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1196 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1197 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1198 status = "disabled"; 1199 }; 1200 1201 spi23: spi@89c000 { 1202 compatible = "qcom,geni-spi"; 1203 reg = <0 0x0089c000 0 0x4000>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1207 clock-names = "se"; 1208 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1209 power-domains = <&rpmhpd SC8280XP_CX>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1212 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1213 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1214 status = "disabled"; 1215 }; 1216 }; 1217 1218 qup0: geniqup@9c0000 { 1219 compatible = "qcom,geni-se-qup"; 1220 reg = <0 0x009c0000 0 0x6000>; 1221 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1222 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1223 clock-names = "m-ahb", "s-ahb"; 1224 iommus = <&apps_smmu 0x563 0>; 1225 1226 #address-cells = <2>; 1227 #size-cells = <2>; 1228 ranges; 1229 1230 status = "disabled"; 1231 1232 i2c0: i2c@980000 { 1233 compatible = "qcom,geni-i2c"; 1234 reg = <0 0x00980000 0 0x4000>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 clock-names = "se"; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1239 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1240 power-domains = <&rpmhpd SC8280XP_CX>; 1241 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1242 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1243 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1244 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1245 status = "disabled"; 1246 }; 1247 1248 spi0: spi@980000 { 1249 compatible = "qcom,geni-spi"; 1250 reg = <0 0x00980000 0 0x4000>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1254 clock-names = "se"; 1255 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1256 power-domains = <&rpmhpd SC8280XP_CX>; 1257 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1258 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1259 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1260 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1261 status = "disabled"; 1262 }; 1263 1264 i2c1: i2c@984000 { 1265 compatible = "qcom,geni-i2c"; 1266 reg = <0 0x00984000 0 0x4000>; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 clock-names = "se"; 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1271 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1272 power-domains = <&rpmhpd SC8280XP_CX>; 1273 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1274 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1275 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1276 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1277 status = "disabled"; 1278 }; 1279 1280 spi1: spi@984000 { 1281 compatible = "qcom,geni-spi"; 1282 reg = <0 0x00984000 0 0x4000>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1286 clock-names = "se"; 1287 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1288 power-domains = <&rpmhpd SC8280XP_CX>; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1290 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1291 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1292 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1293 status = "disabled"; 1294 }; 1295 1296 i2c2: i2c@988000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0 0x00988000 0 0x4000>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1303 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1304 power-domains = <&rpmhpd SC8280XP_CX>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1306 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1307 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1308 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1309 status = "disabled"; 1310 }; 1311 1312 spi2: spi@988000 { 1313 compatible = "qcom,geni-spi"; 1314 reg = <0 0x00988000 0 0x4000>; 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1318 clock-names = "se"; 1319 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1320 power-domains = <&rpmhpd SC8280XP_CX>; 1321 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1322 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1323 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1324 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1325 status = "disabled"; 1326 }; 1327 1328 uart2: serial@988000 { 1329 compatible = "qcom,geni-uart"; 1330 reg = <0 0x00988000 0 0x4000>; 1331 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1332 clock-names = "se"; 1333 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1334 operating-points-v2 = <&qup_opp_table_100mhz>; 1335 power-domains = <&rpmhpd SC8280XP_CX>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1338 interconnect-names = "qup-core", "qup-config"; 1339 status = "disabled"; 1340 }; 1341 1342 i2c3: i2c@98c000 { 1343 compatible = "qcom,geni-i2c"; 1344 reg = <0 0x0098c000 0 0x4000>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 clock-names = "se"; 1348 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1349 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1350 power-domains = <&rpmhpd SC8280XP_CX>; 1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1352 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1353 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1354 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1355 status = "disabled"; 1356 }; 1357 1358 spi3: spi@98c000 { 1359 compatible = "qcom,geni-spi"; 1360 reg = <0 0x0098c000 0 0x4000>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1364 clock-names = "se"; 1365 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1366 power-domains = <&rpmhpd SC8280XP_CX>; 1367 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1368 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1369 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1370 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1371 status = "disabled"; 1372 }; 1373 1374 i2c4: i2c@990000 { 1375 compatible = "qcom,geni-i2c"; 1376 reg = <0 0x00990000 0 0x4000>; 1377 clock-names = "se"; 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1379 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 power-domains = <&rpmhpd SC8280XP_CX>; 1383 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1384 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1385 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1386 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1387 status = "disabled"; 1388 }; 1389 1390 spi4: spi@990000 { 1391 compatible = "qcom,geni-spi"; 1392 reg = <0 0x00990000 0 0x4000>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1396 clock-names = "se"; 1397 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1398 power-domains = <&rpmhpd SC8280XP_CX>; 1399 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1401 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1402 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1403 status = "disabled"; 1404 }; 1405 1406 i2c5: i2c@994000 { 1407 compatible = "qcom,geni-i2c"; 1408 reg = <0 0x00994000 0 0x4000>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 clock-names = "se"; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1413 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1414 power-domains = <&rpmhpd SC8280XP_CX>; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1417 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1418 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1419 status = "disabled"; 1420 }; 1421 1422 spi5: spi@994000 { 1423 compatible = "qcom,geni-spi"; 1424 reg = <0 0x00994000 0 0x4000>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1428 clock-names = "se"; 1429 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1430 power-domains = <&rpmhpd SC8280XP_CX>; 1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1433 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1434 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1435 status = "disabled"; 1436 }; 1437 1438 i2c6: i2c@998000 { 1439 compatible = "qcom,geni-i2c"; 1440 reg = <0 0x00998000 0 0x4000>; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 clock-names = "se"; 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1445 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1446 power-domains = <&rpmhpd SC8280XP_CX>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1449 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1450 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1451 status = "disabled"; 1452 }; 1453 1454 spi6: spi@998000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0x00998000 0 0x4000>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1460 clock-names = "se"; 1461 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1462 power-domains = <&rpmhpd SC8280XP_CX>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1465 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1466 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1467 status = "disabled"; 1468 }; 1469 1470 i2c7: i2c@99c000 { 1471 compatible = "qcom,geni-i2c"; 1472 reg = <0 0x0099c000 0 0x4000>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1477 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1478 power-domains = <&rpmhpd SC8280XP_CX>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1481 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1482 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1483 status = "disabled"; 1484 }; 1485 1486 spi7: spi@99c000 { 1487 compatible = "qcom,geni-spi"; 1488 reg = <0 0x0099c000 0 0x4000>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1492 clock-names = "se"; 1493 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1494 power-domains = <&rpmhpd SC8280XP_CX>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1497 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1498 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1499 status = "disabled"; 1500 }; 1501 }; 1502 1503 qup1: geniqup@ac0000 { 1504 compatible = "qcom,geni-se-qup"; 1505 reg = <0 0x00ac0000 0 0x6000>; 1506 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1507 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1508 clock-names = "m-ahb", "s-ahb"; 1509 iommus = <&apps_smmu 0x83 0>; 1510 1511 #address-cells = <2>; 1512 #size-cells = <2>; 1513 ranges; 1514 1515 status = "disabled"; 1516 1517 i2c8: i2c@a80000 { 1518 compatible = "qcom,geni-i2c"; 1519 reg = <0 0x00a80000 0 0x4000>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1523 clock-names = "se"; 1524 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1525 power-domains = <&rpmhpd SC8280XP_CX>; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1527 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1528 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1529 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1530 status = "disabled"; 1531 }; 1532 1533 spi8: spi@a80000 { 1534 compatible = "qcom,geni-spi"; 1535 reg = <0 0x00a80000 0 0x4000>; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1539 clock-names = "se"; 1540 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1541 power-domains = <&rpmhpd SC8280XP_CX>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1543 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1544 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1545 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1546 status = "disabled"; 1547 }; 1548 1549 i2c9: i2c@a84000 { 1550 compatible = "qcom,geni-i2c"; 1551 reg = <0 0x00a84000 0 0x4000>; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1555 clock-names = "se"; 1556 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1557 power-domains = <&rpmhpd SC8280XP_CX>; 1558 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1559 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1560 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1561 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1562 status = "disabled"; 1563 }; 1564 1565 spi9: spi@a84000 { 1566 compatible = "qcom,geni-spi"; 1567 reg = <0 0x00a84000 0 0x4000>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1571 clock-names = "se"; 1572 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1573 power-domains = <&rpmhpd SC8280XP_CX>; 1574 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1575 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1576 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1578 status = "disabled"; 1579 }; 1580 1581 i2c10: i2c@a88000 { 1582 compatible = "qcom,geni-i2c"; 1583 reg = <0 0x00a88000 0 0x4000>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1587 clock-names = "se"; 1588 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1589 power-domains = <&rpmhpd SC8280XP_CX>; 1590 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1591 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1592 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1593 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1594 status = "disabled"; 1595 }; 1596 1597 spi10: spi@a88000 { 1598 compatible = "qcom,geni-spi"; 1599 reg = <0 0x00a88000 0 0x4000>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1603 clock-names = "se"; 1604 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1605 power-domains = <&rpmhpd SC8280XP_CX>; 1606 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1607 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1608 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1609 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1610 status = "disabled"; 1611 }; 1612 1613 i2c11: i2c@a8c000 { 1614 compatible = "qcom,geni-i2c"; 1615 reg = <0 0x00a8c000 0 0x4000>; 1616 #address-cells = <1>; 1617 #size-cells = <0>; 1618 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1619 clock-names = "se"; 1620 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1621 power-domains = <&rpmhpd SC8280XP_CX>; 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1623 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1624 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1625 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1626 status = "disabled"; 1627 }; 1628 1629 spi11: spi@a8c000 { 1630 compatible = "qcom,geni-spi"; 1631 reg = <0 0x00a8c000 0 0x4000>; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1635 clock-names = "se"; 1636 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1637 power-domains = <&rpmhpd SC8280XP_CX>; 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1639 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1640 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1641 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1642 status = "disabled"; 1643 }; 1644 1645 i2c12: i2c@a90000 { 1646 compatible = "qcom,geni-i2c"; 1647 reg = <0 0x00a90000 0 0x4000>; 1648 #address-cells = <1>; 1649 #size-cells = <0>; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1651 clock-names = "se"; 1652 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1653 power-domains = <&rpmhpd SC8280XP_CX>; 1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1655 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1656 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1657 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1658 status = "disabled"; 1659 }; 1660 1661 spi12: spi@a90000 { 1662 compatible = "qcom,geni-spi"; 1663 reg = <0 0x00a90000 0 0x4000>; 1664 #address-cells = <1>; 1665 #size-cells = <0>; 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1667 clock-names = "se"; 1668 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1669 power-domains = <&rpmhpd SC8280XP_CX>; 1670 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1671 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1672 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1673 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1674 status = "disabled"; 1675 }; 1676 1677 i2c13: i2c@a94000 { 1678 compatible = "qcom,geni-i2c"; 1679 reg = <0 0x00a94000 0 0x4000>; 1680 #address-cells = <1>; 1681 #size-cells = <0>; 1682 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1683 clock-names = "se"; 1684 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1685 power-domains = <&rpmhpd SC8280XP_CX>; 1686 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1687 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1688 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1689 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1690 status = "disabled"; 1691 }; 1692 1693 spi13: spi@a94000 { 1694 compatible = "qcom,geni-spi"; 1695 reg = <0 0x00a94000 0 0x4000>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1699 clock-names = "se"; 1700 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1701 power-domains = <&rpmhpd SC8280XP_CX>; 1702 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1703 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1704 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1705 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1706 status = "disabled"; 1707 }; 1708 1709 i2c14: i2c@a98000 { 1710 compatible = "qcom,geni-i2c"; 1711 reg = <0 0x00a98000 0 0x4000>; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1715 clock-names = "se"; 1716 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1717 power-domains = <&rpmhpd SC8280XP_CX>; 1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1719 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1720 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1721 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1722 status = "disabled"; 1723 }; 1724 1725 spi14: spi@a98000 { 1726 compatible = "qcom,geni-spi"; 1727 reg = <0 0x00a98000 0 0x4000>; 1728 #address-cells = <1>; 1729 #size-cells = <0>; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1731 clock-names = "se"; 1732 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1733 power-domains = <&rpmhpd SC8280XP_CX>; 1734 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1735 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1736 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1737 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1738 status = "disabled"; 1739 }; 1740 1741 i2c15: i2c@a9c000 { 1742 compatible = "qcom,geni-i2c"; 1743 reg = <0 0x00a9c000 0 0x4000>; 1744 #address-cells = <1>; 1745 #size-cells = <0>; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1747 clock-names = "se"; 1748 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1749 power-domains = <&rpmhpd SC8280XP_CX>; 1750 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1751 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1752 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1753 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1754 status = "disabled"; 1755 }; 1756 1757 spi15: spi@a9c000 { 1758 compatible = "qcom,geni-spi"; 1759 reg = <0 0x00a9c000 0 0x4000>; 1760 #address-cells = <1>; 1761 #size-cells = <0>; 1762 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1763 clock-names = "se"; 1764 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1765 power-domains = <&rpmhpd SC8280XP_CX>; 1766 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1767 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1768 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1769 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1770 status = "disabled"; 1771 }; 1772 }; 1773 1774 rng: rng@10d3000 { 1775 compatible = "qcom,prng-ee"; 1776 reg = <0 0x010d3000 0 0x1000>; 1777 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1778 clock-names = "core"; 1779 }; 1780 1781 pcie4: pcie@1c00000 { 1782 device_type = "pci"; 1783 compatible = "qcom,pcie-sc8280xp"; 1784 reg = <0x0 0x01c00000 0x0 0x3000>, 1785 <0x0 0x30000000 0x0 0xf1d>, 1786 <0x0 0x30000f20 0x0 0xa8>, 1787 <0x0 0x30001000 0x0 0x1000>, 1788 <0x0 0x30100000 0x0 0x100000>, 1789 <0x0 0x01c03000 0x0 0x1000>; 1790 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1791 #address-cells = <3>; 1792 #size-cells = <2>; 1793 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1794 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1795 bus-range = <0x00 0xff>; 1796 1797 dma-coherent; 1798 1799 linux,pci-domain = <6>; 1800 num-lanes = <1>; 1801 1802 msi-map = <0x0 &its 0xe0000 0x10000>; 1803 1804 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1808 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1809 1810 #interrupt-cells = <1>; 1811 interrupt-map-mask = <0 0 0 0x7>; 1812 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1813 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1814 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1815 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1816 1817 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1818 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1819 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1820 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1821 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1822 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1823 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1824 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1825 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1826 clock-names = "aux", 1827 "cfg", 1828 "bus_master", 1829 "bus_slave", 1830 "slave_q2a", 1831 "ddrss_sf_tbu", 1832 "noc_aggr_4", 1833 "noc_aggr_south_sf", 1834 "cnoc_qx"; 1835 1836 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1837 assigned-clock-rates = <19200000>; 1838 1839 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1841 interconnect-names = "pcie-mem", "cpu-pcie"; 1842 1843 resets = <&gcc GCC_PCIE_4_BCR>; 1844 reset-names = "pci"; 1845 1846 power-domains = <&gcc PCIE_4_GDSC>; 1847 required-opps = <&rpmhpd_opp_nom>; 1848 1849 phys = <&pcie4_phy>; 1850 phy-names = "pciephy"; 1851 1852 status = "disabled"; 1853 1854 pcie4_port0: pcie@0 { 1855 device_type = "pci"; 1856 reg = <0x0 0x0 0x0 0x0 0x0>; 1857 bus-range = <0x01 0xff>; 1858 1859 #address-cells = <3>; 1860 #size-cells = <2>; 1861 ranges; 1862 }; 1863 }; 1864 1865 pcie4_phy: phy@1c06000 { 1866 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1867 reg = <0x0 0x01c06000 0x0 0x2000>; 1868 1869 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1870 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1871 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1872 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1873 <&gcc GCC_PCIE_4_PIPE_CLK>, 1874 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1875 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1876 "pipe", "pipediv2"; 1877 1878 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1879 assigned-clock-rates = <100000000>; 1880 1881 power-domains = <&gcc PCIE_4_GDSC>; 1882 1883 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1884 reset-names = "phy"; 1885 1886 #clock-cells = <0>; 1887 clock-output-names = "pcie_4_pipe_clk"; 1888 1889 #phy-cells = <0>; 1890 1891 status = "disabled"; 1892 }; 1893 1894 pcie3b: pcie@1c08000 { 1895 device_type = "pci"; 1896 compatible = "qcom,pcie-sc8280xp"; 1897 reg = <0x0 0x01c08000 0x0 0x3000>, 1898 <0x0 0x32000000 0x0 0xf1d>, 1899 <0x0 0x32000f20 0x0 0xa8>, 1900 <0x0 0x32001000 0x0 0x1000>, 1901 <0x0 0x32100000 0x0 0x100000>, 1902 <0x0 0x01c0b000 0x0 0x1000>; 1903 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1904 #address-cells = <3>; 1905 #size-cells = <2>; 1906 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1907 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1908 bus-range = <0x00 0xff>; 1909 1910 dma-coherent; 1911 1912 linux,pci-domain = <5>; 1913 num-lanes = <2>; 1914 1915 msi-map = <0x0 &its 0xd0000 0x10000>; 1916 1917 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1921 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1922 1923 #interrupt-cells = <1>; 1924 interrupt-map-mask = <0 0 0 0x7>; 1925 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1926 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1927 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1928 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1929 1930 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1931 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1932 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1933 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1934 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1935 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1936 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1937 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1938 clock-names = "aux", 1939 "cfg", 1940 "bus_master", 1941 "bus_slave", 1942 "slave_q2a", 1943 "ddrss_sf_tbu", 1944 "noc_aggr_4", 1945 "noc_aggr_south_sf"; 1946 1947 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1948 assigned-clock-rates = <19200000>; 1949 1950 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1952 interconnect-names = "pcie-mem", "cpu-pcie"; 1953 1954 resets = <&gcc GCC_PCIE_3B_BCR>; 1955 reset-names = "pci"; 1956 1957 power-domains = <&gcc PCIE_3B_GDSC>; 1958 required-opps = <&rpmhpd_opp_nom>; 1959 1960 phys = <&pcie3b_phy>; 1961 phy-names = "pciephy"; 1962 1963 status = "disabled"; 1964 1965 pcie3b_port0: pcie@0 { 1966 device_type = "pci"; 1967 reg = <0x0 0x0 0x0 0x0 0x0>; 1968 bus-range = <0x01 0xff>; 1969 1970 #address-cells = <3>; 1971 #size-cells = <2>; 1972 ranges; 1973 }; 1974 }; 1975 1976 pcie3b_phy: phy@1c0e000 { 1977 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1978 reg = <0x0 0x01c0e000 0x0 0x2000>; 1979 1980 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1981 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1982 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1983 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1984 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1985 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1986 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1987 "pipe", "pipediv2"; 1988 1989 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1990 assigned-clock-rates = <100000000>; 1991 1992 power-domains = <&gcc PCIE_3B_GDSC>; 1993 1994 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1995 reset-names = "phy"; 1996 1997 #clock-cells = <0>; 1998 clock-output-names = "pcie_3b_pipe_clk"; 1999 2000 #phy-cells = <0>; 2001 2002 status = "disabled"; 2003 }; 2004 2005 pcie3a: pcie@1c10000 { 2006 device_type = "pci"; 2007 compatible = "qcom,pcie-sc8280xp"; 2008 reg = <0x0 0x01c10000 0x0 0x3000>, 2009 <0x0 0x34000000 0x0 0xf1d>, 2010 <0x0 0x34000f20 0x0 0xa8>, 2011 <0x0 0x34001000 0x0 0x1000>, 2012 <0x0 0x34100000 0x0 0x100000>, 2013 <0x0 0x01c13000 0x0 0x1000>; 2014 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2015 #address-cells = <3>; 2016 #size-cells = <2>; 2017 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 2018 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 2019 bus-range = <0x00 0xff>; 2020 2021 dma-coherent; 2022 2023 linux,pci-domain = <4>; 2024 num-lanes = <4>; 2025 2026 msi-map = <0x0 &its 0xc0000 0x10000>; 2027 2028 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2032 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2033 2034 #interrupt-cells = <1>; 2035 interrupt-map-mask = <0 0 0 0x7>; 2036 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 2037 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 2038 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 2039 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 2040 2041 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2042 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2043 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 2044 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 2045 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 2046 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2047 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2048 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2049 clock-names = "aux", 2050 "cfg", 2051 "bus_master", 2052 "bus_slave", 2053 "slave_q2a", 2054 "ddrss_sf_tbu", 2055 "noc_aggr_4", 2056 "noc_aggr_south_sf"; 2057 2058 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 2059 assigned-clock-rates = <19200000>; 2060 2061 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 2062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 2063 interconnect-names = "pcie-mem", "cpu-pcie"; 2064 2065 resets = <&gcc GCC_PCIE_3A_BCR>; 2066 reset-names = "pci"; 2067 2068 power-domains = <&gcc PCIE_3A_GDSC>; 2069 required-opps = <&rpmhpd_opp_nom>; 2070 2071 phys = <&pcie3a_phy>; 2072 phy-names = "pciephy"; 2073 2074 status = "disabled"; 2075 2076 pcie3a_port0: pcie@0 { 2077 device_type = "pci"; 2078 reg = <0x0 0x0 0x0 0x0 0x0>; 2079 bus-range = <0x01 0xff>; 2080 2081 #address-cells = <3>; 2082 #size-cells = <2>; 2083 ranges; 2084 }; 2085 }; 2086 2087 pcie3a_phy: phy@1c14000 { 2088 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2089 reg = <0x0 0x01c14000 0x0 0x2000>, 2090 <0x0 0x01c16000 0x0 0x2000>; 2091 2092 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2093 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2094 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2095 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 2096 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2097 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 2098 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2099 "pipe", "pipediv2"; 2100 2101 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 2102 assigned-clock-rates = <100000000>; 2103 2104 power-domains = <&gcc PCIE_3A_GDSC>; 2105 2106 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2107 reset-names = "phy"; 2108 2109 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2110 2111 #clock-cells = <0>; 2112 clock-output-names = "pcie_3a_pipe_clk"; 2113 2114 #phy-cells = <0>; 2115 2116 status = "disabled"; 2117 }; 2118 2119 pcie2b: pcie@1c18000 { 2120 device_type = "pci"; 2121 compatible = "qcom,pcie-sc8280xp"; 2122 reg = <0x0 0x01c18000 0x0 0x3000>, 2123 <0x0 0x38000000 0x0 0xf1d>, 2124 <0x0 0x38000f20 0x0 0xa8>, 2125 <0x0 0x38001000 0x0 0x1000>, 2126 <0x0 0x38100000 0x0 0x100000>, 2127 <0x0 0x01c1b000 0x0 0x1000>; 2128 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2129 #address-cells = <3>; 2130 #size-cells = <2>; 2131 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2132 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2133 bus-range = <0x00 0xff>; 2134 2135 dma-coherent; 2136 2137 linux,pci-domain = <3>; 2138 num-lanes = <2>; 2139 2140 msi-map = <0x0 &its 0xb0000 0x10000>; 2141 2142 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2146 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2147 2148 #interrupt-cells = <1>; 2149 interrupt-map-mask = <0 0 0 0x7>; 2150 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2151 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2152 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2153 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2154 2155 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2156 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2157 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2158 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2159 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2160 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2161 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2162 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2163 clock-names = "aux", 2164 "cfg", 2165 "bus_master", 2166 "bus_slave", 2167 "slave_q2a", 2168 "ddrss_sf_tbu", 2169 "noc_aggr_4", 2170 "noc_aggr_south_sf"; 2171 2172 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2173 assigned-clock-rates = <19200000>; 2174 2175 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2176 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2177 interconnect-names = "pcie-mem", "cpu-pcie"; 2178 2179 resets = <&gcc GCC_PCIE_2B_BCR>; 2180 reset-names = "pci"; 2181 2182 power-domains = <&gcc PCIE_2B_GDSC>; 2183 required-opps = <&rpmhpd_opp_nom>; 2184 2185 phys = <&pcie2b_phy>; 2186 phy-names = "pciephy"; 2187 2188 status = "disabled"; 2189 2190 pcie2b_port0: pcie@0 { 2191 device_type = "pci"; 2192 reg = <0x0 0x0 0x0 0x0 0x0>; 2193 bus-range = <0x01 0xff>; 2194 2195 #address-cells = <3>; 2196 #size-cells = <2>; 2197 ranges; 2198 }; 2199 }; 2200 2201 pcie2b_phy: phy@1c1e000 { 2202 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2203 reg = <0x0 0x01c1e000 0x0 0x2000>; 2204 2205 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2206 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2207 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2208 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2209 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2210 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2211 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2212 "pipe", "pipediv2"; 2213 2214 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2215 assigned-clock-rates = <100000000>; 2216 2217 power-domains = <&gcc PCIE_2B_GDSC>; 2218 2219 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2220 reset-names = "phy"; 2221 2222 #clock-cells = <0>; 2223 clock-output-names = "pcie_2b_pipe_clk"; 2224 2225 #phy-cells = <0>; 2226 2227 status = "disabled"; 2228 }; 2229 2230 pcie2a: pcie@1c20000 { 2231 device_type = "pci"; 2232 compatible = "qcom,pcie-sc8280xp"; 2233 reg = <0x0 0x01c20000 0x0 0x3000>, 2234 <0x0 0x3c000000 0x0 0xf1d>, 2235 <0x0 0x3c000f20 0x0 0xa8>, 2236 <0x0 0x3c001000 0x0 0x1000>, 2237 <0x0 0x3c100000 0x0 0x100000>, 2238 <0x0 0x01c23000 0x0 0x1000>; 2239 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2240 #address-cells = <3>; 2241 #size-cells = <2>; 2242 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2243 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2244 bus-range = <0x00 0xff>; 2245 2246 dma-coherent; 2247 2248 linux,pci-domain = <2>; 2249 num-lanes = <4>; 2250 2251 msi-map = <0x0 &its 0xa0000 0x10000>; 2252 2253 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2257 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2258 2259 #interrupt-cells = <1>; 2260 interrupt-map-mask = <0 0 0 0x7>; 2261 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2262 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2263 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2264 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2265 2266 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2267 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2268 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2269 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2270 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2271 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2272 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2273 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2274 clock-names = "aux", 2275 "cfg", 2276 "bus_master", 2277 "bus_slave", 2278 "slave_q2a", 2279 "ddrss_sf_tbu", 2280 "noc_aggr_4", 2281 "noc_aggr_south_sf"; 2282 2283 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2284 assigned-clock-rates = <19200000>; 2285 2286 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2287 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2288 interconnect-names = "pcie-mem", "cpu-pcie"; 2289 2290 resets = <&gcc GCC_PCIE_2A_BCR>; 2291 reset-names = "pci"; 2292 2293 power-domains = <&gcc PCIE_2A_GDSC>; 2294 required-opps = <&rpmhpd_opp_nom>; 2295 2296 phys = <&pcie2a_phy>; 2297 phy-names = "pciephy"; 2298 2299 status = "disabled"; 2300 2301 pcie2a_port0: pcie@0 { 2302 device_type = "pci"; 2303 reg = <0x0 0x0 0x0 0x0 0x0>; 2304 bus-range = <0x01 0xff>; 2305 2306 #address-cells = <3>; 2307 #size-cells = <2>; 2308 ranges; 2309 }; 2310 }; 2311 2312 pcie2a_phy: phy@1c24000 { 2313 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2314 reg = <0x0 0x01c24000 0x0 0x2000>, 2315 <0x0 0x01c26000 0x0 0x2000>; 2316 2317 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2318 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2319 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2320 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2321 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2322 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2323 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2324 "pipe", "pipediv2"; 2325 2326 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2327 assigned-clock-rates = <100000000>; 2328 2329 power-domains = <&gcc PCIE_2A_GDSC>; 2330 2331 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2332 reset-names = "phy"; 2333 2334 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2335 2336 #clock-cells = <0>; 2337 clock-output-names = "pcie_2a_pipe_clk"; 2338 2339 #phy-cells = <0>; 2340 2341 status = "disabled"; 2342 }; 2343 2344 ufs_mem_hc: ufshc@1d84000 { 2345 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2346 "jedec,ufs-2.0"; 2347 reg = <0 0x01d84000 0 0x3000>; 2348 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2349 phys = <&ufs_mem_phy>; 2350 phy-names = "ufsphy"; 2351 lanes-per-direction = <2>; 2352 #reset-cells = <1>; 2353 resets = <&gcc GCC_UFS_PHY_BCR>; 2354 reset-names = "rst"; 2355 2356 power-domains = <&gcc UFS_PHY_GDSC>; 2357 required-opps = <&rpmhpd_opp_nom>; 2358 2359 iommus = <&apps_smmu 0xe0 0x0>; 2360 dma-coherent; 2361 2362 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2363 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2364 <&gcc GCC_UFS_PHY_AHB_CLK>, 2365 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2366 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2367 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2368 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2369 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2370 clock-names = "core_clk", 2371 "bus_aggr_clk", 2372 "iface_clk", 2373 "core_clk_unipro", 2374 "ref_clk", 2375 "tx_lane0_sync_clk", 2376 "rx_lane0_sync_clk", 2377 "rx_lane1_sync_clk"; 2378 freq-table-hz = <75000000 300000000>, 2379 <0 0>, 2380 <0 0>, 2381 <75000000 300000000>, 2382 <0 0>, 2383 <0 0>, 2384 <0 0>, 2385 <0 0>; 2386 status = "disabled"; 2387 }; 2388 2389 ufs_mem_phy: phy@1d87000 { 2390 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2391 reg = <0 0x01d87000 0 0x1000>; 2392 2393 clocks = <&rpmhcc RPMH_CXO_CLK>, 2394 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2395 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2396 clock-names = "ref", 2397 "ref_aux", 2398 "qref"; 2399 2400 power-domains = <&gcc UFS_PHY_GDSC>; 2401 2402 resets = <&ufs_mem_hc 0>; 2403 reset-names = "ufsphy"; 2404 2405 #phy-cells = <0>; 2406 2407 status = "disabled"; 2408 }; 2409 2410 ufs_card_hc: ufshc@1da4000 { 2411 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2412 "jedec,ufs-2.0"; 2413 reg = <0 0x01da4000 0 0x3000>; 2414 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2415 phys = <&ufs_card_phy>; 2416 phy-names = "ufsphy"; 2417 lanes-per-direction = <2>; 2418 #reset-cells = <1>; 2419 resets = <&gcc GCC_UFS_CARD_BCR>; 2420 reset-names = "rst"; 2421 2422 power-domains = <&gcc UFS_CARD_GDSC>; 2423 2424 iommus = <&apps_smmu 0x4a0 0x0>; 2425 dma-coherent; 2426 2427 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2428 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2429 <&gcc GCC_UFS_CARD_AHB_CLK>, 2430 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2431 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2432 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2433 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2434 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2435 clock-names = "core_clk", 2436 "bus_aggr_clk", 2437 "iface_clk", 2438 "core_clk_unipro", 2439 "ref_clk", 2440 "tx_lane0_sync_clk", 2441 "rx_lane0_sync_clk", 2442 "rx_lane1_sync_clk"; 2443 freq-table-hz = <75000000 300000000>, 2444 <0 0>, 2445 <0 0>, 2446 <75000000 300000000>, 2447 <0 0>, 2448 <0 0>, 2449 <0 0>, 2450 <0 0>; 2451 status = "disabled"; 2452 }; 2453 2454 ufs_card_phy: phy@1da7000 { 2455 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2456 reg = <0 0x01da7000 0 0x1000>; 2457 2458 clocks = <&rpmhcc RPMH_CXO_CLK>, 2459 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2460 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2461 clock-names = "ref", 2462 "ref_aux", 2463 "qref"; 2464 2465 power-domains = <&gcc UFS_CARD_GDSC>; 2466 2467 resets = <&ufs_card_hc 0>; 2468 reset-names = "ufsphy"; 2469 2470 #phy-cells = <0>; 2471 2472 status = "disabled"; 2473 }; 2474 2475 tcsr_mutex: hwlock@1f40000 { 2476 compatible = "qcom,tcsr-mutex"; 2477 reg = <0x0 0x01f40000 0x0 0x20000>; 2478 #hwlock-cells = <1>; 2479 }; 2480 2481 tcsr: syscon@1fc0000 { 2482 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2483 reg = <0x0 0x01fc0000 0x0 0x30000>; 2484 }; 2485 2486 remoteproc_slpi: remoteproc@2400000 { 2487 compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas"; 2488 reg = <0 0x02400000 0 0x10000>; 2489 2490 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2491 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2492 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2493 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2494 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2495 interrupt-names = "wdog", 2496 "fatal", 2497 "ready", 2498 "handover", 2499 "stop-ack"; 2500 2501 clocks = <&rpmhcc RPMH_CXO_CLK>; 2502 clock-names = "xo"; 2503 2504 power-domains = <&rpmhpd SC8280XP_LCX>, 2505 <&rpmhpd SC8280XP_LMX>; 2506 power-domain-names = "lcx", "lmx"; 2507 2508 memory-region = <&pil_slpi_mem>; 2509 2510 qcom,qmp = <&aoss_qmp>; 2511 2512 qcom,smem-states = <&smp2p_slpi_out 0>; 2513 qcom,smem-state-names = "stop"; 2514 2515 status = "disabled"; 2516 2517 glink-edge { 2518 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2519 IPCC_MPROC_SIGNAL_GLINK_QMP 2520 IRQ_TYPE_EDGE_RISING>; 2521 mboxes = <&ipcc IPCC_CLIENT_SLPI 2522 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2523 2524 label = "slpi"; 2525 qcom,remote-pid = <3>; 2526 2527 fastrpc { 2528 compatible = "qcom,fastrpc"; 2529 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2530 label = "sdsp"; 2531 qcom,non-secure-domain; 2532 #address-cells = <1>; 2533 #size-cells = <0>; 2534 2535 compute-cb@1 { 2536 compatible = "qcom,fastrpc-compute-cb"; 2537 reg = <1>; 2538 iommus = <&apps_smmu 0x0521 0x0>; 2539 }; 2540 2541 compute-cb@2 { 2542 compatible = "qcom,fastrpc-compute-cb"; 2543 reg = <2>; 2544 iommus = <&apps_smmu 0x0522 0x0>; 2545 }; 2546 2547 compute-cb@3 { 2548 compatible = "qcom,fastrpc-compute-cb"; 2549 reg = <3>; 2550 iommus = <&apps_smmu 0x0523 0x0>; 2551 }; 2552 }; 2553 }; 2554 }; 2555 2556 remoteproc_adsp: remoteproc@3000000 { 2557 compatible = "qcom,sc8280xp-adsp-pas"; 2558 reg = <0 0x03000000 0 0x10000>; 2559 2560 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2561 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2562 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2563 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2564 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2565 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2566 interrupt-names = "wdog", "fatal", "ready", 2567 "handover", "stop-ack", "shutdown-ack"; 2568 2569 clocks = <&rpmhcc RPMH_CXO_CLK>; 2570 clock-names = "xo"; 2571 2572 power-domains = <&rpmhpd SC8280XP_LCX>, 2573 <&rpmhpd SC8280XP_LMX>; 2574 power-domain-names = "lcx", "lmx"; 2575 2576 memory-region = <&pil_adsp_mem>; 2577 2578 qcom,qmp = <&aoss_qmp>; 2579 2580 qcom,smem-states = <&smp2p_adsp_out 0>; 2581 qcom,smem-state-names = "stop"; 2582 2583 status = "disabled"; 2584 2585 remoteproc_adsp_glink: glink-edge { 2586 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2587 IPCC_MPROC_SIGNAL_GLINK_QMP 2588 IRQ_TYPE_EDGE_RISING>; 2589 mboxes = <&ipcc IPCC_CLIENT_LPASS 2590 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2591 2592 label = "lpass"; 2593 qcom,remote-pid = <2>; 2594 2595 gpr { 2596 compatible = "qcom,gpr"; 2597 qcom,glink-channels = "adsp_apps"; 2598 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2599 qcom,intents = <512 20>; 2600 #address-cells = <1>; 2601 #size-cells = <0>; 2602 2603 q6apm: service@1 { 2604 compatible = "qcom,q6apm"; 2605 reg = <GPR_APM_MODULE_IID>; 2606 #sound-dai-cells = <0>; 2607 qcom,protection-domain = "avs/audio", 2608 "msm/adsp/audio_pd"; 2609 q6apmdai: dais { 2610 compatible = "qcom,q6apm-dais"; 2611 iommus = <&apps_smmu 0x0c01 0x0>; 2612 }; 2613 2614 q6apmbedai: bedais { 2615 compatible = "qcom,q6apm-lpass-dais"; 2616 #sound-dai-cells = <1>; 2617 }; 2618 }; 2619 2620 q6prm: service@2 { 2621 compatible = "qcom,q6prm"; 2622 reg = <GPR_PRM_MODULE_IID>; 2623 qcom,protection-domain = "avs/audio", 2624 "msm/adsp/audio_pd"; 2625 q6prmcc: clock-controller { 2626 compatible = "qcom,q6prm-lpass-clocks"; 2627 #clock-cells = <2>; 2628 }; 2629 }; 2630 }; 2631 }; 2632 }; 2633 2634 rxmacro: rxmacro@3200000 { 2635 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2636 reg = <0 0x03200000 0 0x1000>; 2637 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2638 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2639 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2640 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2641 <&vamacro>; 2642 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2643 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2644 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2645 assigned-clock-rates = <19200000>, <19200000>; 2646 2647 clock-output-names = "mclk"; 2648 #clock-cells = <0>; 2649 #sound-dai-cells = <1>; 2650 2651 pinctrl-names = "default"; 2652 pinctrl-0 = <&rx_swr_default>; 2653 2654 status = "disabled"; 2655 }; 2656 2657 swr1: soundwire@3210000 { 2658 compatible = "qcom,soundwire-v1.6.0"; 2659 reg = <0 0x03210000 0 0x2000>; 2660 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2661 clocks = <&rxmacro>; 2662 clock-names = "iface"; 2663 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2664 reset-names = "swr_audio_cgcr"; 2665 label = "RX"; 2666 2667 qcom,din-ports = <0>; 2668 qcom,dout-ports = <5>; 2669 2670 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2671 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2672 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2673 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2674 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2675 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2676 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2677 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2678 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2679 2680 #sound-dai-cells = <1>; 2681 #address-cells = <2>; 2682 #size-cells = <0>; 2683 2684 status = "disabled"; 2685 }; 2686 2687 txmacro: txmacro@3220000 { 2688 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2689 reg = <0 0x03220000 0 0x1000>; 2690 pinctrl-names = "default"; 2691 pinctrl-0 = <&tx_swr_default>; 2692 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2693 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2694 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2695 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2696 <&vamacro>; 2697 2698 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2699 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2700 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2701 assigned-clock-rates = <19200000>, <19200000>; 2702 clock-output-names = "mclk"; 2703 2704 #clock-cells = <0>; 2705 #sound-dai-cells = <1>; 2706 2707 status = "disabled"; 2708 }; 2709 2710 wsamacro: codec@3240000 { 2711 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2712 reg = <0 0x03240000 0 0x1000>; 2713 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2714 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2715 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2716 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2717 <&vamacro>; 2718 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2719 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2720 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2721 assigned-clock-rates = <19200000>, <19200000>; 2722 2723 #clock-cells = <0>; 2724 clock-output-names = "mclk"; 2725 #sound-dai-cells = <1>; 2726 2727 pinctrl-names = "default"; 2728 pinctrl-0 = <&wsa_swr_default>; 2729 2730 status = "disabled"; 2731 }; 2732 2733 swr0: soundwire@3250000 { 2734 reg = <0 0x03250000 0 0x2000>; 2735 compatible = "qcom,soundwire-v1.6.0"; 2736 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2737 clocks = <&wsamacro>; 2738 clock-names = "iface"; 2739 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2740 reset-names = "swr_audio_cgcr"; 2741 label = "WSA"; 2742 2743 qcom,din-ports = <2>; 2744 qcom,dout-ports = <6>; 2745 2746 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2747 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2748 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2749 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2750 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2751 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2752 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2753 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2754 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2755 2756 #sound-dai-cells = <1>; 2757 #address-cells = <2>; 2758 #size-cells = <0>; 2759 2760 status = "disabled"; 2761 }; 2762 2763 lpass_audiocc: clock-controller@32a9000 { 2764 compatible = "qcom,sc8280xp-lpassaudiocc"; 2765 reg = <0 0x032a9000 0 0x1000>; 2766 #clock-cells = <1>; 2767 #reset-cells = <1>; 2768 }; 2769 2770 swr2: soundwire@3330000 { 2771 compatible = "qcom,soundwire-v1.6.0"; 2772 reg = <0 0x03330000 0 0x2000>; 2773 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2775 interrupt-names = "core", "wakeup"; 2776 2777 clocks = <&txmacro>; 2778 clock-names = "iface"; 2779 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2780 reset-names = "swr_audio_cgcr"; 2781 label = "TX"; 2782 #sound-dai-cells = <1>; 2783 #address-cells = <2>; 2784 #size-cells = <0>; 2785 2786 qcom,din-ports = <4>; 2787 qcom,dout-ports = <0>; 2788 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2789 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2790 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2791 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2792 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2793 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2794 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2795 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2796 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2797 2798 status = "disabled"; 2799 }; 2800 2801 vamacro: codec@3370000 { 2802 compatible = "qcom,sc8280xp-lpass-va-macro"; 2803 reg = <0 0x03370000 0 0x1000>; 2804 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2805 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2806 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2807 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2808 clock-names = "mclk", "macro", "dcodec", "npl"; 2809 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2810 assigned-clock-rates = <19200000>; 2811 2812 #clock-cells = <0>; 2813 clock-output-names = "fsgen"; 2814 #sound-dai-cells = <1>; 2815 2816 status = "disabled"; 2817 }; 2818 2819 lpass_tlmm: pinctrl@33c0000 { 2820 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2821 reg = <0 0x33c0000 0x0 0x20000>, 2822 <0 0x3550000 0x0 0x10000>; 2823 gpio-controller; 2824 #gpio-cells = <2>; 2825 gpio-ranges = <&lpass_tlmm 0 0 19>; 2826 2827 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2828 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2829 clock-names = "core", "audio"; 2830 2831 status = "disabled"; 2832 2833 tx_swr_default: tx-swr-default-state { 2834 clk-pins { 2835 pins = "gpio0"; 2836 function = "swr_tx_clk"; 2837 drive-strength = <2>; 2838 slew-rate = <1>; 2839 bias-disable; 2840 }; 2841 2842 data-pins { 2843 pins = "gpio1", "gpio2"; 2844 function = "swr_tx_data"; 2845 drive-strength = <2>; 2846 slew-rate = <1>; 2847 bias-bus-hold; 2848 }; 2849 }; 2850 2851 rx_swr_default: rx-swr-default-state { 2852 clk-pins { 2853 pins = "gpio3"; 2854 function = "swr_rx_clk"; 2855 drive-strength = <2>; 2856 slew-rate = <1>; 2857 bias-disable; 2858 }; 2859 2860 data-pins { 2861 pins = "gpio4", "gpio5"; 2862 function = "swr_rx_data"; 2863 drive-strength = <2>; 2864 slew-rate = <1>; 2865 bias-bus-hold; 2866 }; 2867 }; 2868 2869 dmic01_default: dmic01-default-state { 2870 clk-pins { 2871 pins = "gpio6"; 2872 function = "dmic1_clk"; 2873 drive-strength = <8>; 2874 output-high; 2875 }; 2876 2877 data-pins { 2878 pins = "gpio7"; 2879 function = "dmic1_data"; 2880 drive-strength = <8>; 2881 input-enable; 2882 }; 2883 }; 2884 2885 dmic01_sleep: dmic01-sleep-state { 2886 clk-pins { 2887 pins = "gpio6"; 2888 function = "dmic1_clk"; 2889 drive-strength = <2>; 2890 bias-disable; 2891 output-low; 2892 }; 2893 2894 data-pins { 2895 pins = "gpio7"; 2896 function = "dmic1_data"; 2897 drive-strength = <2>; 2898 bias-pull-down; 2899 input-enable; 2900 }; 2901 }; 2902 2903 dmic23_default: dmic23-default-state { 2904 clk-pins { 2905 pins = "gpio8"; 2906 function = "dmic2_clk"; 2907 drive-strength = <8>; 2908 output-high; 2909 }; 2910 2911 data-pins { 2912 pins = "gpio9"; 2913 function = "dmic2_data"; 2914 drive-strength = <8>; 2915 input-enable; 2916 }; 2917 }; 2918 2919 dmic23_sleep: dmic23-sleep-state { 2920 clk-pins { 2921 pins = "gpio8"; 2922 function = "dmic2_clk"; 2923 drive-strength = <2>; 2924 bias-disable; 2925 output-low; 2926 }; 2927 2928 data-pins { 2929 pins = "gpio9"; 2930 function = "dmic2_data"; 2931 drive-strength = <2>; 2932 bias-pull-down; 2933 input-enable; 2934 }; 2935 }; 2936 2937 wsa_swr_default: wsa-swr-default-state { 2938 clk-pins { 2939 pins = "gpio10"; 2940 function = "wsa_swr_clk"; 2941 drive-strength = <2>; 2942 slew-rate = <1>; 2943 bias-disable; 2944 }; 2945 2946 data-pins { 2947 pins = "gpio11"; 2948 function = "wsa_swr_data"; 2949 drive-strength = <2>; 2950 slew-rate = <1>; 2951 bias-bus-hold; 2952 }; 2953 }; 2954 2955 wsa2_swr_default: wsa2-swr-default-state { 2956 clk-pins { 2957 pins = "gpio15"; 2958 function = "wsa2_swr_clk"; 2959 drive-strength = <2>; 2960 slew-rate = <1>; 2961 bias-disable; 2962 }; 2963 2964 data-pins { 2965 pins = "gpio16"; 2966 function = "wsa2_swr_data"; 2967 drive-strength = <2>; 2968 slew-rate = <1>; 2969 bias-bus-hold; 2970 }; 2971 }; 2972 }; 2973 2974 lpasscc: clock-controller@33e0000 { 2975 compatible = "qcom,sc8280xp-lpasscc"; 2976 reg = <0 0x033e0000 0 0x12000>; 2977 #clock-cells = <1>; 2978 #reset-cells = <1>; 2979 }; 2980 2981 gpu: gpu@3d00000 { 2982 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2983 2984 reg = <0 0x03d00000 0 0x40000>, 2985 <0 0x03d9e000 0 0x1000>, 2986 <0 0x03d61000 0 0x800>; 2987 reg-names = "kgsl_3d0_reg_memory", 2988 "cx_mem", 2989 "cx_dbgc"; 2990 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2991 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2992 operating-points-v2 = <&gpu_opp_table>; 2993 2994 qcom,gmu = <&gmu>; 2995 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2996 interconnect-names = "gfx-mem"; 2997 #cooling-cells = <2>; 2998 2999 status = "disabled"; 3000 3001 gpu_opp_table: opp-table { 3002 compatible = "operating-points-v2"; 3003 3004 opp-270000000 { 3005 opp-hz = /bits/ 64 <270000000>; 3006 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3007 opp-peak-kBps = <451000>; 3008 }; 3009 3010 opp-410000000 { 3011 opp-hz = /bits/ 64 <410000000>; 3012 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3013 opp-peak-kBps = <1555000>; 3014 }; 3015 3016 opp-500000000 { 3017 opp-hz = /bits/ 64 <500000000>; 3018 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3019 opp-peak-kBps = <1555000>; 3020 }; 3021 3022 opp-547000000 { 3023 opp-hz = /bits/ 64 <547000000>; 3024 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3025 opp-peak-kBps = <1555000>; 3026 }; 3027 3028 opp-606000000 { 3029 opp-hz = /bits/ 64 <606000000>; 3030 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3031 opp-peak-kBps = <2736000>; 3032 }; 3033 3034 opp-640000000 { 3035 opp-hz = /bits/ 64 <640000000>; 3036 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3037 opp-peak-kBps = <2736000>; 3038 }; 3039 3040 opp-655000000 { 3041 opp-hz = /bits/ 64 <655000000>; 3042 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3043 opp-peak-kBps = <2736000>; 3044 }; 3045 3046 opp-690000000 { 3047 opp-hz = /bits/ 64 <690000000>; 3048 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3049 opp-peak-kBps = <2736000>; 3050 }; 3051 }; 3052 }; 3053 3054 gmu: gmu@3d6a000 { 3055 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 3056 reg = <0 0x03d6a000 0 0x34000>, 3057 <0 0x03de0000 0 0x10000>, 3058 <0 0x0b290000 0 0x10000>; 3059 reg-names = "gmu", "rscc", "gmu_pdc"; 3060 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3062 interrupt-names = "hfi", "gmu"; 3063 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3064 <&gpucc GPU_CC_CXO_CLK>, 3065 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3066 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3067 <&gpucc GPU_CC_AHB_CLK>, 3068 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3069 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3070 clock-names = "gmu", 3071 "cxo", 3072 "axi", 3073 "memnoc", 3074 "ahb", 3075 "hub", 3076 "smmu_vote"; 3077 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3078 <&gpucc GPU_CC_GX_GDSC>; 3079 power-domain-names = "cx", 3080 "gx"; 3081 iommus = <&gpu_smmu 5 0xc00>; 3082 operating-points-v2 = <&gmu_opp_table>; 3083 3084 gmu_opp_table: opp-table { 3085 compatible = "operating-points-v2"; 3086 3087 opp-200000000 { 3088 opp-hz = /bits/ 64 <200000000>; 3089 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3090 }; 3091 3092 opp-500000000 { 3093 opp-hz = /bits/ 64 <500000000>; 3094 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3095 }; 3096 }; 3097 }; 3098 3099 gpucc: clock-controller@3d90000 { 3100 compatible = "qcom,sc8280xp-gpucc"; 3101 reg = <0 0x03d90000 0 0x9000>; 3102 clocks = <&rpmhcc RPMH_CXO_CLK>, 3103 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3104 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3105 clock-names = "bi_tcxo", 3106 "gcc_gpu_gpll0_clk_src", 3107 "gcc_gpu_gpll0_div_clk_src"; 3108 3109 power-domains = <&rpmhpd SC8280XP_GFX>; 3110 #clock-cells = <1>; 3111 #reset-cells = <1>; 3112 #power-domain-cells = <1>; 3113 }; 3114 3115 gpu_smmu: iommu@3da0000 { 3116 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 3117 "qcom,smmu-500", "arm,mmu-500"; 3118 reg = <0 0x03da0000 0 0x20000>; 3119 #iommu-cells = <2>; 3120 #global-interrupts = <2>; 3121 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 3135 3136 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3137 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3138 <&gpucc GPU_CC_AHB_CLK>, 3139 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3140 <&gpucc GPU_CC_CX_GMU_CLK>, 3141 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3142 <&gpucc GPU_CC_HUB_AON_CLK>; 3143 clock-names = "gcc_gpu_memnoc_gfx_clk", 3144 "gcc_gpu_snoc_dvm_gfx_clk", 3145 "gpu_cc_ahb_clk", 3146 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3147 "gpu_cc_cx_gmu_clk", 3148 "gpu_cc_hub_cx_int_clk", 3149 "gpu_cc_hub_aon_clk"; 3150 3151 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3152 dma-coherent; 3153 }; 3154 3155 sdc2: mmc@8804000 { 3156 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3157 reg = <0 0x08804000 0 0x1000>; 3158 3159 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3161 interrupt-names = "hc_irq", "pwr_irq"; 3162 3163 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3164 <&gcc GCC_SDCC2_APPS_CLK>, 3165 <&rpmhcc RPMH_CXO_CLK>; 3166 clock-names = "iface", "core", "xo"; 3167 resets = <&gcc GCC_SDCC2_BCR>; 3168 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3170 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3171 iommus = <&apps_smmu 0x4e0 0x0>; 3172 power-domains = <&rpmhpd SC8280XP_CX>; 3173 operating-points-v2 = <&sdc2_opp_table>; 3174 bus-width = <4>; 3175 dma-coherent; 3176 3177 status = "disabled"; 3178 3179 sdc2_opp_table: opp-table { 3180 compatible = "operating-points-v2"; 3181 3182 opp-100000000 { 3183 opp-hz = /bits/ 64 <100000000>; 3184 required-opps = <&rpmhpd_opp_low_svs>; 3185 opp-peak-kBps = <1800000 400000>; 3186 opp-avg-kBps = <100000 0>; 3187 }; 3188 3189 opp-202000000 { 3190 opp-hz = /bits/ 64 <202000000>; 3191 required-opps = <&rpmhpd_opp_svs_l1>; 3192 opp-peak-kBps = <5400000 1600000>; 3193 opp-avg-kBps = <200000 0>; 3194 }; 3195 }; 3196 }; 3197 3198 usb_0_hsphy: phy@88e5000 { 3199 compatible = "qcom,sc8280xp-usb-hs-phy", 3200 "qcom,usb-snps-hs-5nm-phy"; 3201 reg = <0 0x088e5000 0 0x400>; 3202 clocks = <&rpmhcc RPMH_CXO_CLK>; 3203 clock-names = "ref"; 3204 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3205 3206 #phy-cells = <0>; 3207 3208 status = "disabled"; 3209 }; 3210 3211 usb_2_hsphy0: phy@88e7000 { 3212 compatible = "qcom,sc8280xp-usb-hs-phy", 3213 "qcom,usb-snps-hs-5nm-phy"; 3214 reg = <0 0x088e7000 0 0x400>; 3215 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 3216 clock-names = "ref"; 3217 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 3218 3219 #phy-cells = <0>; 3220 3221 status = "disabled"; 3222 }; 3223 3224 usb_2_hsphy1: phy@88e8000 { 3225 compatible = "qcom,sc8280xp-usb-hs-phy", 3226 "qcom,usb-snps-hs-5nm-phy"; 3227 reg = <0 0x088e8000 0 0x400>; 3228 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 3229 clock-names = "ref"; 3230 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 3231 3232 #phy-cells = <0>; 3233 3234 status = "disabled"; 3235 }; 3236 3237 usb_2_hsphy2: phy@88e9000 { 3238 compatible = "qcom,sc8280xp-usb-hs-phy", 3239 "qcom,usb-snps-hs-5nm-phy"; 3240 reg = <0 0x088e9000 0 0x400>; 3241 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 3242 clock-names = "ref"; 3243 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 3244 3245 #phy-cells = <0>; 3246 3247 status = "disabled"; 3248 }; 3249 3250 usb_2_hsphy3: phy@88ea000 { 3251 compatible = "qcom,sc8280xp-usb-hs-phy", 3252 "qcom,usb-snps-hs-5nm-phy"; 3253 reg = <0 0x088ea000 0 0x400>; 3254 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 3255 clock-names = "ref"; 3256 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 3257 3258 #phy-cells = <0>; 3259 3260 status = "disabled"; 3261 }; 3262 3263 usb_0_qmpphy: phy@88eb000 { 3264 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3265 reg = <0 0x088eb000 0 0x4000>; 3266 3267 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3268 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3269 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3270 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3271 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3272 3273 power-domains = <&gcc USB30_PRIM_GDSC>; 3274 3275 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3276 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3277 reset-names = "phy", "common"; 3278 3279 #clock-cells = <1>; 3280 #phy-cells = <1>; 3281 3282 status = "disabled"; 3283 3284 ports { 3285 #address-cells = <1>; 3286 #size-cells = <0>; 3287 3288 port@0 { 3289 reg = <0>; 3290 3291 usb_0_qmpphy_out: endpoint {}; 3292 }; 3293 3294 port@1 { 3295 reg = <1>; 3296 3297 usb_0_qmpphy_usb_ss_in: endpoint { 3298 remote-endpoint = <&usb_0_dwc3_ss>; 3299 }; 3300 }; 3301 3302 port@2 { 3303 reg = <2>; 3304 3305 usb_0_qmpphy_dp_in: endpoint {}; 3306 }; 3307 }; 3308 }; 3309 3310 usb_2_qmpphy0: phy@88ef000 { 3311 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3312 reg = <0 0x088ef000 0 0x2000>; 3313 3314 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3315 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 3316 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3317 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 3318 clock-names = "aux", "ref", "com_aux", "pipe"; 3319 3320 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 3321 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 3322 reset-names = "phy", "phy_phy"; 3323 3324 power-domains = <&gcc USB30_MP_GDSC>; 3325 3326 #clock-cells = <0>; 3327 clock-output-names = "usb2_phy0_pipe_clk"; 3328 3329 #phy-cells = <0>; 3330 3331 status = "disabled"; 3332 }; 3333 3334 usb_2_qmpphy1: phy@88f1000 { 3335 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3336 reg = <0 0x088f1000 0 0x2000>; 3337 3338 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3339 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 3340 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3341 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 3342 clock-names = "aux", "ref", "com_aux", "pipe"; 3343 3344 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 3345 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 3346 reset-names = "phy", "phy_phy"; 3347 3348 power-domains = <&gcc USB30_MP_GDSC>; 3349 3350 #clock-cells = <0>; 3351 clock-output-names = "usb2_phy1_pipe_clk"; 3352 3353 #phy-cells = <0>; 3354 3355 status = "disabled"; 3356 }; 3357 3358 usb_1_hsphy: phy@8902000 { 3359 compatible = "qcom,sc8280xp-usb-hs-phy", 3360 "qcom,usb-snps-hs-5nm-phy"; 3361 reg = <0 0x08902000 0 0x400>; 3362 #phy-cells = <0>; 3363 3364 clocks = <&rpmhcc RPMH_CXO_CLK>; 3365 clock-names = "ref"; 3366 3367 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3368 3369 status = "disabled"; 3370 }; 3371 3372 usb_1_qmpphy: phy@8903000 { 3373 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3374 reg = <0 0x08903000 0 0x4000>; 3375 3376 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3377 <&gcc GCC_USB4_CLKREF_CLK>, 3378 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3379 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3380 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3381 3382 power-domains = <&gcc USB30_SEC_GDSC>; 3383 3384 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3385 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3386 reset-names = "phy", "common"; 3387 3388 #clock-cells = <1>; 3389 #phy-cells = <1>; 3390 3391 status = "disabled"; 3392 3393 ports { 3394 #address-cells = <1>; 3395 #size-cells = <0>; 3396 3397 port@0 { 3398 reg = <0>; 3399 3400 usb_1_qmpphy_out: endpoint {}; 3401 }; 3402 3403 port@1 { 3404 reg = <1>; 3405 3406 usb_1_qmpphy_usb_ss_in: endpoint { 3407 remote-endpoint = <&usb_1_dwc3_ss>; 3408 }; 3409 }; 3410 3411 port@2 { 3412 reg = <2>; 3413 3414 usb_1_qmpphy_dp_in: endpoint {}; 3415 }; 3416 }; 3417 }; 3418 3419 mdss1_dp0_phy: phy@8909a00 { 3420 compatible = "qcom,sc8280xp-dp-phy"; 3421 reg = <0 0x08909a00 0 0x19c>, 3422 <0 0x08909200 0 0xec>, 3423 <0 0x08909600 0 0xec>, 3424 <0 0x08909000 0 0x1c8>; 3425 3426 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3427 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3428 clock-names = "aux", "cfg_ahb"; 3429 power-domains = <&rpmhpd SC8280XP_MX>; 3430 3431 #clock-cells = <1>; 3432 #phy-cells = <0>; 3433 3434 status = "disabled"; 3435 }; 3436 3437 mdss1_dp1_phy: phy@890ca00 { 3438 compatible = "qcom,sc8280xp-dp-phy"; 3439 reg = <0 0x0890ca00 0 0x19c>, 3440 <0 0x0890c200 0 0xec>, 3441 <0 0x0890c600 0 0xec>, 3442 <0 0x0890c000 0 0x1c8>; 3443 3444 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3445 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3446 clock-names = "aux", "cfg_ahb"; 3447 power-domains = <&rpmhpd SC8280XP_MX>; 3448 3449 #clock-cells = <1>; 3450 #phy-cells = <0>; 3451 3452 status = "disabled"; 3453 }; 3454 3455 pmu@9091000 { 3456 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3457 reg = <0 0x09091000 0 0x1000>; 3458 3459 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3460 3461 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3462 3463 operating-points-v2 = <&llcc_bwmon_opp_table>; 3464 3465 llcc_bwmon_opp_table: opp-table { 3466 compatible = "operating-points-v2"; 3467 3468 opp-0 { 3469 opp-peak-kBps = <762000>; 3470 }; 3471 opp-1 { 3472 opp-peak-kBps = <1720000>; 3473 }; 3474 opp-2 { 3475 opp-peak-kBps = <2086000>; 3476 }; 3477 opp-3 { 3478 opp-peak-kBps = <2597000>; 3479 }; 3480 opp-4 { 3481 opp-peak-kBps = <2929000>; 3482 }; 3483 opp-5 { 3484 opp-peak-kBps = <3879000>; 3485 }; 3486 opp-6 { 3487 opp-peak-kBps = <5161000>; 3488 }; 3489 opp-7 { 3490 opp-peak-kBps = <5931000>; 3491 }; 3492 opp-8 { 3493 opp-peak-kBps = <6515000>; 3494 }; 3495 opp-9 { 3496 opp-peak-kBps = <7980000>; 3497 }; 3498 opp-10 { 3499 opp-peak-kBps = <8136000>; 3500 }; 3501 opp-11 { 3502 opp-peak-kBps = <10437000>; 3503 }; 3504 opp-12 { 3505 opp-peak-kBps = <12191000>; 3506 }; 3507 }; 3508 }; 3509 3510 pmu@90b6400 { 3511 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3512 reg = <0 0x090b6400 0 0x600>; 3513 3514 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3515 3516 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3517 operating-points-v2 = <&cpu_bwmon_opp_table>; 3518 3519 cpu_bwmon_opp_table: opp-table { 3520 compatible = "operating-points-v2"; 3521 3522 opp-0 { 3523 opp-peak-kBps = <2288000>; 3524 }; 3525 opp-1 { 3526 opp-peak-kBps = <4577000>; 3527 }; 3528 opp-2 { 3529 opp-peak-kBps = <7110000>; 3530 }; 3531 opp-3 { 3532 opp-peak-kBps = <9155000>; 3533 }; 3534 opp-4 { 3535 opp-peak-kBps = <12298000>; 3536 }; 3537 opp-5 { 3538 opp-peak-kBps = <14236000>; 3539 }; 3540 opp-6 { 3541 opp-peak-kBps = <15258001>; 3542 }; 3543 }; 3544 }; 3545 3546 system-cache-controller@9200000 { 3547 compatible = "qcom,sc8280xp-llcc"; 3548 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3549 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3550 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3551 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3552 <0 0x09600000 0 0x58000>; 3553 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3554 "llcc3_base", "llcc4_base", "llcc5_base", 3555 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3556 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3557 }; 3558 3559 usb_2: usb@a4f8800 { 3560 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; 3561 reg = <0 0x0a4f8800 0 0x400>; 3562 #address-cells = <2>; 3563 #size-cells = <2>; 3564 ranges; 3565 3566 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 3567 <&gcc GCC_USB30_MP_MASTER_CLK>, 3568 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 3569 <&gcc GCC_USB30_MP_SLEEP_CLK>, 3570 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3571 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3572 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3573 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3574 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3575 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3576 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3577 3578 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3579 <&gcc GCC_USB30_MP_MASTER_CLK>; 3580 assigned-clock-rates = <19200000>, <200000000>; 3581 3582 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3583 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3584 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 3585 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 3586 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3587 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3588 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, 3589 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, 3590 <&pdc 127 IRQ_TYPE_EDGE_BOTH>, 3591 <&pdc 126 IRQ_TYPE_EDGE_BOTH>, 3592 <&pdc 129 IRQ_TYPE_EDGE_BOTH>, 3593 <&pdc 128 IRQ_TYPE_EDGE_BOTH>, 3594 <&pdc 131 IRQ_TYPE_EDGE_BOTH>, 3595 <&pdc 130 IRQ_TYPE_EDGE_BOTH>, 3596 <&pdc 133 IRQ_TYPE_EDGE_BOTH>, 3597 <&pdc 132 IRQ_TYPE_EDGE_BOTH>, 3598 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3599 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3600 3601 interrupt-names = "pwr_event_1", "pwr_event_2", 3602 "pwr_event_3", "pwr_event_4", 3603 "hs_phy_1", "hs_phy_2", 3604 "hs_phy_3", "hs_phy_4", 3605 "dp_hs_phy_1", "dm_hs_phy_1", 3606 "dp_hs_phy_2", "dm_hs_phy_2", 3607 "dp_hs_phy_3", "dm_hs_phy_3", 3608 "dp_hs_phy_4", "dm_hs_phy_4", 3609 "ss_phy_1", "ss_phy_2"; 3610 3611 power-domains = <&gcc USB30_MP_GDSC>; 3612 required-opps = <&rpmhpd_opp_nom>; 3613 3614 resets = <&gcc GCC_USB30_MP_BCR>; 3615 3616 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, 3617 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; 3618 interconnect-names = "usb-ddr", "apps-usb"; 3619 3620 wakeup-source; 3621 3622 status = "disabled"; 3623 3624 usb_2_dwc3: usb@a400000 { 3625 compatible = "snps,dwc3"; 3626 reg = <0 0x0a400000 0 0xcd00>; 3627 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3628 iommus = <&apps_smmu 0x800 0x0>; 3629 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, 3630 <&usb_2_hsphy1>, <&usb_2_qmpphy1>, 3631 <&usb_2_hsphy2>, 3632 <&usb_2_hsphy3>; 3633 phy-names = "usb2-0", "usb3-0", 3634 "usb2-1", "usb3-1", 3635 "usb2-2", 3636 "usb2-3"; 3637 dr_mode = "host"; 3638 snps,dis-u1-entry-quirk; 3639 snps,dis-u2-entry-quirk; 3640 }; 3641 }; 3642 3643 usb_0: usb@a6f8800 { 3644 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3645 reg = <0 0x0a6f8800 0 0x400>; 3646 #address-cells = <2>; 3647 #size-cells = <2>; 3648 ranges; 3649 3650 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3651 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3652 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3653 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3654 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3655 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3656 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3657 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3658 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3659 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3660 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3661 3662 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3663 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3664 assigned-clock-rates = <19200000>, <200000000>; 3665 3666 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3667 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 3668 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3669 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3670 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3671 interrupt-names = "pwr_event", 3672 "hs_phy_irq", 3673 "dp_hs_phy_irq", 3674 "dm_hs_phy_irq", 3675 "ss_phy_irq"; 3676 3677 power-domains = <&gcc USB30_PRIM_GDSC>; 3678 required-opps = <&rpmhpd_opp_nom>; 3679 3680 resets = <&gcc GCC_USB30_PRIM_BCR>; 3681 3682 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3683 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3684 interconnect-names = "usb-ddr", "apps-usb"; 3685 3686 wakeup-source; 3687 3688 status = "disabled"; 3689 3690 usb_0_dwc3: usb@a600000 { 3691 compatible = "snps,dwc3"; 3692 reg = <0 0x0a600000 0 0xcd00>; 3693 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3694 iommus = <&apps_smmu 0x820 0x0>; 3695 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3696 phy-names = "usb2-phy", "usb3-phy"; 3697 snps,dis-u1-entry-quirk; 3698 snps,dis-u2-entry-quirk; 3699 3700 ports { 3701 #address-cells = <1>; 3702 #size-cells = <0>; 3703 3704 port@0 { 3705 reg = <0>; 3706 3707 usb_0_dwc3_hs: endpoint { 3708 }; 3709 }; 3710 3711 port@1 { 3712 reg = <1>; 3713 3714 usb_0_dwc3_ss: endpoint { 3715 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 3716 }; 3717 }; 3718 }; 3719 }; 3720 }; 3721 3722 usb_1: usb@a8f8800 { 3723 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3724 reg = <0 0x0a8f8800 0 0x400>; 3725 #address-cells = <2>; 3726 #size-cells = <2>; 3727 ranges; 3728 3729 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3730 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3731 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3732 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3733 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3734 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3735 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3736 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3737 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3738 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3739 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3740 3741 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3742 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3743 assigned-clock-rates = <19200000>, <200000000>; 3744 3745 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3746 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 3747 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3748 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3749 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3750 interrupt-names = "pwr_event", 3751 "hs_phy_irq", 3752 "dp_hs_phy_irq", 3753 "dm_hs_phy_irq", 3754 "ss_phy_irq"; 3755 3756 power-domains = <&gcc USB30_SEC_GDSC>; 3757 required-opps = <&rpmhpd_opp_nom>; 3758 3759 resets = <&gcc GCC_USB30_SEC_BCR>; 3760 3761 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3762 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3763 interconnect-names = "usb-ddr", "apps-usb"; 3764 3765 wakeup-source; 3766 3767 status = "disabled"; 3768 3769 usb_1_dwc3: usb@a800000 { 3770 compatible = "snps,dwc3"; 3771 reg = <0 0x0a800000 0 0xcd00>; 3772 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3773 iommus = <&apps_smmu 0x860 0x0>; 3774 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3775 phy-names = "usb2-phy", "usb3-phy"; 3776 snps,dis-u1-entry-quirk; 3777 snps,dis-u2-entry-quirk; 3778 3779 ports { 3780 #address-cells = <1>; 3781 #size-cells = <0>; 3782 3783 port@0 { 3784 reg = <0>; 3785 3786 usb_1_dwc3_hs: endpoint { 3787 }; 3788 }; 3789 3790 port@1 { 3791 reg = <1>; 3792 3793 usb_1_dwc3_ss: endpoint { 3794 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3795 }; 3796 }; 3797 }; 3798 }; 3799 }; 3800 3801 cci0: cci@ac4a000 { 3802 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3803 reg = <0 0x0ac4a000 0 0x1000>; 3804 3805 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3806 3807 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3808 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3809 <&camcc CAMCC_CPAS_AHB_CLK>, 3810 <&camcc CAMCC_CCI_0_CLK>; 3811 clock-names = "camnoc_axi", 3812 "slow_ahb_src", 3813 "cpas_ahb", 3814 "cci"; 3815 3816 power-domains = <&camcc TITAN_TOP_GDSC>; 3817 3818 pinctrl-0 = <&cci0_default>; 3819 pinctrl-1 = <&cci0_sleep>; 3820 pinctrl-names = "default", "sleep"; 3821 3822 #address-cells = <1>; 3823 #size-cells = <0>; 3824 3825 status = "disabled"; 3826 3827 cci0_i2c0: i2c-bus@0 { 3828 reg = <0>; 3829 clock-frequency = <1000000>; 3830 #address-cells = <1>; 3831 #size-cells = <0>; 3832 }; 3833 3834 cci0_i2c1: i2c-bus@1 { 3835 reg = <1>; 3836 clock-frequency = <1000000>; 3837 #address-cells = <1>; 3838 #size-cells = <0>; 3839 }; 3840 }; 3841 3842 cci1: cci@ac4b000 { 3843 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3844 reg = <0 0x0ac4b000 0 0x1000>; 3845 3846 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3847 3848 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3849 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3850 <&camcc CAMCC_CPAS_AHB_CLK>, 3851 <&camcc CAMCC_CCI_1_CLK>; 3852 clock-names = "camnoc_axi", 3853 "slow_ahb_src", 3854 "cpas_ahb", 3855 "cci"; 3856 3857 power-domains = <&camcc TITAN_TOP_GDSC>; 3858 3859 pinctrl-0 = <&cci1_default>; 3860 pinctrl-1 = <&cci1_sleep>; 3861 pinctrl-names = "default", "sleep"; 3862 3863 #address-cells = <1>; 3864 #size-cells = <0>; 3865 3866 status = "disabled"; 3867 3868 cci1_i2c0: i2c-bus@0 { 3869 reg = <0>; 3870 clock-frequency = <1000000>; 3871 #address-cells = <1>; 3872 #size-cells = <0>; 3873 }; 3874 3875 cci1_i2c1: i2c-bus@1 { 3876 reg = <1>; 3877 clock-frequency = <1000000>; 3878 #address-cells = <1>; 3879 #size-cells = <0>; 3880 }; 3881 }; 3882 3883 cci2: cci@ac4c000 { 3884 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3885 reg = <0 0x0ac4c000 0 0x1000>; 3886 3887 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 3888 3889 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3890 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3891 <&camcc CAMCC_CPAS_AHB_CLK>, 3892 <&camcc CAMCC_CCI_2_CLK>; 3893 clock-names = "camnoc_axi", 3894 "slow_ahb_src", 3895 "cpas_ahb", 3896 "cci"; 3897 power-domains = <&camcc TITAN_TOP_GDSC>; 3898 3899 pinctrl-0 = <&cci2_default>; 3900 pinctrl-1 = <&cci2_sleep>; 3901 pinctrl-names = "default", "sleep"; 3902 3903 #address-cells = <1>; 3904 #size-cells = <0>; 3905 3906 status = "disabled"; 3907 3908 cci2_i2c0: i2c-bus@0 { 3909 reg = <0>; 3910 clock-frequency = <1000000>; 3911 #address-cells = <1>; 3912 #size-cells = <0>; 3913 }; 3914 3915 cci2_i2c1: i2c-bus@1 { 3916 reg = <1>; 3917 clock-frequency = <1000000>; 3918 #address-cells = <1>; 3919 #size-cells = <0>; 3920 }; 3921 }; 3922 3923 cci3: cci@ac4d000 { 3924 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3925 reg = <0 0x0ac4d000 0 0x1000>; 3926 3927 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 3928 3929 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3930 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3931 <&camcc CAMCC_CPAS_AHB_CLK>, 3932 <&camcc CAMCC_CCI_3_CLK>; 3933 clock-names = "camnoc_axi", 3934 "slow_ahb_src", 3935 "cpas_ahb", 3936 "cci"; 3937 3938 power-domains = <&camcc TITAN_TOP_GDSC>; 3939 3940 pinctrl-0 = <&cci3_default>; 3941 pinctrl-1 = <&cci3_sleep>; 3942 pinctrl-names = "default", "sleep"; 3943 3944 #address-cells = <1>; 3945 #size-cells = <0>; 3946 3947 status = "disabled"; 3948 3949 cci3_i2c0: i2c-bus@0 { 3950 reg = <0>; 3951 clock-frequency = <1000000>; 3952 #address-cells = <1>; 3953 #size-cells = <0>; 3954 }; 3955 3956 cci3_i2c1: i2c-bus@1 { 3957 reg = <1>; 3958 clock-frequency = <1000000>; 3959 #address-cells = <1>; 3960 #size-cells = <0>; 3961 }; 3962 }; 3963 3964 camss: camss@ac5a000 { 3965 compatible = "qcom,sc8280xp-camss"; 3966 3967 reg = <0 0x0ac5a000 0 0x2000>, 3968 <0 0x0ac5c000 0 0x2000>, 3969 <0 0x0ac65000 0 0x2000>, 3970 <0 0x0ac67000 0 0x2000>, 3971 <0 0x0acaf000 0 0x4000>, 3972 <0 0x0acb3000 0 0x1000>, 3973 <0 0x0acb6000 0 0x4000>, 3974 <0 0x0acba000 0 0x1000>, 3975 <0 0x0acbd000 0 0x4000>, 3976 <0 0x0acc1000 0 0x1000>, 3977 <0 0x0acc4000 0 0x4000>, 3978 <0 0x0acc8000 0 0x1000>, 3979 <0 0x0accb000 0 0x4000>, 3980 <0 0x0accf000 0 0x1000>, 3981 <0 0x0acd2000 0 0x4000>, 3982 <0 0x0acd6000 0 0x1000>, 3983 <0 0x0acd9000 0 0x4000>, 3984 <0 0x0acdd000 0 0x1000>, 3985 <0 0x0ace0000 0 0x4000>, 3986 <0 0x0ace4000 0 0x1000>; 3987 reg-names = "csiphy2", 3988 "csiphy3", 3989 "csiphy0", 3990 "csiphy1", 3991 "vfe0", 3992 "csid0", 3993 "vfe1", 3994 "csid1", 3995 "vfe2", 3996 "csid2", 3997 "vfe_lite0", 3998 "csid0_lite", 3999 "vfe_lite1", 4000 "csid1_lite", 4001 "vfe_lite2", 4002 "csid2_lite", 4003 "vfe_lite3", 4004 "csid3_lite", 4005 "vfe3", 4006 "csid3"; 4007 4008 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4009 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4010 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4011 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4012 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4013 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4014 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4015 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4016 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4017 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4018 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4019 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4020 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4021 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4022 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4023 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4024 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4025 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4026 <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, 4027 <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; 4028 interrupt-names = "csid1_lite", 4029 "vfe_lite1", 4030 "csiphy3", 4031 "csid0", 4032 "vfe0", 4033 "csid1", 4034 "vfe1", 4035 "csid0_lite", 4036 "vfe_lite0", 4037 "csiphy0", 4038 "csiphy1", 4039 "csiphy2", 4040 "csid2", 4041 "vfe2", 4042 "csid3_lite", 4043 "csid2_lite", 4044 "vfe_lite3", 4045 "vfe_lite2", 4046 "csid3", 4047 "vfe3"; 4048 4049 power-domains = <&camcc IFE_0_GDSC>, 4050 <&camcc IFE_1_GDSC>, 4051 <&camcc IFE_2_GDSC>, 4052 <&camcc IFE_3_GDSC>, 4053 <&camcc TITAN_TOP_GDSC>; 4054 power-domain-names = "ife0", 4055 "ife1", 4056 "ife2", 4057 "ife3", 4058 "top"; 4059 4060 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4061 <&camcc CAMCC_CPAS_AHB_CLK>, 4062 <&camcc CAMCC_CSIPHY0_CLK>, 4063 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 4064 <&camcc CAMCC_CSIPHY1_CLK>, 4065 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 4066 <&camcc CAMCC_CSIPHY2_CLK>, 4067 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 4068 <&camcc CAMCC_CSIPHY3_CLK>, 4069 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 4070 <&camcc CAMCC_IFE_0_AXI_CLK>, 4071 <&camcc CAMCC_IFE_0_CLK>, 4072 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 4073 <&camcc CAMCC_IFE_0_CSID_CLK>, 4074 <&camcc CAMCC_IFE_1_AXI_CLK>, 4075 <&camcc CAMCC_IFE_1_CLK>, 4076 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 4077 <&camcc CAMCC_IFE_1_CSID_CLK>, 4078 <&camcc CAMCC_IFE_2_AXI_CLK>, 4079 <&camcc CAMCC_IFE_2_CLK>, 4080 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 4081 <&camcc CAMCC_IFE_2_CSID_CLK>, 4082 <&camcc CAMCC_IFE_3_AXI_CLK>, 4083 <&camcc CAMCC_IFE_3_CLK>, 4084 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 4085 <&camcc CAMCC_IFE_3_CSID_CLK>, 4086 <&camcc CAMCC_IFE_LITE_0_CLK>, 4087 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 4088 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 4089 <&camcc CAMCC_IFE_LITE_1_CLK>, 4090 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 4091 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 4092 <&camcc CAMCC_IFE_LITE_2_CLK>, 4093 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 4094 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 4095 <&camcc CAMCC_IFE_LITE_3_CLK>, 4096 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 4097 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 4098 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4099 <&gcc GCC_CAMERA_SF_AXI_CLK>; 4100 clock-names = "camnoc_axi", 4101 "cpas_ahb", 4102 "csiphy0", 4103 "csiphy0_timer", 4104 "csiphy1", 4105 "csiphy1_timer", 4106 "csiphy2", 4107 "csiphy2_timer", 4108 "csiphy3", 4109 "csiphy3_timer", 4110 "vfe0_axi", 4111 "vfe0", 4112 "vfe0_cphy_rx", 4113 "vfe0_csid", 4114 "vfe1_axi", 4115 "vfe1", 4116 "vfe1_cphy_rx", 4117 "vfe1_csid", 4118 "vfe2_axi", 4119 "vfe2", 4120 "vfe2_cphy_rx", 4121 "vfe2_csid", 4122 "vfe3_axi", 4123 "vfe3", 4124 "vfe3_cphy_rx", 4125 "vfe3_csid", 4126 "vfe_lite0", 4127 "vfe_lite0_cphy_rx", 4128 "vfe_lite0_csid", 4129 "vfe_lite1", 4130 "vfe_lite1_cphy_rx", 4131 "vfe_lite1_csid", 4132 "vfe_lite2", 4133 "vfe_lite2_cphy_rx", 4134 "vfe_lite2_csid", 4135 "vfe_lite3", 4136 "vfe_lite3_cphy_rx", 4137 "vfe_lite3_csid", 4138 "gcc_axi_hf", 4139 "gcc_axi_sf"; 4140 4141 iommus = <&apps_smmu 0x2000 0x4e0>, 4142 <&apps_smmu 0x2020 0x4e0>, 4143 <&apps_smmu 0x2040 0x4e0>, 4144 <&apps_smmu 0x2060 0x4e0>, 4145 <&apps_smmu 0x2080 0x4e0>, 4146 <&apps_smmu 0x20e0 0x4e0>, 4147 <&apps_smmu 0x20c0 0x4e0>, 4148 <&apps_smmu 0x20a0 0x4e0>, 4149 <&apps_smmu 0x2400 0x4e0>, 4150 <&apps_smmu 0x2420 0x4e0>, 4151 <&apps_smmu 0x2440 0x4e0>, 4152 <&apps_smmu 0x2460 0x4e0>, 4153 <&apps_smmu 0x2480 0x4e0>, 4154 <&apps_smmu 0x24e0 0x4e0>, 4155 <&apps_smmu 0x24c0 0x4e0>, 4156 <&apps_smmu 0x24a0 0x4e0>; 4157 4158 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 4159 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 4160 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 4161 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 4162 interconnect-names = "cam_ahb", 4163 "cam_hf_mnoc", 4164 "cam_sf_mnoc", 4165 "cam_sf_icp_mnoc"; 4166 4167 status = "disabled"; 4168 4169 ports { 4170 #address-cells = <1>; 4171 #size-cells = <0>; 4172 4173 port@0 { 4174 reg = <0>; 4175 #address-cells = <1>; 4176 #size-cells = <0>; 4177 }; 4178 4179 port@1 { 4180 reg = <1>; 4181 #address-cells = <1>; 4182 #size-cells = <0>; 4183 }; 4184 4185 port@2 { 4186 reg = <2>; 4187 #address-cells = <1>; 4188 #size-cells = <0>; 4189 }; 4190 4191 port@3 { 4192 reg = <3>; 4193 #address-cells = <1>; 4194 #size-cells = <0>; 4195 }; 4196 }; 4197 }; 4198 4199 camcc: clock-controller@ad00000 { 4200 compatible = "qcom,sc8280xp-camcc"; 4201 reg = <0 0x0ad00000 0 0x20000>; 4202 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4203 <&rpmhcc RPMH_CXO_CLK>, 4204 <&rpmhcc RPMH_CXO_CLK_A>, 4205 <&sleep_clk>; 4206 power-domains = <&rpmhpd SC8280XP_MMCX>; 4207 required-opps = <&rpmhpd_opp_low_svs>; 4208 #clock-cells = <1>; 4209 #reset-cells = <1>; 4210 #power-domain-cells = <1>; 4211 }; 4212 4213 mdss0: display-subsystem@ae00000 { 4214 compatible = "qcom,sc8280xp-mdss"; 4215 reg = <0 0x0ae00000 0 0x1000>; 4216 reg-names = "mdss"; 4217 4218 clocks = <&gcc GCC_DISP_AHB_CLK>, 4219 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4220 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 4221 clock-names = "iface", 4222 "ahb", 4223 "core"; 4224 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4225 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 4226 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 4227 interconnect-names = "mdp0-mem", "mdp1-mem"; 4228 iommus = <&apps_smmu 0x1000 0x402>; 4229 power-domains = <&dispcc0 MDSS_GDSC>; 4230 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 4231 4232 interrupt-controller; 4233 #interrupt-cells = <1>; 4234 #address-cells = <2>; 4235 #size-cells = <2>; 4236 ranges; 4237 4238 status = "disabled"; 4239 4240 mdss0_mdp: display-controller@ae01000 { 4241 compatible = "qcom,sc8280xp-dpu"; 4242 reg = <0 0x0ae01000 0 0x8f000>, 4243 <0 0x0aeb0000 0 0x3000>; 4244 reg-names = "mdp", "vbif"; 4245 4246 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4247 <&gcc GCC_DISP_SF_AXI_CLK>, 4248 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4249 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 4250 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 4251 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4252 clock-names = "bus", 4253 "nrt_bus", 4254 "iface", 4255 "lut", 4256 "core", 4257 "vsync"; 4258 interrupt-parent = <&mdss0>; 4259 interrupts = <0>; 4260 power-domains = <&rpmhpd SC8280XP_MMCX>; 4261 4262 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4263 assigned-clock-rates = <19200000>; 4264 operating-points-v2 = <&mdss0_mdp_opp_table>; 4265 4266 ports { 4267 #address-cells = <1>; 4268 #size-cells = <0>; 4269 4270 port@0 { 4271 reg = <0>; 4272 mdss0_intf0_out: endpoint { 4273 remote-endpoint = <&mdss0_dp0_in>; 4274 }; 4275 }; 4276 4277 port@4 { 4278 reg = <4>; 4279 mdss0_intf4_out: endpoint { 4280 remote-endpoint = <&mdss0_dp1_in>; 4281 }; 4282 }; 4283 4284 port@5 { 4285 reg = <5>; 4286 mdss0_intf5_out: endpoint { 4287 remote-endpoint = <&mdss0_dp3_in>; 4288 }; 4289 }; 4290 4291 port@6 { 4292 reg = <6>; 4293 mdss0_intf6_out: endpoint { 4294 remote-endpoint = <&mdss0_dp2_in>; 4295 }; 4296 }; 4297 }; 4298 4299 mdss0_mdp_opp_table: opp-table { 4300 compatible = "operating-points-v2"; 4301 4302 opp-200000000 { 4303 opp-hz = /bits/ 64 <200000000>; 4304 required-opps = <&rpmhpd_opp_low_svs>; 4305 }; 4306 4307 opp-300000000 { 4308 opp-hz = /bits/ 64 <300000000>; 4309 required-opps = <&rpmhpd_opp_svs>; 4310 }; 4311 4312 opp-375000000 { 4313 opp-hz = /bits/ 64 <375000000>; 4314 required-opps = <&rpmhpd_opp_svs_l1>; 4315 }; 4316 4317 opp-500000000 { 4318 opp-hz = /bits/ 64 <500000000>; 4319 required-opps = <&rpmhpd_opp_nom>; 4320 }; 4321 opp-600000000 { 4322 opp-hz = /bits/ 64 <600000000>; 4323 required-opps = <&rpmhpd_opp_turbo_l1>; 4324 }; 4325 }; 4326 }; 4327 4328 mdss0_dp0: displayport-controller@ae90000 { 4329 compatible = "qcom,sc8280xp-dp"; 4330 reg = <0 0xae90000 0 0x200>, 4331 <0 0xae90200 0 0x200>, 4332 <0 0xae90400 0 0x600>, 4333 <0 0xae91000 0 0x400>, 4334 <0 0xae91400 0 0x400>; 4335 interrupt-parent = <&mdss0>; 4336 interrupts = <12>; 4337 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4338 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4339 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4340 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4341 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4342 clock-names = "core_iface", "core_aux", 4343 "ctrl_link", 4344 "ctrl_link_iface", 4345 "stream_pixel"; 4346 4347 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4348 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4349 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4350 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4351 4352 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4353 phy-names = "dp"; 4354 4355 #sound-dai-cells = <0>; 4356 4357 operating-points-v2 = <&mdss0_dp0_opp_table>; 4358 power-domains = <&rpmhpd SC8280XP_MMCX>; 4359 4360 status = "disabled"; 4361 4362 ports { 4363 #address-cells = <1>; 4364 #size-cells = <0>; 4365 4366 port@0 { 4367 reg = <0>; 4368 4369 mdss0_dp0_in: endpoint { 4370 remote-endpoint = <&mdss0_intf0_out>; 4371 }; 4372 }; 4373 4374 port@1 { 4375 reg = <1>; 4376 4377 mdss0_dp0_out: endpoint { 4378 }; 4379 }; 4380 }; 4381 4382 mdss0_dp0_opp_table: opp-table { 4383 compatible = "operating-points-v2"; 4384 4385 opp-160000000 { 4386 opp-hz = /bits/ 64 <160000000>; 4387 required-opps = <&rpmhpd_opp_low_svs>; 4388 }; 4389 4390 opp-270000000 { 4391 opp-hz = /bits/ 64 <270000000>; 4392 required-opps = <&rpmhpd_opp_svs>; 4393 }; 4394 4395 opp-540000000 { 4396 opp-hz = /bits/ 64 <540000000>; 4397 required-opps = <&rpmhpd_opp_svs_l1>; 4398 }; 4399 4400 opp-810000000 { 4401 opp-hz = /bits/ 64 <810000000>; 4402 required-opps = <&rpmhpd_opp_nom>; 4403 }; 4404 }; 4405 }; 4406 4407 mdss0_dp1: displayport-controller@ae98000 { 4408 compatible = "qcom,sc8280xp-dp"; 4409 reg = <0 0xae98000 0 0x200>, 4410 <0 0xae98200 0 0x200>, 4411 <0 0xae98400 0 0x600>, 4412 <0 0xae99000 0 0x400>, 4413 <0 0xae99400 0 0x400>; 4414 interrupt-parent = <&mdss0>; 4415 interrupts = <13>; 4416 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4417 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4418 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4419 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4420 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4421 clock-names = "core_iface", "core_aux", 4422 "ctrl_link", 4423 "ctrl_link_iface", "stream_pixel"; 4424 4425 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4426 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4427 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4428 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4429 4430 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4431 phy-names = "dp"; 4432 4433 #sound-dai-cells = <0>; 4434 4435 operating-points-v2 = <&mdss0_dp1_opp_table>; 4436 power-domains = <&rpmhpd SC8280XP_MMCX>; 4437 4438 status = "disabled"; 4439 4440 ports { 4441 #address-cells = <1>; 4442 #size-cells = <0>; 4443 4444 port@0 { 4445 reg = <0>; 4446 4447 mdss0_dp1_in: endpoint { 4448 remote-endpoint = <&mdss0_intf4_out>; 4449 }; 4450 }; 4451 4452 port@1 { 4453 reg = <1>; 4454 4455 mdss0_dp1_out: endpoint { 4456 }; 4457 }; 4458 }; 4459 4460 mdss0_dp1_opp_table: opp-table { 4461 compatible = "operating-points-v2"; 4462 4463 opp-160000000 { 4464 opp-hz = /bits/ 64 <160000000>; 4465 required-opps = <&rpmhpd_opp_low_svs>; 4466 }; 4467 4468 opp-270000000 { 4469 opp-hz = /bits/ 64 <270000000>; 4470 required-opps = <&rpmhpd_opp_svs>; 4471 }; 4472 4473 opp-540000000 { 4474 opp-hz = /bits/ 64 <540000000>; 4475 required-opps = <&rpmhpd_opp_svs_l1>; 4476 }; 4477 4478 opp-810000000 { 4479 opp-hz = /bits/ 64 <810000000>; 4480 required-opps = <&rpmhpd_opp_nom>; 4481 }; 4482 }; 4483 }; 4484 4485 mdss0_dp2: displayport-controller@ae9a000 { 4486 compatible = "qcom,sc8280xp-dp"; 4487 reg = <0 0xae9a000 0 0x200>, 4488 <0 0xae9a200 0 0x200>, 4489 <0 0xae9a400 0 0x600>, 4490 <0 0xae9b000 0 0x400>, 4491 <0 0xae9b400 0 0x400>; 4492 4493 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4494 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4495 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4496 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4497 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4498 clock-names = "core_iface", "core_aux", 4499 "ctrl_link", 4500 "ctrl_link_iface", "stream_pixel"; 4501 interrupt-parent = <&mdss0>; 4502 interrupts = <14>; 4503 phys = <&mdss0_dp2_phy>; 4504 phy-names = "dp"; 4505 power-domains = <&rpmhpd SC8280XP_MMCX>; 4506 4507 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4508 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4509 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 4510 operating-points-v2 = <&mdss0_dp2_opp_table>; 4511 4512 #sound-dai-cells = <0>; 4513 4514 status = "disabled"; 4515 4516 ports { 4517 #address-cells = <1>; 4518 #size-cells = <0>; 4519 4520 port@0 { 4521 reg = <0>; 4522 mdss0_dp2_in: endpoint { 4523 remote-endpoint = <&mdss0_intf6_out>; 4524 }; 4525 }; 4526 4527 port@1 { 4528 reg = <1>; 4529 }; 4530 }; 4531 4532 mdss0_dp2_opp_table: opp-table { 4533 compatible = "operating-points-v2"; 4534 4535 opp-160000000 { 4536 opp-hz = /bits/ 64 <160000000>; 4537 required-opps = <&rpmhpd_opp_low_svs>; 4538 }; 4539 4540 opp-270000000 { 4541 opp-hz = /bits/ 64 <270000000>; 4542 required-opps = <&rpmhpd_opp_svs>; 4543 }; 4544 4545 opp-540000000 { 4546 opp-hz = /bits/ 64 <540000000>; 4547 required-opps = <&rpmhpd_opp_svs_l1>; 4548 }; 4549 4550 opp-810000000 { 4551 opp-hz = /bits/ 64 <810000000>; 4552 required-opps = <&rpmhpd_opp_nom>; 4553 }; 4554 }; 4555 }; 4556 4557 mdss0_dp3: displayport-controller@aea0000 { 4558 compatible = "qcom,sc8280xp-dp"; 4559 reg = <0 0xaea0000 0 0x200>, 4560 <0 0xaea0200 0 0x200>, 4561 <0 0xaea0400 0 0x600>, 4562 <0 0xaea1000 0 0x400>, 4563 <0 0xaea1400 0 0x400>; 4564 4565 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4566 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4567 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4568 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4569 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4570 clock-names = "core_iface", "core_aux", 4571 "ctrl_link", 4572 "ctrl_link_iface", "stream_pixel"; 4573 interrupt-parent = <&mdss0>; 4574 interrupts = <15>; 4575 phys = <&mdss0_dp3_phy>; 4576 phy-names = "dp"; 4577 power-domains = <&rpmhpd SC8280XP_MMCX>; 4578 4579 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4580 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4581 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 4582 operating-points-v2 = <&mdss0_dp3_opp_table>; 4583 4584 #sound-dai-cells = <0>; 4585 4586 status = "disabled"; 4587 4588 ports { 4589 #address-cells = <1>; 4590 #size-cells = <0>; 4591 4592 port@0 { 4593 reg = <0>; 4594 mdss0_dp3_in: endpoint { 4595 remote-endpoint = <&mdss0_intf5_out>; 4596 }; 4597 }; 4598 4599 port@1 { 4600 reg = <1>; 4601 }; 4602 }; 4603 4604 mdss0_dp3_opp_table: opp-table { 4605 compatible = "operating-points-v2"; 4606 4607 opp-160000000 { 4608 opp-hz = /bits/ 64 <160000000>; 4609 required-opps = <&rpmhpd_opp_low_svs>; 4610 }; 4611 4612 opp-270000000 { 4613 opp-hz = /bits/ 64 <270000000>; 4614 required-opps = <&rpmhpd_opp_svs>; 4615 }; 4616 4617 opp-540000000 { 4618 opp-hz = /bits/ 64 <540000000>; 4619 required-opps = <&rpmhpd_opp_svs_l1>; 4620 }; 4621 4622 opp-810000000 { 4623 opp-hz = /bits/ 64 <810000000>; 4624 required-opps = <&rpmhpd_opp_nom>; 4625 }; 4626 }; 4627 }; 4628 }; 4629 4630 mdss0_dp2_phy: phy@aec2a00 { 4631 compatible = "qcom,sc8280xp-dp-phy"; 4632 reg = <0 0x0aec2a00 0 0x19c>, 4633 <0 0x0aec2200 0 0xec>, 4634 <0 0x0aec2600 0 0xec>, 4635 <0 0x0aec2000 0 0x1c8>; 4636 4637 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4638 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 4639 clock-names = "aux", "cfg_ahb"; 4640 power-domains = <&rpmhpd SC8280XP_MX>; 4641 4642 #clock-cells = <1>; 4643 #phy-cells = <0>; 4644 4645 status = "disabled"; 4646 }; 4647 4648 mdss0_dp3_phy: phy@aec5a00 { 4649 compatible = "qcom,sc8280xp-dp-phy"; 4650 reg = <0 0x0aec5a00 0 0x19c>, 4651 <0 0x0aec5200 0 0xec>, 4652 <0 0x0aec5600 0 0xec>, 4653 <0 0x0aec5000 0 0x1c8>; 4654 4655 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4656 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 4657 clock-names = "aux", "cfg_ahb"; 4658 power-domains = <&rpmhpd SC8280XP_MX>; 4659 4660 #clock-cells = <1>; 4661 #phy-cells = <0>; 4662 4663 status = "disabled"; 4664 }; 4665 4666 dispcc0: clock-controller@af00000 { 4667 compatible = "qcom,sc8280xp-dispcc0"; 4668 reg = <0 0x0af00000 0 0x20000>; 4669 4670 clocks = <&gcc GCC_DISP_AHB_CLK>, 4671 <&rpmhcc RPMH_CXO_CLK>, 4672 <&sleep_clk>, 4673 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4674 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4675 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4676 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4677 <&mdss0_dp2_phy 0>, 4678 <&mdss0_dp2_phy 1>, 4679 <&mdss0_dp3_phy 0>, 4680 <&mdss0_dp3_phy 1>, 4681 <0>, 4682 <0>, 4683 <0>, 4684 <0>; 4685 power-domains = <&rpmhpd SC8280XP_MMCX>; 4686 4687 #clock-cells = <1>; 4688 #power-domain-cells = <1>; 4689 #reset-cells = <1>; 4690 4691 status = "disabled"; 4692 }; 4693 4694 pdc: interrupt-controller@b220000 { 4695 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 4696 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4697 qcom,pdc-ranges = <0 480 40>, 4698 <40 140 14>, 4699 <54 263 1>, 4700 <55 306 4>, 4701 <59 312 3>, 4702 <62 374 2>, 4703 <64 434 2>, 4704 <66 438 3>, 4705 <69 86 1>, 4706 <70 520 54>, 4707 <124 609 28>, 4708 <159 638 1>, 4709 <160 720 8>, 4710 <168 801 1>, 4711 <169 728 30>, 4712 <199 416 2>, 4713 <201 449 1>, 4714 <202 89 1>, 4715 <203 451 1>, 4716 <204 462 1>, 4717 <205 264 1>, 4718 <206 579 1>, 4719 <207 653 1>, 4720 <208 656 1>, 4721 <209 659 1>, 4722 <210 122 1>, 4723 <211 699 1>, 4724 <212 705 1>, 4725 <213 450 1>, 4726 <214 643 1>, 4727 <216 646 5>, 4728 <221 390 5>, 4729 <226 700 3>, 4730 <229 240 3>, 4731 <232 269 1>, 4732 <233 377 1>, 4733 <234 372 1>, 4734 <235 138 1>, 4735 <236 857 1>, 4736 <237 860 1>, 4737 <238 137 1>, 4738 <239 668 1>, 4739 <240 366 1>, 4740 <241 949 1>, 4741 <242 815 5>, 4742 <247 769 1>, 4743 <248 768 1>, 4744 <249 663 1>, 4745 <250 799 2>, 4746 <252 798 1>, 4747 <253 765 1>, 4748 <254 763 1>, 4749 <255 454 1>, 4750 <258 139 1>, 4751 <259 786 2>, 4752 <261 370 2>, 4753 <263 158 2>; 4754 #interrupt-cells = <2>; 4755 interrupt-parent = <&intc>; 4756 interrupt-controller; 4757 }; 4758 4759 tsens2: thermal-sensor@c251000 { 4760 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4761 reg = <0 0x0c251000 0 0x1ff>, 4762 <0 0x0c224000 0 0x8>; 4763 #qcom,sensors = <11>; 4764 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 4765 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 4766 interrupt-names = "uplow", "critical"; 4767 #thermal-sensor-cells = <1>; 4768 }; 4769 4770 tsens3: thermal-sensor@c252000 { 4771 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4772 reg = <0 0x0c252000 0 0x1ff>, 4773 <0 0x0c225000 0 0x8>; 4774 #qcom,sensors = <5>; 4775 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 4776 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 4777 interrupt-names = "uplow", "critical"; 4778 #thermal-sensor-cells = <1>; 4779 }; 4780 4781 tsens0: thermal-sensor@c263000 { 4782 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4783 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4784 <0 0x0c222000 0 0x8>; /* SROT */ 4785 #qcom,sensors = <14>; 4786 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 4787 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 4788 interrupt-names = "uplow", "critical"; 4789 #thermal-sensor-cells = <1>; 4790 }; 4791 4792 restart@c264000 { 4793 compatible = "qcom,pshold"; 4794 reg = <0 0x0c264000 0 0x4>; 4795 /* TZ seems to block access */ 4796 status = "reserved"; 4797 }; 4798 4799 tsens1: thermal-sensor@c265000 { 4800 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4801 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4802 <0 0x0c223000 0 0x8>; /* SROT */ 4803 #qcom,sensors = <16>; 4804 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4805 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4806 interrupt-names = "uplow", "critical"; 4807 #thermal-sensor-cells = <1>; 4808 }; 4809 4810 aoss_qmp: power-management@c300000 { 4811 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4812 reg = <0 0x0c300000 0 0x400>; 4813 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4814 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4815 4816 #clock-cells = <0>; 4817 }; 4818 4819 sram@c3f0000 { 4820 compatible = "qcom,rpmh-stats"; 4821 reg = <0 0x0c3f0000 0 0x400>; 4822 qcom,qmp = <&aoss_qmp>; 4823 }; 4824 4825 spmi_bus: spmi@c440000 { 4826 compatible = "qcom,spmi-pmic-arb"; 4827 reg = <0 0x0c440000 0 0x1100>, 4828 <0 0x0c600000 0 0x2000000>, 4829 <0 0x0e600000 0 0x100000>, 4830 <0 0x0e700000 0 0xa0000>, 4831 <0 0x0c40a000 0 0x26000>; 4832 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4833 interrupt-names = "periph_irq"; 4834 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4835 qcom,ee = <0>; 4836 qcom,channel = <0>; 4837 #address-cells = <2>; 4838 #size-cells = <0>; 4839 interrupt-controller; 4840 #interrupt-cells = <4>; 4841 }; 4842 4843 tlmm: pinctrl@f100000 { 4844 compatible = "qcom,sc8280xp-tlmm"; 4845 reg = <0 0x0f100000 0 0x300000>; 4846 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4847 gpio-controller; 4848 #gpio-cells = <2>; 4849 interrupt-controller; 4850 #interrupt-cells = <2>; 4851 gpio-ranges = <&tlmm 0 0 230>; 4852 wakeup-parent = <&pdc>; 4853 4854 cci0_default: cci0-default-state { 4855 cci0_i2c0_default: cci0-i2c0-default-pins { 4856 /* cci_i2c_sda0, cci_i2c_scl0 */ 4857 pins = "gpio113", "gpio114"; 4858 function = "cci_i2c"; 4859 drive-strength = <2>; 4860 bias-pull-up; 4861 }; 4862 4863 cci0_i2c1_default: cci0-i2c1-default-pins { 4864 /* cci_i2c_sda1, cci_i2c_scl1 */ 4865 pins = "gpio115", "gpio116"; 4866 function = "cci_i2c"; 4867 drive-strength = <2>; 4868 bias-pull-up; 4869 }; 4870 }; 4871 4872 cci0_sleep: cci0-sleep-state { 4873 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4874 /* cci_i2c_sda0, cci_i2c_scl0 */ 4875 pins = "gpio113", "gpio114"; 4876 function = "cci_i2c"; 4877 drive-strength = <2>; 4878 bias-pull-down; 4879 }; 4880 4881 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4882 /* cci_i2c_sda1, cci_i2c_scl1 */ 4883 pins = "gpio115", "gpio116"; 4884 function = "cci_i2c"; 4885 drive-strength = <2>; 4886 bias-pull-down; 4887 }; 4888 }; 4889 4890 cci1_default: cci1-default-state { 4891 cci1_i2c0_default: cci1-i2c0-default-pins { 4892 /* cci_i2c_sda2, cci_i2c_scl2 */ 4893 pins = "gpio10","gpio11"; 4894 function = "cci_i2c"; 4895 drive-strength = <2>; 4896 bias-pull-up; 4897 }; 4898 4899 cci1_i2c1_default: cci1-i2c1-default-pins { 4900 /* cci_i2c_sda3, cci_i2c_scl3 */ 4901 pins = "gpio123","gpio124"; 4902 function = "cci_i2c"; 4903 drive-strength = <2>; 4904 bias-pull-up; 4905 }; 4906 }; 4907 4908 cci1_sleep: cci1-sleep-state { 4909 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4910 /* cci_i2c_sda2, cci_i2c_scl2 */ 4911 pins = "gpio10","gpio11"; 4912 function = "cci_i2c"; 4913 drive-strength = <2>; 4914 bias-pull-down; 4915 }; 4916 4917 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4918 /* cci_i2c_sda3, cci_i2c_scl3 */ 4919 pins = "gpio123","gpio124"; 4920 function = "cci_i2c"; 4921 drive-strength = <2>; 4922 bias-pull-down; 4923 }; 4924 }; 4925 4926 cci2_default: cci2-default-state { 4927 cci2_i2c0_default: cci2-i2c0-default-pins { 4928 /* cci_i2c_sda4, cci_i2c_scl4 */ 4929 pins = "gpio117","gpio118"; 4930 function = "cci_i2c"; 4931 drive-strength = <2>; 4932 bias-pull-up; 4933 }; 4934 4935 cci2_i2c1_default: cci2-i2c1-default-pins { 4936 /* cci_i2c_sda5, cci_i2c_scl5 */ 4937 pins = "gpio12","gpio13"; 4938 function = "cci_i2c"; 4939 drive-strength = <2>; 4940 bias-pull-up; 4941 }; 4942 }; 4943 4944 cci2_sleep: cci2-sleep-state { 4945 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 4946 /* cci_i2c_sda4, cci_i2c_scl4 */ 4947 pins = "gpio117","gpio118"; 4948 function = "cci_i2c"; 4949 drive-strength = <2>; 4950 bias-pull-down; 4951 }; 4952 4953 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 4954 /* cci_i2c_sda5, cci_i2c_scl5 */ 4955 pins = "gpio12","gpio13"; 4956 function = "cci_i2c"; 4957 drive-strength = <2>; 4958 bias-pull-down; 4959 }; 4960 }; 4961 4962 cci3_default: cci3-default-state { 4963 cci3_i2c0_default: cci3-i2c0-default-pins { 4964 /* cci_i2c_sda6, cci_i2c_scl6 */ 4965 pins = "gpio145","gpio146"; 4966 function = "cci_i2c"; 4967 drive-strength = <2>; 4968 bias-pull-up; 4969 }; 4970 4971 cci3_i2c1_default: cci3-i2c1-default-pins { 4972 /* cci_i2c_sda7, cci_i2c_scl7 */ 4973 pins = "gpio164","gpio165"; 4974 function = "cci_i2c"; 4975 drive-strength = <2>; 4976 bias-pull-up; 4977 }; 4978 }; 4979 4980 cci3_sleep: cci3-sleep-state { 4981 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 4982 /* cci_i2c_sda6, cci_i2c_scl6 */ 4983 pins = "gpio145","gpio146"; 4984 function = "cci_i2c"; 4985 drive-strength = <2>; 4986 bias-pull-down; 4987 }; 4988 4989 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 4990 /* cci_i2c_sda7, cci_i2c_scl7 */ 4991 pins = "gpio164","gpio165"; 4992 function = "cci_i2c"; 4993 drive-strength = <2>; 4994 bias-pull-down; 4995 }; 4996 }; 4997 4998 qup_uart18_default: qup-uart18-default-state { 4999 cts-pins { 5000 pins = "gpio66"; 5001 function = "qup18"; 5002 drive-strength = <2>; 5003 bias-disable; 5004 }; 5005 5006 rts-pins { 5007 pins = "gpio67"; 5008 function = "qup18"; 5009 drive-strength = <2>; 5010 bias-disable; 5011 }; 5012 5013 tx-pins { 5014 pins = "gpio68"; 5015 function = "qup18"; 5016 drive-strength = <2>; 5017 bias-disable; 5018 }; 5019 5020 rx-pins { 5021 pins = "gpio69"; 5022 function = "qup18"; 5023 drive-strength = <2>; 5024 bias-disable; 5025 }; 5026 }; 5027 }; 5028 5029 pcie_smmu: iommu@14f80000 { 5030 compatible = "arm,smmu-v3"; 5031 reg = <0 0x14f80000 0 0x80000>; 5032 #iommu-cells = <1>; 5033 interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>, 5034 <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>, 5035 <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>; 5036 interrupt-names = "eventq", 5037 "gerror", 5038 "cmdq-sync"; 5039 dma-coherent; 5040 status = "reserved"; /* Controlled by QHEE. */ 5041 }; 5042 5043 apps_smmu: iommu@15000000 { 5044 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 5045 reg = <0 0x15000000 0 0x100000>; 5046 #iommu-cells = <2>; 5047 #global-interrupts = <2>; 5048 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 5178 dma-coherent; 5179 }; 5180 5181 intc: interrupt-controller@17a00000 { 5182 compatible = "arm,gic-v3"; 5183 interrupt-controller; 5184 #interrupt-cells = <3>; 5185 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5186 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5187 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5188 #redistributor-regions = <1>; 5189 redistributor-stride = <0 0x20000>; 5190 5191 #address-cells = <2>; 5192 #size-cells = <2>; 5193 ranges; 5194 5195 its: msi-controller@17a40000 { 5196 compatible = "arm,gic-v3-its"; 5197 reg = <0 0x17a40000 0 0x20000>; 5198 msi-controller; 5199 #msi-cells = <1>; 5200 }; 5201 }; 5202 5203 watchdog@17c10000 { 5204 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 5205 reg = <0 0x17c10000 0 0x1000>; 5206 clocks = <&sleep_clk>; 5207 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5208 }; 5209 5210 timer@17c20000 { 5211 compatible = "arm,armv7-timer-mem"; 5212 reg = <0x0 0x17c20000 0x0 0x1000>; 5213 #address-cells = <1>; 5214 #size-cells = <1>; 5215 ranges = <0x0 0x0 0x0 0x20000000>; 5216 5217 frame@17c21000 { 5218 frame-number = <0>; 5219 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5220 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5221 reg = <0x17c21000 0x1000>, 5222 <0x17c22000 0x1000>; 5223 }; 5224 5225 frame@17c23000 { 5226 frame-number = <1>; 5227 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5228 reg = <0x17c23000 0x1000>; 5229 status = "disabled"; 5230 }; 5231 5232 frame@17c25000 { 5233 frame-number = <2>; 5234 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5235 reg = <0x17c25000 0x1000>; 5236 status = "disabled"; 5237 }; 5238 5239 frame@17c27000 { 5240 frame-number = <3>; 5241 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5242 reg = <0x17c26000 0x1000>; 5243 status = "disabled"; 5244 }; 5245 5246 frame@17c29000 { 5247 frame-number = <4>; 5248 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5249 reg = <0x17c29000 0x1000>; 5250 status = "disabled"; 5251 }; 5252 5253 frame@17c2b000 { 5254 frame-number = <5>; 5255 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5256 reg = <0x17c2b000 0x1000>; 5257 status = "disabled"; 5258 }; 5259 5260 frame@17c2d000 { 5261 frame-number = <6>; 5262 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5263 reg = <0x17c2d000 0x1000>; 5264 status = "disabled"; 5265 }; 5266 }; 5267 5268 apps_rsc: rsc@18200000 { 5269 compatible = "qcom,rpmh-rsc"; 5270 reg = <0x0 0x18200000 0x0 0x10000>, 5271 <0x0 0x18210000 0x0 0x10000>, 5272 <0x0 0x18220000 0x0 0x10000>; 5273 reg-names = "drv-0", "drv-1", "drv-2"; 5274 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5275 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5276 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5277 qcom,tcs-offset = <0xd00>; 5278 qcom,drv-id = <2>; 5279 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5280 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5281 label = "apps_rsc"; 5282 power-domains = <&cluster_pd>; 5283 5284 apps_bcm_voter: bcm-voter { 5285 compatible = "qcom,bcm-voter"; 5286 }; 5287 5288 rpmhcc: clock-controller { 5289 compatible = "qcom,sc8280xp-rpmh-clk"; 5290 #clock-cells = <1>; 5291 clock-names = "xo"; 5292 clocks = <&xo_board_clk>; 5293 }; 5294 5295 rpmhpd: power-controller { 5296 compatible = "qcom,sc8280xp-rpmhpd"; 5297 #power-domain-cells = <1>; 5298 operating-points-v2 = <&rpmhpd_opp_table>; 5299 5300 rpmhpd_opp_table: opp-table { 5301 compatible = "operating-points-v2"; 5302 5303 rpmhpd_opp_ret: opp1 { 5304 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5305 }; 5306 5307 rpmhpd_opp_min_svs: opp2 { 5308 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5309 }; 5310 5311 rpmhpd_opp_low_svs: opp3 { 5312 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5313 }; 5314 5315 rpmhpd_opp_svs: opp4 { 5316 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5317 }; 5318 5319 rpmhpd_opp_svs_l1: opp5 { 5320 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5321 }; 5322 5323 rpmhpd_opp_nom: opp6 { 5324 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5325 }; 5326 5327 rpmhpd_opp_nom_l1: opp7 { 5328 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5329 }; 5330 5331 rpmhpd_opp_nom_l2: opp8 { 5332 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5333 }; 5334 5335 rpmhpd_opp_turbo: opp9 { 5336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5337 }; 5338 5339 rpmhpd_opp_turbo_l1: opp10 { 5340 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5341 }; 5342 }; 5343 }; 5344 }; 5345 5346 epss_l3: interconnect@18590000 { 5347 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 5348 reg = <0 0x18590000 0 0x1000>; 5349 5350 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5351 clock-names = "xo", "alternate"; 5352 5353 #interconnect-cells = <1>; 5354 }; 5355 5356 cpufreq_hw: cpufreq@18591000 { 5357 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 5358 reg = <0 0x18591000 0 0x1000>, 5359 <0 0x18592000 0 0x1000>; 5360 reg-names = "freq-domain0", "freq-domain1"; 5361 5362 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5363 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 5364 interrupt-names = "dcvsh-irq-0", 5365 "dcvsh-irq-1"; 5366 5367 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5368 clock-names = "xo", "alternate"; 5369 5370 #freq-domain-cells = <1>; 5371 #clock-cells = <1>; 5372 }; 5373 5374 remoteproc_nsp0: remoteproc@1b300000 { 5375 compatible = "qcom,sc8280xp-nsp0-pas"; 5376 reg = <0 0x1b300000 0 0x10000>; 5377 5378 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5379 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 5380 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 5381 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 5382 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 5383 interrupt-names = "wdog", "fatal", "ready", 5384 "handover", "stop-ack"; 5385 5386 clocks = <&rpmhcc RPMH_CXO_CLK>; 5387 clock-names = "xo"; 5388 5389 power-domains = <&rpmhpd SC8280XP_NSP>; 5390 power-domain-names = "nsp"; 5391 5392 memory-region = <&pil_nsp0_mem>; 5393 5394 qcom,smem-states = <&smp2p_nsp0_out 0>; 5395 qcom,smem-state-names = "stop"; 5396 5397 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 5398 5399 status = "disabled"; 5400 5401 glink-edge { 5402 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5403 IPCC_MPROC_SIGNAL_GLINK_QMP 5404 IRQ_TYPE_EDGE_RISING>; 5405 mboxes = <&ipcc IPCC_CLIENT_CDSP 5406 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5407 5408 label = "nsp0"; 5409 qcom,remote-pid = <5>; 5410 5411 fastrpc { 5412 compatible = "qcom,fastrpc"; 5413 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5414 label = "cdsp"; 5415 #address-cells = <1>; 5416 #size-cells = <0>; 5417 5418 compute-cb@1 { 5419 compatible = "qcom,fastrpc-compute-cb"; 5420 reg = <1>; 5421 iommus = <&apps_smmu 0x3181 0x0420>; 5422 }; 5423 5424 compute-cb@2 { 5425 compatible = "qcom,fastrpc-compute-cb"; 5426 reg = <2>; 5427 iommus = <&apps_smmu 0x3182 0x0420>; 5428 }; 5429 5430 compute-cb@3 { 5431 compatible = "qcom,fastrpc-compute-cb"; 5432 reg = <3>; 5433 iommus = <&apps_smmu 0x3183 0x0420>; 5434 }; 5435 5436 compute-cb@4 { 5437 compatible = "qcom,fastrpc-compute-cb"; 5438 reg = <4>; 5439 iommus = <&apps_smmu 0x3184 0x0420>; 5440 }; 5441 5442 compute-cb@5 { 5443 compatible = "qcom,fastrpc-compute-cb"; 5444 reg = <5>; 5445 iommus = <&apps_smmu 0x3185 0x0420>; 5446 }; 5447 5448 compute-cb@6 { 5449 compatible = "qcom,fastrpc-compute-cb"; 5450 reg = <6>; 5451 iommus = <&apps_smmu 0x3186 0x0420>; 5452 }; 5453 5454 compute-cb@7 { 5455 compatible = "qcom,fastrpc-compute-cb"; 5456 reg = <7>; 5457 iommus = <&apps_smmu 0x3187 0x0420>; 5458 }; 5459 5460 compute-cb@8 { 5461 compatible = "qcom,fastrpc-compute-cb"; 5462 reg = <8>; 5463 iommus = <&apps_smmu 0x3188 0x0420>; 5464 }; 5465 5466 compute-cb@9 { 5467 compatible = "qcom,fastrpc-compute-cb"; 5468 reg = <9>; 5469 iommus = <&apps_smmu 0x318b 0x0420>; 5470 }; 5471 5472 compute-cb@10 { 5473 compatible = "qcom,fastrpc-compute-cb"; 5474 reg = <10>; 5475 iommus = <&apps_smmu 0x318b 0x0420>; 5476 }; 5477 5478 compute-cb@11 { 5479 compatible = "qcom,fastrpc-compute-cb"; 5480 reg = <11>; 5481 iommus = <&apps_smmu 0x318c 0x0420>; 5482 }; 5483 5484 compute-cb@12 { 5485 compatible = "qcom,fastrpc-compute-cb"; 5486 reg = <12>; 5487 iommus = <&apps_smmu 0x318d 0x0420>; 5488 }; 5489 5490 compute-cb@13 { 5491 compatible = "qcom,fastrpc-compute-cb"; 5492 reg = <13>; 5493 iommus = <&apps_smmu 0x318e 0x0420>; 5494 }; 5495 5496 compute-cb@14 { 5497 compatible = "qcom,fastrpc-compute-cb"; 5498 reg = <14>; 5499 iommus = <&apps_smmu 0x318f 0x0420>; 5500 }; 5501 }; 5502 }; 5503 }; 5504 5505 remoteproc_nsp1: remoteproc@21300000 { 5506 compatible = "qcom,sc8280xp-nsp1-pas"; 5507 reg = <0 0x21300000 0 0x10000>; 5508 5509 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 5510 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 5511 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 5512 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 5513 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 5514 interrupt-names = "wdog", "fatal", "ready", 5515 "handover", "stop-ack"; 5516 5517 clocks = <&rpmhcc RPMH_CXO_CLK>; 5518 clock-names = "xo"; 5519 5520 power-domains = <&rpmhpd SC8280XP_NSP>; 5521 power-domain-names = "nsp"; 5522 5523 memory-region = <&pil_nsp1_mem>; 5524 5525 qcom,smem-states = <&smp2p_nsp1_out 0>; 5526 qcom,smem-state-names = "stop"; 5527 5528 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 5529 5530 status = "disabled"; 5531 5532 glink-edge { 5533 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 5534 IPCC_MPROC_SIGNAL_GLINK_QMP 5535 IRQ_TYPE_EDGE_RISING>; 5536 mboxes = <&ipcc IPCC_CLIENT_NSP1 5537 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5538 5539 label = "nsp1"; 5540 qcom,remote-pid = <12>; 5541 }; 5542 }; 5543 5544 mdss1: display-subsystem@22000000 { 5545 compatible = "qcom,sc8280xp-mdss"; 5546 reg = <0 0x22000000 0 0x1000>; 5547 reg-names = "mdss"; 5548 5549 clocks = <&gcc GCC_DISP_AHB_CLK>, 5550 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5551 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 5552 clock-names = "iface", 5553 "ahb", 5554 "core"; 5555 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 5556 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 5557 interconnect-names = "mdp0-mem", "mdp1-mem"; 5558 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 5559 5560 iommus = <&apps_smmu 0x1800 0x402>; 5561 power-domains = <&dispcc1 MDSS_GDSC>; 5562 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 5563 5564 interrupt-controller; 5565 #interrupt-cells = <1>; 5566 #address-cells = <2>; 5567 #size-cells = <2>; 5568 ranges; 5569 5570 status = "disabled"; 5571 5572 mdss1_mdp: display-controller@22001000 { 5573 compatible = "qcom,sc8280xp-dpu"; 5574 reg = <0 0x22001000 0 0x8f000>, 5575 <0 0x220b0000 0 0x3000>; 5576 reg-names = "mdp", "vbif"; 5577 5578 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5579 <&gcc GCC_DISP_SF_AXI_CLK>, 5580 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5581 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 5582 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 5583 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5584 clock-names = "bus", 5585 "nrt_bus", 5586 "iface", 5587 "lut", 5588 "core", 5589 "vsync"; 5590 interrupt-parent = <&mdss1>; 5591 interrupts = <0>; 5592 power-domains = <&rpmhpd SC8280XP_MMCX>; 5593 5594 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5595 assigned-clock-rates = <19200000>; 5596 operating-points-v2 = <&mdss1_mdp_opp_table>; 5597 5598 ports { 5599 #address-cells = <1>; 5600 #size-cells = <0>; 5601 5602 port@0 { 5603 reg = <0>; 5604 mdss1_intf0_out: endpoint { 5605 remote-endpoint = <&mdss1_dp0_in>; 5606 }; 5607 }; 5608 5609 port@4 { 5610 reg = <4>; 5611 mdss1_intf4_out: endpoint { 5612 remote-endpoint = <&mdss1_dp1_in>; 5613 }; 5614 }; 5615 5616 port@5 { 5617 reg = <5>; 5618 mdss1_intf5_out: endpoint { 5619 remote-endpoint = <&mdss1_dp3_in>; 5620 }; 5621 }; 5622 5623 port@6 { 5624 reg = <6>; 5625 mdss1_intf6_out: endpoint { 5626 remote-endpoint = <&mdss1_dp2_in>; 5627 }; 5628 }; 5629 }; 5630 5631 mdss1_mdp_opp_table: opp-table { 5632 compatible = "operating-points-v2"; 5633 5634 opp-200000000 { 5635 opp-hz = /bits/ 64 <200000000>; 5636 required-opps = <&rpmhpd_opp_low_svs>; 5637 }; 5638 5639 opp-300000000 { 5640 opp-hz = /bits/ 64 <300000000>; 5641 required-opps = <&rpmhpd_opp_svs>; 5642 }; 5643 5644 opp-375000000 { 5645 opp-hz = /bits/ 64 <375000000>; 5646 required-opps = <&rpmhpd_opp_svs_l1>; 5647 }; 5648 5649 opp-500000000 { 5650 opp-hz = /bits/ 64 <500000000>; 5651 required-opps = <&rpmhpd_opp_nom>; 5652 }; 5653 opp-600000000 { 5654 opp-hz = /bits/ 64 <600000000>; 5655 required-opps = <&rpmhpd_opp_turbo_l1>; 5656 }; 5657 }; 5658 }; 5659 5660 mdss1_dp0: displayport-controller@22090000 { 5661 compatible = "qcom,sc8280xp-dp"; 5662 reg = <0 0x22090000 0 0x200>, 5663 <0 0x22090200 0 0x200>, 5664 <0 0x22090400 0 0x600>, 5665 <0 0x22091000 0 0x400>, 5666 <0 0x22091400 0 0x400>; 5667 5668 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5669 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 5670 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 5671 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5672 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 5673 clock-names = "core_iface", "core_aux", 5674 "ctrl_link", 5675 "ctrl_link_iface", "stream_pixel"; 5676 interrupt-parent = <&mdss1>; 5677 interrupts = <12>; 5678 phys = <&mdss1_dp0_phy>; 5679 phy-names = "dp"; 5680 power-domains = <&rpmhpd SC8280XP_MMCX>; 5681 5682 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5683 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 5684 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 5685 operating-points-v2 = <&mdss1_dp0_opp_table>; 5686 5687 #sound-dai-cells = <0>; 5688 5689 status = "disabled"; 5690 5691 ports { 5692 #address-cells = <1>; 5693 #size-cells = <0>; 5694 5695 port@0 { 5696 reg = <0>; 5697 mdss1_dp0_in: endpoint { 5698 remote-endpoint = <&mdss1_intf0_out>; 5699 }; 5700 }; 5701 5702 port@1 { 5703 reg = <1>; 5704 }; 5705 }; 5706 5707 mdss1_dp0_opp_table: opp-table { 5708 compatible = "operating-points-v2"; 5709 5710 opp-160000000 { 5711 opp-hz = /bits/ 64 <160000000>; 5712 required-opps = <&rpmhpd_opp_low_svs>; 5713 }; 5714 5715 opp-270000000 { 5716 opp-hz = /bits/ 64 <270000000>; 5717 required-opps = <&rpmhpd_opp_svs>; 5718 }; 5719 5720 opp-540000000 { 5721 opp-hz = /bits/ 64 <540000000>; 5722 required-opps = <&rpmhpd_opp_svs_l1>; 5723 }; 5724 5725 opp-810000000 { 5726 opp-hz = /bits/ 64 <810000000>; 5727 required-opps = <&rpmhpd_opp_nom>; 5728 }; 5729 }; 5730 }; 5731 5732 mdss1_dp1: displayport-controller@22098000 { 5733 compatible = "qcom,sc8280xp-dp"; 5734 reg = <0 0x22098000 0 0x200>, 5735 <0 0x22098200 0 0x200>, 5736 <0 0x22098400 0 0x600>, 5737 <0 0x22099000 0 0x400>, 5738 <0 0x22099400 0 0x400>; 5739 5740 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5741 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 5742 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 5743 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5744 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 5745 clock-names = "core_iface", "core_aux", 5746 "ctrl_link", 5747 "ctrl_link_iface", "stream_pixel"; 5748 interrupt-parent = <&mdss1>; 5749 interrupts = <13>; 5750 phys = <&mdss1_dp1_phy>; 5751 phy-names = "dp"; 5752 power-domains = <&rpmhpd SC8280XP_MMCX>; 5753 5754 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5755 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 5756 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 5757 operating-points-v2 = <&mdss1_dp1_opp_table>; 5758 5759 #sound-dai-cells = <0>; 5760 5761 status = "disabled"; 5762 5763 ports { 5764 #address-cells = <1>; 5765 #size-cells = <0>; 5766 5767 port@0 { 5768 reg = <0>; 5769 mdss1_dp1_in: endpoint { 5770 remote-endpoint = <&mdss1_intf4_out>; 5771 }; 5772 }; 5773 5774 port@1 { 5775 reg = <1>; 5776 }; 5777 }; 5778 5779 mdss1_dp1_opp_table: opp-table { 5780 compatible = "operating-points-v2"; 5781 5782 opp-160000000 { 5783 opp-hz = /bits/ 64 <160000000>; 5784 required-opps = <&rpmhpd_opp_low_svs>; 5785 }; 5786 5787 opp-270000000 { 5788 opp-hz = /bits/ 64 <270000000>; 5789 required-opps = <&rpmhpd_opp_svs>; 5790 }; 5791 5792 opp-540000000 { 5793 opp-hz = /bits/ 64 <540000000>; 5794 required-opps = <&rpmhpd_opp_svs_l1>; 5795 }; 5796 5797 opp-810000000 { 5798 opp-hz = /bits/ 64 <810000000>; 5799 required-opps = <&rpmhpd_opp_nom>; 5800 }; 5801 }; 5802 }; 5803 5804 mdss1_dp2: displayport-controller@2209a000 { 5805 compatible = "qcom,sc8280xp-dp"; 5806 reg = <0 0x2209a000 0 0x200>, 5807 <0 0x2209a200 0 0x200>, 5808 <0 0x2209a400 0 0x600>, 5809 <0 0x2209b000 0 0x400>, 5810 <0 0x2209b400 0 0x400>; 5811 5812 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5813 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5814 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 5815 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5816 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 5817 clock-names = "core_iface", "core_aux", 5818 "ctrl_link", 5819 "ctrl_link_iface", "stream_pixel"; 5820 interrupt-parent = <&mdss1>; 5821 interrupts = <14>; 5822 phys = <&mdss1_dp2_phy>; 5823 phy-names = "dp"; 5824 power-domains = <&rpmhpd SC8280XP_MMCX>; 5825 5826 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5827 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 5828 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 5829 operating-points-v2 = <&mdss1_dp2_opp_table>; 5830 5831 #sound-dai-cells = <0>; 5832 5833 status = "disabled"; 5834 5835 ports { 5836 #address-cells = <1>; 5837 #size-cells = <0>; 5838 5839 port@0 { 5840 reg = <0>; 5841 mdss1_dp2_in: endpoint { 5842 remote-endpoint = <&mdss1_intf6_out>; 5843 }; 5844 }; 5845 5846 port@1 { 5847 reg = <1>; 5848 }; 5849 }; 5850 5851 mdss1_dp2_opp_table: opp-table { 5852 compatible = "operating-points-v2"; 5853 5854 opp-160000000 { 5855 opp-hz = /bits/ 64 <160000000>; 5856 required-opps = <&rpmhpd_opp_low_svs>; 5857 }; 5858 5859 opp-270000000 { 5860 opp-hz = /bits/ 64 <270000000>; 5861 required-opps = <&rpmhpd_opp_svs>; 5862 }; 5863 5864 opp-540000000 { 5865 opp-hz = /bits/ 64 <540000000>; 5866 required-opps = <&rpmhpd_opp_svs_l1>; 5867 }; 5868 5869 opp-810000000 { 5870 opp-hz = /bits/ 64 <810000000>; 5871 required-opps = <&rpmhpd_opp_nom>; 5872 }; 5873 }; 5874 }; 5875 5876 mdss1_dp3: displayport-controller@220a0000 { 5877 compatible = "qcom,sc8280xp-dp"; 5878 reg = <0 0x220a0000 0 0x200>, 5879 <0 0x220a0200 0 0x200>, 5880 <0 0x220a0400 0 0x600>, 5881 <0 0x220a1000 0 0x400>, 5882 <0 0x220a1400 0 0x400>; 5883 5884 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5885 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5886 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 5887 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5888 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5889 clock-names = "core_iface", "core_aux", 5890 "ctrl_link", 5891 "ctrl_link_iface", "stream_pixel"; 5892 interrupt-parent = <&mdss1>; 5893 interrupts = <15>; 5894 phys = <&mdss1_dp3_phy>; 5895 phy-names = "dp"; 5896 power-domains = <&rpmhpd SC8280XP_MMCX>; 5897 5898 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5899 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5900 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 5901 operating-points-v2 = <&mdss1_dp3_opp_table>; 5902 5903 #sound-dai-cells = <0>; 5904 5905 status = "disabled"; 5906 5907 ports { 5908 #address-cells = <1>; 5909 #size-cells = <0>; 5910 5911 port@0 { 5912 reg = <0>; 5913 mdss1_dp3_in: endpoint { 5914 remote-endpoint = <&mdss1_intf5_out>; 5915 }; 5916 }; 5917 5918 port@1 { 5919 reg = <1>; 5920 }; 5921 }; 5922 5923 mdss1_dp3_opp_table: opp-table { 5924 compatible = "operating-points-v2"; 5925 5926 opp-160000000 { 5927 opp-hz = /bits/ 64 <160000000>; 5928 required-opps = <&rpmhpd_opp_low_svs>; 5929 }; 5930 5931 opp-270000000 { 5932 opp-hz = /bits/ 64 <270000000>; 5933 required-opps = <&rpmhpd_opp_svs>; 5934 }; 5935 5936 opp-540000000 { 5937 opp-hz = /bits/ 64 <540000000>; 5938 required-opps = <&rpmhpd_opp_svs_l1>; 5939 }; 5940 5941 opp-810000000 { 5942 opp-hz = /bits/ 64 <810000000>; 5943 required-opps = <&rpmhpd_opp_nom>; 5944 }; 5945 }; 5946 }; 5947 }; 5948 5949 mdss1_dp2_phy: phy@220c2a00 { 5950 compatible = "qcom,sc8280xp-dp-phy"; 5951 reg = <0 0x220c2a00 0 0x19c>, 5952 <0 0x220c2200 0 0xec>, 5953 <0 0x220c2600 0 0xec>, 5954 <0 0x220c2000 0 0x1c8>; 5955 5956 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5957 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5958 clock-names = "aux", "cfg_ahb"; 5959 power-domains = <&rpmhpd SC8280XP_MX>; 5960 5961 #clock-cells = <1>; 5962 #phy-cells = <0>; 5963 5964 status = "disabled"; 5965 }; 5966 5967 mdss1_dp3_phy: phy@220c5a00 { 5968 compatible = "qcom,sc8280xp-dp-phy"; 5969 reg = <0 0x220c5a00 0 0x19c>, 5970 <0 0x220c5200 0 0xec>, 5971 <0 0x220c5600 0 0xec>, 5972 <0 0x220c5000 0 0x1c8>; 5973 5974 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5975 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5976 clock-names = "aux", "cfg_ahb"; 5977 power-domains = <&rpmhpd SC8280XP_MX>; 5978 5979 #clock-cells = <1>; 5980 #phy-cells = <0>; 5981 5982 status = "disabled"; 5983 }; 5984 5985 dispcc1: clock-controller@22100000 { 5986 compatible = "qcom,sc8280xp-dispcc1"; 5987 reg = <0 0x22100000 0 0x20000>; 5988 5989 clocks = <&gcc GCC_DISP_AHB_CLK>, 5990 <&rpmhcc RPMH_CXO_CLK>, 5991 <0>, 5992 <&mdss1_dp0_phy 0>, 5993 <&mdss1_dp0_phy 1>, 5994 <&mdss1_dp1_phy 0>, 5995 <&mdss1_dp1_phy 1>, 5996 <&mdss1_dp2_phy 0>, 5997 <&mdss1_dp2_phy 1>, 5998 <&mdss1_dp3_phy 0>, 5999 <&mdss1_dp3_phy 1>, 6000 <0>, 6001 <0>, 6002 <0>, 6003 <0>; 6004 power-domains = <&rpmhpd SC8280XP_MMCX>; 6005 6006 #clock-cells = <1>; 6007 #power-domain-cells = <1>; 6008 #reset-cells = <1>; 6009 6010 status = "disabled"; 6011 }; 6012 6013 ethernet1: ethernet@23000000 { 6014 compatible = "qcom,sc8280xp-ethqos"; 6015 reg = <0x0 0x23000000 0x0 0x10000>, 6016 <0x0 0x23016000 0x0 0x100>; 6017 reg-names = "stmmaceth", "rgmii"; 6018 6019 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 6020 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 6021 <&gcc GCC_EMAC1_PTP_CLK>, 6022 <&gcc GCC_EMAC1_RGMII_CLK>; 6023 clock-names = "stmmaceth", 6024 "pclk", 6025 "ptp_ref", 6026 "rgmii"; 6027 6028 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 6029 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 6030 interrupt-names = "macirq", "eth_lpi"; 6031 6032 iommus = <&apps_smmu 0x40 0xf>; 6033 power-domains = <&gcc EMAC_1_GDSC>; 6034 6035 snps,tso; 6036 snps,pbl = <32>; 6037 rx-fifo-depth = <4096>; 6038 tx-fifo-depth = <4096>; 6039 6040 status = "disabled"; 6041 }; 6042 }; 6043 6044 sound: sound { 6045 }; 6046 6047 thermal-zones { 6048 cpu0-thermal { 6049 polling-delay-passive = <250>; 6050 6051 thermal-sensors = <&tsens0 1>; 6052 6053 trips { 6054 cpu-crit { 6055 temperature = <110000>; 6056 hysteresis = <1000>; 6057 type = "critical"; 6058 }; 6059 }; 6060 }; 6061 6062 cpu1-thermal { 6063 polling-delay-passive = <250>; 6064 6065 thermal-sensors = <&tsens0 2>; 6066 6067 trips { 6068 cpu-crit { 6069 temperature = <110000>; 6070 hysteresis = <1000>; 6071 type = "critical"; 6072 }; 6073 }; 6074 }; 6075 6076 cpu2-thermal { 6077 polling-delay-passive = <250>; 6078 6079 thermal-sensors = <&tsens0 3>; 6080 6081 trips { 6082 cpu-crit { 6083 temperature = <110000>; 6084 hysteresis = <1000>; 6085 type = "critical"; 6086 }; 6087 }; 6088 }; 6089 6090 cpu3-thermal { 6091 polling-delay-passive = <250>; 6092 6093 thermal-sensors = <&tsens0 4>; 6094 6095 trips { 6096 cpu-crit { 6097 temperature = <110000>; 6098 hysteresis = <1000>; 6099 type = "critical"; 6100 }; 6101 }; 6102 }; 6103 6104 cpu4-thermal { 6105 polling-delay-passive = <250>; 6106 6107 thermal-sensors = <&tsens0 5>; 6108 6109 trips { 6110 cpu-crit { 6111 temperature = <110000>; 6112 hysteresis = <1000>; 6113 type = "critical"; 6114 }; 6115 }; 6116 }; 6117 6118 cpu5-thermal { 6119 polling-delay-passive = <250>; 6120 6121 thermal-sensors = <&tsens0 6>; 6122 6123 trips { 6124 cpu-crit { 6125 temperature = <110000>; 6126 hysteresis = <1000>; 6127 type = "critical"; 6128 }; 6129 }; 6130 }; 6131 6132 cpu6-thermal { 6133 polling-delay-passive = <250>; 6134 6135 thermal-sensors = <&tsens0 7>; 6136 6137 trips { 6138 cpu-crit { 6139 temperature = <110000>; 6140 hysteresis = <1000>; 6141 type = "critical"; 6142 }; 6143 }; 6144 }; 6145 6146 cpu7-thermal { 6147 polling-delay-passive = <250>; 6148 6149 thermal-sensors = <&tsens0 8>; 6150 6151 trips { 6152 cpu-crit { 6153 temperature = <110000>; 6154 hysteresis = <1000>; 6155 type = "critical"; 6156 }; 6157 }; 6158 }; 6159 6160 cluster0-thermal { 6161 polling-delay-passive = <250>; 6162 6163 thermal-sensors = <&tsens0 9>; 6164 6165 trips { 6166 cpu-crit { 6167 temperature = <110000>; 6168 hysteresis = <1000>; 6169 type = "critical"; 6170 }; 6171 }; 6172 }; 6173 6174 gpu-thermal { 6175 polling-delay-passive = <250>; 6176 6177 thermal-sensors = <&tsens2 2>; 6178 6179 cooling-maps { 6180 map0 { 6181 trip = <&gpu_alert0>; 6182 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6183 }; 6184 }; 6185 6186 trips { 6187 gpu_alert0: trip-point0 { 6188 temperature = <85000>; 6189 hysteresis = <1000>; 6190 type = "passive"; 6191 }; 6192 6193 trip-point1 { 6194 temperature = <110000>; 6195 hysteresis = <1000>; 6196 type = "critical"; 6197 }; 6198 }; 6199 }; 6200 6201 mem-thermal { 6202 polling-delay-passive = <250>; 6203 6204 thermal-sensors = <&tsens1 15>; 6205 6206 trips { 6207 trip-point0 { 6208 temperature = <90000>; 6209 hysteresis = <2000>; 6210 type = "hot"; 6211 }; 6212 }; 6213 }; 6214 }; 6215 6216 timer { 6217 compatible = "arm,armv8-timer"; 6218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6222 }; 6223}; 6224