1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sc8180x-camcc.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc8180x.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 clocks { 29 xo_board_clk: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <38400000>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo485"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <602>; 53 next-level-cache = <&l2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58 power-domains = <&cpu_pd0>; 59 power-domain-names = "psci"; 60 #cooling-cells = <2>; 61 clocks = <&cpufreq_hw 0>; 62 63 l2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&l3_0>; 68 l3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo485"; 79 reg = <0x0 0x100>; 80 enable-method = "psci"; 81 capacity-dmips-mhz = <602>; 82 next-level-cache = <&l2_100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 86 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 87 power-domains = <&cpu_pd1>; 88 power-domain-names = "psci"; 89 #cooling-cells = <2>; 90 clocks = <&cpufreq_hw 0>; 91 92 l2_100: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&l3_0>; 97 }; 98 99 }; 100 101 cpu2: cpu@200 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo485"; 104 reg = <0x0 0x200>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <602>; 107 next-level-cache = <&l2_200>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 operating-points-v2 = <&cpu0_opp_table>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 111 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 112 power-domains = <&cpu_pd2>; 113 power-domain-names = "psci"; 114 #cooling-cells = <2>; 115 clocks = <&cpufreq_hw 0>; 116 117 l2_200: l2-cache { 118 compatible = "cache"; 119 cache-level = <2>; 120 cache-unified; 121 next-level-cache = <&l3_0>; 122 }; 123 }; 124 125 cpu3: cpu@300 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo485"; 128 reg = <0x0 0x300>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <602>; 131 next-level-cache = <&l2_300>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 operating-points-v2 = <&cpu0_opp_table>; 134 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 135 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 136 power-domains = <&cpu_pd3>; 137 power-domain-names = "psci"; 138 #cooling-cells = <2>; 139 clocks = <&cpufreq_hw 0>; 140 141 l2_300: l2-cache { 142 compatible = "cache"; 143 cache-unified; 144 cache-level = <2>; 145 next-level-cache = <&l3_0>; 146 }; 147 }; 148 149 cpu4: cpu@400 { 150 device_type = "cpu"; 151 compatible = "qcom,kryo485"; 152 reg = <0x0 0x400>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <1024>; 155 next-level-cache = <&l2_400>; 156 qcom,freq-domain = <&cpufreq_hw 1>; 157 operating-points-v2 = <&cpu4_opp_table>; 158 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 159 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 160 power-domains = <&cpu_pd4>; 161 power-domain-names = "psci"; 162 #cooling-cells = <2>; 163 clocks = <&cpufreq_hw 1>; 164 165 l2_400: l2-cache { 166 compatible = "cache"; 167 cache-unified; 168 cache-level = <2>; 169 next-level-cache = <&l3_0>; 170 }; 171 }; 172 173 cpu5: cpu@500 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo485"; 176 reg = <0x0 0x500>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <1024>; 179 next-level-cache = <&l2_500>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 operating-points-v2 = <&cpu4_opp_table>; 182 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 183 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 184 power-domains = <&cpu_pd5>; 185 power-domain-names = "psci"; 186 #cooling-cells = <2>; 187 clocks = <&cpufreq_hw 1>; 188 189 l2_500: l2-cache { 190 compatible = "cache"; 191 cache-unified; 192 cache-level = <2>; 193 next-level-cache = <&l3_0>; 194 }; 195 }; 196 197 cpu6: cpu@600 { 198 device_type = "cpu"; 199 compatible = "qcom,kryo485"; 200 reg = <0x0 0x600>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 next-level-cache = <&l2_600>; 204 qcom,freq-domain = <&cpufreq_hw 1>; 205 operating-points-v2 = <&cpu4_opp_table>; 206 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 power-domains = <&cpu_pd6>; 209 power-domain-names = "psci"; 210 #cooling-cells = <2>; 211 clocks = <&cpufreq_hw 1>; 212 213 l2_600: l2-cache { 214 compatible = "cache"; 215 cache-unified; 216 cache-level = <2>; 217 next-level-cache = <&l3_0>; 218 }; 219 }; 220 221 cpu7: cpu@700 { 222 device_type = "cpu"; 223 compatible = "qcom,kryo485"; 224 reg = <0x0 0x700>; 225 enable-method = "psci"; 226 capacity-dmips-mhz = <1024>; 227 next-level-cache = <&l2_700>; 228 qcom,freq-domain = <&cpufreq_hw 1>; 229 operating-points-v2 = <&cpu4_opp_table>; 230 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 232 power-domains = <&cpu_pd7>; 233 power-domain-names = "psci"; 234 #cooling-cells = <2>; 235 clocks = <&cpufreq_hw 1>; 236 237 l2_700: l2-cache { 238 compatible = "cache"; 239 cache-unified; 240 cache-level = <2>; 241 next-level-cache = <&l3_0>; 242 }; 243 }; 244 245 cpu-map { 246 cluster0 { 247 core0 { 248 cpu = <&cpu0>; 249 }; 250 251 core1 { 252 cpu = <&cpu1>; 253 }; 254 255 core2 { 256 cpu = <&cpu2>; 257 }; 258 259 core3 { 260 cpu = <&cpu3>; 261 }; 262 263 core4 { 264 cpu = <&cpu4>; 265 }; 266 267 core5 { 268 cpu = <&cpu5>; 269 }; 270 271 core6 { 272 cpu = <&cpu6>; 273 }; 274 275 core7 { 276 cpu = <&cpu7>; 277 }; 278 }; 279 }; 280 281 idle-states { 282 entry-method = "psci"; 283 284 little_cpu_sleep_0: cpu-sleep-0-0 { 285 compatible = "arm,idle-state"; 286 arm,psci-suspend-param = <0x40000004>; 287 entry-latency-us = <355>; 288 exit-latency-us = <909>; 289 min-residency-us = <3934>; 290 local-timer-stop; 291 }; 292 293 big_cpu_sleep_0: cpu-sleep-1-0 { 294 compatible = "arm,idle-state"; 295 arm,psci-suspend-param = <0x40000004>; 296 entry-latency-us = <2411>; 297 exit-latency-us = <1461>; 298 min-residency-us = <4488>; 299 local-timer-stop; 300 }; 301 }; 302 303 domain-idle-states { 304 cluster_sleep_apss_off: cluster-sleep-0 { 305 compatible = "domain-idle-state"; 306 arm,psci-suspend-param = <0x41000044>; 307 entry-latency-us = <3300>; 308 exit-latency-us = <3300>; 309 min-residency-us = <6000>; 310 }; 311 312 cluster_sleep_aoss_sleep: cluster-sleep-1 { 313 compatible = "domain-idle-state"; 314 arm,psci-suspend-param = <0x4100a344>; 315 entry-latency-us = <3263>; 316 exit-latency-us = <6562>; 317 min-residency-us = <9987>; 318 }; 319 }; 320 }; 321 322 cpu0_opp_table: opp-table-cpu0 { 323 compatible = "operating-points-v2"; 324 opp-shared; 325 326 opp-300000000 { 327 opp-hz = /bits/ 64 <300000000>; 328 opp-peak-kBps = <800000 9600000>; 329 }; 330 331 opp-422400000 { 332 opp-hz = /bits/ 64 <422400000>; 333 opp-peak-kBps = <800000 9600000>; 334 }; 335 336 opp-537600000 { 337 opp-hz = /bits/ 64 <537600000>; 338 opp-peak-kBps = <800000 12902400>; 339 }; 340 341 opp-652800000 { 342 opp-hz = /bits/ 64 <652800000>; 343 opp-peak-kBps = <800000 12902400>; 344 }; 345 346 opp-768000000 { 347 opp-hz = /bits/ 64 <768000000>; 348 opp-peak-kBps = <800000 15974400>; 349 }; 350 351 opp-883200000 { 352 opp-hz = /bits/ 64 <883200000>; 353 opp-peak-kBps = <1804000 19660800>; 354 }; 355 356 opp-998400000 { 357 opp-hz = /bits/ 64 <998400000>; 358 opp-peak-kBps = <1804000 19660800>; 359 }; 360 361 opp-1113600000 { 362 opp-hz = /bits/ 64 <1113600000>; 363 opp-peak-kBps = <1804000 22732800>; 364 }; 365 366 opp-1228800000 { 367 opp-hz = /bits/ 64 <1228800000>; 368 opp-peak-kBps = <1804000 22732800>; 369 }; 370 371 opp-1363200000 { 372 opp-hz = /bits/ 64 <1363200000>; 373 opp-peak-kBps = <2188000 25804800>; 374 }; 375 376 opp-1478400000 { 377 opp-hz = /bits/ 64 <1478400000>; 378 opp-peak-kBps = <2188000 31948800>; 379 }; 380 381 opp-1574400000 { 382 opp-hz = /bits/ 64 <1574400000>; 383 opp-peak-kBps = <3072000 31948800>; 384 }; 385 386 opp-1670400000 { 387 opp-hz = /bits/ 64 <1670400000>; 388 opp-peak-kBps = <3072000 31948800>; 389 }; 390 391 opp-1766400000 { 392 opp-hz = /bits/ 64 <1766400000>; 393 opp-peak-kBps = <3072000 31948800>; 394 }; 395 }; 396 397 cpu4_opp_table: opp-table-cpu4 { 398 compatible = "operating-points-v2"; 399 opp-shared; 400 401 opp-825600000 { 402 opp-hz = /bits/ 64 <825600000>; 403 opp-peak-kBps = <1804000 15974400>; 404 }; 405 406 opp-940800000 { 407 opp-hz = /bits/ 64 <940800000>; 408 opp-peak-kBps = <2188000 19660800>; 409 }; 410 411 opp-1056000000 { 412 opp-hz = /bits/ 64 <1056000000>; 413 opp-peak-kBps = <2188000 22732800>; 414 }; 415 416 opp-1171200000 { 417 opp-hz = /bits/ 64 <1171200000>; 418 opp-peak-kBps = <3072000 25804800>; 419 }; 420 421 opp-1286400000 { 422 opp-hz = /bits/ 64 <1286400000>; 423 opp-peak-kBps = <3072000 31948800>; 424 }; 425 426 opp-1420800000 { 427 opp-hz = /bits/ 64 <1420800000>; 428 opp-peak-kBps = <4068000 31948800>; 429 }; 430 431 opp-1536000000 { 432 opp-hz = /bits/ 64 <1536000000>; 433 opp-peak-kBps = <4068000 31948800>; 434 }; 435 436 opp-1651200000 { 437 opp-hz = /bits/ 64 <1651200000>; 438 opp-peak-kBps = <4068000 40550400>; 439 }; 440 441 opp-1766400000 { 442 opp-hz = /bits/ 64 <1766400000>; 443 opp-peak-kBps = <4068000 40550400>; 444 }; 445 446 opp-1881600000 { 447 opp-hz = /bits/ 64 <1881600000>; 448 opp-peak-kBps = <4068000 43008000>; 449 }; 450 451 opp-1996800000 { 452 opp-hz = /bits/ 64 <1996800000>; 453 opp-peak-kBps = <6220000 43008000>; 454 }; 455 456 opp-2131200000 { 457 opp-hz = /bits/ 64 <2131200000>; 458 opp-peak-kBps = <6220000 49152000>; 459 }; 460 461 opp-2246400000 { 462 opp-hz = /bits/ 64 <2246400000>; 463 opp-peak-kBps = <7216000 49152000>; 464 }; 465 466 opp-2361600000 { 467 opp-hz = /bits/ 64 <2361600000>; 468 opp-peak-kBps = <8368000 49152000>; 469 }; 470 471 opp-2457600000 { 472 opp-hz = /bits/ 64 <2457600000>; 473 opp-peak-kBps = <8368000 51609600>; 474 }; 475 476 opp-2553600000 { 477 opp-hz = /bits/ 64 <2553600000>; 478 opp-peak-kBps = <8368000 51609600>; 479 }; 480 481 opp-2649600000 { 482 opp-hz = /bits/ 64 <2649600000>; 483 opp-peak-kBps = <8368000 51609600>; 484 }; 485 486 opp-2745600000 { 487 opp-hz = /bits/ 64 <2745600000>; 488 opp-peak-kBps = <8368000 51609600>; 489 }; 490 491 opp-2841600000 { 492 opp-hz = /bits/ 64 <2841600000>; 493 opp-peak-kBps = <8368000 51609600>; 494 }; 495 496 opp-2918400000 { 497 opp-hz = /bits/ 64 <2918400000>; 498 opp-peak-kBps = <8368000 51609600>; 499 }; 500 501 opp-2995200000 { 502 opp-hz = /bits/ 64 <2995200000>; 503 opp-peak-kBps = <8368000 51609600>; 504 }; 505 }; 506 507 firmware { 508 scm: scm { 509 compatible = "qcom,scm-sc8180x", "qcom,scm"; 510 }; 511 }; 512 513 camnoc_virt: interconnect-camnoc-virt { 514 compatible = "qcom,sc8180x-camnoc-virt"; 515 #interconnect-cells = <2>; 516 qcom,bcm-voters = <&apps_bcm_voter>; 517 }; 518 519 mc_virt: interconnect-mc-virt { 520 compatible = "qcom,sc8180x-mc-virt"; 521 #interconnect-cells = <2>; 522 qcom,bcm-voters = <&apps_bcm_voter>; 523 }; 524 525 qup_virt: interconnect-qup-virt { 526 compatible = "qcom,sc8180x-qup-virt"; 527 #interconnect-cells = <2>; 528 qcom,bcm-voters = <&apps_bcm_voter>; 529 }; 530 531 memory@80000000 { 532 device_type = "memory"; 533 /* We expect the bootloader to fill in the size */ 534 reg = <0x0 0x80000000 0x0 0x0>; 535 }; 536 537 pmu { 538 compatible = "arm,armv8-pmuv3"; 539 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 540 }; 541 542 psci { 543 compatible = "arm,psci-1.0"; 544 method = "smc"; 545 546 cpu_pd0: power-domain-cpu0 { 547 #power-domain-cells = <0>; 548 power-domains = <&cluster_pd>; 549 domain-idle-states = <&little_cpu_sleep_0>; 550 }; 551 552 cpu_pd1: power-domain-cpu1 { 553 #power-domain-cells = <0>; 554 power-domains = <&cluster_pd>; 555 domain-idle-states = <&little_cpu_sleep_0>; 556 }; 557 558 cpu_pd2: power-domain-cpu2 { 559 #power-domain-cells = <0>; 560 power-domains = <&cluster_pd>; 561 domain-idle-states = <&little_cpu_sleep_0>; 562 }; 563 564 cpu_pd3: power-domain-cpu3 { 565 #power-domain-cells = <0>; 566 power-domains = <&cluster_pd>; 567 domain-idle-states = <&little_cpu_sleep_0>; 568 }; 569 570 cpu_pd4: power-domain-cpu4 { 571 #power-domain-cells = <0>; 572 power-domains = <&cluster_pd>; 573 domain-idle-states = <&big_cpu_sleep_0>; 574 }; 575 576 cpu_pd5: power-domain-cpu5 { 577 #power-domain-cells = <0>; 578 power-domains = <&cluster_pd>; 579 domain-idle-states = <&big_cpu_sleep_0>; 580 }; 581 582 cpu_pd6: power-domain-cpu6 { 583 #power-domain-cells = <0>; 584 power-domains = <&cluster_pd>; 585 domain-idle-states = <&big_cpu_sleep_0>; 586 }; 587 588 cpu_pd7: power-domain-cpu7 { 589 #power-domain-cells = <0>; 590 power-domains = <&cluster_pd>; 591 domain-idle-states = <&big_cpu_sleep_0>; 592 }; 593 594 cluster_pd: power-domain-cpu-cluster0 { 595 #power-domain-cells = <0>; 596 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>; 597 }; 598 }; 599 600 reserved-memory { 601 #address-cells = <2>; 602 #size-cells = <2>; 603 ranges; 604 605 hyp_mem: hyp@85700000 { 606 reg = <0x0 0x85700000 0x0 0x600000>; 607 no-map; 608 }; 609 610 xbl_mem: xbl@85d00000 { 611 reg = <0x0 0x85d00000 0x0 0x140000>; 612 no-map; 613 }; 614 615 aop_mem: aop@85f00000 { 616 reg = <0x0 0x85f00000 0x0 0x20000>; 617 no-map; 618 }; 619 620 aop_cmd_db: cmd-db@85f20000 { 621 compatible = "qcom,cmd-db"; 622 reg = <0x0 0x85f20000 0x0 0x20000>; 623 no-map; 624 }; 625 626 reserved@85f40000 { 627 reg = <0x0 0x85f40000 0x0 0x10000>; 628 no-map; 629 }; 630 631 smem_mem: smem@86000000 { 632 compatible = "qcom,smem"; 633 reg = <0x0 0x86000000 0x0 0x200000>; 634 no-map; 635 hwlocks = <&tcsr_mutex 3>; 636 }; 637 638 reserved@86200000 { 639 reg = <0x0 0x86200000 0x0 0x3900000>; 640 no-map; 641 }; 642 643 reserved@89b00000 { 644 reg = <0x0 0x89b00000 0x0 0x1c00000>; 645 no-map; 646 }; 647 648 reserved@9d400000 { 649 reg = <0x0 0x9d400000 0x0 0x1000000>; 650 no-map; 651 }; 652 653 reserved@9e400000 { 654 reg = <0x0 0x9e400000 0x0 0x1400000>; 655 no-map; 656 }; 657 658 reserved@9f800000 { 659 reg = <0x0 0x9f800000 0x0 0x800000>; 660 no-map; 661 }; 662 }; 663 664 smp2p-cdsp { 665 compatible = "qcom,smp2p"; 666 qcom,smem = <94>, <432>; 667 668 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 669 670 mboxes = <&apss_shared 6>; 671 672 qcom,local-pid = <0>; 673 qcom,remote-pid = <5>; 674 675 cdsp_smp2p_out: master-kernel { 676 qcom,entry-name = "master-kernel"; 677 #qcom,smem-state-cells = <1>; 678 }; 679 680 cdsp_smp2p_in: slave-kernel { 681 qcom,entry-name = "slave-kernel"; 682 683 interrupt-controller; 684 #interrupt-cells = <2>; 685 }; 686 }; 687 688 smp2p-lpass { 689 compatible = "qcom,smp2p"; 690 qcom,smem = <443>, <429>; 691 692 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 693 694 mboxes = <&apss_shared 10>; 695 696 qcom,local-pid = <0>; 697 qcom,remote-pid = <2>; 698 699 adsp_smp2p_out: master-kernel { 700 qcom,entry-name = "master-kernel"; 701 #qcom,smem-state-cells = <1>; 702 }; 703 704 adsp_smp2p_in: slave-kernel { 705 qcom,entry-name = "slave-kernel"; 706 707 interrupt-controller; 708 #interrupt-cells = <2>; 709 }; 710 }; 711 712 smp2p-mpss { 713 compatible = "qcom,smp2p"; 714 qcom,smem = <435>, <428>; 715 716 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 717 718 mboxes = <&apss_shared 14>; 719 720 qcom,local-pid = <0>; 721 qcom,remote-pid = <1>; 722 723 modem_smp2p_out: master-kernel { 724 qcom,entry-name = "master-kernel"; 725 #qcom,smem-state-cells = <1>; 726 }; 727 728 modem_smp2p_in: slave-kernel { 729 qcom,entry-name = "slave-kernel"; 730 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 }; 734 735 modem_smp2p_ipa_out: ipa-ap-to-modem { 736 qcom,entry-name = "ipa"; 737 #qcom,smem-state-cells = <1>; 738 }; 739 740 modem_smp2p_ipa_in: ipa-modem-to-ap { 741 qcom,entry-name = "ipa"; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 }; 745 746 modem_smp2p_wlan_in: wlan-wpss-to-ap { 747 qcom,entry-name = "wlan"; 748 interrupt-controller; 749 #interrupt-cells = <2>; 750 }; 751 }; 752 753 smp2p-slpi { 754 compatible = "qcom,smp2p"; 755 qcom,smem = <481>, <430>; 756 757 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 758 759 mboxes = <&apss_shared 26>; 760 761 qcom,local-pid = <0>; 762 qcom,remote-pid = <3>; 763 764 slpi_smp2p_out: master-kernel { 765 qcom,entry-name = "master-kernel"; 766 #qcom,smem-state-cells = <1>; 767 }; 768 769 slpi_smp2p_in: slave-kernel { 770 qcom,entry-name = "slave-kernel"; 771 772 interrupt-controller; 773 #interrupt-cells = <2>; 774 }; 775 }; 776 777 soc: soc@0 { 778 compatible = "simple-bus"; 779 #address-cells = <2>; 780 #size-cells = <2>; 781 ranges = <0 0 0 0 0x10 0>; 782 dma-ranges = <0 0 0 0 0x10 0>; 783 784 gcc: clock-controller@100000 { 785 compatible = "qcom,gcc-sc8180x"; 786 reg = <0x0 0x00100000 0x0 0x1f0000>; 787 #clock-cells = <1>; 788 #reset-cells = <1>; 789 #power-domain-cells = <1>; 790 clocks = <&rpmhcc RPMH_CXO_CLK>, 791 <&rpmhcc RPMH_CXO_CLK_A>, 792 <&sleep_clk>; 793 clock-names = "bi_tcxo", 794 "bi_tcxo_ao", 795 "sleep_clk"; 796 power-domains = <&rpmhpd SC8180X_CX>; 797 }; 798 799 qupv3_id_0: geniqup@8c0000 { 800 compatible = "qcom,geni-se-qup"; 801 reg = <0 0x008c0000 0 0x6000>; 802 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 803 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 804 clock-names = "m-ahb", "s-ahb"; 805 #address-cells = <2>; 806 #size-cells = <2>; 807 ranges; 808 iommus = <&apps_smmu 0x4c3 0>; 809 status = "disabled"; 810 811 i2c0: i2c@880000 { 812 compatible = "qcom,geni-i2c"; 813 reg = <0 0x00880000 0 0x4000>; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 815 clock-names = "se"; 816 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 817 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 818 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 819 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 820 interconnect-names = "qup-core", "qup-config", "qup-memory"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 spi0: spi@880000 { 827 compatible = "qcom,geni-spi"; 828 reg = <0 0x00880000 0 0x4000>; 829 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 830 clock-names = "se"; 831 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 832 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 833 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 834 interconnect-names = "qup-core", "qup-config"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 status = "disabled"; 838 }; 839 840 uart0: serial@880000 { 841 compatible = "qcom,geni-uart"; 842 reg = <0 0x00880000 0 0x4000>; 843 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 844 clock-names = "se"; 845 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 846 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 848 interconnect-names = "qup-core", "qup-config"; 849 status = "disabled"; 850 }; 851 852 i2c1: i2c@884000 { 853 compatible = "qcom,geni-i2c"; 854 reg = <0 0x00884000 0 0x4000>; 855 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 856 clock-names = "se"; 857 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 858 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 859 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 860 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 861 interconnect-names = "qup-core", "qup-config", "qup-memory"; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 status = "disabled"; 865 }; 866 867 spi1: spi@884000 { 868 compatible = "qcom,geni-spi"; 869 reg = <0 0x00884000 0 0x4000>; 870 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 871 clock-names = "se"; 872 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 873 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 874 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 875 interconnect-names = "qup-core", "qup-config"; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 status = "disabled"; 879 }; 880 881 uart1: serial@884000 { 882 compatible = "qcom,geni-uart"; 883 reg = <0 0x00884000 0 0x4000>; 884 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 885 clock-names = "se"; 886 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 887 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 888 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 889 interconnect-names = "qup-core", "qup-config"; 890 status = "disabled"; 891 }; 892 893 i2c2: i2c@888000 { 894 compatible = "qcom,geni-i2c"; 895 reg = <0 0x00888000 0 0x4000>; 896 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 897 clock-names = "se"; 898 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 899 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 900 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 901 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 902 interconnect-names = "qup-core", "qup-config", "qup-memory"; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 status = "disabled"; 906 }; 907 908 spi2: spi@888000 { 909 compatible = "qcom,geni-spi"; 910 reg = <0 0x00888000 0 0x4000>; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 912 clock-names = "se"; 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 914 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 915 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 916 interconnect-names = "qup-core", "qup-config"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 uart2: serial@888000 { 923 compatible = "qcom,geni-uart"; 924 reg = <0 0x00888000 0 0x4000>; 925 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 926 clock-names = "se"; 927 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 928 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 929 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 930 interconnect-names = "qup-core", "qup-config"; 931 status = "disabled"; 932 }; 933 934 i2c3: i2c@88c000 { 935 compatible = "qcom,geni-i2c"; 936 reg = <0 0x0088c000 0 0x4000>; 937 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 938 clock-names = "se"; 939 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 940 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 941 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 942 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 943 interconnect-names = "qup-core", "qup-config", "qup-memory"; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 status = "disabled"; 947 }; 948 949 spi3: spi@88c000 { 950 compatible = "qcom,geni-spi"; 951 reg = <0 0x0088c000 0 0x4000>; 952 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 953 clock-names = "se"; 954 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 955 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 956 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 957 interconnect-names = "qup-core", "qup-config"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 status = "disabled"; 961 }; 962 963 uart3: serial@88c000 { 964 compatible = "qcom,geni-uart"; 965 reg = <0 0x0088c000 0 0x4000>; 966 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 967 clock-names = "se"; 968 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 969 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 970 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 971 interconnect-names = "qup-core", "qup-config"; 972 status = "disabled"; 973 }; 974 975 i2c4: i2c@890000 { 976 compatible = "qcom,geni-i2c"; 977 reg = <0 0x00890000 0 0x4000>; 978 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 979 clock-names = "se"; 980 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 981 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 982 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 983 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 984 interconnect-names = "qup-core", "qup-config", "qup-memory"; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 status = "disabled"; 988 }; 989 990 spi4: spi@890000 { 991 compatible = "qcom,geni-spi"; 992 reg = <0 0x00890000 0 0x4000>; 993 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 994 clock-names = "se"; 995 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 996 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 997 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 998 interconnect-names = "qup-core", "qup-config"; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 uart4: serial@890000 { 1005 compatible = "qcom,geni-uart"; 1006 reg = <0 0x00890000 0 0x4000>; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1008 clock-names = "se"; 1009 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1010 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1011 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1012 interconnect-names = "qup-core", "qup-config"; 1013 status = "disabled"; 1014 }; 1015 1016 i2c5: i2c@894000 { 1017 compatible = "qcom,geni-i2c"; 1018 reg = <0 0x00894000 0 0x4000>; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1020 clock-names = "se"; 1021 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1022 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1023 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1024 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1025 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 spi5: spi@894000 { 1032 compatible = "qcom,geni-spi"; 1033 reg = <0 0x00894000 0 0x4000>; 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1035 clock-names = "se"; 1036 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1037 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1038 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1039 interconnect-names = "qup-core", "qup-config"; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 uart5: serial@894000 { 1046 compatible = "qcom,geni-uart"; 1047 reg = <0 0x00894000 0 0x4000>; 1048 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1049 clock-names = "se"; 1050 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1051 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1052 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1053 interconnect-names = "qup-core", "qup-config"; 1054 status = "disabled"; 1055 }; 1056 1057 i2c6: i2c@898000 { 1058 compatible = "qcom,geni-i2c"; 1059 reg = <0 0x00898000 0 0x4000>; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1061 clock-names = "se"; 1062 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1063 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1065 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1066 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 spi6: spi@898000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00898000 0 0x4000>; 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1076 clock-names = "se"; 1077 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1078 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1079 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1080 interconnect-names = "qup-core", "qup-config"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 status = "disabled"; 1084 }; 1085 1086 uart6: serial@898000 { 1087 compatible = "qcom,geni-uart"; 1088 reg = <0 0x00898000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1090 clock-names = "se"; 1091 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1092 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1093 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1094 interconnect-names = "qup-core", "qup-config"; 1095 status = "disabled"; 1096 }; 1097 1098 i2c7: i2c@89c000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0 0x0089c000 0 0x4000>; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1102 clock-names = "se"; 1103 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1104 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1105 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1106 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1107 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi7: spi@89c000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x0089c000 0 0x4000>; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1117 clock-names = "se"; 1118 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1119 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1120 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1121 interconnect-names = "qup-core", "qup-config"; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 uart7: serial@89c000 { 1128 compatible = "qcom,geni-uart"; 1129 reg = <0 0x0089c000 0 0x4000>; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1131 clock-names = "se"; 1132 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1133 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1134 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1135 interconnect-names = "qup-core", "qup-config"; 1136 status = "disabled"; 1137 }; 1138 }; 1139 1140 qupv3_id_1: geniqup@ac0000 { 1141 compatible = "qcom,geni-se-qup"; 1142 reg = <0x0 0x00ac0000 0x0 0x6000>; 1143 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1144 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1145 clock-names = "m-ahb", "s-ahb"; 1146 #address-cells = <2>; 1147 #size-cells = <2>; 1148 ranges; 1149 iommus = <&apps_smmu 0x603 0>; 1150 status = "disabled"; 1151 1152 i2c8: i2c@a80000 { 1153 compatible = "qcom,geni-i2c"; 1154 reg = <0 0x00a80000 0 0x4000>; 1155 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1156 clock-names = "se"; 1157 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1158 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1159 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1160 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1161 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1162 #address-cells = <1>; 1163 #size-cells = <0>; 1164 status = "disabled"; 1165 }; 1166 1167 spi8: spi@a80000 { 1168 compatible = "qcom,geni-spi"; 1169 reg = <0 0x00a80000 0 0x4000>; 1170 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1171 clock-names = "se"; 1172 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1173 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1174 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1175 interconnect-names = "qup-core", "qup-config"; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 status = "disabled"; 1179 }; 1180 1181 uart8: serial@a80000 { 1182 compatible = "qcom,geni-uart"; 1183 reg = <0 0x00a80000 0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1185 clock-names = "se"; 1186 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1187 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1188 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1189 interconnect-names = "qup-core", "qup-config"; 1190 status = "disabled"; 1191 }; 1192 1193 i2c9: i2c@a84000 { 1194 compatible = "qcom,geni-i2c"; 1195 reg = <0 0x00a84000 0 0x4000>; 1196 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1197 clock-names = "se"; 1198 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1199 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1200 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1201 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1202 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 spi9: spi@a84000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00a84000 0 0x4000>; 1211 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1212 clock-names = "se"; 1213 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1214 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1215 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1216 interconnect-names = "qup-core", "qup-config"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 status = "disabled"; 1220 }; 1221 1222 uart9: serial@a84000 { 1223 compatible = "qcom,geni-debug-uart"; 1224 reg = <0 0x00a84000 0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1226 clock-names = "se"; 1227 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1228 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1229 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1230 interconnect-names = "qup-core", "qup-config"; 1231 status = "disabled"; 1232 }; 1233 1234 i2c10: i2c@a88000 { 1235 compatible = "qcom,geni-i2c"; 1236 reg = <0 0x00a88000 0 0x4000>; 1237 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1238 clock-names = "se"; 1239 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1240 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1241 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1242 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1243 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 status = "disabled"; 1247 }; 1248 1249 spi10: spi@a88000 { 1250 compatible = "qcom,geni-spi"; 1251 reg = <0 0x00a88000 0 0x4000>; 1252 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1253 clock-names = "se"; 1254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1255 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1256 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1257 interconnect-names = "qup-core", "qup-config"; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 uart10: serial@a88000 { 1264 compatible = "qcom,geni-uart"; 1265 reg = <0 0x00a88000 0 0x4000>; 1266 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1267 clock-names = "se"; 1268 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1269 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1270 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1271 interconnect-names = "qup-core", "qup-config"; 1272 status = "disabled"; 1273 }; 1274 1275 i2c11: i2c@a8c000 { 1276 compatible = "qcom,geni-i2c"; 1277 reg = <0 0x00a8c000 0 0x4000>; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1279 clock-names = "se"; 1280 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1281 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1282 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1283 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1284 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 spi11: spi@a8c000 { 1291 compatible = "qcom,geni-spi"; 1292 reg = <0 0x00a8c000 0 0x4000>; 1293 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1294 clock-names = "se"; 1295 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1296 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1297 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1298 interconnect-names = "qup-core", "qup-config"; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 status = "disabled"; 1302 }; 1303 1304 uart11: serial@a8c000 { 1305 compatible = "qcom,geni-uart"; 1306 reg = <0 0x00a8c000 0 0x4000>; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1308 clock-names = "se"; 1309 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1310 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1311 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1312 interconnect-names = "qup-core", "qup-config"; 1313 status = "disabled"; 1314 }; 1315 1316 i2c12: i2c@a90000 { 1317 compatible = "qcom,geni-i2c"; 1318 reg = <0 0x00a90000 0 0x4000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1320 clock-names = "se"; 1321 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1322 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1323 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1324 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1325 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 1331 spi12: spi@a90000 { 1332 compatible = "qcom,geni-spi"; 1333 reg = <0 0x00a90000 0 0x4000>; 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1335 clock-names = "se"; 1336 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1337 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1338 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1339 interconnect-names = "qup-core", "qup-config"; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 status = "disabled"; 1343 }; 1344 1345 uart12: serial@a90000 { 1346 compatible = "qcom,geni-uart"; 1347 reg = <0 0x00a90000 0 0x4000>; 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1349 clock-names = "se"; 1350 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1351 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1352 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1353 interconnect-names = "qup-core", "qup-config"; 1354 status = "disabled"; 1355 }; 1356 1357 i2c16: i2c@a94000 { 1358 compatible = "qcom,geni-i2c"; 1359 reg = <0 0x00a94000 0 0x4000>; 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1361 clock-names = "se"; 1362 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1363 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1364 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1365 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1366 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 status = "disabled"; 1370 }; 1371 1372 spi16: spi@a94000 { 1373 compatible = "qcom,geni-spi"; 1374 reg = <0 0x00a94000 0 0x4000>; 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1376 clock-names = "se"; 1377 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1378 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1379 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1380 interconnect-names = "qup-core", "qup-config"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 uart16: serial@a94000 { 1387 compatible = "qcom,geni-uart"; 1388 reg = <0 0x00a94000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1390 clock-names = "se"; 1391 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1392 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1393 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1394 interconnect-names = "qup-core", "qup-config"; 1395 status = "disabled"; 1396 }; 1397 }; 1398 1399 qupv3_id_2: geniqup@cc0000 { 1400 compatible = "qcom,geni-se-qup"; 1401 reg = <0x0 0x00cc0000 0x0 0x6000>; 1402 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1403 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1404 clock-names = "m-ahb", "s-ahb"; 1405 #address-cells = <2>; 1406 #size-cells = <2>; 1407 ranges; 1408 iommus = <&apps_smmu 0x7a3 0>; 1409 status = "disabled"; 1410 1411 i2c17: i2c@c80000 { 1412 compatible = "qcom,geni-i2c"; 1413 reg = <0 0x00c80000 0 0x4000>; 1414 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1415 clock-names = "se"; 1416 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1417 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1418 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1419 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1420 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 spi17: spi@c80000 { 1427 compatible = "qcom,geni-spi"; 1428 reg = <0 0x00c80000 0 0x4000>; 1429 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1430 clock-names = "se"; 1431 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1432 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1433 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1434 interconnect-names = "qup-core", "qup-config"; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 status = "disabled"; 1438 }; 1439 1440 uart17: serial@c80000 { 1441 compatible = "qcom,geni-uart"; 1442 reg = <0 0x00c80000 0 0x4000>; 1443 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1444 clock-names = "se"; 1445 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1446 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1447 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1448 interconnect-names = "qup-core", "qup-config"; 1449 status = "disabled"; 1450 }; 1451 1452 i2c18: i2c@c84000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00c84000 0 0x4000>; 1455 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1456 clock-names = "se"; 1457 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1458 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1459 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1460 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1461 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 status = "disabled"; 1465 }; 1466 1467 spi18: spi@c84000 { 1468 compatible = "qcom,geni-spi"; 1469 reg = <0 0x00c84000 0 0x4000>; 1470 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1471 clock-names = "se"; 1472 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1473 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1474 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1475 interconnect-names = "qup-core", "qup-config"; 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 status = "disabled"; 1479 }; 1480 1481 uart18: serial@c84000 { 1482 compatible = "qcom,geni-uart"; 1483 reg = <0 0x00c84000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1485 clock-names = "se"; 1486 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1487 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1489 interconnect-names = "qup-core", "qup-config"; 1490 status = "disabled"; 1491 }; 1492 1493 i2c19: i2c@c88000 { 1494 compatible = "qcom,geni-i2c"; 1495 reg = <0 0x00c88000 0 0x4000>; 1496 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1497 clock-names = "se"; 1498 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1499 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1500 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1501 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1502 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 status = "disabled"; 1506 }; 1507 1508 spi19: spi@c88000 { 1509 compatible = "qcom,geni-spi"; 1510 reg = <0 0x00c88000 0 0x4000>; 1511 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1512 clock-names = "se"; 1513 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1514 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1515 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1516 interconnect-names = "qup-core", "qup-config"; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 status = "disabled"; 1520 }; 1521 1522 uart19: serial@c88000 { 1523 compatible = "qcom,geni-uart"; 1524 reg = <0 0x00c88000 0 0x4000>; 1525 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1526 clock-names = "se"; 1527 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1528 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1529 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1530 interconnect-names = "qup-core", "qup-config"; 1531 status = "disabled"; 1532 }; 1533 1534 i2c13: i2c@c8c000 { 1535 compatible = "qcom,geni-i2c"; 1536 reg = <0 0x00c8c000 0 0x4000>; 1537 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1538 clock-names = "se"; 1539 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1540 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1541 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1542 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1543 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 status = "disabled"; 1547 }; 1548 1549 spi13: spi@c8c000 { 1550 compatible = "qcom,geni-spi"; 1551 reg = <0 0x00c8c000 0 0x4000>; 1552 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1553 clock-names = "se"; 1554 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1555 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1556 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1557 interconnect-names = "qup-core", "qup-config"; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 status = "disabled"; 1561 }; 1562 1563 uart13: serial@c8c000 { 1564 compatible = "qcom,geni-uart"; 1565 reg = <0 0x00c8c000 0 0x4000>; 1566 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1567 clock-names = "se"; 1568 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1569 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1570 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1571 interconnect-names = "qup-core", "qup-config"; 1572 status = "disabled"; 1573 }; 1574 1575 i2c14: i2c@c90000 { 1576 compatible = "qcom,geni-i2c"; 1577 reg = <0 0x00c90000 0 0x4000>; 1578 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1579 clock-names = "se"; 1580 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1581 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1582 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1583 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1584 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 status = "disabled"; 1588 }; 1589 1590 spi14: spi@c90000 { 1591 compatible = "qcom,geni-spi"; 1592 reg = <0 0x00c90000 0 0x4000>; 1593 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1594 clock-names = "se"; 1595 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1596 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1597 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1598 interconnect-names = "qup-core", "qup-config"; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 uart14: serial@c90000 { 1605 compatible = "qcom,geni-uart"; 1606 reg = <0 0x00c90000 0 0x4000>; 1607 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1608 clock-names = "se"; 1609 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1610 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1611 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1612 interconnect-names = "qup-core", "qup-config"; 1613 status = "disabled"; 1614 }; 1615 1616 i2c15: i2c@c94000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00c94000 0 0x4000>; 1619 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1620 clock-names = "se"; 1621 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1622 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1623 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1624 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1625 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 status = "disabled"; 1629 }; 1630 1631 spi15: spi@c94000 { 1632 compatible = "qcom,geni-spi"; 1633 reg = <0 0x00c94000 0 0x4000>; 1634 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1635 clock-names = "se"; 1636 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1637 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1638 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1639 interconnect-names = "qup-core", "qup-config"; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 status = "disabled"; 1643 }; 1644 1645 uart15: serial@c94000 { 1646 compatible = "qcom,geni-uart"; 1647 reg = <0 0x00c94000 0 0x4000>; 1648 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1649 clock-names = "se"; 1650 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1651 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1652 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1653 interconnect-names = "qup-core", "qup-config"; 1654 status = "disabled"; 1655 }; 1656 }; 1657 1658 config_noc: interconnect@1500000 { 1659 compatible = "qcom,sc8180x-config-noc"; 1660 reg = <0 0x01500000 0 0x7400>; 1661 #interconnect-cells = <2>; 1662 qcom,bcm-voters = <&apps_bcm_voter>; 1663 }; 1664 1665 system_noc: interconnect@1620000 { 1666 compatible = "qcom,sc8180x-system-noc"; 1667 reg = <0 0x01620000 0 0x19400>; 1668 #interconnect-cells = <2>; 1669 qcom,bcm-voters = <&apps_bcm_voter>; 1670 }; 1671 1672 aggre1_noc: interconnect@16e0000 { 1673 compatible = "qcom,sc8180x-aggre1-noc"; 1674 reg = <0 0x016e0000 0 0xd080>; 1675 #interconnect-cells = <2>; 1676 qcom,bcm-voters = <&apps_bcm_voter>; 1677 }; 1678 1679 aggre2_noc: interconnect@1700000 { 1680 compatible = "qcom,sc8180x-aggre2-noc"; 1681 reg = <0 0x01700000 0 0x20000>; 1682 #interconnect-cells = <2>; 1683 qcom,bcm-voters = <&apps_bcm_voter>; 1684 }; 1685 1686 compute_noc: interconnect@1720000 { 1687 compatible = "qcom,sc8180x-compute-noc"; 1688 reg = <0 0x01720000 0 0x7000>; 1689 #interconnect-cells = <2>; 1690 qcom,bcm-voters = <&apps_bcm_voter>; 1691 }; 1692 1693 mmss_noc: interconnect@1740000 { 1694 compatible = "qcom,sc8180x-mmss-noc"; 1695 reg = <0 0x01740000 0 0x1c100>; 1696 #interconnect-cells = <2>; 1697 qcom,bcm-voters = <&apps_bcm_voter>; 1698 }; 1699 1700 pcie0: pcie@1c00000 { 1701 compatible = "qcom,pcie-sc8180x"; 1702 reg = <0 0x01c00000 0 0x3000>, 1703 <0 0x60000000 0 0xf1d>, 1704 <0 0x60000f20 0 0xa8>, 1705 <0 0x60001000 0 0x1000>, 1706 <0 0x60100000 0 0x100000>; 1707 reg-names = "parf", 1708 "dbi", 1709 "elbi", 1710 "atu", 1711 "config"; 1712 device_type = "pci"; 1713 linux,pci-domain = <0>; 1714 bus-range = <0x00 0xff>; 1715 num-lanes = <2>; 1716 1717 #address-cells = <3>; 1718 #size-cells = <2>; 1719 1720 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1721 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1722 1723 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1732 interrupt-names = "msi0", 1733 "msi1", 1734 "msi2", 1735 "msi3", 1736 "msi4", 1737 "msi5", 1738 "msi6", 1739 "msi7", 1740 "global"; 1741 #interrupt-cells = <1>; 1742 interrupt-map-mask = <0 0 0 0x7>; 1743 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1744 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1745 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1746 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1747 1748 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1749 <&gcc GCC_PCIE_0_AUX_CLK>, 1750 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1751 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1752 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1753 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1754 clock-names = "pipe", 1755 "aux", 1756 "cfg", 1757 "bus_master", 1758 "bus_slave", 1759 "slave_q2a"; 1760 1761 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1762 assigned-clock-rates = <19200000>; 1763 1764 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1765 <0x100 &apps_smmu 0x1d81 0x1>; 1766 1767 resets = <&gcc GCC_PCIE_0_BCR>; 1768 reset-names = "pci"; 1769 1770 power-domains = <&gcc PCIE_0_GDSC>; 1771 1772 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1773 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1774 interconnect-names = "pcie-mem", "cpu-pcie"; 1775 1776 phys = <&pcie0_phy>; 1777 phy-names = "pciephy"; 1778 dma-coherent; 1779 1780 status = "disabled"; 1781 1782 pcie@0 { 1783 device_type = "pci"; 1784 reg = <0x0 0x0 0x0 0x0 0x0>; 1785 bus-range = <0x01 0xff>; 1786 1787 #address-cells = <3>; 1788 #size-cells = <2>; 1789 ranges; 1790 }; 1791 }; 1792 1793 pcie0_phy: phy@1c06000 { 1794 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1795 reg = <0 0x01c06000 0 0x1000>; 1796 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1797 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1798 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1799 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1800 <&gcc GCC_PCIE_0_PIPE_CLK>; 1801 clock-names = "aux", 1802 "cfg_ahb", 1803 "ref", 1804 "refgen", 1805 "pipe"; 1806 #clock-cells = <0>; 1807 clock-output-names = "pcie_0_pipe_clk"; 1808 #phy-cells = <0>; 1809 1810 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1811 reset-names = "phy"; 1812 1813 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1814 assigned-clock-rates = <100000000>; 1815 1816 status = "disabled"; 1817 }; 1818 1819 pcie3: pcie@1c08000 { 1820 compatible = "qcom,pcie-sc8180x"; 1821 reg = <0 0x01c08000 0 0x3000>, 1822 <0 0x40000000 0 0xf1d>, 1823 <0 0x40000f20 0 0xa8>, 1824 <0 0x40001000 0 0x1000>, 1825 <0 0x40100000 0 0x100000>; 1826 reg-names = "parf", 1827 "dbi", 1828 "elbi", 1829 "atu", 1830 "config"; 1831 device_type = "pci"; 1832 linux,pci-domain = <3>; 1833 bus-range = <0x00 0xff>; 1834 num-lanes = <2>; 1835 1836 #address-cells = <3>; 1837 #size-cells = <2>; 1838 1839 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1840 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1841 1842 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1851 interrupt-names = "msi0", 1852 "msi1", 1853 "msi2", 1854 "msi3", 1855 "msi4", 1856 "msi5", 1857 "msi6", 1858 "msi7", 1859 "global"; 1860 #interrupt-cells = <1>; 1861 interrupt-map-mask = <0 0 0 0x7>; 1862 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1863 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1864 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1865 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1866 1867 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1868 <&gcc GCC_PCIE_3_AUX_CLK>, 1869 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1870 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1871 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1872 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>; 1873 clock-names = "pipe", 1874 "aux", 1875 "cfg", 1876 "bus_master", 1877 "bus_slave", 1878 "slave_q2a"; 1879 1880 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1881 assigned-clock-rates = <19200000>; 1882 1883 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1884 <0x100 &apps_smmu 0x1e01 0x1>; 1885 1886 resets = <&gcc GCC_PCIE_3_BCR>; 1887 reset-names = "pci"; 1888 1889 power-domains = <&gcc PCIE_3_GDSC>; 1890 1891 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1892 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; 1893 interconnect-names = "pcie-mem", "cpu-pcie"; 1894 1895 phys = <&pcie3_phy>; 1896 phy-names = "pciephy"; 1897 dma-coherent; 1898 1899 status = "disabled"; 1900 1901 pcie@0 { 1902 device_type = "pci"; 1903 reg = <0x0 0x0 0x0 0x0 0x0>; 1904 bus-range = <0x01 0xff>; 1905 1906 #address-cells = <3>; 1907 #size-cells = <2>; 1908 ranges; 1909 }; 1910 }; 1911 1912 pcie3_phy: phy@1c0c000 { 1913 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1914 reg = <0 0x01c0c000 0 0x1000>; 1915 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1916 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1917 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1918 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1919 <&gcc GCC_PCIE_3_PIPE_CLK>; 1920 clock-names = "aux", 1921 "cfg_ahb", 1922 "ref", 1923 "refgen", 1924 "pipe"; 1925 #clock-cells = <0>; 1926 clock-output-names = "pcie_3_pipe_clk"; 1927 1928 #phy-cells = <0>; 1929 1930 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1931 reset-names = "phy"; 1932 1933 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1934 assigned-clock-rates = <100000000>; 1935 1936 status = "disabled"; 1937 }; 1938 1939 pcie1: pcie@1c10000 { 1940 compatible = "qcom,pcie-sc8180x"; 1941 reg = <0 0x01c10000 0 0x3000>, 1942 <0 0x68000000 0 0xf1d>, 1943 <0 0x68000f20 0 0xa8>, 1944 <0 0x68001000 0 0x1000>, 1945 <0 0x68100000 0 0x100000>; 1946 reg-names = "parf", 1947 "dbi", 1948 "elbi", 1949 "atu", 1950 "config"; 1951 device_type = "pci"; 1952 linux,pci-domain = <1>; 1953 bus-range = <0x00 0xff>; 1954 num-lanes = <2>; 1955 1956 #address-cells = <3>; 1957 #size-cells = <2>; 1958 1959 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1960 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1961 1962 interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>; 1971 interrupt-names = "msi0", 1972 "msi1", 1973 "msi2", 1974 "msi3", 1975 "msi4", 1976 "msi5", 1977 "msi6", 1978 "msi7", 1979 "global"; 1980 #interrupt-cells = <1>; 1981 interrupt-map-mask = <0 0 0 0x7>; 1982 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1983 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1984 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1985 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1986 1987 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1988 <&gcc GCC_PCIE_1_AUX_CLK>, 1989 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1990 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1991 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1992 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 1993 clock-names = "pipe", 1994 "aux", 1995 "cfg", 1996 "bus_master", 1997 "bus_slave", 1998 "slave_q2a"; 1999 2000 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2001 assigned-clock-rates = <19200000>; 2002 2003 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2004 <0x100 &apps_smmu 0x1c81 0x1>; 2005 2006 resets = <&gcc GCC_PCIE_1_BCR>; 2007 reset-names = "pci"; 2008 2009 power-domains = <&gcc PCIE_1_GDSC>; 2010 2011 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2012 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; 2013 interconnect-names = "pcie-mem", "cpu-pcie"; 2014 2015 phys = <&pcie1_phy>; 2016 phy-names = "pciephy"; 2017 dma-coherent; 2018 2019 status = "disabled"; 2020 2021 pcie@0 { 2022 device_type = "pci"; 2023 reg = <0x0 0x0 0x0 0x0 0x0>; 2024 bus-range = <0x01 0xff>; 2025 2026 #address-cells = <3>; 2027 #size-cells = <2>; 2028 ranges; 2029 }; 2030 }; 2031 2032 pcie1_phy: phy@1c16000 { 2033 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2034 reg = <0 0x01c16000 0 0x1000>; 2035 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2036 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2037 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2038 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2039 <&gcc GCC_PCIE_1_PIPE_CLK>; 2040 clock-names = "aux", 2041 "cfg_ahb", 2042 "ref", 2043 "refgen", 2044 "pipe"; 2045 #clock-cells = <0>; 2046 clock-output-names = "pcie_1_pipe_clk"; 2047 2048 #phy-cells = <0>; 2049 2050 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2051 reset-names = "phy"; 2052 2053 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2054 assigned-clock-rates = <100000000>; 2055 2056 status = "disabled"; 2057 }; 2058 2059 pcie2: pcie@1c18000 { 2060 compatible = "qcom,pcie-sc8180x"; 2061 reg = <0 0x01c18000 0 0x3000>, 2062 <0 0x70000000 0 0xf1d>, 2063 <0 0x70000f20 0 0xa8>, 2064 <0 0x70001000 0 0x1000>, 2065 <0 0x70100000 0 0x100000>; 2066 reg-names = "parf", 2067 "dbi", 2068 "elbi", 2069 "atu", 2070 "config"; 2071 device_type = "pci"; 2072 linux,pci-domain = <2>; 2073 bus-range = <0x00 0xff>; 2074 num-lanes = <4>; 2075 2076 #address-cells = <3>; 2077 #size-cells = <2>; 2078 2079 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2080 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2081 2082 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; 2091 interrupt-names = "msi0", 2092 "msi1", 2093 "msi2", 2094 "msi3", 2095 "msi4", 2096 "msi5", 2097 "msi6", 2098 "msi7", 2099 "global"; 2100 #interrupt-cells = <1>; 2101 interrupt-map-mask = <0 0 0 0x7>; 2102 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2103 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2104 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2105 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2106 2107 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2108 <&gcc GCC_PCIE_2_AUX_CLK>, 2109 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2110 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2111 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2112 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>; 2113 clock-names = "pipe", 2114 "aux", 2115 "cfg", 2116 "bus_master", 2117 "bus_slave", 2118 "slave_q2a"; 2119 2120 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2121 assigned-clock-rates = <19200000>; 2122 2123 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2124 <0x100 &apps_smmu 0x1d01 0x1>; 2125 2126 resets = <&gcc GCC_PCIE_2_BCR>; 2127 reset-names = "pci"; 2128 2129 power-domains = <&gcc PCIE_2_GDSC>; 2130 2131 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2132 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; 2133 interconnect-names = "pcie-mem", "cpu-pcie"; 2134 2135 phys = <&pcie2_phy>; 2136 phy-names = "pciephy"; 2137 dma-coherent; 2138 2139 status = "disabled"; 2140 2141 pcie@0 { 2142 device_type = "pci"; 2143 reg = <0x0 0x0 0x0 0x0 0x0>; 2144 bus-range = <0x01 0xff>; 2145 2146 #address-cells = <3>; 2147 #size-cells = <2>; 2148 ranges; 2149 }; 2150 }; 2151 2152 pcie2_phy: phy@1c1c000 { 2153 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2154 reg = <0 0x01c1c000 0 0x1000>; 2155 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2156 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2157 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2158 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2159 <&gcc GCC_PCIE_2_PIPE_CLK>; 2160 clock-names = "aux", 2161 "cfg_ahb", 2162 "ref", 2163 "refgen", 2164 "pipe"; 2165 #clock-cells = <0>; 2166 clock-output-names = "pcie_2_pipe_clk"; 2167 2168 #phy-cells = <0>; 2169 2170 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2171 reset-names = "phy"; 2172 2173 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2174 assigned-clock-rates = <100000000>; 2175 2176 status = "disabled"; 2177 }; 2178 2179 ufs_mem_hc: ufshc@1d84000 { 2180 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2181 "jedec,ufs-2.0"; 2182 reg = <0 0x01d84000 0 0x2500>; 2183 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2184 phys = <&ufs_mem_phy>; 2185 phy-names = "ufsphy"; 2186 lanes-per-direction = <2>; 2187 #reset-cells = <1>; 2188 resets = <&gcc GCC_UFS_PHY_BCR>; 2189 reset-names = "rst"; 2190 2191 iommus = <&apps_smmu 0x300 0>; 2192 2193 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2194 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2195 <&gcc GCC_UFS_PHY_AHB_CLK>, 2196 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2197 <&rpmhcc RPMH_CXO_CLK>, 2198 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2199 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2200 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2201 clock-names = "core_clk", 2202 "bus_aggr_clk", 2203 "iface_clk", 2204 "core_clk_unipro", 2205 "ref_clk", 2206 "tx_lane0_sync_clk", 2207 "rx_lane0_sync_clk", 2208 "rx_lane1_sync_clk"; 2209 freq-table-hz = <37500000 300000000>, 2210 <0 0>, 2211 <0 0>, 2212 <37500000 300000000>, 2213 <0 0>, 2214 <0 0>, 2215 <0 0>, 2216 <0 0>; 2217 2218 power-domains = <&gcc UFS_PHY_GDSC>; 2219 2220 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2221 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2222 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2223 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>; 2224 interconnect-names = "ufs-ddr", "cpu-ufs"; 2225 2226 status = "disabled"; 2227 }; 2228 2229 ufs_mem_phy: phy-wrapper@1d87000 { 2230 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2231 reg = <0 0x01d87000 0 0x1000>; 2232 2233 clocks = <&rpmhcc RPMH_CXO_CLK>, 2234 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2235 <&gcc GCC_UFS_MEM_CLKREF_EN>; 2236 clock-names = "ref", 2237 "ref_aux", 2238 "qref"; 2239 2240 resets = <&ufs_mem_hc 0>; 2241 reset-names = "ufsphy"; 2242 2243 power-domains = <&gcc UFS_PHY_GDSC>; 2244 2245 #phy-cells = <0>; 2246 2247 status = "disabled"; 2248 }; 2249 2250 tcsr_mutex: hwlock@1f40000 { 2251 compatible = "qcom,tcsr-mutex"; 2252 reg = <0x0 0x01f40000 0x0 0x40000>; 2253 #hwlock-cells = <1>; 2254 }; 2255 2256 gpu: gpu@2c00000 { 2257 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2258 2259 reg = <0 0x02c00000 0 0x40000>; 2260 reg-names = "kgsl_3d0_reg_memory"; 2261 2262 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2263 2264 iommus = <&adreno_smmu 0 0xc01>; 2265 2266 operating-points-v2 = <&gpu_opp_table>; 2267 2268 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2269 interconnect-names = "gfx-mem"; 2270 2271 qcom,gmu = <&gmu>; 2272 #cooling-cells = <2>; 2273 2274 status = "disabled"; 2275 2276 gpu_opp_table: opp-table { 2277 compatible = "operating-points-v2"; 2278 2279 opp-514000000 { 2280 opp-hz = /bits/ 64 <514000000>; 2281 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2282 }; 2283 2284 opp-500000000 { 2285 opp-hz = /bits/ 64 <500000000>; 2286 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2287 }; 2288 2289 opp-461000000 { 2290 opp-hz = /bits/ 64 <461000000>; 2291 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2292 }; 2293 2294 opp-405000000 { 2295 opp-hz = /bits/ 64 <405000000>; 2296 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2297 }; 2298 2299 opp-315000000 { 2300 opp-hz = /bits/ 64 <315000000>; 2301 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2302 }; 2303 2304 opp-256000000 { 2305 opp-hz = /bits/ 64 <256000000>; 2306 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2307 }; 2308 2309 opp-177000000 { 2310 opp-hz = /bits/ 64 <177000000>; 2311 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2312 }; 2313 }; 2314 }; 2315 2316 gmu: gmu@2c6a000 { 2317 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2318 2319 reg = <0 0x02c6a000 0 0x30000>, 2320 <0 0x0b290000 0 0x10000>, 2321 <0 0x0b490000 0 0x10000>; 2322 reg-names = "gmu", 2323 "gmu_pdc", 2324 "gmu_pdc_seq"; 2325 2326 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2327 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2328 interrupt-names = "hfi", "gmu"; 2329 2330 clocks = <&gpucc GPU_CC_AHB_CLK>, 2331 <&gpucc GPU_CC_CX_GMU_CLK>, 2332 <&gpucc GPU_CC_CXO_CLK>, 2333 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2334 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2335 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2336 2337 power-domains = <&gpucc GPU_CX_GDSC>, 2338 <&gpucc GPU_GX_GDSC>; 2339 power-domain-names = "cx", "gx"; 2340 2341 iommus = <&adreno_smmu 5 0xc00>; 2342 2343 operating-points-v2 = <&gmu_opp_table>; 2344 2345 gmu_opp_table: opp-table { 2346 compatible = "operating-points-v2"; 2347 2348 opp-200000000 { 2349 opp-hz = /bits/ 64 <200000000>; 2350 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2351 }; 2352 2353 opp-500000000 { 2354 opp-hz = /bits/ 64 <500000000>; 2355 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2356 }; 2357 }; 2358 }; 2359 2360 gpucc: clock-controller@2c90000 { 2361 compatible = "qcom,sc8180x-gpucc"; 2362 reg = <0 0x02c90000 0 0x9000>; 2363 clocks = <&rpmhcc RPMH_CXO_CLK>, 2364 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2365 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2366 clock-names = "bi_tcxo", 2367 "gcc_gpu_gpll0_clk_src", 2368 "gcc_gpu_gpll0_div_clk_src"; 2369 #clock-cells = <1>; 2370 #reset-cells = <1>; 2371 #power-domain-cells = <1>; 2372 }; 2373 2374 adreno_smmu: iommu@2ca0000 { 2375 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2376 "qcom,smmu-500", "arm,mmu-500"; 2377 reg = <0 0x02ca0000 0 0x10000>; 2378 #iommu-cells = <2>; 2379 #global-interrupts = <1>; 2380 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2389 clocks = <&gpucc GPU_CC_AHB_CLK>, 2390 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2391 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2392 clock-names = "ahb", "bus", "iface"; 2393 2394 power-domains = <&gpucc GPU_CX_GDSC>; 2395 }; 2396 2397 tlmm: pinctrl@3100000 { 2398 compatible = "qcom,sc8180x-tlmm"; 2399 reg = <0 0x03100000 0 0x300000>, 2400 <0 0x03500000 0 0x700000>, 2401 <0 0x03d00000 0 0x300000>; 2402 reg-names = "west", "east", "south"; 2403 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2404 gpio-controller; 2405 #gpio-cells = <2>; 2406 interrupt-controller; 2407 #interrupt-cells = <2>; 2408 gpio-ranges = <&tlmm 0 0 191>; 2409 wakeup-parent = <&pdc>; 2410 }; 2411 2412 remoteproc_mpss: remoteproc@4080000 { 2413 compatible = "qcom,sc8180x-mpss-pas"; 2414 reg = <0x0 0x04080000 0x0 0x4040>; 2415 2416 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2417 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2418 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2419 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2420 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2421 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2422 interrupt-names = "wdog", "fatal", "ready", "handover", 2423 "stop-ack", "shutdown-ack"; 2424 2425 clocks = <&rpmhcc RPMH_CXO_CLK>; 2426 clock-names = "xo"; 2427 2428 power-domains = <&rpmhpd SC8180X_CX>, 2429 <&rpmhpd SC8180X_MSS>; 2430 power-domain-names = "cx", "mss"; 2431 2432 qcom,qmp = <&aoss_qmp>; 2433 2434 qcom,smem-states = <&modem_smp2p_out 0>; 2435 qcom,smem-state-names = "stop"; 2436 2437 glink-edge { 2438 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2439 label = "modem"; 2440 qcom,remote-pid = <1>; 2441 mboxes = <&apss_shared 12>; 2442 }; 2443 }; 2444 2445 remoteproc_cdsp: remoteproc@8300000 { 2446 compatible = "qcom,sc8180x-cdsp-pas"; 2447 reg = <0x0 0x08300000 0x0 0x4040>; 2448 2449 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2450 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2451 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2452 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2453 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2454 interrupt-names = "wdog", "fatal", "ready", 2455 "handover", "stop-ack"; 2456 2457 clocks = <&rpmhcc RPMH_CXO_CLK>; 2458 clock-names = "xo"; 2459 2460 power-domains = <&rpmhpd SC8180X_CX>; 2461 power-domain-names = "cx"; 2462 2463 qcom,qmp = <&aoss_qmp>; 2464 2465 qcom,smem-states = <&cdsp_smp2p_out 0>; 2466 qcom,smem-state-names = "stop"; 2467 2468 status = "disabled"; 2469 2470 glink-edge { 2471 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2472 label = "cdsp"; 2473 qcom,remote-pid = <5>; 2474 mboxes = <&apss_shared 4>; 2475 }; 2476 }; 2477 2478 usb_prim_hsphy: phy@88e2000 { 2479 compatible = "qcom,sc8180x-usb-hs-phy", 2480 "qcom,usb-snps-hs-7nm-phy"; 2481 reg = <0 0x088e2000 0 0x400>; 2482 clocks = <&rpmhcc RPMH_CXO_CLK>; 2483 clock-names = "ref"; 2484 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2485 2486 #phy-cells = <0>; 2487 2488 status = "disabled"; 2489 }; 2490 2491 usb_sec_hsphy: phy@88e3000 { 2492 compatible = "qcom,sc8180x-usb-hs-phy", 2493 "qcom,usb-snps-hs-7nm-phy"; 2494 reg = <0 0x088e3000 0 0x400>; 2495 clocks = <&rpmhcc RPMH_CXO_CLK>; 2496 clock-names = "ref"; 2497 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2498 2499 #phy-cells = <0>; 2500 2501 status = "disabled"; 2502 }; 2503 2504 usb_mp_hsphy0: phy@88e4000 { 2505 compatible = "qcom,sc8180x-usb-hs-phy", 2506 "qcom,usb-snps-hs-7nm-phy"; 2507 reg = <0 0x088e4000 0 0x400>; 2508 #phy-cells = <0>; 2509 2510 clocks = <&rpmhcc RPMH_CXO_CLK>; 2511 clock-names = "ref"; 2512 2513 resets = <&gcc GCC_QUSB2PHY_MP0_BCR>; 2514 2515 status = "disabled"; 2516 }; 2517 2518 usb_mp_hsphy1: phy@88e5000 { 2519 compatible = "qcom,sc8180x-usb-hs-phy", 2520 "qcom,usb-snps-hs-7nm-phy"; 2521 reg = <0 0x088e5000 0 0x400>; 2522 #phy-cells = <0>; 2523 2524 clocks = <&rpmhcc RPMH_CXO_CLK>; 2525 clock-names = "ref"; 2526 2527 resets = <&gcc GCC_QUSB2PHY_MP1_BCR>; 2528 2529 status = "disabled"; 2530 }; 2531 2532 usb_prim_qmpphy: phy@88e8000 { 2533 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2534 reg = <0 0x088e8000 0 0x3000>; 2535 2536 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2537 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2538 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2539 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2540 clock-names = "aux", 2541 "ref", 2542 "com_aux", 2543 "usb3_pipe"; 2544 2545 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2546 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2547 reset-names = "phy", "common"; 2548 2549 #clock-cells = <1>; 2550 #phy-cells = <1>; 2551 2552 status = "disabled"; 2553 2554 ports { 2555 #address-cells = <1>; 2556 #size-cells = <0>; 2557 2558 port@0 { 2559 reg = <0>; 2560 2561 usb_prim_qmpphy_out: endpoint {}; 2562 }; 2563 2564 port@1 { 2565 reg = <1>; 2566 2567 usb_prim_qmpphy_usb_ss_in: endpoint { 2568 remote-endpoint = <&usb_prim_dwc3_ss>; 2569 }; 2570 }; 2571 2572 port@2 { 2573 reg = <2>; 2574 2575 usb_prim_qmpphy_dp_in: endpoint {}; 2576 }; 2577 }; 2578 }; 2579 2580 usb_mp_qmpphy0: phy@88eb000 { 2581 compatible = "qcom,sc8180x-qmp-usb3-uni-phy"; 2582 reg = <0 0x088eb000 0 0x1000>; 2583 2584 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2585 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2586 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2587 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2588 clock-names = "aux", 2589 "ref", 2590 "com_aux", 2591 "pipe"; 2592 2593 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2594 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2595 reset-names = "phy", "phy_phy"; 2596 2597 power-domains = <&gcc USB30_MP_GDSC>; 2598 2599 #clock-cells = <0>; 2600 clock-output-names = "usb2_phy0_pipe_clk"; 2601 2602 #phy-cells = <0>; 2603 2604 status = "disabled"; 2605 }; 2606 2607 usb_mp_qmpphy1: phy@88ec000 { 2608 compatible = "qcom,sc8180x-qmp-usb3-uni-phy"; 2609 reg = <0 0x088ec000 0 0x1000>; 2610 2611 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2612 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2613 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2614 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2615 clock-names = "aux", 2616 "ref", 2617 "com_aux", 2618 "pipe"; 2619 2620 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2621 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2622 reset-names = "phy", "phy_phy"; 2623 2624 power-domains = <&gcc USB30_MP_GDSC>; 2625 2626 #clock-cells = <0>; 2627 clock-output-names = "usb2_phy1_pipe_clk"; 2628 2629 #phy-cells = <0>; 2630 2631 status = "disabled"; 2632 }; 2633 2634 usb_sec_qmpphy: phy@88ee000 { 2635 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2636 reg = <0 0x088ed000 0 0x3000>; 2637 2638 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2639 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2640 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2641 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2642 clock-names = "aux", 2643 "ref", 2644 "com_aux", 2645 "usb3_pipe"; 2646 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2647 <&gcc GCC_USB3_PHY_SEC_BCR>; 2648 reset-names = "phy", "common"; 2649 2650 #clock-cells = <1>; 2651 #phy-cells = <1>; 2652 2653 status = "disabled"; 2654 2655 ports { 2656 #address-cells = <1>; 2657 #size-cells = <0>; 2658 2659 port@0 { 2660 reg = <0>; 2661 2662 usb_sec_qmpphy_out: endpoint {}; 2663 }; 2664 2665 port@1 { 2666 reg = <1>; 2667 2668 usb_sec_qmpphy_usb_ss_in: endpoint { 2669 remote-endpoint = <&usb_sec_dwc3_ss>; 2670 }; 2671 }; 2672 2673 port@2 { 2674 reg = <2>; 2675 2676 usb_sec_qmpphy_dp_in: endpoint {}; 2677 }; 2678 }; 2679 }; 2680 2681 system-cache-controller@9200000 { 2682 compatible = "qcom,sc8180x-llcc"; 2683 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2684 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2685 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 2686 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 2687 <0 0x09600000 0 0x58000>; 2688 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2689 "llcc3_base", "llcc4_base", "llcc5_base", 2690 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 2691 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2692 }; 2693 2694 gem_noc: interconnect@9680000 { 2695 compatible = "qcom,sc8180x-gem-noc"; 2696 reg = <0 0x09680000 0 0x58200>; 2697 #interconnect-cells = <2>; 2698 qcom,bcm-voters = <&apps_bcm_voter>; 2699 }; 2700 2701 usb_mp: usb@a4f8800 { 2702 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3"; 2703 reg = <0 0x0a4f8800 0 0x400>; 2704 #address-cells = <2>; 2705 #size-cells = <2>; 2706 ranges; 2707 dma-ranges; 2708 2709 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 2710 <&gcc GCC_USB30_MP_MASTER_CLK>, 2711 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 2712 <&gcc GCC_USB30_MP_SLEEP_CLK>, 2713 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 2714 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2715 clock-names = "cfg_noc", 2716 "core", 2717 "iface", 2718 "sleep", 2719 "mock_utmi", 2720 "xo"; 2721 2722 interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2723 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>; 2724 interconnect-names = "usb-ddr", "apps-usb"; 2725 2726 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 2727 <&gcc GCC_USB30_MP_MASTER_CLK>; 2728 assigned-clock-rates = <19200000>, <200000000>; 2729 2730 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>, 2731 <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>, 2732 <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>, 2733 <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>, 2734 <&pdc 59 IRQ_TYPE_EDGE_BOTH>, 2735 <&pdc 46 IRQ_TYPE_EDGE_BOTH>, 2736 <&pdc 71 IRQ_TYPE_EDGE_BOTH>, 2737 <&pdc 68 IRQ_TYPE_EDGE_BOTH>, 2738 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 2739 <&pdc 30 IRQ_TYPE_LEVEL_HIGH>; 2740 interrupt-names = "pwr_event_1", "pwr_event_2", 2741 "hs_phy_1", "hs_phy_2", 2742 "dp_hs_phy_1", "dm_hs_phy_1", 2743 "dp_hs_phy_2", "dm_hs_phy_2", 2744 "ss_phy_1", "ss_phy_2"; 2745 2746 power-domains = <&gcc USB30_MP_GDSC>; 2747 2748 resets = <&gcc GCC_USB30_MP_BCR>; 2749 2750 status = "disabled"; 2751 2752 usb_mp_dwc3: usb@a400000 { 2753 compatible = "snps,dwc3"; 2754 reg = <0 0x0a400000 0 0xcd00>; 2755 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 2756 iommus = <&apps_smmu 0x60 0>; 2757 snps,dis_u2_susphy_quirk; 2758 snps,dis_enblslpm_quirk; 2759 snps,dis-u1-entry-quirk; 2760 snps,dis-u2-entry-quirk; 2761 phys = <&usb_mp_hsphy0>, 2762 <&usb_mp_qmpphy0>, 2763 <&usb_mp_hsphy1>, 2764 <&usb_mp_qmpphy1>; 2765 phy-names = "usb2-0", 2766 "usb3-0", 2767 "usb2-1", 2768 "usb3-1"; 2769 dr_mode = "host"; 2770 }; 2771 }; 2772 2773 usb_prim: usb@a6f8800 { 2774 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2775 reg = <0 0x0a6f8800 0 0x400>; 2776 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2777 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2778 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 2779 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2780 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 2781 interrupt-names = "pwr_event", 2782 "hs_phy_irq", 2783 "dp_hs_phy_irq", 2784 "dm_hs_phy_irq", 2785 "ss_phy_irq"; 2786 2787 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2788 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2789 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2790 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2791 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2792 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2793 clock-names = "cfg_noc", 2794 "core", 2795 "iface", 2796 "sleep", 2797 "mock_utmi", 2798 "xo"; 2799 resets = <&gcc GCC_USB30_PRIM_BCR>; 2800 power-domains = <&gcc USB30_PRIM_GDSC>; 2801 2802 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2803 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2804 interconnect-names = "usb-ddr", "apps-usb"; 2805 2806 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2807 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2808 assigned-clock-rates = <19200000>, <200000000>; 2809 2810 #address-cells = <2>; 2811 #size-cells = <2>; 2812 ranges; 2813 dma-ranges; 2814 2815 status = "disabled"; 2816 2817 usb_prim_dwc3: usb@a600000 { 2818 compatible = "snps,dwc3"; 2819 reg = <0 0x0a600000 0 0xcd00>; 2820 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2821 iommus = <&apps_smmu 0x140 0>; 2822 snps,dis_u2_susphy_quirk; 2823 snps,dis_enblslpm_quirk; 2824 snps,dis-u1-entry-quirk; 2825 snps,dis-u2-entry-quirk; 2826 phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; 2827 phy-names = "usb2-phy", "usb3-phy"; 2828 2829 ports { 2830 #address-cells = <1>; 2831 #size-cells = <0>; 2832 2833 port@0 { 2834 reg = <0>; 2835 2836 usb_prim_dwc3_hs: endpoint { 2837 }; 2838 }; 2839 2840 port@1 { 2841 reg = <1>; 2842 2843 usb_prim_dwc3_ss: endpoint { 2844 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>; 2845 }; 2846 }; 2847 }; 2848 }; 2849 }; 2850 2851 usb_sec: usb@a8f8800 { 2852 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2853 reg = <0 0x0a8f8800 0 0x400>; 2854 2855 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2856 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2857 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2858 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2859 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2860 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2861 clock-names = "cfg_noc", 2862 "core", 2863 "iface", 2864 "sleep", 2865 "mock_utmi", 2866 "xo"; 2867 resets = <&gcc GCC_USB30_SEC_BCR>; 2868 power-domains = <&gcc USB30_SEC_GDSC>; 2869 2870 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2871 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2872 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 2873 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2874 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; 2875 interrupt-names = "pwr_event", 2876 "hs_phy_irq", 2877 "dp_hs_phy_irq", 2878 "dm_hs_phy_irq", 2879 "ss_phy_irq"; 2880 2881 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2882 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2883 assigned-clock-rates = <19200000>, <200000000>; 2884 2885 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2886 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2887 interconnect-names = "usb-ddr", "apps-usb"; 2888 2889 #address-cells = <2>; 2890 #size-cells = <2>; 2891 ranges; 2892 dma-ranges; 2893 2894 status = "disabled"; 2895 2896 usb_sec_dwc3: usb@a800000 { 2897 compatible = "snps,dwc3"; 2898 reg = <0 0x0a800000 0 0xcd00>; 2899 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2900 iommus = <&apps_smmu 0x160 0>; 2901 snps,dis_u2_susphy_quirk; 2902 snps,dis_enblslpm_quirk; 2903 snps,dis-u1-entry-quirk; 2904 snps,dis-u2-entry-quirk; 2905 phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; 2906 phy-names = "usb2-phy", "usb3-phy"; 2907 2908 ports { 2909 #address-cells = <1>; 2910 #size-cells = <0>; 2911 2912 port@0 { 2913 reg = <0>; 2914 2915 usb_sec_dwc3_hs: endpoint { 2916 }; 2917 }; 2918 2919 port@1 { 2920 reg = <1>; 2921 2922 usb_sec_dwc3_ss: endpoint { 2923 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>; 2924 }; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 camcc: clock-controller@ad00000 { 2931 compatible = "qcom,sc8180x-camcc"; 2932 reg = <0 0x0ad00000 0 0x20000>; 2933 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2934 <&rpmhcc RPMH_CXO_CLK>, 2935 <&sleep_clk>; 2936 power-domains = <&rpmhpd SC8180X_MMCX>; 2937 required-opps = <&rpmhpd_opp_low_svs>; 2938 #clock-cells = <1>; 2939 #reset-cells = <1>; 2940 #power-domain-cells = <1>; 2941 }; 2942 2943 mdss: mdss@ae00000 { 2944 compatible = "qcom,sc8180x-mdss"; 2945 reg = <0 0x0ae00000 0 0x1000>; 2946 reg-names = "mdss"; 2947 2948 power-domains = <&dispcc MDSS_GDSC>; 2949 2950 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2951 <&gcc GCC_DISP_HF_AXI_CLK>, 2952 <&gcc GCC_DISP_SF_AXI_CLK>, 2953 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2954 clock-names = "iface", 2955 "bus", 2956 "nrt_bus", 2957 "core"; 2958 2959 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2960 2961 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2962 interrupt-controller; 2963 #interrupt-cells = <1>; 2964 2965 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2966 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2967 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS 2968 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2969 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2970 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 2971 interconnect-names = "mdp0-mem", 2972 "mdp1-mem", 2973 "cpu-cfg"; 2974 2975 iommus = <&apps_smmu 0x800 0x420>; 2976 2977 #address-cells = <2>; 2978 #size-cells = <2>; 2979 ranges; 2980 2981 status = "disabled"; 2982 2983 mdss_mdp: mdp@ae01000 { 2984 compatible = "qcom,sc8180x-dpu"; 2985 reg = <0 0x0ae01000 0 0x8f000>, 2986 <0 0x0aeb0000 0 0x3000>; 2987 reg-names = "mdp", "vbif"; 2988 2989 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2990 <&gcc GCC_DISP_HF_AXI_CLK>, 2991 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2992 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2993 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2994 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 2995 clock-names = "iface", 2996 "bus", 2997 "core", 2998 "vsync", 2999 "rot", 3000 "lut"; 3001 3002 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3003 assigned-clock-rates = <19200000>; 3004 3005 operating-points-v2 = <&mdp_opp_table>; 3006 power-domains = <&rpmhpd SC8180X_MMCX>; 3007 3008 interrupt-parent = <&mdss>; 3009 interrupts = <0>; 3010 3011 ports { 3012 #address-cells = <1>; 3013 #size-cells = <0>; 3014 3015 port@0 { 3016 reg = <0>; 3017 dpu_intf0_out: endpoint { 3018 remote-endpoint = <&dp0_in>; 3019 }; 3020 }; 3021 3022 port@1 { 3023 reg = <1>; 3024 dpu_intf1_out: endpoint { 3025 remote-endpoint = <&mdss_dsi0_in>; 3026 }; 3027 }; 3028 3029 port@2 { 3030 reg = <2>; 3031 dpu_intf2_out: endpoint { 3032 remote-endpoint = <&mdss_dsi1_in>; 3033 }; 3034 }; 3035 3036 port@4 { 3037 reg = <4>; 3038 dpu_intf4_out: endpoint { 3039 remote-endpoint = <&dp1_in>; 3040 }; 3041 }; 3042 3043 port@5 { 3044 reg = <5>; 3045 dpu_intf5_out: endpoint { 3046 remote-endpoint = <&edp_in>; 3047 }; 3048 }; 3049 }; 3050 3051 mdp_opp_table: opp-table { 3052 compatible = "operating-points-v2"; 3053 3054 opp-200000000 { 3055 opp-hz = /bits/ 64 <200000000>; 3056 required-opps = <&rpmhpd_opp_low_svs>; 3057 }; 3058 3059 opp-300000000 { 3060 opp-hz = /bits/ 64 <300000000>; 3061 required-opps = <&rpmhpd_opp_svs>; 3062 }; 3063 3064 opp-345000000 { 3065 opp-hz = /bits/ 64 <345000000>; 3066 required-opps = <&rpmhpd_opp_svs_l1>; 3067 }; 3068 3069 opp-460000000 { 3070 opp-hz = /bits/ 64 <460000000>; 3071 required-opps = <&rpmhpd_opp_nom>; 3072 }; 3073 }; 3074 }; 3075 3076 mdss_dsi0: dsi@ae94000 { 3077 compatible = "qcom,mdss-dsi-ctrl"; 3078 reg = <0 0x0ae94000 0 0x400>; 3079 reg-names = "dsi_ctrl"; 3080 3081 interrupt-parent = <&mdss>; 3082 interrupts = <4>; 3083 3084 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3085 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3086 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3087 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3088 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3089 <&gcc GCC_DISP_HF_AXI_CLK>; 3090 clock-names = "byte", 3091 "byte_intf", 3092 "pixel", 3093 "core", 3094 "iface", 3095 "bus"; 3096 3097 operating-points-v2 = <&dsi_opp_table>; 3098 power-domains = <&rpmhpd SC8180X_MMCX>; 3099 3100 phys = <&mdss_dsi0_phy>; 3101 phy-names = "dsi"; 3102 3103 status = "disabled"; 3104 3105 ports { 3106 #address-cells = <1>; 3107 #size-cells = <0>; 3108 3109 port@0 { 3110 reg = <0>; 3111 mdss_dsi0_in: endpoint { 3112 remote-endpoint = <&dpu_intf1_out>; 3113 }; 3114 }; 3115 3116 port@1 { 3117 reg = <1>; 3118 mdss_dsi0_out: endpoint { 3119 }; 3120 }; 3121 }; 3122 3123 dsi_opp_table: opp-table { 3124 compatible = "operating-points-v2"; 3125 3126 opp-187500000 { 3127 opp-hz = /bits/ 64 <187500000>; 3128 required-opps = <&rpmhpd_opp_low_svs>; 3129 }; 3130 3131 opp-300000000 { 3132 opp-hz = /bits/ 64 <300000000>; 3133 required-opps = <&rpmhpd_opp_svs>; 3134 }; 3135 3136 opp-358000000 { 3137 opp-hz = /bits/ 64 <358000000>; 3138 required-opps = <&rpmhpd_opp_svs_l1>; 3139 }; 3140 }; 3141 }; 3142 3143 mdss_dsi0_phy: dsi-phy@ae94400 { 3144 compatible = "qcom,dsi-phy-7nm"; 3145 reg = <0 0x0ae94400 0 0x200>, 3146 <0 0x0ae94600 0 0x280>, 3147 <0 0x0ae94900 0 0x260>; 3148 reg-names = "dsi_phy", 3149 "dsi_phy_lane", 3150 "dsi_pll"; 3151 3152 #clock-cells = <1>; 3153 #phy-cells = <0>; 3154 3155 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3156 <&rpmhcc RPMH_CXO_CLK>; 3157 clock-names = "iface", "ref"; 3158 3159 status = "disabled"; 3160 }; 3161 3162 mdss_dsi1: dsi@ae96000 { 3163 compatible = "qcom,mdss-dsi-ctrl"; 3164 reg = <0 0x0ae96000 0 0x400>; 3165 reg-names = "dsi_ctrl"; 3166 3167 interrupt-parent = <&mdss>; 3168 interrupts = <5>; 3169 3170 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3171 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3172 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3173 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3174 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3175 <&gcc GCC_DISP_HF_AXI_CLK>; 3176 clock-names = "byte", 3177 "byte_intf", 3178 "pixel", 3179 "core", 3180 "iface", 3181 "bus"; 3182 3183 operating-points-v2 = <&dsi_opp_table>; 3184 power-domains = <&rpmhpd SC8180X_MMCX>; 3185 3186 phys = <&mdss_dsi1_phy>; 3187 phy-names = "dsi"; 3188 3189 status = "disabled"; 3190 3191 ports { 3192 #address-cells = <1>; 3193 #size-cells = <0>; 3194 3195 port@0 { 3196 reg = <0>; 3197 mdss_dsi1_in: endpoint { 3198 remote-endpoint = <&dpu_intf2_out>; 3199 }; 3200 }; 3201 3202 port@1 { 3203 reg = <1>; 3204 mdss_dsi1_out: endpoint { 3205 }; 3206 }; 3207 }; 3208 }; 3209 3210 mdss_dsi1_phy: dsi-phy@ae96400 { 3211 compatible = "qcom,dsi-phy-7nm"; 3212 reg = <0 0x0ae96400 0 0x200>, 3213 <0 0x0ae96600 0 0x280>, 3214 <0 0x0ae96900 0 0x260>; 3215 reg-names = "dsi_phy", 3216 "dsi_phy_lane", 3217 "dsi_pll"; 3218 3219 #clock-cells = <1>; 3220 #phy-cells = <0>; 3221 3222 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3223 <&rpmhcc RPMH_CXO_CLK>; 3224 clock-names = "iface", "ref"; 3225 3226 status = "disabled"; 3227 }; 3228 3229 mdss_dp0: displayport-controller@ae90000 { 3230 compatible = "qcom,sc8180x-dp"; 3231 reg = <0 0xae90000 0 0x200>, 3232 <0 0xae90200 0 0x200>, 3233 <0 0xae90400 0 0x600>, 3234 <0 0xae90a00 0 0x400>, 3235 <0 0xae91000 0 0x400>; 3236 interrupt-parent = <&mdss>; 3237 interrupts = <12>; 3238 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3239 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3240 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3241 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3242 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3243 clock-names = "core_iface", 3244 "core_aux", 3245 "ctrl_link", 3246 "ctrl_link_iface", 3247 "stream_pixel"; 3248 3249 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3250 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3251 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3252 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3253 3254 phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; 3255 phy-names = "dp"; 3256 3257 #sound-dai-cells = <0>; 3258 3259 operating-points-v2 = <&dp0_opp_table>; 3260 power-domains = <&rpmhpd SC8180X_MMCX>; 3261 3262 status = "disabled"; 3263 3264 ports { 3265 #address-cells = <1>; 3266 #size-cells = <0>; 3267 3268 port@0 { 3269 reg = <0>; 3270 dp0_in: endpoint { 3271 remote-endpoint = <&dpu_intf0_out>; 3272 }; 3273 }; 3274 3275 port@1 { 3276 reg = <1>; 3277 mdss_dp0_out: endpoint { 3278 }; 3279 }; 3280 }; 3281 3282 dp0_opp_table: opp-table { 3283 compatible = "operating-points-v2"; 3284 3285 opp-160000000 { 3286 opp-hz = /bits/ 64 <160000000>; 3287 required-opps = <&rpmhpd_opp_low_svs>; 3288 }; 3289 3290 opp-270000000 { 3291 opp-hz = /bits/ 64 <270000000>; 3292 required-opps = <&rpmhpd_opp_svs>; 3293 }; 3294 3295 opp-540000000 { 3296 opp-hz = /bits/ 64 <540000000>; 3297 required-opps = <&rpmhpd_opp_svs_l1>; 3298 }; 3299 3300 opp-810000000 { 3301 opp-hz = /bits/ 64 <810000000>; 3302 required-opps = <&rpmhpd_opp_nom>; 3303 }; 3304 }; 3305 }; 3306 3307 mdss_dp1: displayport-controller@ae98000 { 3308 compatible = "qcom,sc8180x-dp"; 3309 reg = <0 0xae98000 0 0x200>, 3310 <0 0xae98200 0 0x200>, 3311 <0 0xae98400 0 0x600>, 3312 <0 0xae98a00 0 0x400>, 3313 <0 0xae99000 0 0x400>; 3314 interrupt-parent = <&mdss>; 3315 interrupts = <13>; 3316 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3317 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3318 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3319 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3320 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 3321 clock-names = "core_iface", 3322 "core_aux", 3323 "ctrl_link", 3324 "ctrl_link_iface", 3325 "stream_pixel"; 3326 3327 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3328 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 3329 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3330 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3331 3332 phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; 3333 phy-names = "dp"; 3334 3335 #sound-dai-cells = <0>; 3336 3337 operating-points-v2 = <&dp0_opp_table>; 3338 power-domains = <&rpmhpd SC8180X_MMCX>; 3339 3340 status = "disabled"; 3341 3342 ports { 3343 #address-cells = <1>; 3344 #size-cells = <0>; 3345 3346 port@0 { 3347 reg = <0>; 3348 dp1_in: endpoint { 3349 remote-endpoint = <&dpu_intf4_out>; 3350 }; 3351 }; 3352 3353 port@1 { 3354 reg = <1>; 3355 mdss_dp1_out: endpoint { 3356 }; 3357 }; 3358 }; 3359 3360 dp1_opp_table: opp-table { 3361 compatible = "operating-points-v2"; 3362 3363 opp-160000000 { 3364 opp-hz = /bits/ 64 <160000000>; 3365 required-opps = <&rpmhpd_opp_low_svs>; 3366 }; 3367 3368 opp-270000000 { 3369 opp-hz = /bits/ 64 <270000000>; 3370 required-opps = <&rpmhpd_opp_svs>; 3371 }; 3372 3373 opp-540000000 { 3374 opp-hz = /bits/ 64 <540000000>; 3375 required-opps = <&rpmhpd_opp_svs_l1>; 3376 }; 3377 3378 opp-810000000 { 3379 opp-hz = /bits/ 64 <810000000>; 3380 required-opps = <&rpmhpd_opp_nom>; 3381 }; 3382 }; 3383 }; 3384 3385 mdss_edp: displayport-controller@ae9a000 { 3386 compatible = "qcom,sc8180x-edp"; 3387 reg = <0 0xae9a000 0 0x200>, 3388 <0 0xae9a200 0 0x200>, 3389 <0 0xae9a400 0 0x600>, 3390 <0 0xae9aa00 0 0x400>; 3391 interrupt-parent = <&mdss>; 3392 interrupts = <14>; 3393 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3394 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3395 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3396 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3397 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3398 clock-names = "core_iface", 3399 "core_aux", 3400 "ctrl_link", 3401 "ctrl_link_iface", 3402 "stream_pixel"; 3403 3404 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3405 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3406 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3407 3408 phys = <&edp_phy>; 3409 phy-names = "dp"; 3410 3411 operating-points-v2 = <&edp_opp_table>; 3412 power-domains = <&rpmhpd SC8180X_MMCX>; 3413 3414 status = "disabled"; 3415 3416 ports { 3417 #address-cells = <1>; 3418 #size-cells = <0>; 3419 3420 port@0 { 3421 reg = <0>; 3422 edp_in: endpoint { 3423 remote-endpoint = <&dpu_intf5_out>; 3424 }; 3425 }; 3426 }; 3427 3428 edp_opp_table: opp-table { 3429 compatible = "operating-points-v2"; 3430 3431 opp-160000000 { 3432 opp-hz = /bits/ 64 <160000000>; 3433 required-opps = <&rpmhpd_opp_low_svs>; 3434 }; 3435 3436 opp-270000000 { 3437 opp-hz = /bits/ 64 <270000000>; 3438 required-opps = <&rpmhpd_opp_svs>; 3439 }; 3440 3441 opp-540000000 { 3442 opp-hz = /bits/ 64 <540000000>; 3443 required-opps = <&rpmhpd_opp_svs_l1>; 3444 }; 3445 3446 opp-810000000 { 3447 opp-hz = /bits/ 64 <810000000>; 3448 required-opps = <&rpmhpd_opp_nom>; 3449 }; 3450 }; 3451 }; 3452 }; 3453 3454 edp_phy: phy@aec2a00 { 3455 compatible = "qcom,sc8180x-edp-phy"; 3456 reg = <0 0x0aec2a00 0 0x1c0>, 3457 <0 0x0aec2200 0 0xa0>, 3458 <0 0x0aec2600 0 0xa0>, 3459 <0 0x0aec2000 0 0x19c>; 3460 3461 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3462 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3463 clock-names = "aux", "cfg_ahb"; 3464 3465 power-domains = <&rpmhpd SC8180X_MX>; 3466 3467 #clock-cells = <1>; 3468 #phy-cells = <0>; 3469 }; 3470 3471 dispcc: clock-controller@af00000 { 3472 compatible = "qcom,sc8180x-dispcc"; 3473 reg = <0 0x0af00000 0 0x20000>; 3474 clocks = <&rpmhcc RPMH_CXO_CLK>, 3475 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3476 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3477 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3478 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3479 <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3480 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3481 <&edp_phy 0>, 3482 <&edp_phy 1>, 3483 <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3484 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3485 clock-names = "bi_tcxo", 3486 "dsi0_phy_pll_out_byteclk", 3487 "dsi0_phy_pll_out_dsiclk", 3488 "dsi1_phy_pll_out_byteclk", 3489 "dsi1_phy_pll_out_dsiclk", 3490 "dp_phy_pll_link_clk", 3491 "dp_phy_pll_vco_div_clk", 3492 "edp_phy_pll_link_clk", 3493 "edp_phy_pll_vco_div_clk", 3494 "dptx1_phy_pll_link_clk", 3495 "dptx1_phy_pll_vco_div_clk"; 3496 power-domains = <&rpmhpd SC8180X_MMCX>; 3497 required-opps = <&rpmhpd_opp_low_svs>; 3498 #clock-cells = <1>; 3499 #reset-cells = <1>; 3500 #power-domain-cells = <1>; 3501 }; 3502 3503 pdc: interrupt-controller@b220000 { 3504 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3505 reg = <0 0x0b220000 0 0x30000>; 3506 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3507 #interrupt-cells = <2>; 3508 interrupt-parent = <&intc>; 3509 interrupt-controller; 3510 }; 3511 3512 tsens0: thermal-sensor@c263000 { 3513 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3514 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3515 <0 0x0c222000 0 0x1ff>; /* SROT */ 3516 #qcom,sensors = <16>; 3517 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3519 interrupt-names = "uplow", "critical"; 3520 #thermal-sensor-cells = <1>; 3521 }; 3522 3523 tsens1: thermal-sensor@c265000 { 3524 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3525 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3526 <0 0x0c223000 0 0x1ff>; /* SROT */ 3527 #qcom,sensors = <9>; 3528 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3530 interrupt-names = "uplow", "critical"; 3531 #thermal-sensor-cells = <1>; 3532 }; 3533 3534 aoss_qmp: power-management@c300000 { 3535 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3536 reg = <0x0 0x0c300000 0x0 0x400>; 3537 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3538 mboxes = <&apss_shared 0>; 3539 3540 #clock-cells = <0>; 3541 }; 3542 3543 sram@c3f0000 { 3544 compatible = "qcom,rpmh-stats"; 3545 reg = <0x0 0x0c3f0000 0x0 0x400>; 3546 }; 3547 3548 spmi_bus: spmi@c440000 { 3549 compatible = "qcom,spmi-pmic-arb"; 3550 reg = <0x0 0x0c440000 0x0 0x0001100>, 3551 <0x0 0x0c600000 0x0 0x2000000>, 3552 <0x0 0x0e600000 0x0 0x0100000>, 3553 <0x0 0x0e700000 0x0 0x00a0000>, 3554 <0x0 0x0c40a000 0x0 0x0026000>; 3555 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3556 interrupt-names = "periph_irq"; 3557 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3558 qcom,ee = <0>; 3559 qcom,channel = <0>; 3560 #address-cells = <2>; 3561 #size-cells = <0>; 3562 interrupt-controller; 3563 #interrupt-cells = <4>; 3564 }; 3565 3566 apps_smmu: iommu@15000000 { 3567 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3568 reg = <0 0x15000000 0 0x100000>; 3569 #iommu-cells = <2>; 3570 #global-interrupts = <1>; 3571 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3577 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3582 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3583 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3584 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3678 dma-coherent; 3679 }; 3680 3681 remoteproc_adsp: remoteproc@17300000 { 3682 compatible = "qcom,sc8180x-adsp-pas"; 3683 reg = <0x0 0x17300000 0x0 0x4040>; 3684 3685 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3686 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3687 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3688 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3689 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3690 interrupt-names = "wdog", "fatal", "ready", 3691 "handover", "stop-ack"; 3692 3693 clocks = <&rpmhcc RPMH_CXO_CLK>; 3694 clock-names = "xo"; 3695 3696 power-domains = <&rpmhpd SC8180X_CX>; 3697 power-domain-names = "cx"; 3698 3699 qcom,qmp = <&aoss_qmp>; 3700 3701 qcom,smem-states = <&adsp_smp2p_out 0>; 3702 qcom,smem-state-names = "stop"; 3703 3704 status = "disabled"; 3705 3706 remoteproc_adsp_glink: glink-edge { 3707 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3708 label = "lpass"; 3709 qcom,remote-pid = <2>; 3710 mboxes = <&apss_shared 8>; 3711 }; 3712 }; 3713 3714 intc: interrupt-controller@17a00000 { 3715 compatible = "arm,gic-v3"; 3716 interrupt-controller; 3717 #interrupt-cells = <3>; 3718 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3719 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3720 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3721 #redistributor-regions = <1>; 3722 redistributor-stride = <0 0x20000>; 3723 }; 3724 3725 apss_shared: mailbox@17c00000 { 3726 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared"; 3727 reg = <0x0 0x17c00000 0x0 0x1000>; 3728 #mbox-cells = <1>; 3729 }; 3730 3731 timer@17c20000 { 3732 compatible = "arm,armv7-timer-mem"; 3733 reg = <0x0 0x17c20000 0x0 0x1000>; 3734 3735 #address-cells = <1>; 3736 #size-cells = <1>; 3737 ranges = <0 0 0 0x20000000>; 3738 3739 frame@17c21000 { 3740 reg = <0x17c21000 0x1000>, 3741 <0x17c22000 0x1000>; 3742 frame-number = <0>; 3743 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3745 }; 3746 3747 frame@17c23000 { 3748 reg = <0x17c23000 0x1000>; 3749 frame-number = <1>; 3750 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3751 status = "disabled"; 3752 }; 3753 3754 frame@17c25000 { 3755 reg = <0x17c25000 0x1000>; 3756 frame-number = <2>; 3757 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3758 status = "disabled"; 3759 }; 3760 3761 frame@17c27000 { 3762 reg = <0x17c26000 0x1000>; 3763 frame-number = <3>; 3764 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3765 status = "disabled"; 3766 }; 3767 3768 frame@17c29000 { 3769 reg = <0x17c29000 0x1000>; 3770 frame-number = <4>; 3771 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3772 status = "disabled"; 3773 }; 3774 3775 frame@17c2b000 { 3776 reg = <0x17c2b000 0x1000>; 3777 frame-number = <5>; 3778 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3779 status = "disabled"; 3780 }; 3781 3782 frame@17c2d000 { 3783 reg = <0x17c2d000 0x1000>; 3784 frame-number = <6>; 3785 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3786 status = "disabled"; 3787 }; 3788 }; 3789 3790 apps_rsc: rsc@18200000 { 3791 compatible = "qcom,rpmh-rsc"; 3792 reg = <0x0 0x18200000 0x0 0x10000>, 3793 <0x0 0x18210000 0x0 0x10000>, 3794 <0x0 0x18220000 0x0 0x10000>; 3795 reg-names = "drv-0", "drv-1", "drv-2"; 3796 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3799 qcom,tcs-offset = <0xd00>; 3800 qcom,drv-id = <2>; 3801 qcom,tcs-config = <ACTIVE_TCS 2>, 3802 <SLEEP_TCS 1>, 3803 <WAKE_TCS 1>, 3804 <CONTROL_TCS 0>; 3805 label = "apps_rsc"; 3806 power-domains = <&cluster_pd>; 3807 3808 apps_bcm_voter: bcm-voter { 3809 compatible = "qcom,bcm-voter"; 3810 }; 3811 3812 rpmhcc: clock-controller { 3813 compatible = "qcom,sc8180x-rpmh-clk"; 3814 #clock-cells = <1>; 3815 clock-names = "xo"; 3816 clocks = <&xo_board_clk>; 3817 }; 3818 3819 rpmhpd: power-controller { 3820 compatible = "qcom,sc8180x-rpmhpd"; 3821 #power-domain-cells = <1>; 3822 operating-points-v2 = <&rpmhpd_opp_table>; 3823 3824 rpmhpd_opp_table: opp-table { 3825 compatible = "operating-points-v2"; 3826 3827 rpmhpd_opp_ret: opp1 { 3828 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3829 }; 3830 3831 rpmhpd_opp_min_svs: opp2 { 3832 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3833 }; 3834 3835 rpmhpd_opp_low_svs: opp3 { 3836 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3837 }; 3838 3839 rpmhpd_opp_svs: opp4 { 3840 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3841 }; 3842 3843 rpmhpd_opp_svs_l1: opp5 { 3844 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3845 }; 3846 3847 rpmhpd_opp_nom: opp6 { 3848 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3849 }; 3850 3851 rpmhpd_opp_nom_l1: opp7 { 3852 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3853 }; 3854 3855 rpmhpd_opp_nom_l2: opp8 { 3856 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3857 }; 3858 3859 rpmhpd_opp_turbo: opp9 { 3860 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3861 }; 3862 3863 rpmhpd_opp_turbo_l1: opp10 { 3864 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3865 }; 3866 }; 3867 }; 3868 }; 3869 3870 osm_l3: interconnect@18321000 { 3871 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3872 reg = <0 0x18321000 0 0x1400>; 3873 3874 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3875 clock-names = "xo", "alternate"; 3876 3877 #interconnect-cells = <1>; 3878 }; 3879 3880 lmh@18350800 { 3881 compatible = "qcom,sc8180x-lmh"; 3882 reg = <0 0x18350800 0 0x400>; 3883 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3884 cpus = <&cpu4>; 3885 qcom,lmh-temp-arm-millicelsius = <65000>; 3886 qcom,lmh-temp-low-millicelsius = <94500>; 3887 qcom,lmh-temp-high-millicelsius = <95000>; 3888 interrupt-controller; 3889 #interrupt-cells = <1>; 3890 }; 3891 3892 lmh@18358800 { 3893 compatible = "qcom,sc8180x-lmh"; 3894 reg = <0 0x18358800 0 0x400>; 3895 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3896 cpus = <&cpu0>; 3897 qcom,lmh-temp-arm-millicelsius = <65000>; 3898 qcom,lmh-temp-low-millicelsius = <94500>; 3899 qcom,lmh-temp-high-millicelsius = <95000>; 3900 interrupt-controller; 3901 #interrupt-cells = <1>; 3902 }; 3903 3904 cpufreq_hw: cpufreq@18323000 { 3905 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw"; 3906 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3907 reg-names = "freq-domain0", "freq-domain1"; 3908 3909 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3910 clock-names = "xo", "alternate"; 3911 3912 #freq-domain-cells = <1>; 3913 #clock-cells = <1>; 3914 }; 3915 3916 wifi: wifi@18800000 { 3917 compatible = "qcom,wcn3990-wifi"; 3918 reg = <0 0x18800000 0 0x800000>; 3919 reg-names = "membase"; 3920 clock-names = "cxo_ref_clk_pin"; 3921 clocks = <&rpmhcc RPMH_RF_CLK2>; 3922 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3934 iommus = <&apps_smmu 0x0640 0x1>; 3935 qcom,msa-fixed-perm; 3936 status = "disabled"; 3937 }; 3938 }; 3939 3940 thermal-zones { 3941 cpu0-thermal { 3942 polling-delay-passive = <250>; 3943 3944 thermal-sensors = <&tsens0 1>; 3945 3946 trips { 3947 cpu-crit { 3948 temperature = <110000>; 3949 hysteresis = <1000>; 3950 type = "critical"; 3951 }; 3952 }; 3953 }; 3954 3955 cpu1-thermal { 3956 polling-delay-passive = <250>; 3957 3958 thermal-sensors = <&tsens0 2>; 3959 3960 trips { 3961 cpu-crit { 3962 temperature = <110000>; 3963 hysteresis = <1000>; 3964 type = "critical"; 3965 }; 3966 }; 3967 }; 3968 3969 cpu2-thermal { 3970 polling-delay-passive = <250>; 3971 3972 thermal-sensors = <&tsens0 3>; 3973 3974 trips { 3975 cpu-crit { 3976 temperature = <110000>; 3977 hysteresis = <1000>; 3978 type = "critical"; 3979 }; 3980 }; 3981 }; 3982 3983 cpu3-thermal { 3984 polling-delay-passive = <250>; 3985 3986 thermal-sensors = <&tsens0 4>; 3987 3988 trips { 3989 cpu-crit { 3990 temperature = <110000>; 3991 hysteresis = <1000>; 3992 type = "critical"; 3993 }; 3994 }; 3995 }; 3996 3997 cpu4-top-thermal { 3998 polling-delay-passive = <250>; 3999 4000 thermal-sensors = <&tsens0 7>; 4001 4002 trips { 4003 cpu-crit { 4004 temperature = <110000>; 4005 hysteresis = <1000>; 4006 type = "critical"; 4007 }; 4008 }; 4009 }; 4010 4011 cpu5-top-thermal { 4012 polling-delay-passive = <250>; 4013 4014 thermal-sensors = <&tsens0 8>; 4015 4016 trips { 4017 cpu-crit { 4018 temperature = <110000>; 4019 hysteresis = <1000>; 4020 type = "critical"; 4021 }; 4022 }; 4023 }; 4024 4025 cpu6-top-thermal { 4026 polling-delay-passive = <250>; 4027 4028 thermal-sensors = <&tsens0 9>; 4029 4030 trips { 4031 cpu-crit { 4032 temperature = <110000>; 4033 hysteresis = <1000>; 4034 type = "critical"; 4035 }; 4036 }; 4037 }; 4038 4039 cpu7-top-thermal { 4040 polling-delay-passive = <250>; 4041 4042 thermal-sensors = <&tsens0 10>; 4043 4044 trips { 4045 cpu-crit { 4046 temperature = <110000>; 4047 hysteresis = <1000>; 4048 type = "critical"; 4049 }; 4050 }; 4051 }; 4052 4053 cpu4-bottom-thermal { 4054 polling-delay-passive = <250>; 4055 4056 thermal-sensors = <&tsens0 11>; 4057 4058 trips { 4059 cpu-crit { 4060 temperature = <110000>; 4061 hysteresis = <1000>; 4062 type = "critical"; 4063 }; 4064 }; 4065 }; 4066 4067 cpu5-bottom-thermal { 4068 polling-delay-passive = <250>; 4069 4070 thermal-sensors = <&tsens0 12>; 4071 4072 trips { 4073 cpu-crit { 4074 temperature = <110000>; 4075 hysteresis = <1000>; 4076 type = "critical"; 4077 }; 4078 }; 4079 }; 4080 4081 cpu6-bottom-thermal { 4082 polling-delay-passive = <250>; 4083 4084 thermal-sensors = <&tsens0 13>; 4085 4086 trips { 4087 cpu-crit { 4088 temperature = <110000>; 4089 hysteresis = <1000>; 4090 type = "critical"; 4091 }; 4092 }; 4093 }; 4094 4095 cpu7-bottom-thermal { 4096 polling-delay-passive = <250>; 4097 4098 thermal-sensors = <&tsens0 14>; 4099 4100 trips { 4101 cpu-crit { 4102 temperature = <110000>; 4103 hysteresis = <1000>; 4104 type = "critical"; 4105 }; 4106 }; 4107 }; 4108 4109 aoss0-thermal { 4110 polling-delay-passive = <250>; 4111 4112 thermal-sensors = <&tsens0 0>; 4113 4114 trips { 4115 trip-point0 { 4116 temperature = <90000>; 4117 hysteresis = <2000>; 4118 type = "hot"; 4119 }; 4120 }; 4121 }; 4122 4123 cluster0-thermal { 4124 polling-delay-passive = <250>; 4125 4126 thermal-sensors = <&tsens0 5>; 4127 4128 trips { 4129 cluster-crit { 4130 temperature = <110000>; 4131 hysteresis = <2000>; 4132 type = "critical"; 4133 }; 4134 }; 4135 }; 4136 4137 cluster1-thermal { 4138 polling-delay-passive = <250>; 4139 4140 thermal-sensors = <&tsens0 6>; 4141 4142 trips { 4143 cluster-crit { 4144 temperature = <110000>; 4145 hysteresis = <2000>; 4146 type = "critical"; 4147 }; 4148 }; 4149 }; 4150 4151 gpu-top-thermal { 4152 polling-delay-passive = <250>; 4153 4154 thermal-sensors = <&tsens0 15>; 4155 4156 cooling-maps { 4157 map0 { 4158 trip = <&gpu_top_alert0>; 4159 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4160 }; 4161 }; 4162 4163 trips { 4164 gpu_top_alert0: trip-point0 { 4165 temperature = <85000>; 4166 hysteresis = <1000>; 4167 type = "passive"; 4168 }; 4169 4170 trip-point1 { 4171 temperature = <90000>; 4172 hysteresis = <1000>; 4173 type = "hot"; 4174 }; 4175 4176 trip-point2 { 4177 temperature = <110000>; 4178 hysteresis = <1000>; 4179 type = "critical"; 4180 }; 4181 }; 4182 }; 4183 4184 aoss1-thermal { 4185 polling-delay-passive = <250>; 4186 4187 thermal-sensors = <&tsens1 0>; 4188 4189 trips { 4190 trip-point0 { 4191 temperature = <90000>; 4192 hysteresis = <2000>; 4193 type = "hot"; 4194 }; 4195 }; 4196 }; 4197 4198 wlan-thermal { 4199 polling-delay-passive = <250>; 4200 4201 thermal-sensors = <&tsens1 1>; 4202 4203 trips { 4204 trip-point0 { 4205 temperature = <90000>; 4206 hysteresis = <2000>; 4207 type = "hot"; 4208 }; 4209 }; 4210 }; 4211 4212 video-thermal { 4213 polling-delay-passive = <250>; 4214 4215 thermal-sensors = <&tsens1 2>; 4216 4217 trips { 4218 trip-point0 { 4219 temperature = <90000>; 4220 hysteresis = <2000>; 4221 type = "hot"; 4222 }; 4223 }; 4224 }; 4225 4226 mem-thermal { 4227 polling-delay-passive = <250>; 4228 4229 thermal-sensors = <&tsens1 3>; 4230 4231 trips { 4232 trip-point0 { 4233 temperature = <90000>; 4234 hysteresis = <2000>; 4235 type = "hot"; 4236 }; 4237 }; 4238 }; 4239 4240 q6-hvx-thermal { 4241 polling-delay-passive = <250>; 4242 4243 thermal-sensors = <&tsens1 4>; 4244 4245 trips { 4246 trip-point0 { 4247 temperature = <90000>; 4248 hysteresis = <2000>; 4249 type = "hot"; 4250 }; 4251 }; 4252 }; 4253 4254 camera-thermal { 4255 polling-delay-passive = <250>; 4256 4257 thermal-sensors = <&tsens1 5>; 4258 4259 trips { 4260 trip-point0 { 4261 temperature = <90000>; 4262 hysteresis = <2000>; 4263 type = "hot"; 4264 }; 4265 }; 4266 }; 4267 4268 compute-thermal { 4269 polling-delay-passive = <250>; 4270 4271 thermal-sensors = <&tsens1 6>; 4272 4273 trips { 4274 trip-point0 { 4275 temperature = <90000>; 4276 hysteresis = <2000>; 4277 type = "hot"; 4278 }; 4279 }; 4280 }; 4281 4282 mdm-dsp-thermal { 4283 polling-delay-passive = <250>; 4284 4285 thermal-sensors = <&tsens1 7>; 4286 4287 trips { 4288 trip-point0 { 4289 temperature = <90000>; 4290 hysteresis = <2000>; 4291 type = "hot"; 4292 }; 4293 }; 4294 }; 4295 4296 npu-thermal { 4297 polling-delay-passive = <250>; 4298 4299 thermal-sensors = <&tsens1 8>; 4300 4301 trips { 4302 trip-point0 { 4303 temperature = <90000>; 4304 hysteresis = <2000>; 4305 type = "hot"; 4306 }; 4307 }; 4308 }; 4309 4310 gpu-bottom-thermal { 4311 polling-delay-passive = <250>; 4312 4313 thermal-sensors = <&tsens1 11>; 4314 4315 cooling-maps { 4316 map0 { 4317 trip = <&gpu_bottom_alert0>; 4318 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4319 }; 4320 }; 4321 4322 trips { 4323 gpu_bottom_alert0: trip-point0 { 4324 temperature = <85000>; 4325 hysteresis = <1000>; 4326 type = "passive"; 4327 }; 4328 4329 trip-point1 { 4330 temperature = <90000>; 4331 hysteresis = <1000>; 4332 type = "hot"; 4333 }; 4334 4335 trip-point2 { 4336 temperature = <110000>; 4337 hysteresis = <1000>; 4338 type = "critical"; 4339 }; 4340 }; 4341 }; 4342 }; 4343 4344 timer { 4345 compatible = "arm,armv8-timer"; 4346 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4347 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4348 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4349 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4350 }; 4351}; 4352