1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7280.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 13#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sc7280.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sc7280.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/mailbox/qcom-ipcc.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/sound/qcom,lpass.h> 31#include <dt-bindings/sound/qcom,q6asm.h> 32#include <dt-bindings/thermal/thermal.h> 33 34/ { 35 interrupt-parent = <&intc>; 36 37 #address-cells = <2>; 38 #size-cells = <2>; 39 40 chosen { }; 41 42 aliases { 43 i2c0 = &i2c0; 44 i2c1 = &i2c1; 45 i2c2 = &i2c2; 46 i2c3 = &i2c3; 47 i2c4 = &i2c4; 48 i2c5 = &i2c5; 49 i2c6 = &i2c6; 50 i2c7 = &i2c7; 51 i2c8 = &i2c8; 52 i2c9 = &i2c9; 53 i2c10 = &i2c10; 54 i2c11 = &i2c11; 55 i2c12 = &i2c12; 56 i2c13 = &i2c13; 57 i2c14 = &i2c14; 58 i2c15 = &i2c15; 59 mmc1 = &sdhc_1; 60 mmc2 = &sdhc_2; 61 spi0 = &spi0; 62 spi1 = &spi1; 63 spi2 = &spi2; 64 spi3 = &spi3; 65 spi4 = &spi4; 66 spi5 = &spi5; 67 spi6 = &spi6; 68 spi7 = &spi7; 69 spi8 = &spi8; 70 spi9 = &spi9; 71 spi10 = &spi10; 72 spi11 = &spi11; 73 spi12 = &spi12; 74 spi13 = &spi13; 75 spi14 = &spi14; 76 spi15 = &spi15; 77 }; 78 79 clocks { 80 xo_board: xo-board { 81 compatible = "fixed-clock"; 82 clock-frequency = <76800000>; 83 #clock-cells = <0>; 84 }; 85 86 sleep_clk: sleep-clk { 87 compatible = "fixed-clock"; 88 clock-frequency = <32764>; 89 #clock-cells = <0>; 90 }; 91 }; 92 93 reserved-memory { 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 wlan_ce_mem: wlan-ce@4cd000 { 99 no-map; 100 reg = <0x0 0x004cd000 0x0 0x1000>; 101 }; 102 103 hyp_mem: hyp@80000000 { 104 reg = <0x0 0x80000000 0x0 0x600000>; 105 no-map; 106 }; 107 108 xbl_mem: xbl@80600000 { 109 reg = <0x0 0x80600000 0x0 0x200000>; 110 no-map; 111 }; 112 113 aop_mem: aop@80800000 { 114 reg = <0x0 0x80800000 0x0 0x60000>; 115 no-map; 116 }; 117 118 aop_cmd_db_mem: aop-cmd-db@80860000 { 119 reg = <0x0 0x80860000 0x0 0x20000>; 120 compatible = "qcom,cmd-db"; 121 no-map; 122 }; 123 124 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 125 reg = <0x0 0x80884000 0x0 0x10000>; 126 no-map; 127 }; 128 129 sec_apps_mem: sec-apps@808ff000 { 130 reg = <0x0 0x808ff000 0x0 0x1000>; 131 no-map; 132 }; 133 134 smem_mem: smem@80900000 { 135 reg = <0x0 0x80900000 0x0 0x200000>; 136 no-map; 137 }; 138 139 cpucp_mem: cpucp@80b00000 { 140 no-map; 141 reg = <0x0 0x80b00000 0x0 0x100000>; 142 }; 143 144 wlan_fw_mem: wlan-fw@80c00000 { 145 reg = <0x0 0x80c00000 0x0 0xc00000>; 146 no-map; 147 }; 148 149 adsp_mem: adsp@86700000 { 150 reg = <0x0 0x86700000 0x0 0x2800000>; 151 no-map; 152 }; 153 154 video_mem: video@8b200000 { 155 reg = <0x0 0x8b200000 0x0 0x500000>; 156 no-map; 157 }; 158 159 cdsp_mem: cdsp@88f00000 { 160 reg = <0x0 0x88f00000 0x0 0x1e00000>; 161 no-map; 162 }; 163 164 ipa_fw_mem: ipa-fw@8b700000 { 165 reg = <0 0x8b700000 0 0x10000>; 166 no-map; 167 }; 168 169 gpu_zap_mem: zap@8b71a000 { 170 reg = <0 0x8b71a000 0 0x2000>; 171 no-map; 172 }; 173 174 mpss_mem: mpss@8b800000 { 175 reg = <0x0 0x8b800000 0x0 0xf600000>; 176 no-map; 177 }; 178 179 wpss_mem: wpss@9ae00000 { 180 reg = <0x0 0x9ae00000 0x0 0x1900000>; 181 no-map; 182 }; 183 184 rmtfs_mem: rmtfs@9c900000 { 185 compatible = "qcom,rmtfs-mem"; 186 reg = <0x0 0x9c900000 0x0 0x280000>; 187 no-map; 188 189 qcom,client-id = <1>; 190 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 191 }; 192 }; 193 194 cpus { 195 #address-cells = <2>; 196 #size-cells = <0>; 197 198 cpu0: cpu@0 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo"; 201 reg = <0x0 0x0>; 202 clocks = <&cpufreq_hw 0>; 203 enable-method = "psci"; 204 power-domains = <&cpu_pd0>; 205 power-domain-names = "psci"; 206 next-level-cache = <&l2_0>; 207 operating-points-v2 = <&cpu0_opp_table>; 208 capacity-dmips-mhz = <1024>; 209 dynamic-power-coefficient = <100>; 210 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 211 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 212 qcom,freq-domain = <&cpufreq_hw 0>; 213 #cooling-cells = <2>; 214 l2_0: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 next-level-cache = <&l3_0>; 219 l3_0: l3-cache { 220 compatible = "cache"; 221 cache-level = <3>; 222 cache-unified; 223 }; 224 }; 225 }; 226 227 cpu1: cpu@100 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo"; 230 reg = <0x0 0x100>; 231 clocks = <&cpufreq_hw 0>; 232 enable-method = "psci"; 233 power-domains = <&cpu_pd1>; 234 power-domain-names = "psci"; 235 next-level-cache = <&l2_100>; 236 operating-points-v2 = <&cpu0_opp_table>; 237 capacity-dmips-mhz = <1024>; 238 dynamic-power-coefficient = <100>; 239 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 240 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 241 qcom,freq-domain = <&cpufreq_hw 0>; 242 #cooling-cells = <2>; 243 l2_100: l2-cache { 244 compatible = "cache"; 245 cache-level = <2>; 246 cache-unified; 247 next-level-cache = <&l3_0>; 248 }; 249 }; 250 251 cpu2: cpu@200 { 252 device_type = "cpu"; 253 compatible = "qcom,kryo"; 254 reg = <0x0 0x200>; 255 clocks = <&cpufreq_hw 0>; 256 enable-method = "psci"; 257 power-domains = <&cpu_pd2>; 258 power-domain-names = "psci"; 259 next-level-cache = <&l2_200>; 260 operating-points-v2 = <&cpu0_opp_table>; 261 capacity-dmips-mhz = <1024>; 262 dynamic-power-coefficient = <100>; 263 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 264 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 265 qcom,freq-domain = <&cpufreq_hw 0>; 266 #cooling-cells = <2>; 267 l2_200: l2-cache { 268 compatible = "cache"; 269 cache-level = <2>; 270 cache-unified; 271 next-level-cache = <&l3_0>; 272 }; 273 }; 274 275 cpu3: cpu@300 { 276 device_type = "cpu"; 277 compatible = "qcom,kryo"; 278 reg = <0x0 0x300>; 279 clocks = <&cpufreq_hw 0>; 280 enable-method = "psci"; 281 power-domains = <&cpu_pd3>; 282 power-domain-names = "psci"; 283 next-level-cache = <&l2_300>; 284 operating-points-v2 = <&cpu0_opp_table>; 285 capacity-dmips-mhz = <1024>; 286 dynamic-power-coefficient = <100>; 287 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 288 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 289 qcom,freq-domain = <&cpufreq_hw 0>; 290 #cooling-cells = <2>; 291 l2_300: l2-cache { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-unified; 295 next-level-cache = <&l3_0>; 296 }; 297 }; 298 299 cpu4: cpu@400 { 300 device_type = "cpu"; 301 compatible = "qcom,kryo"; 302 reg = <0x0 0x400>; 303 clocks = <&cpufreq_hw 1>; 304 enable-method = "psci"; 305 power-domains = <&cpu_pd4>; 306 power-domain-names = "psci"; 307 next-level-cache = <&l2_400>; 308 operating-points-v2 = <&cpu4_opp_table>; 309 capacity-dmips-mhz = <1946>; 310 dynamic-power-coefficient = <520>; 311 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 312 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 313 qcom,freq-domain = <&cpufreq_hw 1>; 314 #cooling-cells = <2>; 315 l2_400: l2-cache { 316 compatible = "cache"; 317 cache-level = <2>; 318 cache-unified; 319 next-level-cache = <&l3_0>; 320 }; 321 }; 322 323 cpu5: cpu@500 { 324 device_type = "cpu"; 325 compatible = "qcom,kryo"; 326 reg = <0x0 0x500>; 327 clocks = <&cpufreq_hw 1>; 328 enable-method = "psci"; 329 power-domains = <&cpu_pd5>; 330 power-domain-names = "psci"; 331 next-level-cache = <&l2_500>; 332 operating-points-v2 = <&cpu4_opp_table>; 333 capacity-dmips-mhz = <1946>; 334 dynamic-power-coefficient = <520>; 335 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 336 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 337 qcom,freq-domain = <&cpufreq_hw 1>; 338 #cooling-cells = <2>; 339 l2_500: l2-cache { 340 compatible = "cache"; 341 cache-level = <2>; 342 cache-unified; 343 next-level-cache = <&l3_0>; 344 }; 345 }; 346 347 cpu6: cpu@600 { 348 device_type = "cpu"; 349 compatible = "qcom,kryo"; 350 reg = <0x0 0x600>; 351 clocks = <&cpufreq_hw 1>; 352 enable-method = "psci"; 353 power-domains = <&cpu_pd6>; 354 power-domain-names = "psci"; 355 next-level-cache = <&l2_600>; 356 operating-points-v2 = <&cpu4_opp_table>; 357 capacity-dmips-mhz = <1946>; 358 dynamic-power-coefficient = <520>; 359 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 360 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 361 qcom,freq-domain = <&cpufreq_hw 1>; 362 #cooling-cells = <2>; 363 l2_600: l2-cache { 364 compatible = "cache"; 365 cache-level = <2>; 366 cache-unified; 367 next-level-cache = <&l3_0>; 368 }; 369 }; 370 371 cpu7: cpu@700 { 372 device_type = "cpu"; 373 compatible = "qcom,kryo"; 374 reg = <0x0 0x700>; 375 clocks = <&cpufreq_hw 2>; 376 enable-method = "psci"; 377 power-domains = <&cpu_pd7>; 378 power-domain-names = "psci"; 379 next-level-cache = <&l2_700>; 380 operating-points-v2 = <&cpu7_opp_table>; 381 capacity-dmips-mhz = <1985>; 382 dynamic-power-coefficient = <552>; 383 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 384 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 385 qcom,freq-domain = <&cpufreq_hw 2>; 386 #cooling-cells = <2>; 387 l2_700: l2-cache { 388 compatible = "cache"; 389 cache-level = <2>; 390 cache-unified; 391 next-level-cache = <&l3_0>; 392 }; 393 }; 394 395 cpu-map { 396 cluster0 { 397 core0 { 398 cpu = <&cpu0>; 399 }; 400 401 core1 { 402 cpu = <&cpu1>; 403 }; 404 405 core2 { 406 cpu = <&cpu2>; 407 }; 408 409 core3 { 410 cpu = <&cpu3>; 411 }; 412 413 core4 { 414 cpu = <&cpu4>; 415 }; 416 417 core5 { 418 cpu = <&cpu5>; 419 }; 420 421 core6 { 422 cpu = <&cpu6>; 423 }; 424 425 core7 { 426 cpu = <&cpu7>; 427 }; 428 }; 429 }; 430 431 idle-states { 432 entry-method = "psci"; 433 434 little_cpu_sleep_0: cpu-sleep-0-0 { 435 compatible = "arm,idle-state"; 436 idle-state-name = "little-power-down"; 437 arm,psci-suspend-param = <0x40000003>; 438 entry-latency-us = <549>; 439 exit-latency-us = <901>; 440 min-residency-us = <1774>; 441 local-timer-stop; 442 }; 443 444 little_cpu_sleep_1: cpu-sleep-0-1 { 445 compatible = "arm,idle-state"; 446 idle-state-name = "little-rail-power-down"; 447 arm,psci-suspend-param = <0x40000004>; 448 entry-latency-us = <702>; 449 exit-latency-us = <915>; 450 min-residency-us = <4001>; 451 local-timer-stop; 452 }; 453 454 big_cpu_sleep_0: cpu-sleep-1-0 { 455 compatible = "arm,idle-state"; 456 idle-state-name = "big-power-down"; 457 arm,psci-suspend-param = <0x40000003>; 458 entry-latency-us = <523>; 459 exit-latency-us = <1244>; 460 min-residency-us = <2207>; 461 local-timer-stop; 462 }; 463 464 big_cpu_sleep_1: cpu-sleep-1-1 { 465 compatible = "arm,idle-state"; 466 idle-state-name = "big-rail-power-down"; 467 arm,psci-suspend-param = <0x40000004>; 468 entry-latency-us = <526>; 469 exit-latency-us = <1854>; 470 min-residency-us = <5555>; 471 local-timer-stop; 472 }; 473 }; 474 475 domain_idle_states: domain-idle-states { 476 cluster_sleep_apss_off: cluster-sleep-0 { 477 compatible = "domain-idle-state"; 478 arm,psci-suspend-param = <0x41000044>; 479 entry-latency-us = <2752>; 480 exit-latency-us = <3048>; 481 min-residency-us = <6118>; 482 }; 483 484 cluster_sleep_cx_ret: cluster-sleep-1 { 485 compatible = "domain-idle-state"; 486 arm,psci-suspend-param = <0x41001344>; 487 entry-latency-us = <3263>; 488 exit-latency-us = <4562>; 489 min-residency-us = <8467>; 490 }; 491 492 cluster_sleep_llcc_off: cluster-sleep-2 { 493 compatible = "domain-idle-state"; 494 arm,psci-suspend-param = <0x4100b344>; 495 entry-latency-us = <3638>; 496 exit-latency-us = <6562>; 497 min-residency-us = <9826>; 498 }; 499 }; 500 }; 501 502 cpu0_opp_table: opp-table-cpu0 { 503 compatible = "operating-points-v2"; 504 opp-shared; 505 506 cpu0_opp_300mhz: opp-300000000 { 507 opp-hz = /bits/ 64 <300000000>; 508 opp-peak-kBps = <800000 9600000>; 509 }; 510 511 cpu0_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <800000 17817600>; 514 }; 515 516 cpu0_opp_806mhz: opp-806400000 { 517 opp-hz = /bits/ 64 <806400000>; 518 opp-peak-kBps = <800000 20889600>; 519 }; 520 521 cpu0_opp_941mhz: opp-940800000 { 522 opp-hz = /bits/ 64 <940800000>; 523 opp-peak-kBps = <1804000 24576000>; 524 }; 525 526 cpu0_opp_1152mhz: opp-1152000000 { 527 opp-hz = /bits/ 64 <1152000000>; 528 opp-peak-kBps = <2188000 27033600>; 529 }; 530 531 cpu0_opp_1325mhz: opp-1324800000 { 532 opp-hz = /bits/ 64 <1324800000>; 533 opp-peak-kBps = <2188000 33792000>; 534 }; 535 536 cpu0_opp_1517mhz: opp-1516800000 { 537 opp-hz = /bits/ 64 <1516800000>; 538 opp-peak-kBps = <3072000 38092800>; 539 }; 540 541 cpu0_opp_1651mhz: opp-1651200000 { 542 opp-hz = /bits/ 64 <1651200000>; 543 opp-peak-kBps = <3072000 41779200>; 544 }; 545 546 cpu0_opp_1805mhz: opp-1804800000 { 547 opp-hz = /bits/ 64 <1804800000>; 548 opp-peak-kBps = <4068000 48537600>; 549 }; 550 551 cpu0_opp_1958mhz: opp-1958400000 { 552 opp-hz = /bits/ 64 <1958400000>; 553 opp-peak-kBps = <4068000 48537600>; 554 }; 555 556 cpu0_opp_2016mhz: opp-2016000000 { 557 opp-hz = /bits/ 64 <2016000000>; 558 opp-peak-kBps = <6220000 48537600>; 559 }; 560 }; 561 562 cpu4_opp_table: opp-table-cpu4 { 563 compatible = "operating-points-v2"; 564 opp-shared; 565 566 cpu4_opp_691mhz: opp-691200000 { 567 opp-hz = /bits/ 64 <691200000>; 568 opp-peak-kBps = <1804000 9600000>; 569 }; 570 571 cpu4_opp_941mhz: opp-940800000 { 572 opp-hz = /bits/ 64 <940800000>; 573 opp-peak-kBps = <2188000 17817600>; 574 }; 575 576 cpu4_opp_1229mhz: opp-1228800000 { 577 opp-hz = /bits/ 64 <1228800000>; 578 opp-peak-kBps = <4068000 24576000>; 579 }; 580 581 cpu4_opp_1344mhz: opp-1344000000 { 582 opp-hz = /bits/ 64 <1344000000>; 583 opp-peak-kBps = <4068000 24576000>; 584 }; 585 586 cpu4_opp_1517mhz: opp-1516800000 { 587 opp-hz = /bits/ 64 <1516800000>; 588 opp-peak-kBps = <4068000 24576000>; 589 }; 590 591 cpu4_opp_1651mhz: opp-1651200000 { 592 opp-hz = /bits/ 64 <1651200000>; 593 opp-peak-kBps = <6220000 38092800>; 594 }; 595 596 cpu4_opp_1901mhz: opp-1900800000 { 597 opp-hz = /bits/ 64 <1900800000>; 598 opp-peak-kBps = <6220000 44851200>; 599 }; 600 601 cpu4_opp_2054mhz: opp-2054400000 { 602 opp-hz = /bits/ 64 <2054400000>; 603 opp-peak-kBps = <6220000 44851200>; 604 }; 605 606 cpu4_opp_2112mhz: opp-2112000000 { 607 opp-hz = /bits/ 64 <2112000000>; 608 opp-peak-kBps = <6220000 44851200>; 609 }; 610 611 cpu4_opp_2131mhz: opp-2131200000 { 612 opp-hz = /bits/ 64 <2131200000>; 613 opp-peak-kBps = <6220000 44851200>; 614 }; 615 616 cpu4_opp_2208mhz: opp-2208000000 { 617 opp-hz = /bits/ 64 <2208000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu4_opp_2400mhz: opp-2400000000 { 622 opp-hz = /bits/ 64 <2400000000>; 623 opp-peak-kBps = <8532000 48537600>; 624 }; 625 626 cpu4_opp_2611mhz: opp-2611200000 { 627 opp-hz = /bits/ 64 <2611200000>; 628 opp-peak-kBps = <8532000 48537600>; 629 }; 630 }; 631 632 cpu7_opp_table: opp-table-cpu7 { 633 compatible = "operating-points-v2"; 634 opp-shared; 635 636 cpu7_opp_806mhz: opp-806400000 { 637 opp-hz = /bits/ 64 <806400000>; 638 opp-peak-kBps = <1804000 9600000>; 639 }; 640 641 cpu7_opp_1056mhz: opp-1056000000 { 642 opp-hz = /bits/ 64 <1056000000>; 643 opp-peak-kBps = <2188000 17817600>; 644 }; 645 646 cpu7_opp_1325mhz: opp-1324800000 { 647 opp-hz = /bits/ 64 <1324800000>; 648 opp-peak-kBps = <4068000 24576000>; 649 }; 650 651 cpu7_opp_1517mhz: opp-1516800000 { 652 opp-hz = /bits/ 64 <1516800000>; 653 opp-peak-kBps = <4068000 24576000>; 654 }; 655 656 cpu7_opp_1766mhz: opp-1766400000 { 657 opp-hz = /bits/ 64 <1766400000>; 658 opp-peak-kBps = <6220000 38092800>; 659 }; 660 661 cpu7_opp_1862mhz: opp-1862400000 { 662 opp-hz = /bits/ 64 <1862400000>; 663 opp-peak-kBps = <6220000 38092800>; 664 }; 665 666 cpu7_opp_2035mhz: opp-2035200000 { 667 opp-hz = /bits/ 64 <2035200000>; 668 opp-peak-kBps = <6220000 38092800>; 669 }; 670 671 cpu7_opp_2112mhz: opp-2112000000 { 672 opp-hz = /bits/ 64 <2112000000>; 673 opp-peak-kBps = <6220000 44851200>; 674 }; 675 676 cpu7_opp_2208mhz: opp-2208000000 { 677 opp-hz = /bits/ 64 <2208000000>; 678 opp-peak-kBps = <6220000 44851200>; 679 }; 680 681 cpu7_opp_2381mhz: opp-2380800000 { 682 opp-hz = /bits/ 64 <2380800000>; 683 opp-peak-kBps = <6832000 44851200>; 684 }; 685 686 cpu7_opp_2400mhz: opp-2400000000 { 687 opp-hz = /bits/ 64 <2400000000>; 688 opp-peak-kBps = <8532000 48537600>; 689 }; 690 691 cpu7_opp_2515mhz: opp-2515200000 { 692 opp-hz = /bits/ 64 <2515200000>; 693 opp-peak-kBps = <8532000 48537600>; 694 }; 695 696 cpu7_opp_2707mhz: opp-2707200000 { 697 opp-hz = /bits/ 64 <2707200000>; 698 opp-peak-kBps = <8532000 48537600>; 699 }; 700 701 cpu7_opp_3014mhz: opp-3014400000 { 702 opp-hz = /bits/ 64 <3014400000>; 703 opp-peak-kBps = <8532000 48537600>; 704 }; 705 }; 706 707 memory@80000000 { 708 device_type = "memory"; 709 /* We expect the bootloader to fill in the size */ 710 reg = <0 0x80000000 0 0>; 711 }; 712 713 firmware { 714 scm: scm { 715 compatible = "qcom,scm-sc7280", "qcom,scm"; 716 qcom,dload-mode = <&tcsr_2 0x13000>; 717 }; 718 }; 719 720 clk_virt: interconnect { 721 compatible = "qcom,sc7280-clk-virt"; 722 #interconnect-cells = <2>; 723 qcom,bcm-voters = <&apps_bcm_voter>; 724 }; 725 726 smem { 727 compatible = "qcom,smem"; 728 memory-region = <&smem_mem>; 729 hwlocks = <&tcsr_mutex 3>; 730 }; 731 732 smp2p-adsp { 733 compatible = "qcom,smp2p"; 734 qcom,smem = <443>, <429>; 735 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 736 IPCC_MPROC_SIGNAL_SMP2P 737 IRQ_TYPE_EDGE_RISING>; 738 mboxes = <&ipcc IPCC_CLIENT_LPASS 739 IPCC_MPROC_SIGNAL_SMP2P>; 740 741 qcom,local-pid = <0>; 742 qcom,remote-pid = <2>; 743 744 adsp_smp2p_out: master-kernel { 745 qcom,entry-name = "master-kernel"; 746 #qcom,smem-state-cells = <1>; 747 }; 748 749 adsp_smp2p_in: slave-kernel { 750 qcom,entry-name = "slave-kernel"; 751 interrupt-controller; 752 #interrupt-cells = <2>; 753 }; 754 }; 755 756 smp2p-cdsp { 757 compatible = "qcom,smp2p"; 758 qcom,smem = <94>, <432>; 759 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 760 IPCC_MPROC_SIGNAL_SMP2P 761 IRQ_TYPE_EDGE_RISING>; 762 mboxes = <&ipcc IPCC_CLIENT_CDSP 763 IPCC_MPROC_SIGNAL_SMP2P>; 764 765 qcom,local-pid = <0>; 766 qcom,remote-pid = <5>; 767 768 cdsp_smp2p_out: master-kernel { 769 qcom,entry-name = "master-kernel"; 770 #qcom,smem-state-cells = <1>; 771 }; 772 773 cdsp_smp2p_in: slave-kernel { 774 qcom,entry-name = "slave-kernel"; 775 interrupt-controller; 776 #interrupt-cells = <2>; 777 }; 778 }; 779 780 smp2p-mpss { 781 compatible = "qcom,smp2p"; 782 qcom,smem = <435>, <428>; 783 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 784 IPCC_MPROC_SIGNAL_SMP2P 785 IRQ_TYPE_EDGE_RISING>; 786 mboxes = <&ipcc IPCC_CLIENT_MPSS 787 IPCC_MPROC_SIGNAL_SMP2P>; 788 789 qcom,local-pid = <0>; 790 qcom,remote-pid = <1>; 791 792 modem_smp2p_out: master-kernel { 793 qcom,entry-name = "master-kernel"; 794 #qcom,smem-state-cells = <1>; 795 }; 796 797 modem_smp2p_in: slave-kernel { 798 qcom,entry-name = "slave-kernel"; 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 }; 802 803 ipa_smp2p_out: ipa-ap-to-modem { 804 qcom,entry-name = "ipa"; 805 #qcom,smem-state-cells = <1>; 806 }; 807 808 ipa_smp2p_in: ipa-modem-to-ap { 809 qcom,entry-name = "ipa"; 810 interrupt-controller; 811 #interrupt-cells = <2>; 812 }; 813 }; 814 815 smp2p-wpss { 816 compatible = "qcom,smp2p"; 817 qcom,smem = <617>, <616>; 818 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 819 IPCC_MPROC_SIGNAL_SMP2P 820 IRQ_TYPE_EDGE_RISING>; 821 mboxes = <&ipcc IPCC_CLIENT_WPSS 822 IPCC_MPROC_SIGNAL_SMP2P>; 823 824 qcom,local-pid = <0>; 825 qcom,remote-pid = <13>; 826 827 wpss_smp2p_out: master-kernel { 828 qcom,entry-name = "master-kernel"; 829 #qcom,smem-state-cells = <1>; 830 }; 831 832 wpss_smp2p_in: slave-kernel { 833 qcom,entry-name = "slave-kernel"; 834 interrupt-controller; 835 #interrupt-cells = <2>; 836 }; 837 838 wlan_smp2p_out: wlan-ap-to-wpss { 839 qcom,entry-name = "wlan"; 840 #qcom,smem-state-cells = <1>; 841 }; 842 843 wlan_smp2p_in: wlan-wpss-to-ap { 844 qcom,entry-name = "wlan"; 845 interrupt-controller; 846 #interrupt-cells = <2>; 847 }; 848 }; 849 850 pmu-a55 { 851 compatible = "arm,cortex-a55-pmu"; 852 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 853 }; 854 855 pmu-a78 { 856 compatible = "arm,cortex-a78-pmu"; 857 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 858 }; 859 860 psci { 861 compatible = "arm,psci-1.0"; 862 method = "smc"; 863 864 cpu_pd0: power-domain-cpu0 { 865 #power-domain-cells = <0>; 866 power-domains = <&cluster_pd>; 867 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 868 }; 869 870 cpu_pd1: power-domain-cpu1 { 871 #power-domain-cells = <0>; 872 power-domains = <&cluster_pd>; 873 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 874 }; 875 876 cpu_pd2: power-domain-cpu2 { 877 #power-domain-cells = <0>; 878 power-domains = <&cluster_pd>; 879 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 880 }; 881 882 cpu_pd3: power-domain-cpu3 { 883 #power-domain-cells = <0>; 884 power-domains = <&cluster_pd>; 885 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 886 }; 887 888 cpu_pd4: power-domain-cpu4 { 889 #power-domain-cells = <0>; 890 power-domains = <&cluster_pd>; 891 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 892 }; 893 894 cpu_pd5: power-domain-cpu5 { 895 #power-domain-cells = <0>; 896 power-domains = <&cluster_pd>; 897 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 898 }; 899 900 cpu_pd6: power-domain-cpu6 { 901 #power-domain-cells = <0>; 902 power-domains = <&cluster_pd>; 903 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 904 }; 905 906 cpu_pd7: power-domain-cpu7 { 907 #power-domain-cells = <0>; 908 power-domains = <&cluster_pd>; 909 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 910 }; 911 912 cluster_pd: power-domain-cluster { 913 #power-domain-cells = <0>; 914 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>; 915 }; 916 }; 917 918 qspi_opp_table: opp-table-qspi { 919 compatible = "operating-points-v2"; 920 921 opp-75000000 { 922 opp-hz = /bits/ 64 <75000000>; 923 required-opps = <&rpmhpd_opp_low_svs>; 924 }; 925 926 opp-150000000 { 927 opp-hz = /bits/ 64 <150000000>; 928 required-opps = <&rpmhpd_opp_svs>; 929 }; 930 931 opp-200000000 { 932 opp-hz = /bits/ 64 <200000000>; 933 required-opps = <&rpmhpd_opp_svs_l1>; 934 }; 935 936 opp-300000000 { 937 opp-hz = /bits/ 64 <300000000>; 938 required-opps = <&rpmhpd_opp_nom>; 939 }; 940 }; 941 942 qup_opp_table: opp-table-qup { 943 compatible = "operating-points-v2"; 944 945 opp-75000000 { 946 opp-hz = /bits/ 64 <75000000>; 947 required-opps = <&rpmhpd_opp_low_svs>; 948 }; 949 950 opp-100000000 { 951 opp-hz = /bits/ 64 <100000000>; 952 required-opps = <&rpmhpd_opp_svs>; 953 }; 954 955 opp-128000000 { 956 opp-hz = /bits/ 64 <128000000>; 957 required-opps = <&rpmhpd_opp_nom>; 958 }; 959 }; 960 961 soc: soc@0 { 962 #address-cells = <2>; 963 #size-cells = <2>; 964 ranges = <0 0 0 0 0x10 0>; 965 dma-ranges = <0 0 0 0 0x10 0>; 966 compatible = "simple-bus"; 967 968 gcc: clock-controller@100000 { 969 compatible = "qcom,gcc-sc7280"; 970 reg = <0 0x00100000 0 0x1f0000>; 971 clocks = <&rpmhcc RPMH_CXO_CLK>, 972 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 973 <0>, <&pcie1_phy>, 974 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 975 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 976 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 977 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 978 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 979 "ufs_phy_tx_symbol_0_clk", 980 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 981 #clock-cells = <1>; 982 #reset-cells = <1>; 983 #power-domain-cells = <1>; 984 power-domains = <&rpmhpd SC7280_CX>; 985 }; 986 987 ipcc: mailbox@408000 { 988 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 989 reg = <0 0x00408000 0 0x1000>; 990 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 991 interrupt-controller; 992 #interrupt-cells = <3>; 993 #mbox-cells = <2>; 994 }; 995 996 qfprom: efuse@784000 { 997 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 998 reg = <0 0x00784000 0 0xa20>, 999 <0 0x00780000 0 0xa20>, 1000 <0 0x00782000 0 0x120>, 1001 <0 0x00786000 0 0x1fff>; 1002 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 1003 clock-names = "core"; 1004 power-domains = <&rpmhpd SC7280_MX>; 1005 #address-cells = <1>; 1006 #size-cells = <1>; 1007 1008 gpu_speed_bin: gpu-speed-bin@1e9 { 1009 reg = <0x1e9 0x2>; 1010 bits = <5 8>; 1011 }; 1012 }; 1013 1014 sdhc_1: mmc@7c4000 { 1015 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1016 pinctrl-names = "default", "sleep"; 1017 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1018 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1019 status = "disabled"; 1020 1021 reg = <0 0x007c4000 0 0x1000>, 1022 <0 0x007c5000 0 0x1000>; 1023 reg-names = "hc", "cqhci"; 1024 1025 iommus = <&apps_smmu 0xc0 0x0>; 1026 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1028 interrupt-names = "hc_irq", "pwr_irq"; 1029 1030 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1031 <&gcc GCC_SDCC1_APPS_CLK>, 1032 <&rpmhcc RPMH_CXO_CLK>; 1033 clock-names = "iface", "core", "xo"; 1034 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1035 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1036 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1037 power-domains = <&rpmhpd SC7280_CX>; 1038 operating-points-v2 = <&sdhc1_opp_table>; 1039 1040 bus-width = <8>; 1041 supports-cqe; 1042 dma-coherent; 1043 1044 qcom,dll-config = <0x0007642c>; 1045 qcom,ddr-config = <0x80040868>; 1046 1047 mmc-ddr-1_8v; 1048 mmc-hs200-1_8v; 1049 mmc-hs400-1_8v; 1050 mmc-hs400-enhanced-strobe; 1051 1052 resets = <&gcc GCC_SDCC1_BCR>; 1053 1054 sdhc1_opp_table: opp-table { 1055 compatible = "operating-points-v2"; 1056 1057 opp-100000000 { 1058 opp-hz = /bits/ 64 <100000000>; 1059 required-opps = <&rpmhpd_opp_low_svs>; 1060 opp-peak-kBps = <1800000 400000>; 1061 opp-avg-kBps = <100000 0>; 1062 }; 1063 1064 opp-384000000 { 1065 opp-hz = /bits/ 64 <384000000>; 1066 required-opps = <&rpmhpd_opp_nom>; 1067 opp-peak-kBps = <5400000 1600000>; 1068 opp-avg-kBps = <390000 0>; 1069 }; 1070 }; 1071 }; 1072 1073 gpi_dma0: dma-controller@900000 { 1074 #dma-cells = <3>; 1075 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1076 reg = <0 0x00900000 0 0x60000>; 1077 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1089 dma-channels = <12>; 1090 dma-channel-mask = <0x7f>; 1091 iommus = <&apps_smmu 0x0136 0x0>; 1092 status = "disabled"; 1093 }; 1094 1095 qupv3_id_0: geniqup@9c0000 { 1096 compatible = "qcom,geni-se-qup"; 1097 reg = <0 0x009c0000 0 0x2000>; 1098 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1099 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1100 clock-names = "m-ahb", "s-ahb"; 1101 #address-cells = <2>; 1102 #size-cells = <2>; 1103 ranges; 1104 iommus = <&apps_smmu 0x123 0x0>; 1105 status = "disabled"; 1106 1107 i2c0: i2c@980000 { 1108 compatible = "qcom,geni-i2c"; 1109 reg = <0 0x00980000 0 0x4000>; 1110 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1111 clock-names = "se"; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&qup_i2c0_data_clk>; 1114 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1118 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1119 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1120 interconnect-names = "qup-core", "qup-config", 1121 "qup-memory"; 1122 power-domains = <&rpmhpd SC7280_CX>; 1123 required-opps = <&rpmhpd_opp_low_svs>; 1124 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1125 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1126 dma-names = "tx", "rx"; 1127 status = "disabled"; 1128 }; 1129 1130 spi0: spi@980000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00980000 0 0x4000>; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1134 clock-names = "se"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1137 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 power-domains = <&rpmhpd SC7280_CX>; 1141 operating-points-v2 = <&qup_opp_table>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1143 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1144 interconnect-names = "qup-core", "qup-config"; 1145 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1146 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1147 dma-names = "tx", "rx"; 1148 status = "disabled"; 1149 }; 1150 1151 uart0: serial@980000 { 1152 compatible = "qcom,geni-uart"; 1153 reg = <0 0x00980000 0 0x4000>; 1154 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1155 clock-names = "se"; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1158 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1159 power-domains = <&rpmhpd SC7280_CX>; 1160 operating-points-v2 = <&qup_opp_table>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1162 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1163 interconnect-names = "qup-core", "qup-config"; 1164 status = "disabled"; 1165 }; 1166 1167 i2c1: i2c@984000 { 1168 compatible = "qcom,geni-i2c"; 1169 reg = <0 0x00984000 0 0x4000>; 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1171 clock-names = "se"; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&qup_i2c1_data_clk>; 1174 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1178 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1179 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1180 interconnect-names = "qup-core", "qup-config", 1181 "qup-memory"; 1182 power-domains = <&rpmhpd SC7280_CX>; 1183 required-opps = <&rpmhpd_opp_low_svs>; 1184 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1185 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1186 dma-names = "tx", "rx"; 1187 status = "disabled"; 1188 }; 1189 1190 spi1: spi@984000 { 1191 compatible = "qcom,geni-spi"; 1192 reg = <0 0x00984000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1194 clock-names = "se"; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1197 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 power-domains = <&rpmhpd SC7280_CX>; 1201 operating-points-v2 = <&qup_opp_table>; 1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1203 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1204 interconnect-names = "qup-core", "qup-config"; 1205 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1206 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1207 dma-names = "tx", "rx"; 1208 status = "disabled"; 1209 }; 1210 1211 uart1: serial@984000 { 1212 compatible = "qcom,geni-uart"; 1213 reg = <0 0x00984000 0 0x4000>; 1214 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1215 clock-names = "se"; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1218 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1219 power-domains = <&rpmhpd SC7280_CX>; 1220 operating-points-v2 = <&qup_opp_table>; 1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1222 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1223 interconnect-names = "qup-core", "qup-config"; 1224 status = "disabled"; 1225 }; 1226 1227 i2c2: i2c@988000 { 1228 compatible = "qcom,geni-i2c"; 1229 reg = <0 0x00988000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_i2c2_data_clk>; 1234 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1239 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1240 interconnect-names = "qup-core", "qup-config", 1241 "qup-memory"; 1242 power-domains = <&rpmhpd SC7280_CX>; 1243 required-opps = <&rpmhpd_opp_low_svs>; 1244 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1245 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1246 dma-names = "tx", "rx"; 1247 status = "disabled"; 1248 }; 1249 1250 spi2: spi@988000 { 1251 compatible = "qcom,geni-spi"; 1252 reg = <0 0x00988000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1254 clock-names = "se"; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1257 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 power-domains = <&rpmhpd SC7280_CX>; 1261 operating-points-v2 = <&qup_opp_table>; 1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1263 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1264 interconnect-names = "qup-core", "qup-config"; 1265 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1266 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1267 dma-names = "tx", "rx"; 1268 status = "disabled"; 1269 }; 1270 1271 uart2: serial@988000 { 1272 compatible = "qcom,geni-uart"; 1273 reg = <0 0x00988000 0 0x4000>; 1274 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1275 clock-names = "se"; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1278 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1279 power-domains = <&rpmhpd SC7280_CX>; 1280 operating-points-v2 = <&qup_opp_table>; 1281 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1282 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1283 interconnect-names = "qup-core", "qup-config"; 1284 status = "disabled"; 1285 }; 1286 1287 i2c3: i2c@98c000 { 1288 compatible = "qcom,geni-i2c"; 1289 reg = <0 0x0098c000 0 0x4000>; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1291 clock-names = "se"; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_i2c3_data_clk>; 1294 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1299 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1300 interconnect-names = "qup-core", "qup-config", 1301 "qup-memory"; 1302 power-domains = <&rpmhpd SC7280_CX>; 1303 required-opps = <&rpmhpd_opp_low_svs>; 1304 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1305 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1306 dma-names = "tx", "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 spi3: spi@98c000 { 1311 compatible = "qcom,geni-spi"; 1312 reg = <0 0x0098c000 0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1314 clock-names = "se"; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1317 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 power-domains = <&rpmhpd SC7280_CX>; 1321 operating-points-v2 = <&qup_opp_table>; 1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1323 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1324 interconnect-names = "qup-core", "qup-config"; 1325 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1326 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1327 dma-names = "tx", "rx"; 1328 status = "disabled"; 1329 }; 1330 1331 uart3: serial@98c000 { 1332 compatible = "qcom,geni-uart"; 1333 reg = <0 0x0098c000 0 0x4000>; 1334 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1335 clock-names = "se"; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1338 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1339 power-domains = <&rpmhpd SC7280_CX>; 1340 operating-points-v2 = <&qup_opp_table>; 1341 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1342 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1343 interconnect-names = "qup-core", "qup-config"; 1344 status = "disabled"; 1345 }; 1346 1347 i2c4: i2c@990000 { 1348 compatible = "qcom,geni-i2c"; 1349 reg = <0 0x00990000 0 0x4000>; 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1351 clock-names = "se"; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_i2c4_data_clk>; 1354 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1358 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1359 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1360 interconnect-names = "qup-core", "qup-config", 1361 "qup-memory"; 1362 power-domains = <&rpmhpd SC7280_CX>; 1363 required-opps = <&rpmhpd_opp_low_svs>; 1364 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1365 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1366 dma-names = "tx", "rx"; 1367 status = "disabled"; 1368 }; 1369 1370 spi4: spi@990000 { 1371 compatible = "qcom,geni-spi"; 1372 reg = <0 0x00990000 0 0x4000>; 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1374 clock-names = "se"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1377 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 power-domains = <&rpmhpd SC7280_CX>; 1381 operating-points-v2 = <&qup_opp_table>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1383 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1384 interconnect-names = "qup-core", "qup-config"; 1385 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1386 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1387 dma-names = "tx", "rx"; 1388 status = "disabled"; 1389 }; 1390 1391 uart4: serial@990000 { 1392 compatible = "qcom,geni-uart"; 1393 reg = <0 0x00990000 0 0x4000>; 1394 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1395 clock-names = "se"; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1398 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1399 power-domains = <&rpmhpd SC7280_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1402 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1403 interconnect-names = "qup-core", "qup-config"; 1404 status = "disabled"; 1405 }; 1406 1407 i2c5: i2c@994000 { 1408 compatible = "qcom,geni-i2c"; 1409 reg = <0 0x00994000 0 0x4000>; 1410 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1411 clock-names = "se"; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_i2c5_data_clk>; 1414 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1418 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1419 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1420 interconnect-names = "qup-core", "qup-config", 1421 "qup-memory"; 1422 power-domains = <&rpmhpd SC7280_CX>; 1423 required-opps = <&rpmhpd_opp_low_svs>; 1424 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1425 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1426 dma-names = "tx", "rx"; 1427 status = "disabled"; 1428 }; 1429 1430 spi5: spi@994000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00994000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1437 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 power-domains = <&rpmhpd SC7280_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1443 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1446 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1447 dma-names = "tx", "rx"; 1448 status = "disabled"; 1449 }; 1450 1451 uart5: serial@994000 { 1452 compatible = "qcom,geni-debug-uart"; 1453 reg = <0 0x00994000 0 0x4000>; 1454 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1455 clock-names = "se"; 1456 pinctrl-names = "default"; 1457 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; 1458 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1459 power-domains = <&rpmhpd SC7280_CX>; 1460 operating-points-v2 = <&qup_opp_table>; 1461 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1462 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1463 interconnect-names = "qup-core", "qup-config"; 1464 status = "disabled"; 1465 }; 1466 1467 i2c6: i2c@998000 { 1468 compatible = "qcom,geni-i2c"; 1469 reg = <0 0x00998000 0 0x4000>; 1470 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1471 clock-names = "se"; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&qup_i2c6_data_clk>; 1474 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1478 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1479 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1480 interconnect-names = "qup-core", "qup-config", 1481 "qup-memory"; 1482 power-domains = <&rpmhpd SC7280_CX>; 1483 required-opps = <&rpmhpd_opp_low_svs>; 1484 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1485 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1486 dma-names = "tx", "rx"; 1487 status = "disabled"; 1488 }; 1489 1490 spi6: spi@998000 { 1491 compatible = "qcom,geni-spi"; 1492 reg = <0 0x00998000 0 0x4000>; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1494 clock-names = "se"; 1495 pinctrl-names = "default"; 1496 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1497 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 power-domains = <&rpmhpd SC7280_CX>; 1501 operating-points-v2 = <&qup_opp_table>; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1503 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1504 interconnect-names = "qup-core", "qup-config"; 1505 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1506 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1507 dma-names = "tx", "rx"; 1508 status = "disabled"; 1509 }; 1510 1511 uart6: serial@998000 { 1512 compatible = "qcom,geni-uart"; 1513 reg = <0 0x00998000 0 0x4000>; 1514 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1515 clock-names = "se"; 1516 pinctrl-names = "default"; 1517 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1518 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1519 power-domains = <&rpmhpd SC7280_CX>; 1520 operating-points-v2 = <&qup_opp_table>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1523 interconnect-names = "qup-core", "qup-config"; 1524 status = "disabled"; 1525 }; 1526 1527 i2c7: i2c@99c000 { 1528 compatible = "qcom,geni-i2c"; 1529 reg = <0 0x0099c000 0 0x4000>; 1530 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1531 clock-names = "se"; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_i2c7_data_clk>; 1534 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1538 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1539 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1540 interconnect-names = "qup-core", "qup-config", 1541 "qup-memory"; 1542 power-domains = <&rpmhpd SC7280_CX>; 1543 required-opps = <&rpmhpd_opp_low_svs>; 1544 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1545 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1546 dma-names = "tx", "rx"; 1547 status = "disabled"; 1548 }; 1549 1550 spi7: spi@99c000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0 0x0099c000 0 0x4000>; 1553 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1554 clock-names = "se"; 1555 pinctrl-names = "default"; 1556 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1557 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 power-domains = <&rpmhpd SC7280_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1564 interconnect-names = "qup-core", "qup-config"; 1565 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1566 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1567 dma-names = "tx", "rx"; 1568 status = "disabled"; 1569 }; 1570 1571 uart7: serial@99c000 { 1572 compatible = "qcom,geni-uart"; 1573 reg = <0 0x0099c000 0 0x4000>; 1574 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1575 clock-names = "se"; 1576 pinctrl-names = "default"; 1577 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1578 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1579 power-domains = <&rpmhpd SC7280_CX>; 1580 operating-points-v2 = <&qup_opp_table>; 1581 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1582 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1583 interconnect-names = "qup-core", "qup-config"; 1584 status = "disabled"; 1585 }; 1586 }; 1587 1588 gpi_dma1: dma-controller@a00000 { 1589 #dma-cells = <3>; 1590 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1591 reg = <0 0x00a00000 0 0x60000>; 1592 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1604 dma-channels = <12>; 1605 dma-channel-mask = <0x1e>; 1606 iommus = <&apps_smmu 0x56 0x0>; 1607 status = "disabled"; 1608 }; 1609 1610 qupv3_id_1: geniqup@ac0000 { 1611 compatible = "qcom,geni-se-qup"; 1612 reg = <0 0x00ac0000 0 0x2000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1614 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1615 clock-names = "m-ahb", "s-ahb"; 1616 #address-cells = <2>; 1617 #size-cells = <2>; 1618 ranges; 1619 iommus = <&apps_smmu 0x43 0x0>; 1620 status = "disabled"; 1621 1622 i2c8: i2c@a80000 { 1623 compatible = "qcom,geni-i2c"; 1624 reg = <0 0x00a80000 0 0x4000>; 1625 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1626 clock-names = "se"; 1627 pinctrl-names = "default"; 1628 pinctrl-0 = <&qup_i2c8_data_clk>; 1629 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1633 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1634 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1635 interconnect-names = "qup-core", "qup-config", 1636 "qup-memory"; 1637 power-domains = <&rpmhpd SC7280_CX>; 1638 required-opps = <&rpmhpd_opp_low_svs>; 1639 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1640 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1641 dma-names = "tx", "rx"; 1642 status = "disabled"; 1643 }; 1644 1645 spi8: spi@a80000 { 1646 compatible = "qcom,geni-spi"; 1647 reg = <0 0x00a80000 0 0x4000>; 1648 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1649 clock-names = "se"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1652 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 power-domains = <&rpmhpd SC7280_CX>; 1656 operating-points-v2 = <&qup_opp_table>; 1657 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1658 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1659 interconnect-names = "qup-core", "qup-config"; 1660 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1661 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1662 dma-names = "tx", "rx"; 1663 status = "disabled"; 1664 }; 1665 1666 uart8: serial@a80000 { 1667 compatible = "qcom,geni-uart"; 1668 reg = <0 0x00a80000 0 0x4000>; 1669 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1670 clock-names = "se"; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1673 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1674 power-domains = <&rpmhpd SC7280_CX>; 1675 operating-points-v2 = <&qup_opp_table>; 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1677 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1678 interconnect-names = "qup-core", "qup-config"; 1679 status = "disabled"; 1680 }; 1681 1682 i2c9: i2c@a84000 { 1683 compatible = "qcom,geni-i2c"; 1684 reg = <0 0x00a84000 0 0x4000>; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1686 clock-names = "se"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_i2c9_data_clk>; 1689 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1694 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1695 interconnect-names = "qup-core", "qup-config", 1696 "qup-memory"; 1697 power-domains = <&rpmhpd SC7280_CX>; 1698 required-opps = <&rpmhpd_opp_low_svs>; 1699 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1700 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 spi9: spi@a84000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00a84000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1712 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 power-domains = <&rpmhpd SC7280_CX>; 1716 operating-points-v2 = <&qup_opp_table>; 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1721 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1722 dma-names = "tx", "rx"; 1723 status = "disabled"; 1724 }; 1725 1726 uart9: serial@a84000 { 1727 compatible = "qcom,geni-uart"; 1728 reg = <0 0x00a84000 0 0x4000>; 1729 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1730 clock-names = "se"; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1733 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1734 power-domains = <&rpmhpd SC7280_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1737 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1738 interconnect-names = "qup-core", "qup-config"; 1739 status = "disabled"; 1740 }; 1741 1742 i2c10: i2c@a88000 { 1743 compatible = "qcom,geni-i2c"; 1744 reg = <0 0x00a88000 0 0x4000>; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1746 clock-names = "se"; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_i2c10_data_clk>; 1749 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1755 interconnect-names = "qup-core", "qup-config", 1756 "qup-memory"; 1757 power-domains = <&rpmhpd SC7280_CX>; 1758 required-opps = <&rpmhpd_opp_low_svs>; 1759 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1760 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1761 dma-names = "tx", "rx"; 1762 status = "disabled"; 1763 }; 1764 1765 spi10: spi@a88000 { 1766 compatible = "qcom,geni-spi"; 1767 reg = <0 0x00a88000 0 0x4000>; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1769 clock-names = "se"; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1772 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 power-domains = <&rpmhpd SC7280_CX>; 1776 operating-points-v2 = <&qup_opp_table>; 1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1778 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1779 interconnect-names = "qup-core", "qup-config"; 1780 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1781 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1782 dma-names = "tx", "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 uart10: serial@a88000 { 1787 compatible = "qcom,geni-uart"; 1788 reg = <0 0x00a88000 0 0x4000>; 1789 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1790 clock-names = "se"; 1791 pinctrl-names = "default"; 1792 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1793 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1794 power-domains = <&rpmhpd SC7280_CX>; 1795 operating-points-v2 = <&qup_opp_table>; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1798 interconnect-names = "qup-core", "qup-config"; 1799 status = "disabled"; 1800 }; 1801 1802 i2c11: i2c@a8c000 { 1803 compatible = "qcom,geni-i2c"; 1804 reg = <0 0x00a8c000 0 0x4000>; 1805 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1806 clock-names = "se"; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&qup_i2c11_data_clk>; 1809 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1813 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1814 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1815 interconnect-names = "qup-core", "qup-config", 1816 "qup-memory"; 1817 power-domains = <&rpmhpd SC7280_CX>; 1818 required-opps = <&rpmhpd_opp_low_svs>; 1819 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1820 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1821 dma-names = "tx", "rx"; 1822 status = "disabled"; 1823 }; 1824 1825 spi11: spi@a8c000 { 1826 compatible = "qcom,geni-spi"; 1827 reg = <0 0x00a8c000 0 0x4000>; 1828 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1829 clock-names = "se"; 1830 pinctrl-names = "default"; 1831 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1832 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 power-domains = <&rpmhpd SC7280_CX>; 1836 operating-points-v2 = <&qup_opp_table>; 1837 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1838 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1839 interconnect-names = "qup-core", "qup-config"; 1840 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1841 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1842 dma-names = "tx", "rx"; 1843 status = "disabled"; 1844 }; 1845 1846 uart11: serial@a8c000 { 1847 compatible = "qcom,geni-uart"; 1848 reg = <0 0x00a8c000 0 0x4000>; 1849 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1850 clock-names = "se"; 1851 pinctrl-names = "default"; 1852 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1853 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1854 power-domains = <&rpmhpd SC7280_CX>; 1855 operating-points-v2 = <&qup_opp_table>; 1856 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1857 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1858 interconnect-names = "qup-core", "qup-config"; 1859 status = "disabled"; 1860 }; 1861 1862 i2c12: i2c@a90000 { 1863 compatible = "qcom,geni-i2c"; 1864 reg = <0 0x00a90000 0 0x4000>; 1865 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1866 clock-names = "se"; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_i2c12_data_clk>; 1869 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1873 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1874 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1875 interconnect-names = "qup-core", "qup-config", 1876 "qup-memory"; 1877 power-domains = <&rpmhpd SC7280_CX>; 1878 required-opps = <&rpmhpd_opp_low_svs>; 1879 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1880 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1881 dma-names = "tx", "rx"; 1882 status = "disabled"; 1883 }; 1884 1885 spi12: spi@a90000 { 1886 compatible = "qcom,geni-spi"; 1887 reg = <0 0x00a90000 0 0x4000>; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1889 clock-names = "se"; 1890 pinctrl-names = "default"; 1891 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1892 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1893 #address-cells = <1>; 1894 #size-cells = <0>; 1895 power-domains = <&rpmhpd SC7280_CX>; 1896 operating-points-v2 = <&qup_opp_table>; 1897 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1898 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1899 interconnect-names = "qup-core", "qup-config"; 1900 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1901 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1902 dma-names = "tx", "rx"; 1903 status = "disabled"; 1904 }; 1905 1906 uart12: serial@a90000 { 1907 compatible = "qcom,geni-uart"; 1908 reg = <0 0x00a90000 0 0x4000>; 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1910 clock-names = "se"; 1911 pinctrl-names = "default"; 1912 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1913 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1914 power-domains = <&rpmhpd SC7280_CX>; 1915 operating-points-v2 = <&qup_opp_table>; 1916 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1917 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1918 interconnect-names = "qup-core", "qup-config"; 1919 status = "disabled"; 1920 }; 1921 1922 i2c13: i2c@a94000 { 1923 compatible = "qcom,geni-i2c"; 1924 reg = <0 0x00a94000 0 0x4000>; 1925 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1926 clock-names = "se"; 1927 pinctrl-names = "default"; 1928 pinctrl-0 = <&qup_i2c13_data_clk>; 1929 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1933 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1934 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1935 interconnect-names = "qup-core", "qup-config", 1936 "qup-memory"; 1937 power-domains = <&rpmhpd SC7280_CX>; 1938 required-opps = <&rpmhpd_opp_low_svs>; 1939 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1940 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1941 dma-names = "tx", "rx"; 1942 status = "disabled"; 1943 }; 1944 1945 spi13: spi@a94000 { 1946 compatible = "qcom,geni-spi"; 1947 reg = <0 0x00a94000 0 0x4000>; 1948 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1949 clock-names = "se"; 1950 pinctrl-names = "default"; 1951 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1952 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1953 #address-cells = <1>; 1954 #size-cells = <0>; 1955 power-domains = <&rpmhpd SC7280_CX>; 1956 operating-points-v2 = <&qup_opp_table>; 1957 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1958 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1959 interconnect-names = "qup-core", "qup-config"; 1960 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1961 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1962 dma-names = "tx", "rx"; 1963 status = "disabled"; 1964 }; 1965 1966 uart13: serial@a94000 { 1967 compatible = "qcom,geni-uart"; 1968 reg = <0 0x00a94000 0 0x4000>; 1969 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1970 clock-names = "se"; 1971 pinctrl-names = "default"; 1972 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1973 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1974 power-domains = <&rpmhpd SC7280_CX>; 1975 operating-points-v2 = <&qup_opp_table>; 1976 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1978 interconnect-names = "qup-core", "qup-config"; 1979 status = "disabled"; 1980 }; 1981 1982 i2c14: i2c@a98000 { 1983 compatible = "qcom,geni-i2c"; 1984 reg = <0 0x00a98000 0 0x4000>; 1985 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1986 clock-names = "se"; 1987 pinctrl-names = "default"; 1988 pinctrl-0 = <&qup_i2c14_data_clk>; 1989 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1990 #address-cells = <1>; 1991 #size-cells = <0>; 1992 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1994 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1995 interconnect-names = "qup-core", "qup-config", 1996 "qup-memory"; 1997 power-domains = <&rpmhpd SC7280_CX>; 1998 required-opps = <&rpmhpd_opp_low_svs>; 1999 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2000 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2001 dma-names = "tx", "rx"; 2002 status = "disabled"; 2003 }; 2004 2005 spi14: spi@a98000 { 2006 compatible = "qcom,geni-spi"; 2007 reg = <0 0x00a98000 0 0x4000>; 2008 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2009 clock-names = "se"; 2010 pinctrl-names = "default"; 2011 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2012 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2013 #address-cells = <1>; 2014 #size-cells = <0>; 2015 power-domains = <&rpmhpd SC7280_CX>; 2016 operating-points-v2 = <&qup_opp_table>; 2017 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2018 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2019 interconnect-names = "qup-core", "qup-config"; 2020 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2021 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2022 dma-names = "tx", "rx"; 2023 status = "disabled"; 2024 }; 2025 2026 uart14: serial@a98000 { 2027 compatible = "qcom,geni-uart"; 2028 reg = <0 0x00a98000 0 0x4000>; 2029 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2030 clock-names = "se"; 2031 pinctrl-names = "default"; 2032 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2033 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2034 power-domains = <&rpmhpd SC7280_CX>; 2035 operating-points-v2 = <&qup_opp_table>; 2036 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2038 interconnect-names = "qup-core", "qup-config"; 2039 status = "disabled"; 2040 }; 2041 2042 i2c15: i2c@a9c000 { 2043 compatible = "qcom,geni-i2c"; 2044 reg = <0 0x00a9c000 0 0x4000>; 2045 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2046 clock-names = "se"; 2047 pinctrl-names = "default"; 2048 pinctrl-0 = <&qup_i2c15_data_clk>; 2049 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2050 #address-cells = <1>; 2051 #size-cells = <0>; 2052 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2053 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2054 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2055 interconnect-names = "qup-core", "qup-config", 2056 "qup-memory"; 2057 power-domains = <&rpmhpd SC7280_CX>; 2058 required-opps = <&rpmhpd_opp_low_svs>; 2059 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2060 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2061 dma-names = "tx", "rx"; 2062 status = "disabled"; 2063 }; 2064 2065 spi15: spi@a9c000 { 2066 compatible = "qcom,geni-spi"; 2067 reg = <0 0x00a9c000 0 0x4000>; 2068 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2069 clock-names = "se"; 2070 pinctrl-names = "default"; 2071 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2072 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 power-domains = <&rpmhpd SC7280_CX>; 2076 operating-points-v2 = <&qup_opp_table>; 2077 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2078 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2079 interconnect-names = "qup-core", "qup-config"; 2080 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2081 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2082 dma-names = "tx", "rx"; 2083 status = "disabled"; 2084 }; 2085 2086 uart15: serial@a9c000 { 2087 compatible = "qcom,geni-uart"; 2088 reg = <0 0x00a9c000 0 0x4000>; 2089 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2090 clock-names = "se"; 2091 pinctrl-names = "default"; 2092 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2093 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2094 power-domains = <&rpmhpd SC7280_CX>; 2095 operating-points-v2 = <&qup_opp_table>; 2096 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2098 interconnect-names = "qup-core", "qup-config"; 2099 status = "disabled"; 2100 }; 2101 }; 2102 2103 rng: rng@10d3000 { 2104 compatible = "qcom,sc7280-trng", "qcom,trng"; 2105 reg = <0 0x010d3000 0 0x1000>; 2106 }; 2107 2108 cnoc2: interconnect@1500000 { 2109 reg = <0 0x01500000 0 0x1000>; 2110 compatible = "qcom,sc7280-cnoc2"; 2111 #interconnect-cells = <2>; 2112 qcom,bcm-voters = <&apps_bcm_voter>; 2113 }; 2114 2115 cnoc3: interconnect@1502000 { 2116 reg = <0 0x01502000 0 0x1000>; 2117 compatible = "qcom,sc7280-cnoc3"; 2118 #interconnect-cells = <2>; 2119 qcom,bcm-voters = <&apps_bcm_voter>; 2120 }; 2121 2122 mc_virt: interconnect@1580000 { 2123 reg = <0 0x01580000 0 0x4>; 2124 compatible = "qcom,sc7280-mc-virt"; 2125 #interconnect-cells = <2>; 2126 qcom,bcm-voters = <&apps_bcm_voter>; 2127 }; 2128 2129 system_noc: interconnect@1680000 { 2130 reg = <0 0x01680000 0 0x15480>; 2131 compatible = "qcom,sc7280-system-noc"; 2132 #interconnect-cells = <2>; 2133 qcom,bcm-voters = <&apps_bcm_voter>; 2134 }; 2135 2136 aggre1_noc: interconnect@16e0000 { 2137 compatible = "qcom,sc7280-aggre1-noc"; 2138 reg = <0 0x016e0000 0 0x1c080>; 2139 #interconnect-cells = <2>; 2140 qcom,bcm-voters = <&apps_bcm_voter>; 2141 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2142 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2143 }; 2144 2145 aggre2_noc: interconnect@1700000 { 2146 reg = <0 0x01700000 0 0x2b080>; 2147 compatible = "qcom,sc7280-aggre2-noc"; 2148 #interconnect-cells = <2>; 2149 qcom,bcm-voters = <&apps_bcm_voter>; 2150 clocks = <&rpmhcc RPMH_IPA_CLK>; 2151 }; 2152 2153 mmss_noc: interconnect@1740000 { 2154 reg = <0 0x01740000 0 0x1e080>; 2155 compatible = "qcom,sc7280-mmss-noc"; 2156 #interconnect-cells = <2>; 2157 qcom,bcm-voters = <&apps_bcm_voter>; 2158 }; 2159 2160 wifi: wifi@17a10040 { 2161 compatible = "qcom,wcn6750-wifi"; 2162 reg = <0 0x17a10040 0 0x0>; 2163 iommus = <&apps_smmu 0x1c00 0x1>; 2164 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2165 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2166 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2184 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2185 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2186 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2187 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2189 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2190 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2191 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2192 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2193 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2194 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2195 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2196 qcom,rproc = <&remoteproc_wpss>; 2197 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2198 status = "disabled"; 2199 qcom,smem-states = <&wlan_smp2p_out 0>; 2200 qcom,smem-state-names = "wlan-smp2p-out"; 2201 }; 2202 2203 pcie1: pcie@1c08000 { 2204 compatible = "qcom,pcie-sc7280"; 2205 reg = <0 0x01c08000 0 0x3000>, 2206 <0 0x40000000 0 0xf1d>, 2207 <0 0x40000f20 0 0xa8>, 2208 <0 0x40001000 0 0x1000>, 2209 <0 0x40100000 0 0x100000>; 2210 2211 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2212 device_type = "pci"; 2213 linux,pci-domain = <1>; 2214 bus-range = <0x00 0xff>; 2215 num-lanes = <2>; 2216 2217 #address-cells = <3>; 2218 #size-cells = <2>; 2219 2220 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2221 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2222 2223 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2232 interrupt-names = "msi0", 2233 "msi1", 2234 "msi2", 2235 "msi3", 2236 "msi4", 2237 "msi5", 2238 "msi6", 2239 "msi7", 2240 "global"; 2241 #interrupt-cells = <1>; 2242 interrupt-map-mask = <0 0 0 0x7>; 2243 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2244 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2245 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2246 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2247 2248 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2249 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2250 <&pcie1_phy>, 2251 <&rpmhcc RPMH_CXO_CLK>, 2252 <&gcc GCC_PCIE_1_AUX_CLK>, 2253 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2254 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2255 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2256 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2257 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2258 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2259 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2260 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2261 2262 clock-names = "pipe", 2263 "pipe_mux", 2264 "phy_pipe", 2265 "ref", 2266 "aux", 2267 "cfg", 2268 "bus_master", 2269 "bus_slave", 2270 "slave_q2a", 2271 "tbu", 2272 "ddrss_sf_tbu", 2273 "aggre0", 2274 "aggre1"; 2275 2276 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2277 assigned-clock-rates = <19200000>; 2278 2279 resets = <&gcc GCC_PCIE_1_BCR>; 2280 reset-names = "pci"; 2281 2282 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2283 2284 phys = <&pcie1_phy>; 2285 phy-names = "pciephy"; 2286 2287 pinctrl-names = "default"; 2288 pinctrl-0 = <&pcie1_clkreq_n>; 2289 2290 dma-coherent; 2291 2292 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2293 <0x100 &apps_smmu 0x1c81 0x1>; 2294 2295 status = "disabled"; 2296 2297 pcie@0 { 2298 device_type = "pci"; 2299 reg = <0x0 0x0 0x0 0x0 0x0>; 2300 bus-range = <0x01 0xff>; 2301 2302 #address-cells = <3>; 2303 #size-cells = <2>; 2304 ranges; 2305 }; 2306 }; 2307 2308 pcie1_phy: phy@1c0e000 { 2309 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2310 reg = <0 0x01c0e000 0 0x1000>; 2311 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2312 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2313 <&gcc GCC_PCIE_CLKREF_EN>, 2314 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2315 <&gcc GCC_PCIE_1_PIPE_CLK>; 2316 clock-names = "aux", 2317 "cfg_ahb", 2318 "ref", 2319 "refgen", 2320 "pipe"; 2321 2322 clock-output-names = "pcie_1_pipe_clk"; 2323 #clock-cells = <0>; 2324 2325 #phy-cells = <0>; 2326 2327 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2328 reset-names = "phy"; 2329 2330 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2331 assigned-clock-rates = <100000000>; 2332 2333 status = "disabled"; 2334 }; 2335 2336 ufs_mem_hc: ufshc@1d84000 { 2337 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2338 "jedec,ufs-2.0"; 2339 reg = <0x0 0x01d84000 0x0 0x3000>; 2340 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2341 phys = <&ufs_mem_phy>; 2342 phy-names = "ufsphy"; 2343 lanes-per-direction = <2>; 2344 #reset-cells = <1>; 2345 resets = <&gcc GCC_UFS_PHY_BCR>; 2346 reset-names = "rst"; 2347 2348 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2349 required-opps = <&rpmhpd_opp_nom>; 2350 2351 iommus = <&apps_smmu 0x80 0x0>; 2352 dma-coherent; 2353 2354 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2355 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2356 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2357 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2358 interconnect-names = "ufs-ddr", "cpu-ufs"; 2359 2360 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2361 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2362 <&gcc GCC_UFS_PHY_AHB_CLK>, 2363 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2364 <&rpmhcc RPMH_CXO_CLK>, 2365 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2366 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2367 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2368 clock-names = "core_clk", 2369 "bus_aggr_clk", 2370 "iface_clk", 2371 "core_clk_unipro", 2372 "ref_clk", 2373 "tx_lane0_sync_clk", 2374 "rx_lane0_sync_clk", 2375 "rx_lane1_sync_clk"; 2376 2377 operating-points-v2 = <&ufs_opp_table>; 2378 2379 qcom,ice = <&ice>; 2380 2381 status = "disabled"; 2382 2383 ufs_opp_table: opp-table { 2384 compatible = "operating-points-v2"; 2385 2386 opp-75000000 { 2387 opp-hz = /bits/ 64 <75000000>, 2388 /bits/ 64 <0>, 2389 /bits/ 64 <0>, 2390 /bits/ 64 <75000000>, 2391 /bits/ 64 <0>, 2392 /bits/ 64 <0>, 2393 /bits/ 64 <0>, 2394 /bits/ 64 <0>; 2395 required-opps = <&rpmhpd_opp_low_svs>; 2396 }; 2397 2398 opp-150000000 { 2399 opp-hz = /bits/ 64 <150000000>, 2400 /bits/ 64 <0>, 2401 /bits/ 64 <0>, 2402 /bits/ 64 <150000000>, 2403 /bits/ 64 <0>, 2404 /bits/ 64 <0>, 2405 /bits/ 64 <0>, 2406 /bits/ 64 <0>; 2407 required-opps = <&rpmhpd_opp_svs>; 2408 }; 2409 2410 opp-300000000 { 2411 opp-hz = /bits/ 64 <300000000>, 2412 /bits/ 64 <0>, 2413 /bits/ 64 <0>, 2414 /bits/ 64 <300000000>, 2415 /bits/ 64 <0>, 2416 /bits/ 64 <0>, 2417 /bits/ 64 <0>, 2418 /bits/ 64 <0>; 2419 required-opps = <&rpmhpd_opp_nom>; 2420 }; 2421 }; 2422 }; 2423 2424 ufs_mem_phy: phy@1d87000 { 2425 compatible = "qcom,sc7280-qmp-ufs-phy"; 2426 reg = <0x0 0x01d87000 0x0 0xe00>; 2427 clocks = <&rpmhcc RPMH_CXO_CLK>, 2428 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2429 <&gcc GCC_UFS_1_CLKREF_EN>; 2430 clock-names = "ref", "ref_aux", "qref"; 2431 2432 power-domains = <&rpmhpd SC7280_MX>; 2433 2434 resets = <&ufs_mem_hc 0>; 2435 reset-names = "ufsphy"; 2436 2437 #clock-cells = <1>; 2438 #phy-cells = <0>; 2439 2440 status = "disabled"; 2441 }; 2442 2443 ice: crypto@1d88000 { 2444 compatible = "qcom,sc7280-inline-crypto-engine", 2445 "qcom,inline-crypto-engine"; 2446 reg = <0 0x01d88000 0 0x8000>; 2447 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2448 }; 2449 2450 cryptobam: dma-controller@1dc4000 { 2451 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2452 reg = <0x0 0x01dc4000 0x0 0x28000>; 2453 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2454 #dma-cells = <1>; 2455 iommus = <&apps_smmu 0x4e4 0x0011>, 2456 <&apps_smmu 0x4e6 0x0011>; 2457 qcom,ee = <0>; 2458 qcom,controlled-remotely; 2459 num-channels = <16>; 2460 qcom,num-ees = <4>; 2461 }; 2462 2463 crypto: crypto@1dfa000 { 2464 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2465 reg = <0x0 0x01dfa000 0x0 0x6000>; 2466 dmas = <&cryptobam 4>, <&cryptobam 5>; 2467 dma-names = "rx", "tx"; 2468 iommus = <&apps_smmu 0x4e4 0x0011>, 2469 <&apps_smmu 0x4e4 0x0011>; 2470 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2471 interconnect-names = "memory"; 2472 }; 2473 2474 ipa: ipa@1e40000 { 2475 compatible = "qcom,sc7280-ipa"; 2476 2477 iommus = <&apps_smmu 0x480 0x0>, 2478 <&apps_smmu 0x482 0x0>; 2479 reg = <0 0x01e40000 0 0x8000>, 2480 <0 0x01e50000 0 0x4ad0>, 2481 <0 0x01e04000 0 0x23000>; 2482 reg-names = "ipa-reg", 2483 "ipa-shared", 2484 "gsi"; 2485 2486 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2487 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2488 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2489 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2490 interrupt-names = "ipa", 2491 "gsi", 2492 "ipa-clock-query", 2493 "ipa-setup-ready"; 2494 2495 clocks = <&rpmhcc RPMH_IPA_CLK>; 2496 clock-names = "core"; 2497 2498 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2499 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2500 interconnect-names = "memory", 2501 "config"; 2502 2503 qcom,qmp = <&aoss_qmp>; 2504 2505 qcom,smem-states = <&ipa_smp2p_out 0>, 2506 <&ipa_smp2p_out 1>; 2507 qcom,smem-state-names = "ipa-clock-enabled-valid", 2508 "ipa-clock-enabled"; 2509 2510 status = "disabled"; 2511 }; 2512 2513 tcsr_mutex: hwlock@1f40000 { 2514 compatible = "qcom,tcsr-mutex"; 2515 reg = <0 0x01f40000 0 0x20000>; 2516 #hwlock-cells = <1>; 2517 }; 2518 2519 tcsr_1: syscon@1f60000 { 2520 compatible = "qcom,sc7280-tcsr", "syscon"; 2521 reg = <0 0x01f60000 0 0x20000>; 2522 }; 2523 2524 tcsr_2: syscon@1fc0000 { 2525 compatible = "qcom,sc7280-tcsr", "syscon"; 2526 reg = <0 0x01fc0000 0 0x30000>; 2527 }; 2528 2529 lpasscc: lpasscc@3000000 { 2530 compatible = "qcom,sc7280-lpasscc"; 2531 reg = <0 0x03000000 0 0x40>, 2532 <0 0x03c04000 0 0x4>; 2533 reg-names = "qdsp6ss", "top_cc"; 2534 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2535 clock-names = "iface"; 2536 #clock-cells = <1>; 2537 status = "reserved"; /* Owned by ADSP firmware */ 2538 }; 2539 2540 lpass_rx_macro: codec@3200000 { 2541 compatible = "qcom,sc7280-lpass-rx-macro"; 2542 reg = <0 0x03200000 0 0x1000>; 2543 2544 pinctrl-names = "default"; 2545 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2546 2547 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2548 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2549 <&lpass_va_macro>; 2550 clock-names = "mclk", "npl", "fsgen"; 2551 2552 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2553 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2554 power-domain-names = "macro", "dcodec"; 2555 2556 #clock-cells = <0>; 2557 #sound-dai-cells = <1>; 2558 2559 status = "disabled"; 2560 }; 2561 2562 swr0: soundwire@3210000 { 2563 compatible = "qcom,soundwire-v1.6.0"; 2564 reg = <0 0x03210000 0 0x2000>; 2565 2566 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2567 clocks = <&lpass_rx_macro>; 2568 clock-names = "iface"; 2569 2570 qcom,din-ports = <0>; 2571 qcom,dout-ports = <5>; 2572 2573 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2574 reset-names = "swr_audio_cgcr"; 2575 2576 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2577 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2578 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2579 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2580 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2581 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2582 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2583 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2584 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2585 2586 #sound-dai-cells = <1>; 2587 #address-cells = <2>; 2588 #size-cells = <0>; 2589 2590 status = "disabled"; 2591 }; 2592 2593 lpass_tx_macro: codec@3220000 { 2594 compatible = "qcom,sc7280-lpass-tx-macro"; 2595 reg = <0 0x03220000 0 0x1000>; 2596 2597 pinctrl-names = "default"; 2598 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2599 2600 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2601 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2602 <&lpass_va_macro>; 2603 clock-names = "mclk", "npl", "fsgen"; 2604 2605 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2606 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2607 power-domain-names = "macro", "dcodec"; 2608 2609 #clock-cells = <0>; 2610 #sound-dai-cells = <1>; 2611 2612 status = "disabled"; 2613 }; 2614 2615 swr1: soundwire@3230000 { 2616 compatible = "qcom,soundwire-v1.6.0"; 2617 reg = <0 0x03230000 0 0x2000>; 2618 2619 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2620 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2621 clocks = <&lpass_tx_macro>; 2622 clock-names = "iface"; 2623 2624 qcom,din-ports = <3>; 2625 qcom,dout-ports = <0>; 2626 2627 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2628 reset-names = "swr_audio_cgcr"; 2629 2630 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2631 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2632 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2633 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2634 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2635 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2636 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2637 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2638 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2639 2640 #sound-dai-cells = <1>; 2641 #address-cells = <2>; 2642 #size-cells = <0>; 2643 2644 status = "disabled"; 2645 }; 2646 2647 lpass_audiocc: clock-controller@3300000 { 2648 compatible = "qcom,sc7280-lpassaudiocc"; 2649 reg = <0 0x03300000 0 0x30000>, 2650 <0 0x032a9000 0 0x1000>; 2651 clocks = <&rpmhcc RPMH_CXO_CLK>, 2652 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2653 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2654 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2655 #clock-cells = <1>; 2656 #power-domain-cells = <1>; 2657 #reset-cells = <1>; 2658 }; 2659 2660 lpass_va_macro: codec@3370000 { 2661 compatible = "qcom,sc7280-lpass-va-macro"; 2662 reg = <0 0x03370000 0 0x1000>; 2663 2664 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2665 clock-names = "mclk"; 2666 2667 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2668 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2669 power-domain-names = "macro", "dcodec"; 2670 2671 #clock-cells = <0>; 2672 #sound-dai-cells = <1>; 2673 2674 status = "disabled"; 2675 }; 2676 2677 lpass_aon: clock-controller@3380000 { 2678 compatible = "qcom,sc7280-lpassaoncc"; 2679 reg = <0 0x03380000 0 0x30000>; 2680 clocks = <&rpmhcc RPMH_CXO_CLK>, 2681 <&rpmhcc RPMH_CXO_CLK_A>, 2682 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2683 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2684 #clock-cells = <1>; 2685 #power-domain-cells = <1>; 2686 status = "reserved"; /* Owned by ADSP firmware */ 2687 }; 2688 2689 lpass_core: clock-controller@3900000 { 2690 compatible = "qcom,sc7280-lpasscorecc"; 2691 reg = <0 0x03900000 0 0x50000>; 2692 clocks = <&rpmhcc RPMH_CXO_CLK>; 2693 clock-names = "bi_tcxo"; 2694 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2695 #clock-cells = <1>; 2696 #power-domain-cells = <1>; 2697 status = "reserved"; /* Owned by ADSP firmware */ 2698 }; 2699 2700 lpass_cpu: audio@3987000 { 2701 compatible = "qcom,sc7280-lpass-cpu"; 2702 2703 reg = <0 0x03987000 0 0x68000>, 2704 <0 0x03b00000 0 0x29000>, 2705 <0 0x03260000 0 0xc000>, 2706 <0 0x03280000 0 0x29000>, 2707 <0 0x03340000 0 0x29000>, 2708 <0 0x0336c000 0 0x3000>; 2709 reg-names = "lpass-hdmiif", 2710 "lpass-lpaif", 2711 "lpass-rxtx-cdc-dma-lpm", 2712 "lpass-rxtx-lpaif", 2713 "lpass-va-lpaif", 2714 "lpass-va-cdc-dma-lpm"; 2715 2716 iommus = <&apps_smmu 0x1820 0>, 2717 <&apps_smmu 0x1821 0>, 2718 <&apps_smmu 0x1832 0>; 2719 2720 power-domains = <&rpmhpd SC7280_LCX>; 2721 power-domain-names = "lcx"; 2722 required-opps = <&rpmhpd_opp_nom>; 2723 2724 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2725 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2726 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2727 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2728 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2729 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2730 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2731 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2732 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2733 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2734 clock-names = "aon_cc_audio_hm_h", 2735 "audio_cc_ext_mclk0", 2736 "core_cc_sysnoc_mport_core", 2737 "core_cc_ext_if0_ibit", 2738 "core_cc_ext_if1_ibit", 2739 "audio_cc_codec_mem", 2740 "audio_cc_codec_mem0", 2741 "audio_cc_codec_mem1", 2742 "audio_cc_codec_mem2", 2743 "aon_cc_va_mem0"; 2744 2745 #sound-dai-cells = <1>; 2746 #address-cells = <1>; 2747 #size-cells = <0>; 2748 2749 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2752 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2753 interrupt-names = "lpass-irq-lpaif", 2754 "lpass-irq-hdmi", 2755 "lpass-irq-vaif", 2756 "lpass-irq-rxtxif"; 2757 2758 status = "disabled"; 2759 }; 2760 2761 slimbam: dma-controller@3a84000 { 2762 compatible = "qcom,bam-v1.7.0"; 2763 reg = <0 0x03a84000 0 0x20000>; 2764 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2765 #dma-cells = <1>; 2766 qcom,controlled-remotely; 2767 num-channels = <31>; 2768 qcom,ee = <1>; 2769 qcom,num-ees = <2>; 2770 iommus = <&apps_smmu 0x1826 0x0>; 2771 status = "disabled"; 2772 }; 2773 2774 slim: slim-ngd@3ac0000 { 2775 compatible = "qcom,slim-ngd-v1.5.0"; 2776 reg = <0 0x03ac0000 0 0x2c000>; 2777 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2778 dmas = <&slimbam 3>, <&slimbam 4>; 2779 dma-names = "rx", "tx"; 2780 iommus = <&apps_smmu 0x1826 0x0>; 2781 #address-cells = <1>; 2782 #size-cells = <0>; 2783 status = "disabled"; 2784 }; 2785 2786 lpass_hm: clock-controller@3c00000 { 2787 compatible = "qcom,sc7280-lpasshm"; 2788 reg = <0 0x03c00000 0 0x28>; 2789 clocks = <&rpmhcc RPMH_CXO_CLK>; 2790 clock-names = "bi_tcxo"; 2791 #clock-cells = <1>; 2792 #power-domain-cells = <1>; 2793 status = "reserved"; /* Owned by ADSP firmware */ 2794 }; 2795 2796 lpass_ag_noc: interconnect@3c40000 { 2797 reg = <0 0x03c40000 0 0xf080>; 2798 compatible = "qcom,sc7280-lpass-ag-noc"; 2799 #interconnect-cells = <2>; 2800 qcom,bcm-voters = <&apps_bcm_voter>; 2801 }; 2802 2803 lpass_tlmm: pinctrl@33c0000 { 2804 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2805 reg = <0 0x033c0000 0x0 0x20000>, 2806 <0 0x03550000 0x0 0x10000>; 2807 gpio-controller; 2808 #gpio-cells = <2>; 2809 gpio-ranges = <&lpass_tlmm 0 0 15>; 2810 2811 lpass_dmic01_clk: dmic01-clk-state { 2812 pins = "gpio6"; 2813 function = "dmic1_clk"; 2814 }; 2815 2816 lpass_dmic01_data: dmic01-data-state { 2817 pins = "gpio7"; 2818 function = "dmic1_data"; 2819 }; 2820 2821 lpass_dmic23_clk: dmic23-clk-state { 2822 pins = "gpio8"; 2823 function = "dmic2_clk"; 2824 }; 2825 2826 lpass_dmic23_data: dmic23-data-state { 2827 pins = "gpio9"; 2828 function = "dmic2_data"; 2829 }; 2830 2831 lpass_rx_swr_clk: rx-swr-clk-state { 2832 pins = "gpio3"; 2833 function = "swr_rx_clk"; 2834 }; 2835 2836 lpass_rx_swr_data: rx-swr-data-state { 2837 pins = "gpio4", "gpio5"; 2838 function = "swr_rx_data"; 2839 }; 2840 2841 lpass_tx_swr_clk: tx-swr-clk-state { 2842 pins = "gpio0"; 2843 function = "swr_tx_clk"; 2844 }; 2845 2846 lpass_tx_swr_data: tx-swr-data-state { 2847 pins = "gpio1", "gpio2", "gpio14"; 2848 function = "swr_tx_data"; 2849 }; 2850 }; 2851 2852 gpu: gpu@3d00000 { 2853 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2854 reg = <0 0x03d00000 0 0x40000>, 2855 <0 0x03d9e000 0 0x1000>, 2856 <0 0x03d61000 0 0x800>; 2857 reg-names = "kgsl_3d0_reg_memory", 2858 "cx_mem", 2859 "cx_dbgc"; 2860 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2861 iommus = <&adreno_smmu 0 0x400>, 2862 <&adreno_smmu 1 0x400>; 2863 operating-points-v2 = <&gpu_opp_table>; 2864 qcom,gmu = <&gmu>; 2865 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2866 interconnect-names = "gfx-mem"; 2867 #cooling-cells = <2>; 2868 2869 nvmem-cells = <&gpu_speed_bin>; 2870 nvmem-cell-names = "speed_bin"; 2871 2872 status = "disabled"; 2873 2874 gpu_zap_shader: zap-shader { 2875 memory-region = <&gpu_zap_mem>; 2876 }; 2877 2878 gpu_opp_table: opp-table { 2879 compatible = "operating-points-v2"; 2880 2881 opp-315000000 { 2882 opp-hz = /bits/ 64 <315000000>; 2883 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2884 opp-peak-kBps = <1804000>; 2885 opp-supported-hw = <0x17>; 2886 }; 2887 2888 opp-450000000 { 2889 opp-hz = /bits/ 64 <450000000>; 2890 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2891 opp-peak-kBps = <4068000>; 2892 opp-supported-hw = <0x17>; 2893 }; 2894 2895 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2896 opp-550000000-0 { 2897 opp-hz = /bits/ 64 <550000000>; 2898 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2899 opp-peak-kBps = <8368000>; 2900 opp-supported-hw = <0x01>; 2901 }; 2902 2903 opp-550000000-1 { 2904 opp-hz = /bits/ 64 <550000000>; 2905 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2906 opp-peak-kBps = <6832000>; 2907 opp-supported-hw = <0x16>; 2908 }; 2909 2910 opp-608000000 { 2911 opp-hz = /bits/ 64 <608000000>; 2912 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2913 opp-peak-kBps = <8368000>; 2914 opp-supported-hw = <0x16>; 2915 }; 2916 2917 opp-700000000 { 2918 opp-hz = /bits/ 64 <700000000>; 2919 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2920 opp-peak-kBps = <8532000>; 2921 opp-supported-hw = <0x06>; 2922 }; 2923 2924 opp-812000000 { 2925 opp-hz = /bits/ 64 <812000000>; 2926 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2927 opp-peak-kBps = <8532000>; 2928 opp-supported-hw = <0x06>; 2929 }; 2930 2931 opp-840000000 { 2932 opp-hz = /bits/ 64 <840000000>; 2933 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2934 opp-peak-kBps = <8532000>; 2935 opp-supported-hw = <0x02>; 2936 }; 2937 2938 opp-900000000 { 2939 opp-hz = /bits/ 64 <900000000>; 2940 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2941 opp-peak-kBps = <8532000>; 2942 opp-supported-hw = <0x02>; 2943 }; 2944 }; 2945 }; 2946 2947 gmu: gmu@3d6a000 { 2948 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2949 reg = <0 0x03d6a000 0 0x34000>, 2950 <0 0x3de0000 0 0x10000>, 2951 <0 0x0b290000 0 0x10000>; 2952 reg-names = "gmu", "rscc", "gmu_pdc"; 2953 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2955 interrupt-names = "hfi", "gmu"; 2956 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2957 <&gpucc GPU_CC_CXO_CLK>, 2958 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2959 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2960 <&gpucc GPU_CC_AHB_CLK>, 2961 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2962 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2963 clock-names = "gmu", 2964 "cxo", 2965 "axi", 2966 "memnoc", 2967 "ahb", 2968 "hub", 2969 "smmu_vote"; 2970 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2971 <&gpucc GPU_CC_GX_GDSC>; 2972 power-domain-names = "cx", 2973 "gx"; 2974 iommus = <&adreno_smmu 5 0x400>; 2975 operating-points-v2 = <&gmu_opp_table>; 2976 2977 gmu_opp_table: opp-table { 2978 compatible = "operating-points-v2"; 2979 2980 opp-200000000 { 2981 opp-hz = /bits/ 64 <200000000>; 2982 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2983 }; 2984 }; 2985 }; 2986 2987 gpucc: clock-controller@3d90000 { 2988 compatible = "qcom,sc7280-gpucc"; 2989 reg = <0 0x03d90000 0 0x9000>; 2990 clocks = <&rpmhcc RPMH_CXO_CLK>, 2991 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2992 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2993 clock-names = "bi_tcxo", 2994 "gcc_gpu_gpll0_clk_src", 2995 "gcc_gpu_gpll0_div_clk_src"; 2996 #clock-cells = <1>; 2997 #reset-cells = <1>; 2998 #power-domain-cells = <1>; 2999 }; 3000 3001 dma@117f000 { 3002 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 3003 reg = <0x0 0x0117f000 0x0 0x1000>, 3004 <0x0 0x01112000 0x0 0x6000>; 3005 }; 3006 3007 adreno_smmu: iommu@3da0000 { 3008 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 3009 "qcom,smmu-500", "arm,mmu-500"; 3010 reg = <0 0x03da0000 0 0x20000>; 3011 #iommu-cells = <2>; 3012 #global-interrupts = <2>; 3013 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3014 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 3015 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3016 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3017 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3018 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3019 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3020 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3021 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3022 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3023 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3025 3026 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3027 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3028 <&gpucc GPU_CC_AHB_CLK>, 3029 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3030 <&gpucc GPU_CC_CX_GMU_CLK>, 3031 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3032 <&gpucc GPU_CC_HUB_AON_CLK>; 3033 clock-names = "gcc_gpu_memnoc_gfx_clk", 3034 "gcc_gpu_snoc_dvm_gfx_clk", 3035 "gpu_cc_ahb_clk", 3036 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3037 "gpu_cc_cx_gmu_clk", 3038 "gpu_cc_hub_cx_int_clk", 3039 "gpu_cc_hub_aon_clk"; 3040 3041 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3042 dma-coherent; 3043 }; 3044 3045 gfx_0_tbu: tbu@3dd9000 { 3046 compatible = "qcom,sc7280-tbu"; 3047 reg = <0x0 0x3dd9000 0x0 0x1000>; 3048 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; 3049 }; 3050 3051 gfx_1_tbu: tbu@3ddd000 { 3052 compatible = "qcom,sc7280-tbu"; 3053 reg = <0x0 0x3ddd000 0x0 0x1000>; 3054 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; 3055 }; 3056 3057 remoteproc_mpss: remoteproc@4080000 { 3058 compatible = "qcom,sc7280-mpss-pas"; 3059 reg = <0 0x04080000 0 0x10000>; 3060 3061 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3062 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3063 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3064 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3065 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3066 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3067 interrupt-names = "wdog", "fatal", "ready", "handover", 3068 "stop-ack", "shutdown-ack"; 3069 3070 clocks = <&rpmhcc RPMH_CXO_CLK>; 3071 clock-names = "xo"; 3072 3073 power-domains = <&rpmhpd SC7280_CX>, 3074 <&rpmhpd SC7280_MSS>; 3075 power-domain-names = "cx", "mss"; 3076 3077 memory-region = <&mpss_mem>; 3078 3079 qcom,qmp = <&aoss_qmp>; 3080 3081 qcom,smem-states = <&modem_smp2p_out 0>; 3082 qcom,smem-state-names = "stop"; 3083 3084 status = "disabled"; 3085 3086 glink-edge { 3087 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3088 IPCC_MPROC_SIGNAL_GLINK_QMP 3089 IRQ_TYPE_EDGE_RISING>; 3090 mboxes = <&ipcc IPCC_CLIENT_MPSS 3091 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3092 label = "modem"; 3093 qcom,remote-pid = <1>; 3094 }; 3095 }; 3096 3097 stm@6002000 { 3098 compatible = "arm,coresight-stm", "arm,primecell"; 3099 reg = <0 0x06002000 0 0x1000>, 3100 <0 0x16280000 0 0x180000>; 3101 reg-names = "stm-base", "stm-stimulus-base"; 3102 3103 clocks = <&aoss_qmp>; 3104 clock-names = "apb_pclk"; 3105 3106 out-ports { 3107 port { 3108 stm_out: endpoint { 3109 remote-endpoint = <&funnel0_in7>; 3110 }; 3111 }; 3112 }; 3113 }; 3114 3115 funnel@6041000 { 3116 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3117 reg = <0 0x06041000 0 0x1000>; 3118 3119 clocks = <&aoss_qmp>; 3120 clock-names = "apb_pclk"; 3121 3122 out-ports { 3123 port { 3124 funnel0_out: endpoint { 3125 remote-endpoint = <&merge_funnel_in0>; 3126 }; 3127 }; 3128 }; 3129 3130 in-ports { 3131 #address-cells = <1>; 3132 #size-cells = <0>; 3133 3134 port@7 { 3135 reg = <7>; 3136 funnel0_in7: endpoint { 3137 remote-endpoint = <&stm_out>; 3138 }; 3139 }; 3140 }; 3141 }; 3142 3143 funnel@6042000 { 3144 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3145 reg = <0 0x06042000 0 0x1000>; 3146 3147 clocks = <&aoss_qmp>; 3148 clock-names = "apb_pclk"; 3149 3150 out-ports { 3151 port { 3152 funnel1_out: endpoint { 3153 remote-endpoint = <&merge_funnel_in1>; 3154 }; 3155 }; 3156 }; 3157 3158 in-ports { 3159 #address-cells = <1>; 3160 #size-cells = <0>; 3161 3162 port@4 { 3163 reg = <4>; 3164 funnel1_in4: endpoint { 3165 remote-endpoint = <&apss_merge_funnel_out>; 3166 }; 3167 }; 3168 }; 3169 }; 3170 3171 funnel@6045000 { 3172 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3173 reg = <0 0x06045000 0 0x1000>; 3174 3175 clocks = <&aoss_qmp>; 3176 clock-names = "apb_pclk"; 3177 3178 out-ports { 3179 port { 3180 merge_funnel_out: endpoint { 3181 remote-endpoint = <&swao_funnel_in>; 3182 }; 3183 }; 3184 }; 3185 3186 in-ports { 3187 #address-cells = <1>; 3188 #size-cells = <0>; 3189 3190 port@0 { 3191 reg = <0>; 3192 merge_funnel_in0: endpoint { 3193 remote-endpoint = <&funnel0_out>; 3194 }; 3195 }; 3196 3197 port@1 { 3198 reg = <1>; 3199 merge_funnel_in1: endpoint { 3200 remote-endpoint = <&funnel1_out>; 3201 }; 3202 }; 3203 }; 3204 }; 3205 3206 replicator@6046000 { 3207 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3208 reg = <0 0x06046000 0 0x1000>; 3209 3210 clocks = <&aoss_qmp>; 3211 clock-names = "apb_pclk"; 3212 3213 out-ports { 3214 port { 3215 replicator_out: endpoint { 3216 remote-endpoint = <&etr_in>; 3217 }; 3218 }; 3219 }; 3220 3221 in-ports { 3222 port { 3223 replicator_in: endpoint { 3224 remote-endpoint = <&swao_replicator_out>; 3225 }; 3226 }; 3227 }; 3228 }; 3229 3230 etr@6048000 { 3231 compatible = "arm,coresight-tmc", "arm,primecell"; 3232 reg = <0 0x06048000 0 0x1000>; 3233 iommus = <&apps_smmu 0x04c0 0>; 3234 3235 clocks = <&aoss_qmp>; 3236 clock-names = "apb_pclk"; 3237 arm,scatter-gather; 3238 3239 in-ports { 3240 port { 3241 etr_in: endpoint { 3242 remote-endpoint = <&replicator_out>; 3243 }; 3244 }; 3245 }; 3246 }; 3247 3248 funnel@6b04000 { 3249 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3250 reg = <0 0x06b04000 0 0x1000>; 3251 3252 clocks = <&aoss_qmp>; 3253 clock-names = "apb_pclk"; 3254 3255 out-ports { 3256 port { 3257 swao_funnel_out: endpoint { 3258 remote-endpoint = <&etf_in>; 3259 }; 3260 }; 3261 }; 3262 3263 in-ports { 3264 #address-cells = <1>; 3265 #size-cells = <0>; 3266 3267 port@7 { 3268 reg = <7>; 3269 swao_funnel_in: endpoint { 3270 remote-endpoint = <&merge_funnel_out>; 3271 }; 3272 }; 3273 }; 3274 }; 3275 3276 etf@6b05000 { 3277 compatible = "arm,coresight-tmc", "arm,primecell"; 3278 reg = <0 0x06b05000 0 0x1000>; 3279 3280 clocks = <&aoss_qmp>; 3281 clock-names = "apb_pclk"; 3282 3283 out-ports { 3284 port { 3285 etf_out: endpoint { 3286 remote-endpoint = <&swao_replicator_in>; 3287 }; 3288 }; 3289 }; 3290 3291 in-ports { 3292 port { 3293 etf_in: endpoint { 3294 remote-endpoint = <&swao_funnel_out>; 3295 }; 3296 }; 3297 }; 3298 }; 3299 3300 replicator@6b06000 { 3301 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3302 reg = <0 0x06b06000 0 0x1000>; 3303 3304 clocks = <&aoss_qmp>; 3305 clock-names = "apb_pclk"; 3306 qcom,replicator-loses-context; 3307 3308 out-ports { 3309 port { 3310 swao_replicator_out: endpoint { 3311 remote-endpoint = <&replicator_in>; 3312 }; 3313 }; 3314 }; 3315 3316 in-ports { 3317 port { 3318 swao_replicator_in: endpoint { 3319 remote-endpoint = <&etf_out>; 3320 }; 3321 }; 3322 }; 3323 }; 3324 3325 etm@7040000 { 3326 compatible = "arm,coresight-etm4x", "arm,primecell"; 3327 reg = <0 0x07040000 0 0x1000>; 3328 3329 cpu = <&cpu0>; 3330 3331 clocks = <&aoss_qmp>; 3332 clock-names = "apb_pclk"; 3333 arm,coresight-loses-context-with-cpu; 3334 qcom,skip-power-up; 3335 3336 out-ports { 3337 port { 3338 etm0_out: endpoint { 3339 remote-endpoint = <&apss_funnel_in0>; 3340 }; 3341 }; 3342 }; 3343 }; 3344 3345 etm@7140000 { 3346 compatible = "arm,coresight-etm4x", "arm,primecell"; 3347 reg = <0 0x07140000 0 0x1000>; 3348 3349 cpu = <&cpu1>; 3350 3351 clocks = <&aoss_qmp>; 3352 clock-names = "apb_pclk"; 3353 arm,coresight-loses-context-with-cpu; 3354 qcom,skip-power-up; 3355 3356 out-ports { 3357 port { 3358 etm1_out: endpoint { 3359 remote-endpoint = <&apss_funnel_in1>; 3360 }; 3361 }; 3362 }; 3363 }; 3364 3365 etm@7240000 { 3366 compatible = "arm,coresight-etm4x", "arm,primecell"; 3367 reg = <0 0x07240000 0 0x1000>; 3368 3369 cpu = <&cpu2>; 3370 3371 clocks = <&aoss_qmp>; 3372 clock-names = "apb_pclk"; 3373 arm,coresight-loses-context-with-cpu; 3374 qcom,skip-power-up; 3375 3376 out-ports { 3377 port { 3378 etm2_out: endpoint { 3379 remote-endpoint = <&apss_funnel_in2>; 3380 }; 3381 }; 3382 }; 3383 }; 3384 3385 etm@7340000 { 3386 compatible = "arm,coresight-etm4x", "arm,primecell"; 3387 reg = <0 0x07340000 0 0x1000>; 3388 3389 cpu = <&cpu3>; 3390 3391 clocks = <&aoss_qmp>; 3392 clock-names = "apb_pclk"; 3393 arm,coresight-loses-context-with-cpu; 3394 qcom,skip-power-up; 3395 3396 out-ports { 3397 port { 3398 etm3_out: endpoint { 3399 remote-endpoint = <&apss_funnel_in3>; 3400 }; 3401 }; 3402 }; 3403 }; 3404 3405 etm@7440000 { 3406 compatible = "arm,coresight-etm4x", "arm,primecell"; 3407 reg = <0 0x07440000 0 0x1000>; 3408 3409 cpu = <&cpu4>; 3410 3411 clocks = <&aoss_qmp>; 3412 clock-names = "apb_pclk"; 3413 arm,coresight-loses-context-with-cpu; 3414 qcom,skip-power-up; 3415 3416 out-ports { 3417 port { 3418 etm4_out: endpoint { 3419 remote-endpoint = <&apss_funnel_in4>; 3420 }; 3421 }; 3422 }; 3423 }; 3424 3425 etm@7540000 { 3426 compatible = "arm,coresight-etm4x", "arm,primecell"; 3427 reg = <0 0x07540000 0 0x1000>; 3428 3429 cpu = <&cpu5>; 3430 3431 clocks = <&aoss_qmp>; 3432 clock-names = "apb_pclk"; 3433 arm,coresight-loses-context-with-cpu; 3434 qcom,skip-power-up; 3435 3436 out-ports { 3437 port { 3438 etm5_out: endpoint { 3439 remote-endpoint = <&apss_funnel_in5>; 3440 }; 3441 }; 3442 }; 3443 }; 3444 3445 etm@7640000 { 3446 compatible = "arm,coresight-etm4x", "arm,primecell"; 3447 reg = <0 0x07640000 0 0x1000>; 3448 3449 cpu = <&cpu6>; 3450 3451 clocks = <&aoss_qmp>; 3452 clock-names = "apb_pclk"; 3453 arm,coresight-loses-context-with-cpu; 3454 qcom,skip-power-up; 3455 3456 out-ports { 3457 port { 3458 etm6_out: endpoint { 3459 remote-endpoint = <&apss_funnel_in6>; 3460 }; 3461 }; 3462 }; 3463 }; 3464 3465 etm@7740000 { 3466 compatible = "arm,coresight-etm4x", "arm,primecell"; 3467 reg = <0 0x07740000 0 0x1000>; 3468 3469 cpu = <&cpu7>; 3470 3471 clocks = <&aoss_qmp>; 3472 clock-names = "apb_pclk"; 3473 arm,coresight-loses-context-with-cpu; 3474 qcom,skip-power-up; 3475 3476 out-ports { 3477 port { 3478 etm7_out: endpoint { 3479 remote-endpoint = <&apss_funnel_in7>; 3480 }; 3481 }; 3482 }; 3483 }; 3484 3485 funnel@7800000 { /* APSS Funnel */ 3486 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3487 reg = <0 0x07800000 0 0x1000>; 3488 3489 clocks = <&aoss_qmp>; 3490 clock-names = "apb_pclk"; 3491 3492 out-ports { 3493 port { 3494 apss_funnel_out: endpoint { 3495 remote-endpoint = <&apss_merge_funnel_in>; 3496 }; 3497 }; 3498 }; 3499 3500 in-ports { 3501 #address-cells = <1>; 3502 #size-cells = <0>; 3503 3504 port@0 { 3505 reg = <0>; 3506 apss_funnel_in0: endpoint { 3507 remote-endpoint = <&etm0_out>; 3508 }; 3509 }; 3510 3511 port@1 { 3512 reg = <1>; 3513 apss_funnel_in1: endpoint { 3514 remote-endpoint = <&etm1_out>; 3515 }; 3516 }; 3517 3518 port@2 { 3519 reg = <2>; 3520 apss_funnel_in2: endpoint { 3521 remote-endpoint = <&etm2_out>; 3522 }; 3523 }; 3524 3525 port@3 { 3526 reg = <3>; 3527 apss_funnel_in3: endpoint { 3528 remote-endpoint = <&etm3_out>; 3529 }; 3530 }; 3531 3532 port@4 { 3533 reg = <4>; 3534 apss_funnel_in4: endpoint { 3535 remote-endpoint = <&etm4_out>; 3536 }; 3537 }; 3538 3539 port@5 { 3540 reg = <5>; 3541 apss_funnel_in5: endpoint { 3542 remote-endpoint = <&etm5_out>; 3543 }; 3544 }; 3545 3546 port@6 { 3547 reg = <6>; 3548 apss_funnel_in6: endpoint { 3549 remote-endpoint = <&etm6_out>; 3550 }; 3551 }; 3552 3553 port@7 { 3554 reg = <7>; 3555 apss_funnel_in7: endpoint { 3556 remote-endpoint = <&etm7_out>; 3557 }; 3558 }; 3559 }; 3560 }; 3561 3562 funnel@7810000 { 3563 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3564 reg = <0 0x07810000 0 0x1000>; 3565 3566 clocks = <&aoss_qmp>; 3567 clock-names = "apb_pclk"; 3568 3569 out-ports { 3570 port { 3571 apss_merge_funnel_out: endpoint { 3572 remote-endpoint = <&funnel1_in4>; 3573 }; 3574 }; 3575 }; 3576 3577 in-ports { 3578 port { 3579 apss_merge_funnel_in: endpoint { 3580 remote-endpoint = <&apss_funnel_out>; 3581 }; 3582 }; 3583 }; 3584 }; 3585 3586 sdhc_2: mmc@8804000 { 3587 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3588 pinctrl-names = "default", "sleep"; 3589 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3590 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3591 status = "disabled"; 3592 3593 reg = <0 0x08804000 0 0x1000>; 3594 3595 iommus = <&apps_smmu 0x100 0x0>; 3596 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3598 interrupt-names = "hc_irq", "pwr_irq"; 3599 3600 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3601 <&gcc GCC_SDCC2_APPS_CLK>, 3602 <&rpmhcc RPMH_CXO_CLK>; 3603 clock-names = "iface", "core", "xo"; 3604 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3605 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3606 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3607 power-domains = <&rpmhpd SC7280_CX>; 3608 operating-points-v2 = <&sdhc2_opp_table>; 3609 3610 bus-width = <4>; 3611 dma-coherent; 3612 3613 qcom,dll-config = <0x0007642c>; 3614 3615 resets = <&gcc GCC_SDCC2_BCR>; 3616 3617 sdhc2_opp_table: opp-table { 3618 compatible = "operating-points-v2"; 3619 3620 opp-100000000 { 3621 opp-hz = /bits/ 64 <100000000>; 3622 required-opps = <&rpmhpd_opp_low_svs>; 3623 opp-peak-kBps = <1800000 400000>; 3624 opp-avg-kBps = <100000 0>; 3625 }; 3626 3627 opp-202000000 { 3628 opp-hz = /bits/ 64 <202000000>; 3629 required-opps = <&rpmhpd_opp_nom>; 3630 opp-peak-kBps = <5400000 1600000>; 3631 opp-avg-kBps = <200000 0>; 3632 }; 3633 }; 3634 }; 3635 3636 usb_1_hsphy: phy@88e3000 { 3637 compatible = "qcom,sc7280-usb-hs-phy", 3638 "qcom,usb-snps-hs-7nm-phy"; 3639 reg = <0 0x088e3000 0 0x400>; 3640 status = "disabled"; 3641 #phy-cells = <0>; 3642 3643 clocks = <&rpmhcc RPMH_CXO_CLK>; 3644 clock-names = "ref"; 3645 3646 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3647 }; 3648 3649 usb_2_hsphy: phy@88e4000 { 3650 compatible = "qcom,sc7280-usb-hs-phy", 3651 "qcom,usb-snps-hs-7nm-phy"; 3652 reg = <0 0x088e4000 0 0x400>; 3653 status = "disabled"; 3654 #phy-cells = <0>; 3655 3656 clocks = <&rpmhcc RPMH_CXO_CLK>; 3657 clock-names = "ref"; 3658 3659 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3660 }; 3661 3662 usb_1_qmpphy: phy@88e8000 { 3663 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3664 reg = <0 0x088e8000 0 0x3000>; 3665 status = "disabled"; 3666 3667 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3668 <&rpmhcc RPMH_CXO_CLK>, 3669 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3670 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3671 clock-names = "aux", 3672 "ref", 3673 "com_aux", 3674 "usb3_pipe"; 3675 3676 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3677 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3678 reset-names = "phy", "common"; 3679 3680 #clock-cells = <1>; 3681 #phy-cells = <1>; 3682 3683 orientation-switch; 3684 3685 ports { 3686 #address-cells = <1>; 3687 #size-cells = <0>; 3688 3689 port@0 { 3690 reg = <0>; 3691 3692 usb_dp_qmpphy_out: endpoint { 3693 }; 3694 }; 3695 3696 port@1 { 3697 reg = <1>; 3698 3699 usb_dp_qmpphy_usb_ss_in: endpoint { 3700 remote-endpoint = <&usb_1_dwc3_ss>; 3701 }; 3702 }; 3703 3704 port@2 { 3705 reg = <2>; 3706 3707 usb_dp_qmpphy_dp_in: endpoint { 3708 remote-endpoint = <&mdss_dp_out>; 3709 }; 3710 }; 3711 }; 3712 }; 3713 3714 usb_2: usb@8cf8800 { 3715 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3716 reg = <0 0x08cf8800 0 0x400>; 3717 status = "disabled"; 3718 #address-cells = <2>; 3719 #size-cells = <2>; 3720 ranges; 3721 dma-ranges; 3722 3723 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3724 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3725 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3726 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3727 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3728 clock-names = "cfg_noc", 3729 "core", 3730 "iface", 3731 "sleep", 3732 "mock_utmi"; 3733 3734 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3735 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3736 assigned-clock-rates = <19200000>, <200000000>; 3737 3738 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3739 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3740 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3741 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3742 interrupt-names = "pwr_event", 3743 "hs_phy_irq", 3744 "dp_hs_phy_irq", 3745 "dm_hs_phy_irq"; 3746 3747 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3748 required-opps = <&rpmhpd_opp_nom>; 3749 3750 resets = <&gcc GCC_USB30_SEC_BCR>; 3751 3752 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3754 interconnect-names = "usb-ddr", "apps-usb"; 3755 3756 usb_2_dwc3: usb@8c00000 { 3757 compatible = "snps,dwc3"; 3758 reg = <0 0x08c00000 0 0xe000>; 3759 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3760 iommus = <&apps_smmu 0xa0 0x0>; 3761 snps,dis_u2_susphy_quirk; 3762 snps,dis_enblslpm_quirk; 3763 snps,dis-u1-entry-quirk; 3764 snps,dis-u2-entry-quirk; 3765 phys = <&usb_2_hsphy>; 3766 phy-names = "usb2-phy"; 3767 maximum-speed = "high-speed"; 3768 usb-role-switch; 3769 3770 port { 3771 usb2_role_switch: endpoint { 3772 remote-endpoint = <&eud_ep>; 3773 }; 3774 }; 3775 }; 3776 }; 3777 3778 qspi: spi@88dc000 { 3779 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3780 reg = <0 0x088dc000 0 0x1000>; 3781 iommus = <&apps_smmu 0x20 0x0>; 3782 #address-cells = <1>; 3783 #size-cells = <0>; 3784 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3785 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3786 <&gcc GCC_QSPI_CORE_CLK>; 3787 clock-names = "iface", "core"; 3788 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3789 &cnoc2 SLAVE_QSPI_0 0>; 3790 interconnect-names = "qspi-config"; 3791 power-domains = <&rpmhpd SC7280_CX>; 3792 operating-points-v2 = <&qspi_opp_table>; 3793 status = "disabled"; 3794 }; 3795 3796 remoteproc_adsp: remoteproc@3700000 { 3797 compatible = "qcom,sc7280-adsp-pas"; 3798 reg = <0 0x03700000 0 0x100>; 3799 3800 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3801 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3802 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3803 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3804 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3805 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3806 interrupt-names = "wdog", "fatal", "ready", "handover", 3807 "stop-ack", "shutdown-ack"; 3808 3809 clocks = <&rpmhcc RPMH_CXO_CLK>; 3810 clock-names = "xo"; 3811 3812 power-domains = <&rpmhpd SC7280_LCX>, 3813 <&rpmhpd SC7280_LMX>; 3814 power-domain-names = "lcx", "lmx"; 3815 3816 memory-region = <&adsp_mem>; 3817 3818 qcom,qmp = <&aoss_qmp>; 3819 3820 qcom,smem-states = <&adsp_smp2p_out 0>; 3821 qcom,smem-state-names = "stop"; 3822 3823 status = "disabled"; 3824 3825 glink-edge { 3826 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3827 IPCC_MPROC_SIGNAL_GLINK_QMP 3828 IRQ_TYPE_EDGE_RISING>; 3829 3830 mboxes = <&ipcc IPCC_CLIENT_LPASS 3831 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3832 3833 label = "lpass"; 3834 qcom,remote-pid = <2>; 3835 3836 apr { 3837 compatible = "qcom,apr-v2"; 3838 qcom,glink-channels = "apr_audio_svc"; 3839 qcom,domain = <APR_DOMAIN_ADSP>; 3840 #address-cells = <1>; 3841 #size-cells = <0>; 3842 3843 service@3 { 3844 reg = <APR_SVC_ADSP_CORE>; 3845 compatible = "qcom,q6core"; 3846 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3847 }; 3848 3849 q6afe: service@4 { 3850 compatible = "qcom,q6afe"; 3851 reg = <APR_SVC_AFE>; 3852 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3853 3854 q6afedai: dais { 3855 compatible = "qcom,q6afe-dais"; 3856 #address-cells = <1>; 3857 #size-cells = <0>; 3858 #sound-dai-cells = <1>; 3859 }; 3860 3861 q6afecc: clock-controller { 3862 compatible = "qcom,q6afe-clocks"; 3863 #clock-cells = <2>; 3864 }; 3865 }; 3866 3867 q6asm: service@7 { 3868 compatible = "qcom,q6asm"; 3869 reg = <APR_SVC_ASM>; 3870 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3871 3872 q6asmdai: dais { 3873 compatible = "qcom,q6asm-dais"; 3874 #address-cells = <1>; 3875 #size-cells = <0>; 3876 #sound-dai-cells = <1>; 3877 iommus = <&apps_smmu 0x1801 0x0>; 3878 3879 dai@0 { 3880 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 3881 }; 3882 3883 dai@1 { 3884 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 3885 }; 3886 3887 dai@2 { 3888 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 3889 }; 3890 }; 3891 }; 3892 3893 q6adm: service@8 { 3894 compatible = "qcom,q6adm"; 3895 reg = <APR_SVC_ADM>; 3896 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3897 3898 q6routing: routing { 3899 compatible = "qcom,q6adm-routing"; 3900 #sound-dai-cells = <0>; 3901 }; 3902 }; 3903 }; 3904 3905 fastrpc { 3906 compatible = "qcom,fastrpc"; 3907 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3908 label = "adsp"; 3909 qcom,non-secure-domain; 3910 #address-cells = <1>; 3911 #size-cells = <0>; 3912 3913 compute-cb@3 { 3914 compatible = "qcom,fastrpc-compute-cb"; 3915 reg = <3>; 3916 iommus = <&apps_smmu 0x1803 0x0>; 3917 dma-coherent; 3918 }; 3919 3920 compute-cb@4 { 3921 compatible = "qcom,fastrpc-compute-cb"; 3922 reg = <4>; 3923 iommus = <&apps_smmu 0x1804 0x0>; 3924 dma-coherent; 3925 }; 3926 3927 compute-cb@5 { 3928 compatible = "qcom,fastrpc-compute-cb"; 3929 reg = <5>; 3930 iommus = <&apps_smmu 0x1805 0x0>; 3931 dma-coherent; 3932 }; 3933 }; 3934 }; 3935 }; 3936 3937 remoteproc_wpss: remoteproc@8a00000 { 3938 compatible = "qcom,sc7280-wpss-pas"; 3939 reg = <0 0x08a00000 0 0x10000>; 3940 3941 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3942 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3943 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3944 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3945 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3946 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3947 interrupt-names = "wdog", "fatal", "ready", "handover", 3948 "stop-ack", "shutdown-ack"; 3949 3950 clocks = <&rpmhcc RPMH_CXO_CLK>; 3951 clock-names = "xo"; 3952 3953 power-domains = <&rpmhpd SC7280_CX>, 3954 <&rpmhpd SC7280_MX>; 3955 power-domain-names = "cx", "mx"; 3956 3957 memory-region = <&wpss_mem>; 3958 3959 qcom,qmp = <&aoss_qmp>; 3960 3961 qcom,smem-states = <&wpss_smp2p_out 0>; 3962 qcom,smem-state-names = "stop"; 3963 3964 3965 status = "disabled"; 3966 3967 glink-edge { 3968 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3969 IPCC_MPROC_SIGNAL_GLINK_QMP 3970 IRQ_TYPE_EDGE_RISING>; 3971 mboxes = <&ipcc IPCC_CLIENT_WPSS 3972 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3973 3974 label = "wpss"; 3975 qcom,remote-pid = <13>; 3976 }; 3977 }; 3978 3979 pmu@9091000 { 3980 compatible = "qcom,sc7280-llcc-bwmon"; 3981 reg = <0 0x09091000 0 0x1000>; 3982 3983 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3984 3985 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3986 3987 operating-points-v2 = <&llcc_bwmon_opp_table>; 3988 3989 llcc_bwmon_opp_table: opp-table { 3990 compatible = "operating-points-v2"; 3991 3992 opp-0 { 3993 opp-peak-kBps = <800000>; 3994 }; 3995 opp-1 { 3996 opp-peak-kBps = <1804000>; 3997 }; 3998 opp-2 { 3999 opp-peak-kBps = <2188000>; 4000 }; 4001 opp-3 { 4002 opp-peak-kBps = <3072000>; 4003 }; 4004 opp-4 { 4005 opp-peak-kBps = <4068000>; 4006 }; 4007 opp-5 { 4008 opp-peak-kBps = <6220000>; 4009 }; 4010 opp-6 { 4011 opp-peak-kBps = <6832000>; 4012 }; 4013 opp-7 { 4014 opp-peak-kBps = <8532000>; 4015 }; 4016 }; 4017 }; 4018 4019 pmu@90b6400 { 4020 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 4021 reg = <0 0x090b6400 0 0x600>; 4022 4023 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4024 4025 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4026 operating-points-v2 = <&cpu_bwmon_opp_table>; 4027 4028 cpu_bwmon_opp_table: opp-table { 4029 compatible = "operating-points-v2"; 4030 4031 opp-0 { 4032 opp-peak-kBps = <2400000>; 4033 }; 4034 opp-1 { 4035 opp-peak-kBps = <4800000>; 4036 }; 4037 opp-2 { 4038 opp-peak-kBps = <7456000>; 4039 }; 4040 opp-3 { 4041 opp-peak-kBps = <9600000>; 4042 }; 4043 opp-4 { 4044 opp-peak-kBps = <12896000>; 4045 }; 4046 opp-5 { 4047 opp-peak-kBps = <14928000>; 4048 }; 4049 opp-6 { 4050 opp-peak-kBps = <17056000>; 4051 }; 4052 }; 4053 }; 4054 4055 dc_noc: interconnect@90e0000 { 4056 reg = <0 0x090e0000 0 0x5080>; 4057 compatible = "qcom,sc7280-dc-noc"; 4058 #interconnect-cells = <2>; 4059 qcom,bcm-voters = <&apps_bcm_voter>; 4060 }; 4061 4062 gem_noc: interconnect@9100000 { 4063 reg = <0 0x09100000 0 0xe2200>; 4064 compatible = "qcom,sc7280-gem-noc"; 4065 #interconnect-cells = <2>; 4066 qcom,bcm-voters = <&apps_bcm_voter>; 4067 }; 4068 4069 system-cache-controller@9200000 { 4070 compatible = "qcom,sc7280-llcc"; 4071 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 4072 <0 0x09600000 0 0x58000>; 4073 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 4074 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4075 }; 4076 4077 eud: eud@88e0000 { 4078 compatible = "qcom,sc7280-eud", "qcom,eud"; 4079 reg = <0 0x88e0000 0 0x2000>, 4080 <0 0x88e2000 0 0x1000>; 4081 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 4082 4083 status = "disabled"; 4084 4085 ports { 4086 #address-cells = <1>; 4087 #size-cells = <0>; 4088 4089 port@0 { 4090 reg = <0>; 4091 eud_ep: endpoint { 4092 remote-endpoint = <&usb2_role_switch>; 4093 }; 4094 }; 4095 }; 4096 }; 4097 4098 nsp_noc: interconnect@a0c0000 { 4099 reg = <0 0x0a0c0000 0 0x10000>; 4100 compatible = "qcom,sc7280-nsp-noc"; 4101 #interconnect-cells = <2>; 4102 qcom,bcm-voters = <&apps_bcm_voter>; 4103 }; 4104 4105 remoteproc_cdsp: remoteproc@a300000 { 4106 compatible = "qcom,sc7280-cdsp-pas"; 4107 reg = <0 0x0a300000 0 0x10000>; 4108 4109 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4110 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4111 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4112 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4113 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4114 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4115 interrupt-names = "wdog", "fatal", "ready", "handover", 4116 "stop-ack", "shutdown-ack"; 4117 4118 clocks = <&rpmhcc RPMH_CXO_CLK>; 4119 clock-names = "xo"; 4120 4121 power-domains = <&rpmhpd SC7280_CX>, 4122 <&rpmhpd SC7280_MX>; 4123 power-domain-names = "cx", "mx"; 4124 4125 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4126 4127 memory-region = <&cdsp_mem>; 4128 4129 qcom,qmp = <&aoss_qmp>; 4130 4131 qcom,smem-states = <&cdsp_smp2p_out 0>; 4132 qcom,smem-state-names = "stop"; 4133 4134 status = "disabled"; 4135 4136 glink-edge { 4137 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4138 IPCC_MPROC_SIGNAL_GLINK_QMP 4139 IRQ_TYPE_EDGE_RISING>; 4140 mboxes = <&ipcc IPCC_CLIENT_CDSP 4141 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4142 4143 label = "cdsp"; 4144 qcom,remote-pid = <5>; 4145 4146 fastrpc { 4147 compatible = "qcom,fastrpc"; 4148 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4149 label = "cdsp"; 4150 qcom,non-secure-domain; 4151 #address-cells = <1>; 4152 #size-cells = <0>; 4153 4154 compute-cb@1 { 4155 compatible = "qcom,fastrpc-compute-cb"; 4156 reg = <1>; 4157 iommus = <&apps_smmu 0x11a1 0x0420>, 4158 <&apps_smmu 0x1181 0x0420>; 4159 dma-coherent; 4160 }; 4161 4162 compute-cb@2 { 4163 compatible = "qcom,fastrpc-compute-cb"; 4164 reg = <2>; 4165 iommus = <&apps_smmu 0x11a2 0x0420>, 4166 <&apps_smmu 0x1182 0x0420>; 4167 dma-coherent; 4168 }; 4169 4170 compute-cb@3 { 4171 compatible = "qcom,fastrpc-compute-cb"; 4172 reg = <3>; 4173 iommus = <&apps_smmu 0x11a3 0x0420>, 4174 <&apps_smmu 0x1183 0x0420>; 4175 dma-coherent; 4176 }; 4177 4178 compute-cb@4 { 4179 compatible = "qcom,fastrpc-compute-cb"; 4180 reg = <4>; 4181 iommus = <&apps_smmu 0x11a4 0x0420>, 4182 <&apps_smmu 0x1184 0x0420>; 4183 dma-coherent; 4184 }; 4185 4186 compute-cb@5 { 4187 compatible = "qcom,fastrpc-compute-cb"; 4188 reg = <5>; 4189 iommus = <&apps_smmu 0x11a5 0x0420>, 4190 <&apps_smmu 0x1185 0x0420>; 4191 dma-coherent; 4192 }; 4193 4194 compute-cb@6 { 4195 compatible = "qcom,fastrpc-compute-cb"; 4196 reg = <6>; 4197 iommus = <&apps_smmu 0x11a6 0x0420>, 4198 <&apps_smmu 0x1186 0x0420>; 4199 dma-coherent; 4200 }; 4201 4202 compute-cb@7 { 4203 compatible = "qcom,fastrpc-compute-cb"; 4204 reg = <7>; 4205 iommus = <&apps_smmu 0x11a7 0x0420>, 4206 <&apps_smmu 0x1187 0x0420>; 4207 dma-coherent; 4208 }; 4209 4210 compute-cb@8 { 4211 compatible = "qcom,fastrpc-compute-cb"; 4212 reg = <8>; 4213 iommus = <&apps_smmu 0x11a8 0x0420>, 4214 <&apps_smmu 0x1188 0x0420>; 4215 dma-coherent; 4216 }; 4217 4218 /* note: secure cb9 in downstream */ 4219 4220 compute-cb@11 { 4221 compatible = "qcom,fastrpc-compute-cb"; 4222 reg = <11>; 4223 iommus = <&apps_smmu 0x11ab 0x0420>, 4224 <&apps_smmu 0x118b 0x0420>; 4225 dma-coherent; 4226 }; 4227 4228 compute-cb@12 { 4229 compatible = "qcom,fastrpc-compute-cb"; 4230 reg = <12>; 4231 iommus = <&apps_smmu 0x11ac 0x0420>, 4232 <&apps_smmu 0x118c 0x0420>; 4233 dma-coherent; 4234 }; 4235 4236 compute-cb@13 { 4237 compatible = "qcom,fastrpc-compute-cb"; 4238 reg = <13>; 4239 iommus = <&apps_smmu 0x11ad 0x0420>, 4240 <&apps_smmu 0x118d 0x0420>; 4241 dma-coherent; 4242 }; 4243 4244 compute-cb@14 { 4245 compatible = "qcom,fastrpc-compute-cb"; 4246 reg = <14>; 4247 iommus = <&apps_smmu 0x11ae 0x0420>, 4248 <&apps_smmu 0x118e 0x0420>; 4249 dma-coherent; 4250 }; 4251 }; 4252 }; 4253 }; 4254 4255 usb_1: usb@a6f8800 { 4256 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 4257 reg = <0 0x0a6f8800 0 0x400>; 4258 status = "disabled"; 4259 #address-cells = <2>; 4260 #size-cells = <2>; 4261 ranges; 4262 dma-ranges; 4263 4264 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4265 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4266 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4267 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4268 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4269 clock-names = "cfg_noc", 4270 "core", 4271 "iface", 4272 "sleep", 4273 "mock_utmi"; 4274 4275 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4276 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4277 assigned-clock-rates = <19200000>, <200000000>; 4278 4279 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4280 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4281 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4282 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4283 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4284 interrupt-names = "pwr_event", 4285 "hs_phy_irq", 4286 "dp_hs_phy_irq", 4287 "dm_hs_phy_irq", 4288 "ss_phy_irq"; 4289 4290 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4291 required-opps = <&rpmhpd_opp_nom>; 4292 4293 resets = <&gcc GCC_USB30_PRIM_BCR>; 4294 4295 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4296 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4297 interconnect-names = "usb-ddr", "apps-usb"; 4298 4299 wakeup-source; 4300 4301 usb_1_dwc3: usb@a600000 { 4302 compatible = "snps,dwc3"; 4303 reg = <0 0x0a600000 0 0xe000>; 4304 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4305 iommus = <&apps_smmu 0xe0 0x0>; 4306 snps,dis_u2_susphy_quirk; 4307 snps,dis_enblslpm_quirk; 4308 snps,parkmode-disable-ss-quirk; 4309 snps,dis-u1-entry-quirk; 4310 snps,dis-u2-entry-quirk; 4311 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4312 phy-names = "usb2-phy", "usb3-phy"; 4313 maximum-speed = "super-speed"; 4314 4315 ports { 4316 #address-cells = <1>; 4317 #size-cells = <0>; 4318 4319 port@0 { 4320 reg = <0>; 4321 4322 usb_1_dwc3_hs: endpoint { 4323 }; 4324 }; 4325 4326 port@1 { 4327 reg = <1>; 4328 4329 usb_1_dwc3_ss: endpoint { 4330 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4331 }; 4332 }; 4333 }; 4334 }; 4335 }; 4336 4337 venus: video-codec@aa00000 { 4338 compatible = "qcom,sc7280-venus"; 4339 reg = <0 0x0aa00000 0 0xd0600>; 4340 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4341 4342 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4343 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4344 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4345 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4346 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4347 clock-names = "core", "bus", "iface", 4348 "vcodec_core", "vcodec_bus"; 4349 4350 power-domains = <&videocc MVSC_GDSC>, 4351 <&videocc MVS0_GDSC>, 4352 <&rpmhpd SC7280_CX>; 4353 power-domain-names = "venus", "vcodec0", "cx"; 4354 operating-points-v2 = <&venus_opp_table>; 4355 4356 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4357 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4358 interconnect-names = "cpu-cfg", "video-mem"; 4359 4360 iommus = <&apps_smmu 0x2180 0x20>; 4361 memory-region = <&video_mem>; 4362 4363 status = "disabled"; 4364 4365 venus_opp_table: opp-table { 4366 compatible = "operating-points-v2"; 4367 4368 opp-133330000 { 4369 opp-hz = /bits/ 64 <133330000>; 4370 required-opps = <&rpmhpd_opp_low_svs>; 4371 }; 4372 4373 opp-240000000 { 4374 opp-hz = /bits/ 64 <240000000>; 4375 required-opps = <&rpmhpd_opp_svs>; 4376 }; 4377 4378 opp-335000000 { 4379 opp-hz = /bits/ 64 <335000000>; 4380 required-opps = <&rpmhpd_opp_svs_l1>; 4381 }; 4382 4383 opp-424000000 { 4384 opp-hz = /bits/ 64 <424000000>; 4385 required-opps = <&rpmhpd_opp_nom>; 4386 }; 4387 4388 opp-460000048 { 4389 opp-hz = /bits/ 64 <460000048>; 4390 required-opps = <&rpmhpd_opp_turbo>; 4391 }; 4392 }; 4393 }; 4394 4395 videocc: clock-controller@aaf0000 { 4396 compatible = "qcom,sc7280-videocc"; 4397 reg = <0 0x0aaf0000 0 0x10000>; 4398 clocks = <&rpmhcc RPMH_CXO_CLK>, 4399 <&rpmhcc RPMH_CXO_CLK_A>; 4400 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4401 #clock-cells = <1>; 4402 #reset-cells = <1>; 4403 #power-domain-cells = <1>; 4404 }; 4405 4406 cci0: cci@ac4a000 { 4407 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4408 reg = <0 0x0ac4a000 0 0x1000>; 4409 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4410 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4411 4412 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4413 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4414 <&camcc CAM_CC_CPAS_AHB_CLK>, 4415 <&camcc CAM_CC_CCI_0_CLK>, 4416 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4417 clock-names = "camnoc_axi", 4418 "slow_ahb_src", 4419 "cpas_ahb", 4420 "cci", 4421 "cci_src"; 4422 pinctrl-0 = <&cci0_default &cci1_default>; 4423 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4424 pinctrl-names = "default", "sleep"; 4425 4426 #address-cells = <1>; 4427 #size-cells = <0>; 4428 4429 status = "disabled"; 4430 4431 cci0_i2c0: i2c-bus@0 { 4432 reg = <0>; 4433 clock-frequency = <1000000>; 4434 #address-cells = <1>; 4435 #size-cells = <0>; 4436 }; 4437 4438 cci0_i2c1: i2c-bus@1 { 4439 reg = <1>; 4440 clock-frequency = <1000000>; 4441 #address-cells = <1>; 4442 #size-cells = <0>; 4443 }; 4444 }; 4445 4446 cci1: cci@ac4b000 { 4447 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4448 reg = <0 0x0ac4b000 0 0x1000>; 4449 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4450 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4451 4452 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4453 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4454 <&camcc CAM_CC_CPAS_AHB_CLK>, 4455 <&camcc CAM_CC_CCI_1_CLK>, 4456 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4457 clock-names = "camnoc_axi", 4458 "slow_ahb_src", 4459 "cpas_ahb", 4460 "cci", 4461 "cci_src"; 4462 pinctrl-0 = <&cci2_default &cci3_default>; 4463 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 4464 pinctrl-names = "default", "sleep"; 4465 4466 #address-cells = <1>; 4467 #size-cells = <0>; 4468 4469 status = "disabled"; 4470 4471 cci1_i2c0: i2c-bus@0 { 4472 reg = <0>; 4473 clock-frequency = <1000000>; 4474 #address-cells = <1>; 4475 #size-cells = <0>; 4476 }; 4477 4478 cci1_i2c1: i2c-bus@1 { 4479 reg = <1>; 4480 clock-frequency = <1000000>; 4481 #address-cells = <1>; 4482 #size-cells = <0>; 4483 }; 4484 }; 4485 4486 camss: isp@acb3000 { 4487 compatible = "qcom,sc7280-camss"; 4488 4489 reg = <0x0 0x0acb3000 0x0 0x1000>, 4490 <0x0 0x0acba000 0x0 0x1000>, 4491 <0x0 0x0acc1000 0x0 0x1000>, 4492 <0x0 0x0acc8000 0x0 0x1000>, 4493 <0x0 0x0accf000 0x0 0x1000>, 4494 <0x0 0x0ace0000 0x0 0x2000>, 4495 <0x0 0x0ace2000 0x0 0x2000>, 4496 <0x0 0x0ace4000 0x0 0x2000>, 4497 <0x0 0x0ace6000 0x0 0x2000>, 4498 <0x0 0x0ace8000 0x0 0x2000>, 4499 <0x0 0x0acaf000 0x0 0x4000>, 4500 <0x0 0x0acb6000 0x0 0x4000>, 4501 <0x0 0x0acbd000 0x0 0x4000>, 4502 <0x0 0x0acc4000 0x0 0x4000>, 4503 <0x0 0x0accb000 0x0 0x4000>; 4504 reg-names = "csid0", 4505 "csid1", 4506 "csid2", 4507 "csid_lite0", 4508 "csid_lite1", 4509 "csiphy0", 4510 "csiphy1", 4511 "csiphy2", 4512 "csiphy3", 4513 "csiphy4", 4514 "vfe0", 4515 "vfe1", 4516 "vfe2", 4517 "vfe_lite0", 4518 "vfe_lite1"; 4519 4520 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4521 <&camcc CAM_CC_CPAS_AHB_CLK>, 4522 <&camcc CAM_CC_CSIPHY0_CLK>, 4523 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4524 <&camcc CAM_CC_CSIPHY1_CLK>, 4525 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4526 <&camcc CAM_CC_CSIPHY2_CLK>, 4527 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4528 <&camcc CAM_CC_CSIPHY3_CLK>, 4529 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4530 <&camcc CAM_CC_CSIPHY4_CLK>, 4531 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4532 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4533 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4534 <&camcc CAM_CC_ICP_AHB_CLK>, 4535 <&camcc CAM_CC_IFE_0_CLK>, 4536 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4537 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4538 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4539 <&camcc CAM_CC_IFE_1_CLK>, 4540 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4541 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4542 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4543 <&camcc CAM_CC_IFE_2_CLK>, 4544 <&camcc CAM_CC_IFE_2_AXI_CLK>, 4545 <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, 4546 <&camcc CAM_CC_IFE_2_CSID_CLK>, 4547 <&camcc CAM_CC_IFE_LITE_0_CLK>, 4548 <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, 4549 <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, 4550 <&camcc CAM_CC_IFE_LITE_1_CLK>, 4551 <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, 4552 <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; 4553 clock-names = "camnoc_axi", 4554 "cpas_ahb", 4555 "csiphy0", 4556 "csiphy0_timer", 4557 "csiphy1", 4558 "csiphy1_timer", 4559 "csiphy2", 4560 "csiphy2_timer", 4561 "csiphy3", 4562 "csiphy3_timer", 4563 "csiphy4", 4564 "csiphy4_timer", 4565 "gcc_axi_hf", 4566 "gcc_axi_sf", 4567 "icp_ahb", 4568 "vfe0", 4569 "vfe0_axi", 4570 "vfe0_cphy_rx", 4571 "vfe0_csid", 4572 "vfe1", 4573 "vfe1_axi", 4574 "vfe1_cphy_rx", 4575 "vfe1_csid", 4576 "vfe2", 4577 "vfe2_axi", 4578 "vfe2_cphy_rx", 4579 "vfe2_csid", 4580 "vfe_lite0", 4581 "vfe_lite0_cphy_rx", 4582 "vfe_lite0_csid", 4583 "vfe_lite1", 4584 "vfe_lite1_cphy_rx", 4585 "vfe_lite1_csid"; 4586 4587 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4588 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4589 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4590 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4591 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4592 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4593 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4594 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4595 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4596 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 4597 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4598 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4599 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4600 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4601 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 4602 interrupt-names = "csid0", 4603 "csid1", 4604 "csid2", 4605 "csid_lite0", 4606 "csid_lite1", 4607 "csiphy0", 4608 "csiphy1", 4609 "csiphy2", 4610 "csiphy3", 4611 "csiphy4", 4612 "vfe0", 4613 "vfe1", 4614 "vfe2", 4615 "vfe_lite0", 4616 "vfe_lite1"; 4617 4618 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4619 &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4620 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 4621 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4622 interconnect-names = "ahb", 4623 "hf_0"; 4624 4625 iommus = <&apps_smmu 0x800 0x4e0>; 4626 4627 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 4628 <&camcc CAM_CC_IFE_1_GDSC>, 4629 <&camcc CAM_CC_IFE_2_GDSC>, 4630 <&camcc CAM_CC_TITAN_TOP_GDSC>; 4631 power-domain-names = "ife0", 4632 "ife1", 4633 "ife2", 4634 "top"; 4635 4636 status = "disabled"; 4637 4638 ports { 4639 #address-cells = <1>; 4640 #size-cells = <0>; 4641 4642 port@0 { 4643 reg = <0>; 4644 }; 4645 4646 port@1 { 4647 reg = <1>; 4648 }; 4649 4650 port@2 { 4651 reg = <2>; 4652 }; 4653 4654 port@3 { 4655 reg = <3>; 4656 }; 4657 4658 port@4 { 4659 reg = <4>; 4660 }; 4661 }; 4662 }; 4663 4664 camcc: clock-controller@ad00000 { 4665 compatible = "qcom,sc7280-camcc"; 4666 reg = <0 0x0ad00000 0 0x10000>; 4667 clocks = <&rpmhcc RPMH_CXO_CLK>, 4668 <&rpmhcc RPMH_CXO_CLK_A>, 4669 <&sleep_clk>; 4670 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4671 #clock-cells = <1>; 4672 #reset-cells = <1>; 4673 #power-domain-cells = <1>; 4674 }; 4675 4676 dispcc: clock-controller@af00000 { 4677 compatible = "qcom,sc7280-dispcc"; 4678 reg = <0 0x0af00000 0 0x20000>; 4679 clocks = <&rpmhcc RPMH_CXO_CLK>, 4680 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4681 <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 4682 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>, 4683 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4684 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4685 <&mdss_edp_phy 0>, 4686 <&mdss_edp_phy 1>; 4687 clock-names = "bi_tcxo", 4688 "gcc_disp_gpll0_clk", 4689 "dsi0_phy_pll_out_byteclk", 4690 "dsi0_phy_pll_out_dsiclk", 4691 "dp_phy_pll_link_clk", 4692 "dp_phy_pll_vco_div_clk", 4693 "edp_phy_pll_link_clk", 4694 "edp_phy_pll_vco_div_clk"; 4695 #clock-cells = <1>; 4696 #reset-cells = <1>; 4697 #power-domain-cells = <1>; 4698 }; 4699 4700 mdss: display-subsystem@ae00000 { 4701 compatible = "qcom,sc7280-mdss"; 4702 reg = <0 0x0ae00000 0 0x1000>; 4703 reg-names = "mdss"; 4704 4705 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4706 4707 clocks = <&gcc GCC_DISP_AHB_CLK>, 4708 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4709 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4710 clock-names = "iface", 4711 "ahb", 4712 "core"; 4713 4714 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4715 interrupt-controller; 4716 #interrupt-cells = <1>; 4717 4718 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4720 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4721 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 4722 interconnect-names = "mdp0-mem", 4723 "cpu-cfg"; 4724 4725 iommus = <&apps_smmu 0x900 0x402>; 4726 4727 #address-cells = <2>; 4728 #size-cells = <2>; 4729 ranges; 4730 4731 status = "disabled"; 4732 4733 mdss_mdp: display-controller@ae01000 { 4734 compatible = "qcom,sc7280-dpu"; 4735 reg = <0 0x0ae01000 0 0x8f030>, 4736 <0 0x0aeb0000 0 0x3000>; 4737 reg-names = "mdp", "vbif"; 4738 4739 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4740 <&gcc GCC_DISP_SF_AXI_CLK>, 4741 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4742 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4743 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4744 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4745 clock-names = "bus", 4746 "nrt_bus", 4747 "iface", 4748 "lut", 4749 "core", 4750 "vsync"; 4751 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 4752 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4753 assigned-clock-rates = <19200000>, 4754 <19200000>; 4755 operating-points-v2 = <&mdp_opp_table>; 4756 power-domains = <&rpmhpd SC7280_CX>; 4757 4758 interrupt-parent = <&mdss>; 4759 interrupts = <0>; 4760 4761 ports { 4762 #address-cells = <1>; 4763 #size-cells = <0>; 4764 4765 port@0 { 4766 reg = <0>; 4767 dpu_intf1_out: endpoint { 4768 remote-endpoint = <&mdss_dsi0_in>; 4769 }; 4770 }; 4771 4772 port@1 { 4773 reg = <1>; 4774 dpu_intf5_out: endpoint { 4775 remote-endpoint = <&edp_in>; 4776 }; 4777 }; 4778 4779 port@2 { 4780 reg = <2>; 4781 dpu_intf0_out: endpoint { 4782 remote-endpoint = <&dp_in>; 4783 }; 4784 }; 4785 }; 4786 4787 mdp_opp_table: opp-table { 4788 compatible = "operating-points-v2"; 4789 4790 opp-200000000 { 4791 opp-hz = /bits/ 64 <200000000>; 4792 required-opps = <&rpmhpd_opp_low_svs>; 4793 }; 4794 4795 opp-300000000 { 4796 opp-hz = /bits/ 64 <300000000>; 4797 required-opps = <&rpmhpd_opp_svs>; 4798 }; 4799 4800 opp-380000000 { 4801 opp-hz = /bits/ 64 <380000000>; 4802 required-opps = <&rpmhpd_opp_svs_l1>; 4803 }; 4804 4805 opp-506666667 { 4806 opp-hz = /bits/ 64 <506666667>; 4807 required-opps = <&rpmhpd_opp_nom>; 4808 }; 4809 4810 opp-608000000 { 4811 opp-hz = /bits/ 64 <608000000>; 4812 required-opps = <&rpmhpd_opp_turbo>; 4813 }; 4814 }; 4815 }; 4816 4817 mdss_dsi: dsi@ae94000 { 4818 compatible = "qcom,sc7280-dsi-ctrl", 4819 "qcom,mdss-dsi-ctrl"; 4820 reg = <0 0x0ae94000 0 0x400>; 4821 reg-names = "dsi_ctrl"; 4822 4823 interrupt-parent = <&mdss>; 4824 interrupts = <4>; 4825 4826 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4827 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4828 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4829 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4830 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4831 <&gcc GCC_DISP_HF_AXI_CLK>; 4832 clock-names = "byte", 4833 "byte_intf", 4834 "pixel", 4835 "core", 4836 "iface", 4837 "bus"; 4838 4839 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4840 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4841 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 4842 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>; 4843 4844 operating-points-v2 = <&dsi_opp_table>; 4845 power-domains = <&rpmhpd SC7280_CX>; 4846 4847 phys = <&mdss_dsi_phy>; 4848 4849 #address-cells = <1>; 4850 #size-cells = <0>; 4851 4852 status = "disabled"; 4853 4854 ports { 4855 #address-cells = <1>; 4856 #size-cells = <0>; 4857 4858 port@0 { 4859 reg = <0>; 4860 mdss_dsi0_in: endpoint { 4861 remote-endpoint = <&dpu_intf1_out>; 4862 }; 4863 }; 4864 4865 port@1 { 4866 reg = <1>; 4867 mdss_dsi0_out: endpoint { 4868 }; 4869 }; 4870 }; 4871 4872 dsi_opp_table: opp-table { 4873 compatible = "operating-points-v2"; 4874 4875 opp-187500000 { 4876 opp-hz = /bits/ 64 <187500000>; 4877 required-opps = <&rpmhpd_opp_low_svs>; 4878 }; 4879 4880 opp-300000000 { 4881 opp-hz = /bits/ 64 <300000000>; 4882 required-opps = <&rpmhpd_opp_svs>; 4883 }; 4884 4885 opp-358000000 { 4886 opp-hz = /bits/ 64 <358000000>; 4887 required-opps = <&rpmhpd_opp_svs_l1>; 4888 }; 4889 }; 4890 }; 4891 4892 mdss_dsi_phy: phy@ae94400 { 4893 compatible = "qcom,sc7280-dsi-phy-7nm"; 4894 reg = <0 0x0ae94400 0 0x200>, 4895 <0 0x0ae94600 0 0x280>, 4896 <0 0x0ae94900 0 0x280>; 4897 reg-names = "dsi_phy", 4898 "dsi_phy_lane", 4899 "dsi_pll"; 4900 4901 #clock-cells = <1>; 4902 #phy-cells = <0>; 4903 4904 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4905 <&rpmhcc RPMH_CXO_CLK>; 4906 clock-names = "iface", "ref"; 4907 4908 status = "disabled"; 4909 }; 4910 4911 mdss_edp: edp@aea0000 { 4912 compatible = "qcom,sc7280-edp"; 4913 pinctrl-names = "default"; 4914 pinctrl-0 = <&edp_hot_plug_det>; 4915 4916 reg = <0 0x0aea0000 0 0x200>, 4917 <0 0x0aea0200 0 0x200>, 4918 <0 0x0aea0400 0 0xc00>, 4919 <0 0x0aea1000 0 0x400>; 4920 4921 interrupt-parent = <&mdss>; 4922 interrupts = <14>; 4923 4924 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4925 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4926 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4927 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4928 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4929 clock-names = "core_iface", 4930 "core_aux", 4931 "ctrl_link", 4932 "ctrl_link_iface", 4933 "stream_pixel"; 4934 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4935 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4936 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4937 4938 phys = <&mdss_edp_phy>; 4939 phy-names = "dp"; 4940 4941 operating-points-v2 = <&edp_opp_table>; 4942 power-domains = <&rpmhpd SC7280_CX>; 4943 4944 status = "disabled"; 4945 4946 ports { 4947 #address-cells = <1>; 4948 #size-cells = <0>; 4949 4950 port@0 { 4951 reg = <0>; 4952 edp_in: endpoint { 4953 remote-endpoint = <&dpu_intf5_out>; 4954 }; 4955 }; 4956 4957 port@1 { 4958 reg = <1>; 4959 mdss_edp_out: endpoint { }; 4960 }; 4961 }; 4962 4963 edp_opp_table: opp-table { 4964 compatible = "operating-points-v2"; 4965 4966 opp-160000000 { 4967 opp-hz = /bits/ 64 <160000000>; 4968 required-opps = <&rpmhpd_opp_low_svs>; 4969 }; 4970 4971 opp-270000000 { 4972 opp-hz = /bits/ 64 <270000000>; 4973 required-opps = <&rpmhpd_opp_svs>; 4974 }; 4975 4976 opp-540000000 { 4977 opp-hz = /bits/ 64 <540000000>; 4978 required-opps = <&rpmhpd_opp_nom>; 4979 }; 4980 4981 opp-810000000 { 4982 opp-hz = /bits/ 64 <810000000>; 4983 required-opps = <&rpmhpd_opp_nom>; 4984 }; 4985 }; 4986 }; 4987 4988 mdss_edp_phy: phy@aec2a00 { 4989 compatible = "qcom,sc7280-edp-phy"; 4990 4991 reg = <0 0x0aec2a00 0 0x19c>, 4992 <0 0x0aec2200 0 0xa0>, 4993 <0 0x0aec2600 0 0xa0>, 4994 <0 0x0aec2000 0 0x1c0>; 4995 4996 clocks = <&rpmhcc RPMH_CXO_CLK>, 4997 <&gcc GCC_EDP_CLKREF_EN>; 4998 clock-names = "aux", 4999 "cfg_ahb"; 5000 5001 #clock-cells = <1>; 5002 #phy-cells = <0>; 5003 5004 status = "disabled"; 5005 }; 5006 5007 mdss_dp: displayport-controller@ae90000 { 5008 compatible = "qcom,sc7280-dp"; 5009 5010 reg = <0 0x0ae90000 0 0x200>, 5011 <0 0x0ae90200 0 0x200>, 5012 <0 0x0ae90400 0 0xc00>, 5013 <0 0x0ae91000 0 0x400>, 5014 <0 0x0ae91400 0 0x400>; 5015 5016 interrupt-parent = <&mdss>; 5017 interrupts = <12>; 5018 5019 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5020 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 5021 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 5022 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 5023 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 5024 clock-names = "core_iface", 5025 "core_aux", 5026 "ctrl_link", 5027 "ctrl_link_iface", 5028 "stream_pixel"; 5029 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 5030 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 5031 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5032 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5033 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5034 phy-names = "dp"; 5035 5036 operating-points-v2 = <&dp_opp_table>; 5037 power-domains = <&rpmhpd SC7280_CX>; 5038 5039 #sound-dai-cells = <0>; 5040 5041 status = "disabled"; 5042 5043 ports { 5044 #address-cells = <1>; 5045 #size-cells = <0>; 5046 5047 port@0 { 5048 reg = <0>; 5049 dp_in: endpoint { 5050 remote-endpoint = <&dpu_intf0_out>; 5051 }; 5052 }; 5053 5054 port@1 { 5055 reg = <1>; 5056 mdss_dp_out: endpoint { 5057 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5058 }; 5059 }; 5060 }; 5061 5062 dp_opp_table: opp-table { 5063 compatible = "operating-points-v2"; 5064 5065 opp-160000000 { 5066 opp-hz = /bits/ 64 <160000000>; 5067 required-opps = <&rpmhpd_opp_low_svs>; 5068 }; 5069 5070 opp-270000000 { 5071 opp-hz = /bits/ 64 <270000000>; 5072 required-opps = <&rpmhpd_opp_svs>; 5073 }; 5074 5075 opp-540000000 { 5076 opp-hz = /bits/ 64 <540000000>; 5077 required-opps = <&rpmhpd_opp_svs_l1>; 5078 }; 5079 5080 opp-810000000 { 5081 opp-hz = /bits/ 64 <810000000>; 5082 required-opps = <&rpmhpd_opp_nom>; 5083 }; 5084 }; 5085 }; 5086 }; 5087 5088 pdc: interrupt-controller@b220000 { 5089 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 5090 reg = <0 0x0b220000 0 0x30000>; 5091 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 5092 <55 306 4>, <59 312 3>, <62 374 2>, 5093 <64 434 2>, <66 438 3>, <69 86 1>, 5094 <70 520 54>, <124 609 31>, <155 63 1>, 5095 <156 716 12>; 5096 #interrupt-cells = <2>; 5097 interrupt-parent = <&intc>; 5098 interrupt-controller; 5099 }; 5100 5101 pdc_reset: reset-controller@b5e0000 { 5102 compatible = "qcom,sc7280-pdc-global"; 5103 reg = <0 0x0b5e0000 0 0x20000>; 5104 #reset-cells = <1>; 5105 status = "reserved"; /* Owned by firmware */ 5106 }; 5107 5108 tsens0: thermal-sensor@c263000 { 5109 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5110 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5111 <0 0x0c222000 0 0x1ff>; /* SROT */ 5112 #qcom,sensors = <15>; 5113 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5115 interrupt-names = "uplow","critical"; 5116 #thermal-sensor-cells = <1>; 5117 }; 5118 5119 tsens1: thermal-sensor@c265000 { 5120 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5121 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5122 <0 0x0c223000 0 0x1ff>; /* SROT */ 5123 #qcom,sensors = <12>; 5124 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5126 interrupt-names = "uplow","critical"; 5127 #thermal-sensor-cells = <1>; 5128 }; 5129 5130 aoss_reset: reset-controller@c2a0000 { 5131 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 5132 reg = <0 0x0c2a0000 0 0x31000>; 5133 #reset-cells = <1>; 5134 }; 5135 5136 aoss_qmp: power-management@c300000 { 5137 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 5138 reg = <0 0x0c300000 0 0x400>; 5139 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5140 IPCC_MPROC_SIGNAL_GLINK_QMP 5141 IRQ_TYPE_EDGE_RISING>; 5142 mboxes = <&ipcc IPCC_CLIENT_AOP 5143 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5144 5145 #clock-cells = <0>; 5146 }; 5147 5148 sram@c3f0000 { 5149 compatible = "qcom,rpmh-stats"; 5150 reg = <0 0x0c3f0000 0 0x400>; 5151 }; 5152 5153 spmi_bus: spmi@c440000 { 5154 compatible = "qcom,spmi-pmic-arb"; 5155 reg = <0 0x0c440000 0 0x1100>, 5156 <0 0x0c600000 0 0x2000000>, 5157 <0 0x0e600000 0 0x100000>, 5158 <0 0x0e700000 0 0xa0000>, 5159 <0 0x0c40a000 0 0x26000>; 5160 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5161 interrupt-names = "periph_irq"; 5162 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5163 qcom,ee = <0>; 5164 qcom,channel = <0>; 5165 #address-cells = <2>; 5166 #size-cells = <0>; 5167 interrupt-controller; 5168 #interrupt-cells = <4>; 5169 }; 5170 5171 tlmm: pinctrl@f100000 { 5172 compatible = "qcom,sc7280-pinctrl"; 5173 reg = <0 0x0f100000 0 0x300000>; 5174 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5175 gpio-controller; 5176 #gpio-cells = <2>; 5177 interrupt-controller; 5178 #interrupt-cells = <2>; 5179 gpio-ranges = <&tlmm 0 0 175>; 5180 wakeup-parent = <&pdc>; 5181 5182 cci0_default: cci0-default-state { 5183 pins = "gpio69", "gpio70"; 5184 function = "cci_i2c"; 5185 drive-strength = <2>; 5186 bias-pull-up; 5187 }; 5188 5189 cci0_sleep: cci0-sleep-state { 5190 pins = "gpio69", "gpio70"; 5191 function = "cci_i2c"; 5192 drive-strength = <2>; 5193 bias-pull-down; 5194 }; 5195 5196 cci1_default: cci1-default-state { 5197 pins = "gpio71", "gpio72"; 5198 function = "cci_i2c"; 5199 drive-strength = <2>; 5200 bias-pull-up; 5201 }; 5202 5203 cci1_sleep: cci1-sleep-state { 5204 pins = "gpio71", "gpio72"; 5205 function = "cci_i2c"; 5206 drive-strength = <2>; 5207 bias-pull-down; 5208 }; 5209 5210 cci2_default: cci2-default-state { 5211 pins = "gpio73", "gpio74"; 5212 function = "cci_i2c"; 5213 drive-strength = <2>; 5214 bias-pull-up; 5215 }; 5216 5217 cci2_sleep: cci2-sleep-state { 5218 pins = "gpio73", "gpio74"; 5219 function = "cci_i2c"; 5220 drive-strength = <2>; 5221 bias-pull-down; 5222 }; 5223 5224 cci3_default: cci3-default-state { 5225 pins = "gpio75", "gpio76"; 5226 function = "cci_i2c"; 5227 drive-strength = <2>; 5228 bias-pull-up; 5229 }; 5230 5231 cci3_sleep: cci3-sleep-state { 5232 pins = "gpio75", "gpio76"; 5233 function = "cci_i2c"; 5234 drive-strength = <2>; 5235 bias-pull-down; 5236 }; 5237 5238 dp_hot_plug_det: dp-hot-plug-det-state { 5239 pins = "gpio47"; 5240 function = "dp_hot"; 5241 }; 5242 5243 edp_hot_plug_det: edp-hot-plug-det-state { 5244 pins = "gpio60"; 5245 function = "edp_hot"; 5246 }; 5247 5248 mi2s0_data0: mi2s0-data0-state { 5249 pins = "gpio98"; 5250 function = "mi2s0_data0"; 5251 }; 5252 5253 mi2s0_data1: mi2s0-data1-state { 5254 pins = "gpio99"; 5255 function = "mi2s0_data1"; 5256 }; 5257 5258 mi2s0_mclk: mi2s0-mclk-state { 5259 pins = "gpio96"; 5260 function = "pri_mi2s"; 5261 }; 5262 5263 mi2s0_sclk: mi2s0-sclk-state { 5264 pins = "gpio97"; 5265 function = "mi2s0_sck"; 5266 }; 5267 5268 mi2s0_ws: mi2s0-ws-state { 5269 pins = "gpio100"; 5270 function = "mi2s0_ws"; 5271 }; 5272 5273 mi2s1_data0: mi2s1-data0-state { 5274 pins = "gpio107"; 5275 function = "mi2s1_data0"; 5276 }; 5277 5278 mi2s1_sclk: mi2s1-sclk-state { 5279 pins = "gpio106"; 5280 function = "mi2s1_sck"; 5281 }; 5282 5283 mi2s1_ws: mi2s1-ws-state { 5284 pins = "gpio108"; 5285 function = "mi2s1_ws"; 5286 }; 5287 5288 pcie1_clkreq_n: pcie1-clkreq-n-state { 5289 pins = "gpio79"; 5290 function = "pcie1_clkreqn"; 5291 }; 5292 5293 qspi_clk: qspi-clk-state { 5294 pins = "gpio14"; 5295 function = "qspi_clk"; 5296 }; 5297 5298 qspi_cs0: qspi-cs0-state { 5299 pins = "gpio15"; 5300 function = "qspi_cs"; 5301 }; 5302 5303 qspi_cs1: qspi-cs1-state { 5304 pins = "gpio19"; 5305 function = "qspi_cs"; 5306 }; 5307 5308 qspi_data0: qspi-data0-state { 5309 pins = "gpio12"; 5310 function = "qspi_data"; 5311 }; 5312 5313 qspi_data1: qspi-data1-state { 5314 pins = "gpio13"; 5315 function = "qspi_data"; 5316 }; 5317 5318 qspi_data23: qspi-data23-state { 5319 pins = "gpio16", "gpio17"; 5320 function = "qspi_data"; 5321 }; 5322 5323 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5324 pins = "gpio0", "gpio1"; 5325 function = "qup00"; 5326 }; 5327 5328 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5329 pins = "gpio4", "gpio5"; 5330 function = "qup01"; 5331 }; 5332 5333 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5334 pins = "gpio8", "gpio9"; 5335 function = "qup02"; 5336 }; 5337 5338 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5339 pins = "gpio12", "gpio13"; 5340 function = "qup03"; 5341 }; 5342 5343 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5344 pins = "gpio16", "gpio17"; 5345 function = "qup04"; 5346 }; 5347 5348 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5349 pins = "gpio20", "gpio21"; 5350 function = "qup05"; 5351 }; 5352 5353 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5354 pins = "gpio24", "gpio25"; 5355 function = "qup06"; 5356 }; 5357 5358 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5359 pins = "gpio28", "gpio29"; 5360 function = "qup07"; 5361 }; 5362 5363 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5364 pins = "gpio32", "gpio33"; 5365 function = "qup10"; 5366 }; 5367 5368 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5369 pins = "gpio36", "gpio37"; 5370 function = "qup11"; 5371 }; 5372 5373 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5374 pins = "gpio40", "gpio41"; 5375 function = "qup12"; 5376 }; 5377 5378 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5379 pins = "gpio44", "gpio45"; 5380 function = "qup13"; 5381 }; 5382 5383 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5384 pins = "gpio48", "gpio49"; 5385 function = "qup14"; 5386 }; 5387 5388 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5389 pins = "gpio52", "gpio53"; 5390 function = "qup15"; 5391 }; 5392 5393 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5394 pins = "gpio56", "gpio57"; 5395 function = "qup16"; 5396 }; 5397 5398 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5399 pins = "gpio60", "gpio61"; 5400 function = "qup17"; 5401 }; 5402 5403 qup_spi0_data_clk: qup-spi0-data-clk-state { 5404 pins = "gpio0", "gpio1", "gpio2"; 5405 function = "qup00"; 5406 }; 5407 5408 qup_spi0_cs: qup-spi0-cs-state { 5409 pins = "gpio3"; 5410 function = "qup00"; 5411 }; 5412 5413 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5414 pins = "gpio3"; 5415 function = "gpio"; 5416 }; 5417 5418 qup_spi1_data_clk: qup-spi1-data-clk-state { 5419 pins = "gpio4", "gpio5", "gpio6"; 5420 function = "qup01"; 5421 }; 5422 5423 qup_spi1_cs: qup-spi1-cs-state { 5424 pins = "gpio7"; 5425 function = "qup01"; 5426 }; 5427 5428 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5429 pins = "gpio7"; 5430 function = "gpio"; 5431 }; 5432 5433 qup_spi2_data_clk: qup-spi2-data-clk-state { 5434 pins = "gpio8", "gpio9", "gpio10"; 5435 function = "qup02"; 5436 }; 5437 5438 qup_spi2_cs: qup-spi2-cs-state { 5439 pins = "gpio11"; 5440 function = "qup02"; 5441 }; 5442 5443 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5444 pins = "gpio11"; 5445 function = "gpio"; 5446 }; 5447 5448 qup_spi3_data_clk: qup-spi3-data-clk-state { 5449 pins = "gpio12", "gpio13", "gpio14"; 5450 function = "qup03"; 5451 }; 5452 5453 qup_spi3_cs: qup-spi3-cs-state { 5454 pins = "gpio15"; 5455 function = "qup03"; 5456 }; 5457 5458 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5459 pins = "gpio15"; 5460 function = "gpio"; 5461 }; 5462 5463 qup_spi4_data_clk: qup-spi4-data-clk-state { 5464 pins = "gpio16", "gpio17", "gpio18"; 5465 function = "qup04"; 5466 }; 5467 5468 qup_spi4_cs: qup-spi4-cs-state { 5469 pins = "gpio19"; 5470 function = "qup04"; 5471 }; 5472 5473 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5474 pins = "gpio19"; 5475 function = "gpio"; 5476 }; 5477 5478 qup_spi5_data_clk: qup-spi5-data-clk-state { 5479 pins = "gpio20", "gpio21", "gpio22"; 5480 function = "qup05"; 5481 }; 5482 5483 qup_spi5_cs: qup-spi5-cs-state { 5484 pins = "gpio23"; 5485 function = "qup05"; 5486 }; 5487 5488 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5489 pins = "gpio23"; 5490 function = "gpio"; 5491 }; 5492 5493 qup_spi6_data_clk: qup-spi6-data-clk-state { 5494 pins = "gpio24", "gpio25", "gpio26"; 5495 function = "qup06"; 5496 }; 5497 5498 qup_spi6_cs: qup-spi6-cs-state { 5499 pins = "gpio27"; 5500 function = "qup06"; 5501 }; 5502 5503 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5504 pins = "gpio27"; 5505 function = "gpio"; 5506 }; 5507 5508 qup_spi7_data_clk: qup-spi7-data-clk-state { 5509 pins = "gpio28", "gpio29", "gpio30"; 5510 function = "qup07"; 5511 }; 5512 5513 qup_spi7_cs: qup-spi7-cs-state { 5514 pins = "gpio31"; 5515 function = "qup07"; 5516 }; 5517 5518 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5519 pins = "gpio31"; 5520 function = "gpio"; 5521 }; 5522 5523 qup_spi8_data_clk: qup-spi8-data-clk-state { 5524 pins = "gpio32", "gpio33", "gpio34"; 5525 function = "qup10"; 5526 }; 5527 5528 qup_spi8_cs: qup-spi8-cs-state { 5529 pins = "gpio35"; 5530 function = "qup10"; 5531 }; 5532 5533 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5534 pins = "gpio35"; 5535 function = "gpio"; 5536 }; 5537 5538 qup_spi9_data_clk: qup-spi9-data-clk-state { 5539 pins = "gpio36", "gpio37", "gpio38"; 5540 function = "qup11"; 5541 }; 5542 5543 qup_spi9_cs: qup-spi9-cs-state { 5544 pins = "gpio39"; 5545 function = "qup11"; 5546 }; 5547 5548 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5549 pins = "gpio39"; 5550 function = "gpio"; 5551 }; 5552 5553 qup_spi10_data_clk: qup-spi10-data-clk-state { 5554 pins = "gpio40", "gpio41", "gpio42"; 5555 function = "qup12"; 5556 }; 5557 5558 qup_spi10_cs: qup-spi10-cs-state { 5559 pins = "gpio43"; 5560 function = "qup12"; 5561 }; 5562 5563 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5564 pins = "gpio43"; 5565 function = "gpio"; 5566 }; 5567 5568 qup_spi11_data_clk: qup-spi11-data-clk-state { 5569 pins = "gpio44", "gpio45", "gpio46"; 5570 function = "qup13"; 5571 }; 5572 5573 qup_spi11_cs: qup-spi11-cs-state { 5574 pins = "gpio47"; 5575 function = "qup13"; 5576 }; 5577 5578 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5579 pins = "gpio47"; 5580 function = "gpio"; 5581 }; 5582 5583 qup_spi12_data_clk: qup-spi12-data-clk-state { 5584 pins = "gpio48", "gpio49", "gpio50"; 5585 function = "qup14"; 5586 }; 5587 5588 qup_spi12_cs: qup-spi12-cs-state { 5589 pins = "gpio51"; 5590 function = "qup14"; 5591 }; 5592 5593 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5594 pins = "gpio51"; 5595 function = "gpio"; 5596 }; 5597 5598 qup_spi13_data_clk: qup-spi13-data-clk-state { 5599 pins = "gpio52", "gpio53", "gpio54"; 5600 function = "qup15"; 5601 }; 5602 5603 qup_spi13_cs: qup-spi13-cs-state { 5604 pins = "gpio55"; 5605 function = "qup15"; 5606 }; 5607 5608 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5609 pins = "gpio55"; 5610 function = "gpio"; 5611 }; 5612 5613 qup_spi14_data_clk: qup-spi14-data-clk-state { 5614 pins = "gpio56", "gpio57", "gpio58"; 5615 function = "qup16"; 5616 }; 5617 5618 qup_spi14_cs: qup-spi14-cs-state { 5619 pins = "gpio59"; 5620 function = "qup16"; 5621 }; 5622 5623 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5624 pins = "gpio59"; 5625 function = "gpio"; 5626 }; 5627 5628 qup_spi15_data_clk: qup-spi15-data-clk-state { 5629 pins = "gpio60", "gpio61", "gpio62"; 5630 function = "qup17"; 5631 }; 5632 5633 qup_spi15_cs: qup-spi15-cs-state { 5634 pins = "gpio63"; 5635 function = "qup17"; 5636 }; 5637 5638 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5639 pins = "gpio63"; 5640 function = "gpio"; 5641 }; 5642 5643 qup_uart0_cts: qup-uart0-cts-state { 5644 pins = "gpio0"; 5645 function = "qup00"; 5646 }; 5647 5648 qup_uart0_rts: qup-uart0-rts-state { 5649 pins = "gpio1"; 5650 function = "qup00"; 5651 }; 5652 5653 qup_uart0_tx: qup-uart0-tx-state { 5654 pins = "gpio2"; 5655 function = "qup00"; 5656 }; 5657 5658 qup_uart0_rx: qup-uart0-rx-state { 5659 pins = "gpio3"; 5660 function = "qup00"; 5661 }; 5662 5663 qup_uart1_cts: qup-uart1-cts-state { 5664 pins = "gpio4"; 5665 function = "qup01"; 5666 }; 5667 5668 qup_uart1_rts: qup-uart1-rts-state { 5669 pins = "gpio5"; 5670 function = "qup01"; 5671 }; 5672 5673 qup_uart1_tx: qup-uart1-tx-state { 5674 pins = "gpio6"; 5675 function = "qup01"; 5676 }; 5677 5678 qup_uart1_rx: qup-uart1-rx-state { 5679 pins = "gpio7"; 5680 function = "qup01"; 5681 }; 5682 5683 qup_uart2_cts: qup-uart2-cts-state { 5684 pins = "gpio8"; 5685 function = "qup02"; 5686 }; 5687 5688 qup_uart2_rts: qup-uart2-rts-state { 5689 pins = "gpio9"; 5690 function = "qup02"; 5691 }; 5692 5693 qup_uart2_tx: qup-uart2-tx-state { 5694 pins = "gpio10"; 5695 function = "qup02"; 5696 }; 5697 5698 qup_uart2_rx: qup-uart2-rx-state { 5699 pins = "gpio11"; 5700 function = "qup02"; 5701 }; 5702 5703 qup_uart3_cts: qup-uart3-cts-state { 5704 pins = "gpio12"; 5705 function = "qup03"; 5706 }; 5707 5708 qup_uart3_rts: qup-uart3-rts-state { 5709 pins = "gpio13"; 5710 function = "qup03"; 5711 }; 5712 5713 qup_uart3_tx: qup-uart3-tx-state { 5714 pins = "gpio14"; 5715 function = "qup03"; 5716 }; 5717 5718 qup_uart3_rx: qup-uart3-rx-state { 5719 pins = "gpio15"; 5720 function = "qup03"; 5721 }; 5722 5723 qup_uart4_cts: qup-uart4-cts-state { 5724 pins = "gpio16"; 5725 function = "qup04"; 5726 }; 5727 5728 qup_uart4_rts: qup-uart4-rts-state { 5729 pins = "gpio17"; 5730 function = "qup04"; 5731 }; 5732 5733 qup_uart4_tx: qup-uart4-tx-state { 5734 pins = "gpio18"; 5735 function = "qup04"; 5736 }; 5737 5738 qup_uart4_rx: qup-uart4-rx-state { 5739 pins = "gpio19"; 5740 function = "qup04"; 5741 }; 5742 5743 qup_uart5_tx: qup-uart5-tx-state { 5744 pins = "gpio22"; 5745 function = "qup05"; 5746 }; 5747 5748 qup_uart5_rx: qup-uart5-rx-state { 5749 pins = "gpio23"; 5750 function = "qup05"; 5751 }; 5752 5753 qup_uart6_cts: qup-uart6-cts-state { 5754 pins = "gpio24"; 5755 function = "qup06"; 5756 }; 5757 5758 qup_uart6_rts: qup-uart6-rts-state { 5759 pins = "gpio25"; 5760 function = "qup06"; 5761 }; 5762 5763 qup_uart6_tx: qup-uart6-tx-state { 5764 pins = "gpio26"; 5765 function = "qup06"; 5766 }; 5767 5768 qup_uart6_rx: qup-uart6-rx-state { 5769 pins = "gpio27"; 5770 function = "qup06"; 5771 }; 5772 5773 qup_uart7_cts: qup-uart7-cts-state { 5774 pins = "gpio28"; 5775 function = "qup07"; 5776 }; 5777 5778 qup_uart7_rts: qup-uart7-rts-state { 5779 pins = "gpio29"; 5780 function = "qup07"; 5781 }; 5782 5783 qup_uart7_tx: qup-uart7-tx-state { 5784 pins = "gpio30"; 5785 function = "qup07"; 5786 }; 5787 5788 qup_uart7_rx: qup-uart7-rx-state { 5789 pins = "gpio31"; 5790 function = "qup07"; 5791 }; 5792 5793 qup_uart8_cts: qup-uart8-cts-state { 5794 pins = "gpio32"; 5795 function = "qup10"; 5796 }; 5797 5798 qup_uart8_rts: qup-uart8-rts-state { 5799 pins = "gpio33"; 5800 function = "qup10"; 5801 }; 5802 5803 qup_uart8_tx: qup-uart8-tx-state { 5804 pins = "gpio34"; 5805 function = "qup10"; 5806 }; 5807 5808 qup_uart8_rx: qup-uart8-rx-state { 5809 pins = "gpio35"; 5810 function = "qup10"; 5811 }; 5812 5813 qup_uart9_cts: qup-uart9-cts-state { 5814 pins = "gpio36"; 5815 function = "qup11"; 5816 }; 5817 5818 qup_uart9_rts: qup-uart9-rts-state { 5819 pins = "gpio37"; 5820 function = "qup11"; 5821 }; 5822 5823 qup_uart9_tx: qup-uart9-tx-state { 5824 pins = "gpio38"; 5825 function = "qup11"; 5826 }; 5827 5828 qup_uart9_rx: qup-uart9-rx-state { 5829 pins = "gpio39"; 5830 function = "qup11"; 5831 }; 5832 5833 qup_uart10_cts: qup-uart10-cts-state { 5834 pins = "gpio40"; 5835 function = "qup12"; 5836 }; 5837 5838 qup_uart10_rts: qup-uart10-rts-state { 5839 pins = "gpio41"; 5840 function = "qup12"; 5841 }; 5842 5843 qup_uart10_tx: qup-uart10-tx-state { 5844 pins = "gpio42"; 5845 function = "qup12"; 5846 }; 5847 5848 qup_uart10_rx: qup-uart10-rx-state { 5849 pins = "gpio43"; 5850 function = "qup12"; 5851 }; 5852 5853 qup_uart11_cts: qup-uart11-cts-state { 5854 pins = "gpio44"; 5855 function = "qup13"; 5856 }; 5857 5858 qup_uart11_rts: qup-uart11-rts-state { 5859 pins = "gpio45"; 5860 function = "qup13"; 5861 }; 5862 5863 qup_uart11_tx: qup-uart11-tx-state { 5864 pins = "gpio46"; 5865 function = "qup13"; 5866 }; 5867 5868 qup_uart11_rx: qup-uart11-rx-state { 5869 pins = "gpio47"; 5870 function = "qup13"; 5871 }; 5872 5873 qup_uart12_cts: qup-uart12-cts-state { 5874 pins = "gpio48"; 5875 function = "qup14"; 5876 }; 5877 5878 qup_uart12_rts: qup-uart12-rts-state { 5879 pins = "gpio49"; 5880 function = "qup14"; 5881 }; 5882 5883 qup_uart12_tx: qup-uart12-tx-state { 5884 pins = "gpio50"; 5885 function = "qup14"; 5886 }; 5887 5888 qup_uart12_rx: qup-uart12-rx-state { 5889 pins = "gpio51"; 5890 function = "qup14"; 5891 }; 5892 5893 qup_uart13_cts: qup-uart13-cts-state { 5894 pins = "gpio52"; 5895 function = "qup15"; 5896 }; 5897 5898 qup_uart13_rts: qup-uart13-rts-state { 5899 pins = "gpio53"; 5900 function = "qup15"; 5901 }; 5902 5903 qup_uart13_tx: qup-uart13-tx-state { 5904 pins = "gpio54"; 5905 function = "qup15"; 5906 }; 5907 5908 qup_uart13_rx: qup-uart13-rx-state { 5909 pins = "gpio55"; 5910 function = "qup15"; 5911 }; 5912 5913 qup_uart14_cts: qup-uart14-cts-state { 5914 pins = "gpio56"; 5915 function = "qup16"; 5916 }; 5917 5918 qup_uart14_rts: qup-uart14-rts-state { 5919 pins = "gpio57"; 5920 function = "qup16"; 5921 }; 5922 5923 qup_uart14_tx: qup-uart14-tx-state { 5924 pins = "gpio58"; 5925 function = "qup16"; 5926 }; 5927 5928 qup_uart14_rx: qup-uart14-rx-state { 5929 pins = "gpio59"; 5930 function = "qup16"; 5931 }; 5932 5933 qup_uart15_cts: qup-uart15-cts-state { 5934 pins = "gpio60"; 5935 function = "qup17"; 5936 }; 5937 5938 qup_uart15_rts: qup-uart15-rts-state { 5939 pins = "gpio61"; 5940 function = "qup17"; 5941 }; 5942 5943 qup_uart15_tx: qup-uart15-tx-state { 5944 pins = "gpio62"; 5945 function = "qup17"; 5946 }; 5947 5948 qup_uart15_rx: qup-uart15-rx-state { 5949 pins = "gpio63"; 5950 function = "qup17"; 5951 }; 5952 5953 sdc1_clk: sdc1-clk-state { 5954 pins = "sdc1_clk"; 5955 }; 5956 5957 sdc1_cmd: sdc1-cmd-state { 5958 pins = "sdc1_cmd"; 5959 }; 5960 5961 sdc1_data: sdc1-data-state { 5962 pins = "sdc1_data"; 5963 }; 5964 5965 sdc1_rclk: sdc1-rclk-state { 5966 pins = "sdc1_rclk"; 5967 }; 5968 5969 sdc1_clk_sleep: sdc1-clk-sleep-state { 5970 pins = "sdc1_clk"; 5971 drive-strength = <2>; 5972 bias-bus-hold; 5973 }; 5974 5975 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5976 pins = "sdc1_cmd"; 5977 drive-strength = <2>; 5978 bias-bus-hold; 5979 }; 5980 5981 sdc1_data_sleep: sdc1-data-sleep-state { 5982 pins = "sdc1_data"; 5983 drive-strength = <2>; 5984 bias-bus-hold; 5985 }; 5986 5987 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5988 pins = "sdc1_rclk"; 5989 drive-strength = <2>; 5990 bias-bus-hold; 5991 }; 5992 5993 sdc2_clk: sdc2-clk-state { 5994 pins = "sdc2_clk"; 5995 }; 5996 5997 sdc2_cmd: sdc2-cmd-state { 5998 pins = "sdc2_cmd"; 5999 }; 6000 6001 sdc2_data: sdc2-data-state { 6002 pins = "sdc2_data"; 6003 }; 6004 6005 sdc2_clk_sleep: sdc2-clk-sleep-state { 6006 pins = "sdc2_clk"; 6007 drive-strength = <2>; 6008 bias-bus-hold; 6009 }; 6010 6011 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 6012 pins = "sdc2_cmd"; 6013 drive-strength = <2>; 6014 bias-bus-hold; 6015 }; 6016 6017 sdc2_data_sleep: sdc2-data-sleep-state { 6018 pins = "sdc2_data"; 6019 drive-strength = <2>; 6020 bias-bus-hold; 6021 }; 6022 }; 6023 6024 sram@146a5000 { 6025 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 6026 reg = <0 0x146a5000 0 0x6000>; 6027 6028 #address-cells = <1>; 6029 #size-cells = <1>; 6030 6031 ranges = <0 0 0x146a5000 0x6000>; 6032 6033 pil-reloc@594c { 6034 compatible = "qcom,pil-reloc-info"; 6035 reg = <0x594c 0xc8>; 6036 }; 6037 }; 6038 6039 apps_smmu: iommu@15000000 { 6040 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 6041 reg = <0 0x15000000 0 0x100000>; 6042 #iommu-cells = <2>; 6043 #global-interrupts = <1>; 6044 dma-coherent; 6045 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 6046 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 6047 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 6048 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6049 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6050 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6051 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6052 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6053 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6054 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6055 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6056 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6057 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6058 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6059 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6060 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6061 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6062 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6063 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6064 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6065 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6066 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6067 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6068 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6069 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6070 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6071 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6072 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6073 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6074 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6075 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6076 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6077 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6078 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6079 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6080 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6081 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6082 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6083 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6084 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6085 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6086 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6087 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6088 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6089 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6090 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6091 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6092 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6093 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6094 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6095 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6096 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6097 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6098 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6099 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6100 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6101 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6102 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6103 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6104 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6105 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6106 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6107 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6108 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6109 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6110 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6111 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6112 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6113 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6114 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6115 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6116 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6117 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6118 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6119 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6120 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6121 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6122 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6123 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6124 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6125 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 6126 }; 6127 6128 anoc_1_tbu: tbu@151dd000 { 6129 compatible = "qcom,sc7280-tbu"; 6130 reg = <0x0 0x151dd000 0x0 0x1000>; 6131 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6132 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6133 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 6134 }; 6135 6136 anoc_2_tbu: tbu@151e1000 { 6137 compatible = "qcom,sc7280-tbu"; 6138 reg = <0x0 0x151e1000 0x0 0x1000>; 6139 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6140 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6141 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 6142 }; 6143 6144 mnoc_hf_0_tbu: tbu@151e5000 { 6145 compatible = "qcom,sc7280-tbu"; 6146 reg = <0x0 0x151e5000 0x0 0x1000>; 6147 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6148 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6149 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 6150 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 6151 }; 6152 6153 mnoc_hf_1_tbu: tbu@151e9000 { 6154 compatible = "qcom,sc7280-tbu"; 6155 reg = <0x0 0x151e9000 0x0 0x1000>; 6156 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6157 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6158 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 6159 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 6160 }; 6161 6162 compute_dsp_1_tbu: tbu@151ed000 { 6163 compatible = "qcom,sc7280-tbu"; 6164 reg = <0x0 0x151ed000 0x0 0x1000>; 6165 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6166 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6167 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; 6168 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 6169 }; 6170 6171 compute_dsp_0_tbu: tbu@151f1000 { 6172 compatible = "qcom,sc7280-tbu"; 6173 reg = <0x0 0x151f1000 0x0 0x1000>; 6174 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6176 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 6177 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 6178 }; 6179 6180 adsp_tbu: tbu@151f5000 { 6181 compatible = "qcom,sc7280-tbu"; 6182 reg = <0x0 0x151f5000 0x0 0x1000>; 6183 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6184 &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 6185 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 6186 }; 6187 6188 anoc_1_pcie_tbu: tbu@151f9000 { 6189 compatible = "qcom,sc7280-tbu"; 6190 reg = <0x0 0x151f9000 0x0 0x1000>; 6191 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6192 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6193 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 6194 }; 6195 6196 mnoc_sf_0_tbu: tbu@151fd000 { 6197 compatible = "qcom,sc7280-tbu"; 6198 reg = <0x0 0x151fd000 0x0 0x1000>; 6199 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 6200 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6201 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; 6202 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; 6203 }; 6204 6205 intc: interrupt-controller@17a00000 { 6206 compatible = "arm,gic-v3"; 6207 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 6208 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 6209 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 6210 #interrupt-cells = <3>; 6211 interrupt-controller; 6212 #address-cells = <2>; 6213 #size-cells = <2>; 6214 ranges; 6215 6216 msi-controller@17a40000 { 6217 compatible = "arm,gic-v3-its"; 6218 reg = <0 0x17a40000 0 0x20000>; 6219 msi-controller; 6220 #msi-cells = <1>; 6221 status = "disabled"; 6222 }; 6223 }; 6224 6225 watchdog: watchdog@17c10000 { 6226 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 6227 reg = <0 0x17c10000 0 0x1000>; 6228 clocks = <&sleep_clk>; 6229 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6230 status = "reserved"; /* Owned by Gunyah hyp */ 6231 }; 6232 6233 timer@17c20000 { 6234 #address-cells = <1>; 6235 #size-cells = <1>; 6236 ranges = <0 0 0 0x20000000>; 6237 compatible = "arm,armv7-timer-mem"; 6238 reg = <0 0x17c20000 0 0x1000>; 6239 6240 frame@17c21000 { 6241 frame-number = <0>; 6242 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6243 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6244 reg = <0x17c21000 0x1000>, 6245 <0x17c22000 0x1000>; 6246 }; 6247 6248 frame@17c23000 { 6249 frame-number = <1>; 6250 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6251 reg = <0x17c23000 0x1000>; 6252 status = "disabled"; 6253 }; 6254 6255 frame@17c25000 { 6256 frame-number = <2>; 6257 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6258 reg = <0x17c25000 0x1000>; 6259 status = "disabled"; 6260 }; 6261 6262 frame@17c27000 { 6263 frame-number = <3>; 6264 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6265 reg = <0x17c27000 0x1000>; 6266 status = "disabled"; 6267 }; 6268 6269 frame@17c29000 { 6270 frame-number = <4>; 6271 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6272 reg = <0x17c29000 0x1000>; 6273 status = "disabled"; 6274 }; 6275 6276 frame@17c2b000 { 6277 frame-number = <5>; 6278 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6279 reg = <0x17c2b000 0x1000>; 6280 status = "disabled"; 6281 }; 6282 6283 frame@17c2d000 { 6284 frame-number = <6>; 6285 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6286 reg = <0x17c2d000 0x1000>; 6287 status = "disabled"; 6288 }; 6289 }; 6290 6291 apps_rsc: rsc@18200000 { 6292 compatible = "qcom,rpmh-rsc"; 6293 reg = <0 0x18200000 0 0x10000>, 6294 <0 0x18210000 0 0x10000>, 6295 <0 0x18220000 0 0x10000>; 6296 reg-names = "drv-0", "drv-1", "drv-2"; 6297 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6298 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6299 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6300 qcom,tcs-offset = <0xd00>; 6301 qcom,drv-id = <2>; 6302 qcom,tcs-config = <ACTIVE_TCS 2>, 6303 <SLEEP_TCS 3>, 6304 <WAKE_TCS 3>, 6305 <CONTROL_TCS 1>; 6306 power-domains = <&cluster_pd>; 6307 6308 apps_bcm_voter: bcm-voter { 6309 compatible = "qcom,bcm-voter"; 6310 }; 6311 6312 rpmhpd: power-controller { 6313 compatible = "qcom,sc7280-rpmhpd"; 6314 #power-domain-cells = <1>; 6315 operating-points-v2 = <&rpmhpd_opp_table>; 6316 6317 rpmhpd_opp_table: opp-table { 6318 compatible = "operating-points-v2"; 6319 6320 rpmhpd_opp_ret: opp1 { 6321 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6322 }; 6323 6324 rpmhpd_opp_low_svs: opp2 { 6325 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6326 }; 6327 6328 rpmhpd_opp_svs: opp3 { 6329 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6330 }; 6331 6332 rpmhpd_opp_svs_l1: opp4 { 6333 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6334 }; 6335 6336 rpmhpd_opp_svs_l2: opp5 { 6337 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 6338 }; 6339 6340 rpmhpd_opp_nom: opp6 { 6341 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6342 }; 6343 6344 rpmhpd_opp_nom_l1: opp7 { 6345 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6346 }; 6347 6348 rpmhpd_opp_turbo: opp8 { 6349 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6350 }; 6351 6352 rpmhpd_opp_turbo_l1: opp9 { 6353 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6354 }; 6355 }; 6356 }; 6357 6358 rpmhcc: clock-controller { 6359 compatible = "qcom,sc7280-rpmh-clk"; 6360 clocks = <&xo_board>; 6361 clock-names = "xo"; 6362 #clock-cells = <1>; 6363 }; 6364 }; 6365 6366 epss_l3: interconnect@18590000 { 6367 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 6368 reg = <0 0x18590000 0 0x1000>; 6369 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6370 clock-names = "xo", "alternate"; 6371 #interconnect-cells = <1>; 6372 }; 6373 6374 cpufreq_hw: cpufreq@18591000 { 6375 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 6376 reg = <0 0x18591000 0 0x1000>, 6377 <0 0x18592000 0 0x1000>, 6378 <0 0x18593000 0 0x1000>; 6379 6380 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6381 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6382 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6383 interrupt-names = "dcvsh-irq-0", 6384 "dcvsh-irq-1", 6385 "dcvsh-irq-2"; 6386 6387 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6388 clock-names = "xo", "alternate"; 6389 #freq-domain-cells = <1>; 6390 #clock-cells = <1>; 6391 }; 6392 }; 6393 6394 sound: sound { 6395 }; 6396 6397 thermal_zones: thermal-zones { 6398 cpu0-thermal { 6399 polling-delay-passive = <250>; 6400 6401 thermal-sensors = <&tsens0 1>; 6402 6403 trips { 6404 cpu0_alert0: trip-point0 { 6405 temperature = <90000>; 6406 hysteresis = <2000>; 6407 type = "passive"; 6408 }; 6409 6410 cpu0_alert1: trip-point1 { 6411 temperature = <95000>; 6412 hysteresis = <2000>; 6413 type = "passive"; 6414 }; 6415 6416 cpu0_crit: cpu-crit { 6417 temperature = <110000>; 6418 hysteresis = <0>; 6419 type = "critical"; 6420 }; 6421 }; 6422 6423 cooling-maps { 6424 map0 { 6425 trip = <&cpu0_alert0>; 6426 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6427 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6428 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6429 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6430 }; 6431 map1 { 6432 trip = <&cpu0_alert1>; 6433 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6434 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6435 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6436 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6437 }; 6438 }; 6439 }; 6440 6441 cpu1-thermal { 6442 polling-delay-passive = <250>; 6443 6444 thermal-sensors = <&tsens0 2>; 6445 6446 trips { 6447 cpu1_alert0: trip-point0 { 6448 temperature = <90000>; 6449 hysteresis = <2000>; 6450 type = "passive"; 6451 }; 6452 6453 cpu1_alert1: trip-point1 { 6454 temperature = <95000>; 6455 hysteresis = <2000>; 6456 type = "passive"; 6457 }; 6458 6459 cpu1_crit: cpu-crit { 6460 temperature = <110000>; 6461 hysteresis = <0>; 6462 type = "critical"; 6463 }; 6464 }; 6465 6466 cooling-maps { 6467 map0 { 6468 trip = <&cpu1_alert0>; 6469 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6470 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6471 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6472 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6473 }; 6474 map1 { 6475 trip = <&cpu1_alert1>; 6476 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6477 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6478 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6479 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6480 }; 6481 }; 6482 }; 6483 6484 cpu2-thermal { 6485 polling-delay-passive = <250>; 6486 6487 thermal-sensors = <&tsens0 3>; 6488 6489 trips { 6490 cpu2_alert0: trip-point0 { 6491 temperature = <90000>; 6492 hysteresis = <2000>; 6493 type = "passive"; 6494 }; 6495 6496 cpu2_alert1: trip-point1 { 6497 temperature = <95000>; 6498 hysteresis = <2000>; 6499 type = "passive"; 6500 }; 6501 6502 cpu2_crit: cpu-crit { 6503 temperature = <110000>; 6504 hysteresis = <0>; 6505 type = "critical"; 6506 }; 6507 }; 6508 6509 cooling-maps { 6510 map0 { 6511 trip = <&cpu2_alert0>; 6512 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6513 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6514 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6515 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6516 }; 6517 map1 { 6518 trip = <&cpu2_alert1>; 6519 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6520 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6521 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6522 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6523 }; 6524 }; 6525 }; 6526 6527 cpu3-thermal { 6528 polling-delay-passive = <250>; 6529 6530 thermal-sensors = <&tsens0 4>; 6531 6532 trips { 6533 cpu3_alert0: trip-point0 { 6534 temperature = <90000>; 6535 hysteresis = <2000>; 6536 type = "passive"; 6537 }; 6538 6539 cpu3_alert1: trip-point1 { 6540 temperature = <95000>; 6541 hysteresis = <2000>; 6542 type = "passive"; 6543 }; 6544 6545 cpu3_crit: cpu-crit { 6546 temperature = <110000>; 6547 hysteresis = <0>; 6548 type = "critical"; 6549 }; 6550 }; 6551 6552 cooling-maps { 6553 map0 { 6554 trip = <&cpu3_alert0>; 6555 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6556 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6557 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6558 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6559 }; 6560 map1 { 6561 trip = <&cpu3_alert1>; 6562 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6563 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6564 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6565 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6566 }; 6567 }; 6568 }; 6569 6570 cpu4-thermal { 6571 polling-delay-passive = <250>; 6572 6573 thermal-sensors = <&tsens0 7>; 6574 6575 trips { 6576 cpu4_alert0: trip-point0 { 6577 temperature = <90000>; 6578 hysteresis = <2000>; 6579 type = "passive"; 6580 }; 6581 6582 cpu4_alert1: trip-point1 { 6583 temperature = <95000>; 6584 hysteresis = <2000>; 6585 type = "passive"; 6586 }; 6587 6588 cpu4_crit: cpu-crit { 6589 temperature = <110000>; 6590 hysteresis = <0>; 6591 type = "critical"; 6592 }; 6593 }; 6594 6595 cooling-maps { 6596 map0 { 6597 trip = <&cpu4_alert0>; 6598 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6599 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6600 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6601 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6602 }; 6603 map1 { 6604 trip = <&cpu4_alert1>; 6605 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6606 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6607 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6608 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6609 }; 6610 }; 6611 }; 6612 6613 cpu5-thermal { 6614 polling-delay-passive = <250>; 6615 6616 thermal-sensors = <&tsens0 8>; 6617 6618 trips { 6619 cpu5_alert0: trip-point0 { 6620 temperature = <90000>; 6621 hysteresis = <2000>; 6622 type = "passive"; 6623 }; 6624 6625 cpu5_alert1: trip-point1 { 6626 temperature = <95000>; 6627 hysteresis = <2000>; 6628 type = "passive"; 6629 }; 6630 6631 cpu5_crit: cpu-crit { 6632 temperature = <110000>; 6633 hysteresis = <0>; 6634 type = "critical"; 6635 }; 6636 }; 6637 6638 cooling-maps { 6639 map0 { 6640 trip = <&cpu5_alert0>; 6641 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6642 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6643 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6644 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6645 }; 6646 map1 { 6647 trip = <&cpu5_alert1>; 6648 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6649 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6650 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6651 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6652 }; 6653 }; 6654 }; 6655 6656 cpu6-thermal { 6657 polling-delay-passive = <250>; 6658 6659 thermal-sensors = <&tsens0 9>; 6660 6661 trips { 6662 cpu6_alert0: trip-point0 { 6663 temperature = <90000>; 6664 hysteresis = <2000>; 6665 type = "passive"; 6666 }; 6667 6668 cpu6_alert1: trip-point1 { 6669 temperature = <95000>; 6670 hysteresis = <2000>; 6671 type = "passive"; 6672 }; 6673 6674 cpu6_crit: cpu-crit { 6675 temperature = <110000>; 6676 hysteresis = <0>; 6677 type = "critical"; 6678 }; 6679 }; 6680 6681 cooling-maps { 6682 map0 { 6683 trip = <&cpu6_alert0>; 6684 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6685 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6686 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6687 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6688 }; 6689 map1 { 6690 trip = <&cpu6_alert1>; 6691 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6692 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6693 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6694 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6695 }; 6696 }; 6697 }; 6698 6699 cpu7-thermal { 6700 polling-delay-passive = <250>; 6701 6702 thermal-sensors = <&tsens0 10>; 6703 6704 trips { 6705 cpu7_alert0: trip-point0 { 6706 temperature = <90000>; 6707 hysteresis = <2000>; 6708 type = "passive"; 6709 }; 6710 6711 cpu7_alert1: trip-point1 { 6712 temperature = <95000>; 6713 hysteresis = <2000>; 6714 type = "passive"; 6715 }; 6716 6717 cpu7_crit: cpu-crit { 6718 temperature = <110000>; 6719 hysteresis = <0>; 6720 type = "critical"; 6721 }; 6722 }; 6723 6724 cooling-maps { 6725 map0 { 6726 trip = <&cpu7_alert0>; 6727 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6728 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6729 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6730 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6731 }; 6732 map1 { 6733 trip = <&cpu7_alert1>; 6734 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6735 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6736 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6737 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6738 }; 6739 }; 6740 }; 6741 6742 cpu8-thermal { 6743 polling-delay-passive = <250>; 6744 6745 thermal-sensors = <&tsens0 11>; 6746 6747 trips { 6748 cpu8_alert0: trip-point0 { 6749 temperature = <90000>; 6750 hysteresis = <2000>; 6751 type = "passive"; 6752 }; 6753 6754 cpu8_alert1: trip-point1 { 6755 temperature = <95000>; 6756 hysteresis = <2000>; 6757 type = "passive"; 6758 }; 6759 6760 cpu8_crit: cpu-crit { 6761 temperature = <110000>; 6762 hysteresis = <0>; 6763 type = "critical"; 6764 }; 6765 }; 6766 6767 cooling-maps { 6768 map0 { 6769 trip = <&cpu8_alert0>; 6770 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6771 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6772 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6773 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6774 }; 6775 map1 { 6776 trip = <&cpu8_alert1>; 6777 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6778 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6779 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6780 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6781 }; 6782 }; 6783 }; 6784 6785 cpu9-thermal { 6786 polling-delay-passive = <250>; 6787 6788 thermal-sensors = <&tsens0 12>; 6789 6790 trips { 6791 cpu9_alert0: trip-point0 { 6792 temperature = <90000>; 6793 hysteresis = <2000>; 6794 type = "passive"; 6795 }; 6796 6797 cpu9_alert1: trip-point1 { 6798 temperature = <95000>; 6799 hysteresis = <2000>; 6800 type = "passive"; 6801 }; 6802 6803 cpu9_crit: cpu-crit { 6804 temperature = <110000>; 6805 hysteresis = <0>; 6806 type = "critical"; 6807 }; 6808 }; 6809 6810 cooling-maps { 6811 map0 { 6812 trip = <&cpu9_alert0>; 6813 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6814 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6815 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6816 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6817 }; 6818 map1 { 6819 trip = <&cpu9_alert1>; 6820 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6821 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6822 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6823 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6824 }; 6825 }; 6826 }; 6827 6828 cpu10-thermal { 6829 polling-delay-passive = <250>; 6830 6831 thermal-sensors = <&tsens0 13>; 6832 6833 trips { 6834 cpu10_alert0: trip-point0 { 6835 temperature = <90000>; 6836 hysteresis = <2000>; 6837 type = "passive"; 6838 }; 6839 6840 cpu10_alert1: trip-point1 { 6841 temperature = <95000>; 6842 hysteresis = <2000>; 6843 type = "passive"; 6844 }; 6845 6846 cpu10_crit: cpu-crit { 6847 temperature = <110000>; 6848 hysteresis = <0>; 6849 type = "critical"; 6850 }; 6851 }; 6852 6853 cooling-maps { 6854 map0 { 6855 trip = <&cpu10_alert0>; 6856 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6857 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6858 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6859 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6860 }; 6861 map1 { 6862 trip = <&cpu10_alert1>; 6863 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6864 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6865 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6866 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6867 }; 6868 }; 6869 }; 6870 6871 cpu11-thermal { 6872 polling-delay-passive = <250>; 6873 6874 thermal-sensors = <&tsens0 14>; 6875 6876 trips { 6877 cpu11_alert0: trip-point0 { 6878 temperature = <90000>; 6879 hysteresis = <2000>; 6880 type = "passive"; 6881 }; 6882 6883 cpu11_alert1: trip-point1 { 6884 temperature = <95000>; 6885 hysteresis = <2000>; 6886 type = "passive"; 6887 }; 6888 6889 cpu11_crit: cpu-crit { 6890 temperature = <110000>; 6891 hysteresis = <0>; 6892 type = "critical"; 6893 }; 6894 }; 6895 6896 cooling-maps { 6897 map0 { 6898 trip = <&cpu11_alert0>; 6899 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6900 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6901 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6902 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6903 }; 6904 map1 { 6905 trip = <&cpu11_alert1>; 6906 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6907 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6908 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6909 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6910 }; 6911 }; 6912 }; 6913 6914 aoss0-thermal { 6915 polling-delay-passive = <0>; 6916 6917 thermal-sensors = <&tsens0 0>; 6918 6919 trips { 6920 aoss0_alert0: trip-point0 { 6921 temperature = <90000>; 6922 hysteresis = <2000>; 6923 type = "hot"; 6924 }; 6925 6926 aoss0_crit: aoss0-crit { 6927 temperature = <110000>; 6928 hysteresis = <0>; 6929 type = "critical"; 6930 }; 6931 }; 6932 }; 6933 6934 aoss1-thermal { 6935 polling-delay-passive = <0>; 6936 6937 thermal-sensors = <&tsens1 0>; 6938 6939 trips { 6940 aoss1_alert0: trip-point0 { 6941 temperature = <90000>; 6942 hysteresis = <2000>; 6943 type = "hot"; 6944 }; 6945 6946 aoss1_crit: aoss1-crit { 6947 temperature = <110000>; 6948 hysteresis = <0>; 6949 type = "critical"; 6950 }; 6951 }; 6952 }; 6953 6954 cpuss0-thermal { 6955 polling-delay-passive = <0>; 6956 6957 thermal-sensors = <&tsens0 5>; 6958 6959 trips { 6960 cpuss0_alert0: trip-point0 { 6961 temperature = <90000>; 6962 hysteresis = <2000>; 6963 type = "hot"; 6964 }; 6965 cpuss0_crit: cluster0-crit { 6966 temperature = <110000>; 6967 hysteresis = <0>; 6968 type = "critical"; 6969 }; 6970 }; 6971 }; 6972 6973 cpuss1-thermal { 6974 polling-delay-passive = <0>; 6975 6976 thermal-sensors = <&tsens0 6>; 6977 6978 trips { 6979 cpuss1_alert0: trip-point0 { 6980 temperature = <90000>; 6981 hysteresis = <2000>; 6982 type = "hot"; 6983 }; 6984 cpuss1_crit: cluster0-crit { 6985 temperature = <110000>; 6986 hysteresis = <0>; 6987 type = "critical"; 6988 }; 6989 }; 6990 }; 6991 6992 gpuss0-thermal { 6993 polling-delay-passive = <100>; 6994 6995 thermal-sensors = <&tsens1 1>; 6996 6997 trips { 6998 gpuss0_alert0: trip-point0 { 6999 temperature = <95000>; 7000 hysteresis = <2000>; 7001 type = "passive"; 7002 }; 7003 7004 gpuss0_crit: gpuss0-crit { 7005 temperature = <110000>; 7006 hysteresis = <0>; 7007 type = "critical"; 7008 }; 7009 }; 7010 7011 cooling-maps { 7012 map0 { 7013 trip = <&gpuss0_alert0>; 7014 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7015 }; 7016 }; 7017 }; 7018 7019 gpuss1-thermal { 7020 polling-delay-passive = <100>; 7021 7022 thermal-sensors = <&tsens1 2>; 7023 7024 trips { 7025 gpuss1_alert0: trip-point0 { 7026 temperature = <95000>; 7027 hysteresis = <2000>; 7028 type = "passive"; 7029 }; 7030 7031 gpuss1_crit: gpuss1-crit { 7032 temperature = <110000>; 7033 hysteresis = <0>; 7034 type = "critical"; 7035 }; 7036 }; 7037 7038 cooling-maps { 7039 map0 { 7040 trip = <&gpuss1_alert0>; 7041 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7042 }; 7043 }; 7044 }; 7045 7046 nspss0-thermal { 7047 thermal-sensors = <&tsens1 3>; 7048 7049 trips { 7050 nspss0_alert0: trip-point0 { 7051 temperature = <90000>; 7052 hysteresis = <2000>; 7053 type = "hot"; 7054 }; 7055 7056 nspss0_crit: nspss0-crit { 7057 temperature = <110000>; 7058 hysteresis = <0>; 7059 type = "critical"; 7060 }; 7061 }; 7062 }; 7063 7064 nspss1-thermal { 7065 thermal-sensors = <&tsens1 4>; 7066 7067 trips { 7068 nspss1_alert0: trip-point0 { 7069 temperature = <90000>; 7070 hysteresis = <2000>; 7071 type = "hot"; 7072 }; 7073 7074 nspss1_crit: nspss1-crit { 7075 temperature = <110000>; 7076 hysteresis = <0>; 7077 type = "critical"; 7078 }; 7079 }; 7080 }; 7081 7082 video-thermal { 7083 thermal-sensors = <&tsens1 5>; 7084 7085 trips { 7086 video_alert0: trip-point0 { 7087 temperature = <90000>; 7088 hysteresis = <2000>; 7089 type = "hot"; 7090 }; 7091 7092 video_crit: video-crit { 7093 temperature = <110000>; 7094 hysteresis = <0>; 7095 type = "critical"; 7096 }; 7097 }; 7098 }; 7099 7100 ddr-thermal { 7101 thermal-sensors = <&tsens1 6>; 7102 7103 trips { 7104 ddr_alert0: trip-point0 { 7105 temperature = <90000>; 7106 hysteresis = <2000>; 7107 type = "hot"; 7108 }; 7109 7110 ddr_crit: ddr-crit { 7111 temperature = <110000>; 7112 hysteresis = <0>; 7113 type = "critical"; 7114 }; 7115 }; 7116 }; 7117 7118 mdmss0-thermal { 7119 thermal-sensors = <&tsens1 7>; 7120 7121 trips { 7122 mdmss0_alert0: trip-point0 { 7123 temperature = <90000>; 7124 hysteresis = <2000>; 7125 type = "hot"; 7126 }; 7127 7128 mdmss0_crit: mdmss0-crit { 7129 temperature = <110000>; 7130 hysteresis = <0>; 7131 type = "critical"; 7132 }; 7133 }; 7134 }; 7135 7136 mdmss1-thermal { 7137 thermal-sensors = <&tsens1 8>; 7138 7139 trips { 7140 mdmss1_alert0: trip-point0 { 7141 temperature = <90000>; 7142 hysteresis = <2000>; 7143 type = "hot"; 7144 }; 7145 7146 mdmss1_crit: mdmss1-crit { 7147 temperature = <110000>; 7148 hysteresis = <0>; 7149 type = "critical"; 7150 }; 7151 }; 7152 }; 7153 7154 mdmss2-thermal { 7155 thermal-sensors = <&tsens1 9>; 7156 7157 trips { 7158 mdmss2_alert0: trip-point0 { 7159 temperature = <90000>; 7160 hysteresis = <2000>; 7161 type = "hot"; 7162 }; 7163 7164 mdmss2_crit: mdmss2-crit { 7165 temperature = <110000>; 7166 hysteresis = <0>; 7167 type = "critical"; 7168 }; 7169 }; 7170 }; 7171 7172 mdmss3-thermal { 7173 thermal-sensors = <&tsens1 10>; 7174 7175 trips { 7176 mdmss3_alert0: trip-point0 { 7177 temperature = <90000>; 7178 hysteresis = <2000>; 7179 type = "hot"; 7180 }; 7181 7182 mdmss3_crit: mdmss3-crit { 7183 temperature = <110000>; 7184 hysteresis = <0>; 7185 type = "critical"; 7186 }; 7187 }; 7188 }; 7189 7190 camera0-thermal { 7191 thermal-sensors = <&tsens1 11>; 7192 7193 trips { 7194 camera0_alert0: trip-point0 { 7195 temperature = <90000>; 7196 hysteresis = <2000>; 7197 type = "hot"; 7198 }; 7199 7200 camera0_crit: camera0-crit { 7201 temperature = <110000>; 7202 hysteresis = <0>; 7203 type = "critical"; 7204 }; 7205 }; 7206 }; 7207 }; 7208 7209 timer { 7210 compatible = "arm,armv8-timer"; 7211 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7212 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7213 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7214 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7215 }; 7216}; 7217