1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sar2130p-gcc.h> 8#include <dt-bindings/clock/qcom,sar2130p-gpucc.h> 9#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 10#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <19200000>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 power-domains = <&cpu_pd0>; 58 power-domain-names = "psci"; 59 #cooling-cells = <2>; 60 61 l2_0: l2-cache { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 next-level-cache = <&l3_0>; 66 67 l3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x0 0x100>; 79 clocks = <&cpufreq_hw 0>; 80 enable-method = "psci"; 81 next-level-cache = <&l2_100>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 power-domains = <&cpu_pd1>; 84 power-domain-names = "psci"; 85 #cooling-cells = <2>; 86 87 l2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&l3_0>; 92 }; 93 }; 94 95 cpu2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a55"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_200>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 power-domains = <&cpu_pd2>; 104 power-domain-names = "psci"; 105 #cooling-cells = <2>; 106 107 l2_200: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&l3_0>; 112 }; 113 }; 114 115 cpu3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x0 0x300>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 next-level-cache = <&l2_300>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 power-domains = <&cpu_pd3>; 124 power-domain-names = "psci"; 125 #cooling-cells = <2>; 126 127 l2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&l3_0>; 132 }; 133 }; 134 135 cpu-map { 136 cluster0 { 137 core0 { 138 cpu = <&cpu0>; 139 }; 140 141 core1 { 142 cpu = <&cpu1>; 143 }; 144 145 core2 { 146 cpu = <&cpu2>; 147 }; 148 149 core3 { 150 cpu = <&cpu3>; 151 }; 152 }; 153 }; 154 155 idle-states { 156 entry-method = "psci"; 157 158 cpu_sleep_0: cpu-sleep-0-0 { 159 compatible = "arm,idle-state"; 160 idle-state-name = "silver-power-collapse"; 161 arm,psci-suspend-param = <0x40000003>; 162 entry-latency-us = <549>; 163 exit-latency-us = <901>; 164 min-residency-us = <1774>; 165 local-timer-stop; 166 }; 167 168 cpu_sleep_1: cpu-sleep-0-1 { 169 compatible = "arm,idle-state"; 170 idle-state-name = "silver-rail-power-collapse"; 171 arm,psci-suspend-param = <0x40000004>; 172 entry-latency-us = <702>; 173 exit-latency-us = <915>; 174 min-residency-us = <4001>; 175 local-timer-stop; 176 }; 177 }; 178 179 domain-idle-states { 180 cluster_sleep_0: cluster-sleep-0 { 181 compatible = "domain-idle-state"; 182 arm,psci-suspend-param = <0x41000044>; 183 entry-latency-us = <2752>; 184 exit-latency-us = <3048>; 185 min-residency-us = <6118>; 186 }; 187 188 cluster_sleep_1: cluster-sleep-1 { 189 compatible = "domain-idle-state"; 190 arm,psci-suspend-param = <0x41002344>; 191 entry-latency-us = <3263>; 192 exit-latency-us = <4562>; 193 min-residency-us = <8467>; 194 }; 195 196 cluster_sleep_2: cluster-sleep-2 { 197 compatible = "domain-idle-state"; 198 arm,psci-suspend-param = <0x4100c344>; 199 entry-latency-us = <3638>; 200 exit-latency-us = <6562>; 201 min-residency-us = <9862>; 202 }; 203 }; 204 }; 205 206 firmware { 207 scm: scm { 208 compatible = "qcom,scm-sar2130p", "qcom,scm"; 209 qcom,dload-mode = <&tcsr_mutex 0x13000>; 210 interconnects = <&system_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 211 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 212 }; 213 }; 214 215 clk_virt: interconnect-0 { 216 compatible = "qcom,sar2130p-clk-virt"; 217 #interconnect-cells = <2>; 218 qcom,bcm-voters = <&apps_bcm_voter>; 219 }; 220 221 mc_virt: interconnect-1 { 222 compatible = "qcom,sar2130p-mc-virt"; 223 #interconnect-cells = <2>; 224 qcom,bcm-voters = <&apps_bcm_voter>; 225 }; 226 227 memory@80000000 { 228 device_type = "memory"; 229 /* We expect the bootloader to fill in the size */ 230 reg = <0x0 0x80000000 0x0 0x0>; 231 }; 232 233 pmu { 234 compatible = "arm,armv8-pmuv3"; 235 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 236 }; 237 238 psci { 239 compatible = "arm,psci-1.0"; 240 method = "smc"; 241 242 cpu_pd0: power-domain-cpu0 { 243 #power-domain-cells = <0>; 244 power-domains = <&cluster_pd>; 245 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 246 }; 247 248 cpu_pd1: power-domain-cpu1 { 249 #power-domain-cells = <0>; 250 power-domains = <&cluster_pd>; 251 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 252 }; 253 254 cpu_pd2: power-domain-cpu2 { 255 #power-domain-cells = <0>; 256 power-domains = <&cluster_pd>; 257 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 258 }; 259 260 cpu_pd3: power-domain-cpu3 { 261 #power-domain-cells = <0>; 262 power-domains = <&cluster_pd>; 263 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 264 }; 265 266 cluster_pd: power-domain-cpu-cluster0 { 267 #power-domain-cells = <0>; 268 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>; 269 }; 270 }; 271 272 reserved_memory: reserved-memory { 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 277 hyp_mem: hyp@80000000 { 278 reg = <0x0 0x80000000 0x0 0x600000>; 279 no-map; 280 }; 281 282 xbl_dt_log_mem: xbl-dt-log@80600000 { 283 reg = <0x0 0x80600000 0x0 0x40000>; 284 no-map; 285 }; 286 287 xbl_ramdump_mem: xbl-ramdump@80640000 { 288 reg = <0x0 0x80640000 0x0 0x1c0000>; 289 no-map; 290 }; 291 292 aop_image_mem: aop-image@80800000 { 293 reg = <0x0 0x80800000 0x0 0x60000>; 294 no-map; 295 }; 296 297 aop_cmd_db_mem: aop-cmd-db@80860000 { 298 compatible = "qcom,cmd-db"; 299 reg = <0x0 0x80860000 0x0 0x20000>; 300 no-map; 301 }; 302 303 aop_config_mem: aop-config@80880000 { 304 reg = <0x0 0x80880000 0x0 0x20000>; 305 no-map; 306 }; 307 308 tme_crash_dump_mem: tme-crash-dump@808a0000 { 309 reg = <0x0 0x808a0000 0x0 0x40000>; 310 no-map; 311 }; 312 313 tme_log_mem: tme-log@808e0000 { 314 reg = <0x0 0x808e0000 0x0 0x4000>; 315 no-map; 316 }; 317 318 uefi_log_mem: uefi-log@808e4000 { 319 reg = <0x0 0x808e4000 0x0 0x10000>; 320 no-map; 321 }; 322 323 secdata_apss_mem: secdata-apss@808ff000 { 324 reg = <0x0 0x808ff000 0x0 0x1000>; 325 no-map; 326 }; 327 328 smem: smem@80900000 { 329 compatible = "qcom,smem"; 330 reg = <0x0 0x80900000 0x0 0x200000>; 331 hwlocks = <&tcsr_mutex 3>; 332 no-map; 333 }; 334 335 cpucp_fw_mem: cpucp-fw@80b00000 { 336 reg = <0x0 0x80b00000 0x0 0x100000>; 337 no-map; 338 }; 339 340 helios_ram_dump_mem: helios-ram-dump@80c00000 { 341 reg = <0x0 0x80c00000 0x0 0xe00000>; 342 no-map; 343 }; 344 345 camera_mem: camera@84e00000 { 346 reg = <0x0 0x84e00000 0x0 0x800000>; 347 no-map; 348 }; 349 350 video_mem: video@86f00000 { 351 reg = <0x0 0x86f00000 0x0 0x500000>; 352 no-map; 353 }; 354 355 adsp_mem: adsp@87600000 { 356 reg = <0x0 0x87600000 0x0 0x1e00000>; 357 no-map; 358 }; 359 360 cdsp_mem: cdsp@89400000 { 361 reg = <0x0 0x89400000 0x0 0xf00000>; 362 no-map; 363 }; 364 365 ipa_fw_mem: ipa-fw@8a300000 { 366 reg = <0x0 0x8a300000 0x0 0x10000>; 367 no-map; 368 }; 369 370 ipa_gsi_mem: ipa-gsi@8a3a0000 { 371 reg = <0x0 0x8a310000 0x0 0xa000>; 372 no-map; 373 }; 374 375 gpu_micro_code_mem: gpu-micro-code@8a31a000 { 376 reg = <0x0 0x8a31a000 0x0 0x2000>; 377 no-map; 378 }; 379 380 cvp_mem: cvp@8a400000 { 381 reg = <0x0 0x8a400000 0x0 0x700000>; 382 no-map; 383 }; 384 385 xbl_sc_mem: xbl-sc@a6e00000 { 386 no-map; 387 reg = <0x0 0xa6e00000 0x0 0x40000>; 388 }; 389 390 global_sync_mem: global-sync@a6f00000 { 391 no-map; 392 reg = <0x0 0xa6f00000 0x0 0x100000>; 393 }; 394 395 tz_stat_mem: tz-stat@e8800000 { 396 no-map; 397 reg = <0x0 0xe8800000 0x0 0x100000>; 398 }; 399 400 tags_mem: tags@e8900000 { 401 no-map; 402 reg = <0x0 0xe8900000 0x0 0x500000>; 403 }; 404 405 qtee_mem: qtee@e8e00000 { 406 no-map; 407 reg = <0x0 0xe8e00000 0x0 0x500000>; 408 }; 409 410 trusted_apps_mem: trusted-apps@e9300000 { 411 no-map; 412 reg = <0x0 0xe9300000 0x0 0xc00000>; 413 }; 414 }; 415 416 smp2p-adsp { 417 compatible = "qcom,smp2p"; 418 qcom,smem = <443>, <429>; 419 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 420 IPCC_MPROC_SIGNAL_SMP2P 421 IRQ_TYPE_EDGE_RISING>; 422 mboxes = <&ipcc IPCC_CLIENT_LPASS 423 IPCC_MPROC_SIGNAL_SMP2P>; 424 425 qcom,local-pid = <0>; 426 qcom,remote-pid = <2>; 427 428 smp2p_adsp_out: master-kernel { 429 qcom,entry-name = "master-kernel"; 430 #qcom,smem-state-cells = <1>; 431 }; 432 433 smp2p_adsp_in: slave-kernel { 434 qcom,entry-name = "slave-kernel"; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 }; 438 }; 439 440 smp2p-cdsp { 441 compatible = "qcom,smp2p"; 442 qcom,smem = <94>, <432>; 443 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 444 IPCC_MPROC_SIGNAL_SMP2P 445 IRQ_TYPE_EDGE_RISING>; 446 mboxes = <&ipcc IPCC_CLIENT_CDSP 447 IPCC_MPROC_SIGNAL_SMP2P>; 448 449 qcom,local-pid = <0>; 450 qcom,remote-pid = <5>; 451 452 smp2p_cdsp_out: master-kernel { 453 qcom,entry-name = "master-kernel"; 454 #qcom,smem-state-cells = <1>; 455 }; 456 457 smp2p_cdsp_in: slave-kernel { 458 qcom,entry-name = "slave-kernel"; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 }; 462 }; 463 464 soc: soc@0 { 465 compatible = "simple-bus"; 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges = <0 0 0 0 0x10 0>; 469 dma-ranges = <0 0 0 0 0x10 0>; 470 471 gcc: clock-controller@100000 { 472 compatible = "qcom,sar2130p-gcc"; 473 reg = <0x0 0x00100000 0x0 0x1f4200>; 474 #clock-cells = <1>; 475 #reset-cells = <1>; 476 #power-domain-cells = <1>; 477 clocks = <&rpmhcc RPMH_CXO_CLK>, 478 <&sleep_clk>, 479 <&pcie0_phy>, 480 <&pcie1_phy>, 481 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 482 }; 483 484 sdhc_1: mmc@7c4000 { 485 compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5"; 486 reg = <0x0 0x007c4000 0x0 0x1000>, 487 <0x0 0x007c5000 0x0 0x1000>; 488 reg-names = "hc", "cqhci"; 489 490 iommus = <&apps_smmu 0x160 0x0>; 491 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-names = "hc_irq", "pwr_irq"; 494 495 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 496 <&gcc GCC_SDCC1_APPS_CLK>, 497 <&rpmhcc RPMH_CXO_CLK>; 498 clock-names = "iface", "core", "xo"; 499 interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 500 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 501 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 502 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; 503 interconnect-names = "sdhc-ddr","cpu-sdhc"; 504 power-domains = <&rpmhpd RPMHPD_CX>; 505 operating-points-v2 = <&sdhc1_opp_table>; 506 507 pinctrl-0 = <&sdc1_default>; 508 pinctrl-1 = <&sdc1_sleep>; 509 pinctrl-names = "default", "sleep"; 510 511 bus-width = <8>; 512 non-removable; 513 supports-cqe; 514 515 mmc-ddr-1_8v; 516 mmc-hs200-1_8v; 517 mmc-hs400-1_8v; 518 mmc-hs400-enhanced-strobe; 519 520 status = "disabled"; 521 522 sdhc1_opp_table: opp-table { 523 compatible = "operating-points-v2"; 524 525 opp-100000000 { 526 opp-hz = /bits/ 64 <100000000>; 527 required-opps = <&rpmhpd_opp_low_svs>; 528 opp-peak-kBps = <500000 200000>; 529 opp-avg-kBps = <104000 0>; 530 }; 531 532 opp-384000000 { 533 opp-hz = /bits/ 64 <384000000>; 534 required-opps = <&rpmhpd_opp_nom>; 535 opp-peak-kBps = <2500000 1000000>; 536 opp-avg-kBps = <400000 0>; 537 }; 538 }; 539 }; 540 541 gpi_dma0: dma-controller@900000 { 542 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma"; 543 reg = <0x0 0x00900000 0x0 0x60000>; 544 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 556 #dma-cells = <3>; 557 dma-channels = <12>; 558 dma-channel-mask = <0x7e>; 559 iommus = <&apps_smmu 0x76 0x0>; 560 561 status = "disabled"; 562 }; 563 564 qupv3_id_0: geniqup@9c0000 { 565 compatible = "qcom,geni-se-qup"; 566 reg = <0x0 0x009c0000 0x0 0x2000>; 567 clock-names = "m-ahb", "s-ahb"; 568 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 569 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 570 iommus = <&apps_smmu 0x63 0x0>; 571 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 572 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; 573 interconnect-names = "qup-core"; 574 #address-cells = <2>; 575 #size-cells = <2>; 576 ranges; 577 578 status = "disabled"; 579 580 i2c0: i2c@980000 { 581 compatible = "qcom,geni-i2c"; 582 reg = <0x0 0x00980000 0x0 0x4000>; 583 clock-names = "se"; 584 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 585 pinctrl-0 = <&qup_i2c0_data_clk>; 586 pinctrl-names = "default"; 587 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 591 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 592 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 593 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 594 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 595 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 596 interconnect-names = "qup-core", "qup-config", "qup-memory"; 597 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 598 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 599 dma-names = "tx", "rx"; 600 601 status = "disabled"; 602 }; 603 604 spi0: spi@980000 { 605 compatible = "qcom,geni-spi"; 606 reg = <0x0 0x00980000 0x0 0x4000>; 607 clock-names = "se"; 608 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 609 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 610 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>; 611 pinctrl-names = "default"; 612 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 613 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 614 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 615 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 616 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 617 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 618 interconnect-names = "qup-core", "qup-config", "qup-memory"; 619 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 620 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 621 dma-names = "tx", "rx"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 625 status = "disabled"; 626 }; 627 628 i2c1: i2c@984000 { 629 compatible = "qcom,geni-i2c"; 630 reg = <0x0 0x00984000 0x0 0x4000>; 631 clock-names = "se"; 632 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 633 pinctrl-0 = <&qup_i2c1_data_clk>; 634 pinctrl-names = "default"; 635 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 639 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 640 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 641 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 642 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 643 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 644 interconnect-names = "qup-core", "qup-config", "qup-memory"; 645 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 646 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 647 dma-names = "tx", "rx"; 648 649 status = "disabled"; 650 }; 651 652 spi1: spi@984000 { 653 compatible = "qcom,geni-spi"; 654 reg = <0x0 0x00984000 0x0 0x4000>; 655 clock-names = "se"; 656 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 657 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 658 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 659 pinctrl-names = "default"; 660 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 661 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 662 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 663 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 664 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 665 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 666 interconnect-names = "qup-core", "qup-config", "qup-memory"; 667 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 668 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 669 dma-names = "tx", "rx"; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 673 status = "disabled"; 674 }; 675 676 i2c2: i2c@988000 { 677 compatible = "qcom,geni-i2c"; 678 reg = <0x0 0x00988000 0x0 0x4000>; 679 clock-names = "se"; 680 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 681 pinctrl-0 = <&qup_i2c2_data_clk>; 682 pinctrl-names = "default"; 683 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 687 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 688 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 689 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 690 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 691 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 692 interconnect-names = "qup-core", "qup-config", "qup-memory"; 693 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 694 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 695 dma-names = "tx", "rx"; 696 697 status = "disabled"; 698 }; 699 700 spi2: spi@988000 { 701 compatible = "qcom,geni-spi"; 702 reg = <0x0 0x00988000 0x0 0x4000>; 703 clock-names = "se"; 704 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 705 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 706 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 707 pinctrl-names = "default"; 708 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 709 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 710 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 711 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 712 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 713 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 714 interconnect-names = "qup-core", "qup-config", "qup-memory"; 715 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 716 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 717 dma-names = "tx", "rx"; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 status = "disabled"; 722 }; 723 724 725 i2c3: i2c@98c000 { 726 compatible = "qcom,geni-i2c"; 727 reg = <0x0 0x0098c000 0x0 0x4000>; 728 clock-names = "se"; 729 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 730 pinctrl-0 = <&qup_i2c3_data_clk>; 731 pinctrl-names = "default"; 732 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 736 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 737 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 738 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 739 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 740 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 741 interconnect-names = "qup-core", "qup-config", "qup-memory"; 742 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 743 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 744 dma-names = "tx", "rx"; 745 746 status = "disabled"; 747 }; 748 749 spi3: spi@98c000 { 750 compatible = "qcom,geni-spi"; 751 reg = <0x0 0x0098c000 0x0 0x4000>; 752 clock-names = "se"; 753 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 754 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 755 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>; 756 pinctrl-names = "default"; 757 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 758 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 759 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 760 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 761 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 762 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 763 interconnect-names = "qup-core", "qup-config", "qup-memory"; 764 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 765 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 766 dma-names = "tx", "rx"; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 770 status = "disabled"; 771 }; 772 773 i2c4: i2c@990000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0x0 0x00990000 0x0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 778 pinctrl-0 = <&qup_i2c4_data_clk>; 779 pinctrl-names = "default"; 780 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 784 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 785 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 786 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 787 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 788 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 789 interconnect-names = "qup-core", "qup-config", "qup-memory"; 790 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 791 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 792 dma-names = "tx", "rx"; 793 794 status = "disabled"; 795 }; 796 797 spi4: spi@990000 { 798 compatible = "qcom,geni-spi"; 799 reg = <0x0 0x00990000 0x0 0x4000>; 800 clock-names = "se"; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 802 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 803 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>; 804 pinctrl-names = "default"; 805 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 806 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 807 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 808 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 809 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 810 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 811 interconnect-names = "qup-core", "qup-config", "qup-memory"; 812 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 813 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 814 dma-names = "tx", "rx"; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 818 status = "disabled"; 819 }; 820 821 i2c5: i2c@994000 { 822 compatible = "qcom,geni-i2c"; 823 reg = <0x0 0x00994000 0x0 0x4000>; 824 clock-names = "se"; 825 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 826 pinctrl-0 = <&qup_i2c5_data_clk>; 827 pinctrl-names = "default"; 828 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 832 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 833 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 834 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 835 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 836 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 837 interconnect-names = "qup-core", "qup-config", "qup-memory"; 838 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 839 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 840 dma-names = "tx", "rx"; 841 842 status = "disabled"; 843 }; 844 845 spi5: spi@994000 { 846 compatible = "qcom,geni-spi"; 847 reg = <0x0 0x00994000 0x0 0x4000>; 848 clock-names = "se"; 849 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 850 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 851 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 852 pinctrl-names = "default"; 853 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 854 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 855 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 856 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 857 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 858 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 859 interconnect-names = "qup-core", "qup-config", "qup-memory"; 860 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 861 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 862 dma-names = "tx", "rx"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 866 status = "disabled"; 867 }; 868 }; 869 870 gpi_dma1: dma-controller@a00000 { 871 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma"; 872 #dma-cells = <3>; 873 reg = <0x0 0x00a00000 0x0 0x60000>; 874 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 886 dma-channels = <12>; 887 dma-channel-mask = <0x7e>; 888 iommus = <&apps_smmu 0x16 0x0>; 889 890 status = "disabled"; 891 }; 892 893 qupv3_id_1: geniqup@ac0000 { 894 compatible = "qcom,geni-se-qup"; 895 reg = <0x0 0x00ac0000 0x0 0x6000>; 896 clock-names = "m-ahb", "s-ahb"; 897 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 898 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 899 iommus = <&apps_smmu 0x3 0x0>; 900 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 901 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 902 interconnect-names = "qup-core"; 903 #address-cells = <2>; 904 #size-cells = <2>; 905 ranges; 906 907 status = "disabled"; 908 909 i2c6: i2c@a80000 { 910 compatible = "qcom,geni-i2c"; 911 reg = <0x0 0x00a80000 0x0 0x4000>; 912 clock-names = "se"; 913 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 914 pinctrl-0 = <&qup_i2c6_data_clk>; 915 pinctrl-names = "default"; 916 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 920 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 921 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 922 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 923 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 924 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 925 interconnect-names = "qup-core", "qup-config", "qup-memory"; 926 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 927 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 928 dma-names = "tx", "rx"; 929 930 status = "disabled"; 931 }; 932 933 spi6: spi@a80000 { 934 compatible = "qcom,geni-spi"; 935 reg = <0x0 0x00a80000 0x0 0x4000>; 936 clock-names = "se"; 937 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 938 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 939 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 940 pinctrl-names = "default"; 941 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 942 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 943 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 944 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 945 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 946 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 947 interconnect-names = "qup-core", "qup-config", "qup-memory"; 948 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 949 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 950 dma-names = "tx", "rx"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 954 status = "disabled"; 955 }; 956 957 i2c7: i2c@a84000 { 958 compatible = "qcom,geni-i2c"; 959 reg = <0x0 0x00a84000 0x0 0x4000>; 960 clock-names = "se"; 961 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 962 pinctrl-0 = <&qup_i2c7_data_clk>; 963 pinctrl-names = "default"; 964 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 968 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 969 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 970 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 971 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 972 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 973 interconnect-names = "qup-core", "qup-config", "qup-memory"; 974 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 975 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 976 dma-names = "tx", "rx"; 977 978 status = "disabled"; 979 }; 980 981 spi7: spi@a84000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0x0 0x00a84000 0x0 0x4000>; 984 clock-names = "se"; 985 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 986 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 987 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 988 pinctrl-names = "default"; 989 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 990 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 991 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 992 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 993 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 995 interconnect-names = "qup-core", "qup-config", "qup-memory"; 996 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 997 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 998 dma-names = "tx", "rx"; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 status = "disabled"; 1003 }; 1004 1005 uart7: serial@a84000 { 1006 compatible = "qcom,geni-uart"; 1007 reg = <0x0 0x00a84000 0x0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1010 pinctrl-0 = <&qup_uart7_default>; 1011 pinctrl-names = "default"; 1012 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1014 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1015 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1016 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; 1017 interconnect-names = "qup-core", "qup-config"; 1018 1019 status = "disabled"; 1020 }; 1021 1022 i2c8: i2c@a88000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0x0 0x00a88000 0x0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1027 pinctrl-0 = <&qup_i2c8_data_clk>; 1028 pinctrl-names = "default"; 1029 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1033 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1034 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1035 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1036 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1037 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1038 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1039 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1040 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1041 dma-names = "tx", "rx"; 1042 1043 status = "disabled"; 1044 }; 1045 1046 spi8: spi@a88000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0x0 0x00a88000 0x0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1051 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1052 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1053 pinctrl-names = "default"; 1054 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1055 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1056 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1057 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1058 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1060 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1061 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1062 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1063 dma-names = "tx", "rx"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 1067 status = "disabled"; 1068 }; 1069 1070 i2c9: i2c@a8c000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0x0 0x00a8c000 0x0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1075 pinctrl-0 = <&qup_i2c9_data_clk>; 1076 pinctrl-names = "default"; 1077 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1081 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1082 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1083 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1084 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1085 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1088 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1089 dma-names = "tx", "rx"; 1090 1091 status = "disabled"; 1092 }; 1093 1094 spi9: spi@a8c000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0x0 0x00a8c000 0x0 0x4000>; 1097 clock-names = "se"; 1098 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1099 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1100 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1101 pinctrl-names = "default"; 1102 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1103 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1104 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1105 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1106 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1107 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1108 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1109 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1110 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1111 dma-names = "tx", "rx"; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 1115 status = "disabled"; 1116 }; 1117 1118 i2c10: i2c@a90000 { 1119 compatible = "qcom,geni-i2c"; 1120 reg = <0x0 0x00a90000 0x0 0x4000>; 1121 clock-names = "se"; 1122 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1123 pinctrl-0 = <&qup_i2c10_data_clk>; 1124 pinctrl-names = "default"; 1125 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1129 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1130 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1131 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1132 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1133 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1134 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1135 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1136 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1137 dma-names = "tx", "rx"; 1138 1139 status = "disabled"; 1140 }; 1141 1142 spi10: spi@a90000 { 1143 compatible = "qcom,geni-spi"; 1144 reg = <0x0 0x00a90000 0x0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1147 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1148 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1149 pinctrl-names = "default"; 1150 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1151 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1152 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1153 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1154 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1155 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1156 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1157 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1158 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1159 dma-names = "tx", "rx"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 1163 status = "disabled"; 1164 }; 1165 1166 i2c11: i2c@a94000 { 1167 compatible = "qcom,geni-i2c"; 1168 reg = <0x0 0x00a94000 0x0 0x4000>; 1169 clock-names = "se"; 1170 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1171 pinctrl-0 = <&qup_i2c11_data_clk>; 1172 pinctrl-names = "default"; 1173 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1177 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1178 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1179 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1180 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1181 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1182 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1183 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1184 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1185 dma-names = "tx", "rx"; 1186 1187 status = "disabled"; 1188 }; 1189 1190 spi11: spi@a94000 { 1191 compatible = "qcom,geni-spi"; 1192 reg = <0x0 0x00a94000 0x0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1195 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1196 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1197 pinctrl-names = "default"; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1199 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1200 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1201 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1202 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1203 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1204 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1205 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1206 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1207 dma-names = "tx", "rx"; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 1211 status = "disabled"; 1212 }; 1213 1214 uart11: serial@a94000 { 1215 compatible = "qcom,geni-debug-uart"; 1216 reg = <0x0 0x00a94000 0x0 0x4000>; 1217 clock-names = "se"; 1218 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1219 pinctrl-0 = <&qup_uart11_default>; 1220 pinctrl-names = "default"; 1221 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1222 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1223 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1224 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1225 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1226 interconnect-names = "qup-core", 1227 "qup-config"; 1228 1229 status = "disabled"; 1230 }; 1231 }; 1232 1233 config_noc: interconnect@1500000 { 1234 compatible = "qcom,sar2130p-config-noc"; 1235 reg = <0x0 0x01500000 0x0 0x10>; 1236 #interconnect-cells = <2>; 1237 qcom,bcm-voters = <&apps_bcm_voter>; 1238 }; 1239 1240 system_noc: interconnect@1680000 { 1241 compatible = "qcom,sar2130p-system-noc"; 1242 reg = <0x0 0x01680000 0x0 0x29080>; 1243 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1244 #interconnect-cells = <2>; 1245 qcom,bcm-voters = <&apps_bcm_voter>; 1246 }; 1247 1248 pcie_noc: interconnect@16c0000 { 1249 compatible = "qcom,sar2130p-pcie-anoc"; 1250 reg = <0x0 0x016c0000 0x0 0xa080>; 1251 clocks = <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1252 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1253 #interconnect-cells = <2>; 1254 qcom,bcm-voters = <&apps_bcm_voter>; 1255 }; 1256 1257 mmss_noc: interconnect@1740000 { 1258 compatible = "qcom,sar2130p-mmss-noc"; 1259 reg = <0x0 0x01740000 0x0 0x1f100>; 1260 #interconnect-cells = <2>; 1261 qcom,bcm-voters = <&apps_bcm_voter>; 1262 }; 1263 1264 pcie0: pcie@1c00000 { 1265 device_type = "pci"; 1266 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; 1267 reg = <0x0 0x01c00000 0x0 0x3000>, 1268 <0x0 0x60000000 0x0 0xf1d>, 1269 <0x0 0x60000f20 0x0 0xa8>, 1270 <0x0 0x60001000 0x0 0x1000>, 1271 <0x0 0x60100000 0x0 0x100000>, 1272 <0x0 0x01c0c000 0x0 0x1000>; 1273 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1274 #address-cells = <3>; 1275 #size-cells = <2>; 1276 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1277 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1278 bus-range = <0x00 0xff>; 1279 1280 dma-coherent; 1281 1282 linux,pci-domain = <0>; 1283 num-lanes = <2>; 1284 1285 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1294 interrupt-names = "msi0", 1295 "msi1", 1296 "msi2", 1297 "msi3", 1298 "msi4", 1299 "msi5", 1300 "msi6", 1301 "msi7", 1302 "global"; 1303 #interrupt-cells = <1>; 1304 interrupt-map-mask = <0 0 0 0x7>; 1305 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1306 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1307 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1308 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1309 1310 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1311 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1312 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1313 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1314 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1315 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1316 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1317 clock-names = "aux", 1318 "cfg", 1319 "bus_master", 1320 "bus_slave", 1321 "slave_q2a", 1322 "ddrss_sf_tbu", 1323 "noc_aggr"; 1324 1325 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 1326 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1327 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1328 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 1329 interconnect-names = "pcie-mem", "cpu-pcie"; 1330 1331 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1332 <0x100 &apps_smmu 0x1c01 0x1>; 1333 1334 resets = <&gcc GCC_PCIE_0_BCR>; 1335 reset-names = "pci"; 1336 1337 power-domains = <&gcc PCIE_0_GDSC>; 1338 1339 phys = <&pcie0_phy>; 1340 phy-names = "pciephy"; 1341 1342 status = "disabled"; 1343 1344 pcieport0: pcie@0 { 1345 device_type = "pci"; 1346 reg = <0x0 0x0 0x0 0x0 0x0>; 1347 bus-range = <0x01 0xff>; 1348 1349 #address-cells = <3>; 1350 #size-cells = <2>; 1351 ranges; 1352 }; 1353 }; 1354 1355 pcie0_phy: phy@1c06000 { 1356 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; 1357 reg = <0x0 0x01c06000 0x0 0x2000>; 1358 1359 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1360 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1361 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1362 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1363 <&gcc GCC_PCIE_0_PIPE_CLK>; 1364 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1365 "pipe"; 1366 1367 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1368 reset-names = "phy"; 1369 1370 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1371 assigned-clock-rates = <100000000>; 1372 1373 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1374 1375 #clock-cells = <0>; 1376 clock-output-names = "pcie0_pipe_clk"; 1377 1378 #phy-cells = <0>; 1379 1380 status = "disabled"; 1381 }; 1382 1383 pcie1: pcie@1c08000 { 1384 device_type = "pci"; 1385 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; 1386 reg = <0x0 0x01c08000 0x0 0x3000>, 1387 <0x0 0x40000000 0x0 0xf1d>, 1388 <0x0 0x40000f20 0x0 0xa8>, 1389 <0x0 0x40001000 0x0 0x1000>, 1390 <0x0 0x40100000 0x0 0x100000>, 1391 <0x0 0x01c0b000 0x0 0x1000>; 1392 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1393 #address-cells = <3>; 1394 #size-cells = <2>; 1395 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1396 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1397 bus-range = <0x00 0xff>; 1398 1399 dma-coherent; 1400 1401 linux,pci-domain = <1>; 1402 num-lanes = <2>; 1403 1404 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1413 interrupt-names = "msi0", 1414 "msi1", 1415 "msi2", 1416 "msi3", 1417 "msi4", 1418 "msi5", 1419 "msi6", 1420 "msi7", 1421 "global"; 1422 #interrupt-cells = <1>; 1423 interrupt-map-mask = <0 0 0 0x7>; 1424 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1425 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1426 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1427 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1428 1429 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1430 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1431 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1432 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1433 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1434 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1435 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1436 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, 1437 <&gcc GCC_QMIP_PCIE_AHB_CLK>; 1438 clock-names = "aux", 1439 "cfg", 1440 "bus_master", 1441 "bus_slave", 1442 "slave_q2a", 1443 "ddrss_sf_tbu", 1444 "noc_aggr", 1445 "cnoc_sf_axi", 1446 "qmip_pcie_ahb"; 1447 1448 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1449 assigned-clock-rates = <19200000>; 1450 1451 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 1452 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1454 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 1455 interconnect-names = "pcie-mem", "cpu-pcie"; 1456 1457 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1458 <0x100 &apps_smmu 0x1e01 0x1>; 1459 1460 resets = <&gcc GCC_PCIE_1_BCR>, 1461 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1462 reset-names = "pci", "link_down"; 1463 1464 power-domains = <&gcc PCIE_1_GDSC>; 1465 1466 phys = <&pcie1_phy>; 1467 phy-names = "pciephy"; 1468 1469 status = "disabled"; 1470 1471 pcie@0 { 1472 device_type = "pci"; 1473 reg = <0x0 0x0 0x0 0x0 0x0>; 1474 bus-range = <0x01 0xff>; 1475 1476 #address-cells = <3>; 1477 #size-cells = <2>; 1478 ranges; 1479 }; 1480 }; 1481 1482 pcie1_ep: pcie-ep@1c08000 { 1483 compatible = "qcom,sar2130p-pcie-ep"; 1484 reg = <0x0 0x01c08000 0x0 0x3000>, 1485 <0x0 0x40000000 0x0 0xf1d>, 1486 <0x0 0x40000f20 0x0 0xa8>, 1487 <0x0 0x40001000 0x0 0x1000>, 1488 <0x0 0x40200000 0x0 0x1000000>, 1489 <0x0 0x01c0b000 0x0 0x1000>, 1490 <0x0 0x40002000 0x0 0x2000>; 1491 reg-names = "parf", 1492 "dbi", 1493 "elbi", 1494 "atu", 1495 "addr_space", 1496 "mmio", 1497 "dma"; 1498 1499 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1500 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1501 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1502 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1503 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1504 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1505 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1506 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, 1507 <&gcc GCC_QMIP_PCIE_AHB_CLK>; 1508 clock-names = "aux", 1509 "cfg", 1510 "bus_master", 1511 "bus_slave", 1512 "slave_q2a", 1513 "ddrss_sf_tbu", 1514 "aggre_noc_axi", 1515 "cnoc_sf_axi", 1516 "qmip_pcie_ahb"; 1517 1518 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupt-names = "global", 1522 "doorbell", 1523 "dma"; 1524 1525 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 1526 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1527 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1528 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1529 interconnect-names = "pcie-mem", 1530 "cpu-pcie"; 1531 iommus = <&apps_smmu 0x1e00 0x1>; 1532 resets = <&gcc GCC_PCIE_1_BCR>; 1533 reset-names = "core"; 1534 power-domains = <&gcc PCIE_1_GDSC>; 1535 phys = <&pcie1_phy>; 1536 phy-names = "pciephy"; 1537 1538 num-lanes = <2>; 1539 1540 status = "disabled"; 1541 }; 1542 1543 pcie1_phy: phy@1c0e000 { 1544 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; 1545 reg = <0x0 0x01c0e000 0x0 0x2000>; 1546 1547 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1548 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1549 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1550 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1551 <&gcc GCC_PCIE_1_PIPE_CLK>; 1552 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1553 "pipe"; 1554 1555 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1556 reset-names = "phy"; 1557 1558 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1559 assigned-clock-rates = <100000000>; 1560 1561 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1562 1563 #clock-cells = <0>; 1564 clock-output-names = "pcie1_pipe_clk"; 1565 1566 #phy-cells = <0>; 1567 1568 status = "disabled"; 1569 }; 1570 1571 tcsr_mutex: hwlock@1f40000 { 1572 compatible = "qcom,tcsr-mutex"; 1573 reg = <0x0 0x01f40000 0x0 0x20000>; 1574 1575 #hwlock-cells = <1>; 1576 }; 1577 1578 tcsr: clock-controller@1fc0000 { 1579 compatible = "qcom,sar2130p-tcsr", "syscon"; 1580 reg = <0x0 0x01fc0000 0x0 0x30000>; 1581 clocks = <&rpmhcc RPMH_CXO_CLK>; 1582 #clock-cells = <1>; 1583 #reset-cells = <1>; 1584 }; 1585 1586 remoteproc_adsp: remoteproc@3000000 { 1587 compatible = "qcom,sar2130p-adsp-pas"; 1588 reg = <0x0 0x03000000 0x0 0x10000>; 1589 1590 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1591 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1592 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1593 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1594 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1595 interrupt-names = "wdog", "fatal", "ready", 1596 "handover", "stop-ack"; 1597 1598 clocks = <&rpmhcc RPMH_CXO_CLK>; 1599 clock-names = "xo"; 1600 1601 power-domains = <&rpmhpd RPMHPD_LCX>, 1602 <&rpmhpd RPMHPD_LMX>; 1603 power-domain-names = "lcx", "lmx"; 1604 1605 memory-region = <&adsp_mem>; 1606 1607 qcom,qmp = <&aoss_qmp>; 1608 1609 qcom,smem-states = <&smp2p_adsp_out 0>; 1610 qcom,smem-state-names = "stop"; 1611 1612 status = "disabled"; 1613 1614 remoteproc_adsp_glink: glink-edge { 1615 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1616 IPCC_MPROC_SIGNAL_GLINK_QMP 1617 IRQ_TYPE_EDGE_RISING>; 1618 mboxes = <&ipcc IPCC_CLIENT_LPASS 1619 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1620 1621 label = "lpass"; 1622 qcom,remote-pid = <2>; 1623 1624 gpr { 1625 compatible = "qcom,gpr"; 1626 qcom,glink-channels = "adsp_apps"; 1627 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 1628 qcom,intents = <512 20>; 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 1632 q6apm: service@1 { 1633 compatible = "qcom,q6apm"; 1634 reg = <GPR_APM_MODULE_IID>; 1635 #sound-dai-cells = <0>; 1636 qcom,protection-domain = "avs/audio", 1637 "msm/adsp/audio_pd"; 1638 1639 q6apmdai: dais { 1640 compatible = "qcom,q6apm-dais"; 1641 iommus = <&apps_smmu 0x1801 0x0>; 1642 }; 1643 1644 q6apmbedai: bedais { 1645 compatible = "qcom,q6apm-lpass-dais"; 1646 #sound-dai-cells = <1>; 1647 }; 1648 }; 1649 1650 q6prm: service@2 { 1651 compatible = "qcom,q6prm"; 1652 reg = <GPR_PRM_MODULE_IID>; 1653 qcom,protection-domain = "avs/audio", 1654 "msm/adsp/audio_pd"; 1655 1656 q6prmcc: clock-controller { 1657 compatible = "qcom,q6prm-lpass-clocks"; 1658 #clock-cells = <2>; 1659 }; 1660 }; 1661 }; 1662 1663 fastrpc { 1664 compatible = "qcom,fastrpc"; 1665 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1666 label = "adsp"; 1667 qcom,non-secure-domain; 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 1671 compute-cb@3 { 1672 compatible = "qcom,fastrpc-compute-cb"; 1673 reg = <3>; 1674 iommus = <&apps_smmu 0x1803 0x0>; 1675 }; 1676 1677 compute-cb@4 { 1678 compatible = "qcom,fastrpc-compute-cb"; 1679 reg = <4>; 1680 iommus = <&apps_smmu 0x1804 0x0>; 1681 }; 1682 1683 compute-cb@5 { 1684 compatible = "qcom,fastrpc-compute-cb"; 1685 reg = <5>; 1686 iommus = <&apps_smmu 0x1805 0x0>; 1687 }; 1688 1689 compute-cb@6 { 1690 compatible = "qcom,fastrpc-compute-cb"; 1691 reg = <6>; 1692 iommus = <&apps_smmu 0x1806 0x0>; 1693 }; 1694 }; 1695 }; 1696 }; 1697 1698 gpu: gpu@3d00000 { 1699 compatible = "qcom,adreno-621.0", "qcom,adreno"; 1700 reg = <0x0 0x03d00000 0x0 0x40000>, 1701 <0x0 0x03d9e000 0x0 0x2000>, 1702 <0x0 0x03d61000 0x0 0x800>; 1703 reg-names = "kgsl_3d0_reg_memory", 1704 "cx_mem", 1705 "cx_dbgc"; 1706 1707 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1708 1709 iommus = <&adreno_smmu 0 0x401>; 1710 1711 operating-points-v2 = <&gpu_opp_table>; 1712 1713 qcom,gmu = <&gmu>; 1714 1715 nvmem-cells = <&gpu_speed_bin>; 1716 nvmem-cell-names = "speed_bin"; 1717 #cooling-cells = <2>; 1718 1719 status = "disabled"; 1720 1721 gpu_zap_shader: zap-shader { 1722 memory-region = <&gpu_micro_code_mem>; 1723 }; 1724 1725 gpu_opp_table: opp-table { 1726 compatible = "operating-points-v2"; 1727 1728 opp-843000000 { 1729 opp-hz = /bits/ 64 <843000000>; 1730 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1731 opp-supported-hw = <0x1>; 1732 }; 1733 1734 opp-780000000 { 1735 opp-hz = /bits/ 64 <780000000>; 1736 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1737 opp-supported-hw = <0x1>; 1738 }; 1739 1740 opp-644000000 { 1741 opp-hz = /bits/ 64 <644000000>; 1742 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1743 opp-supported-hw = <0x3>; 1744 }; 1745 1746 opp-570000000 { 1747 opp-hz = /bits/ 64 <570000000>; 1748 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1749 opp-supported-hw = <0x3>; 1750 }; 1751 1752 opp-450000000 { 1753 opp-hz = /bits/ 64 <450000000>; 1754 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1755 opp-supported-hw = <0x3>; 1756 }; 1757 1758 opp-320000000 { 1759 opp-hz = /bits/ 64 <320000000>; 1760 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1761 opp-supported-hw = <0x3>; 1762 }; 1763 1764 opp-235000000 { 1765 opp-hz = /bits/ 64 <235000000>; 1766 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 1767 opp-supported-hw = <0x3>; 1768 }; 1769 }; 1770 }; 1771 1772 gmu: gmu@3d6a000 { 1773 compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu"; 1774 reg = <0x0 0x03d6a000 0x0 0x35000>, 1775 <0x0 0x03de0000 0x0 0x10000>, 1776 <0x0 0x0b290000 0x0 0x10000>; 1777 reg-names = "gmu", "rscc", "gmu_pdc"; 1778 1779 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1781 interrupt-names = "hfi", "gmu"; 1782 1783 clocks = <&gpucc GPU_CC_AHB_CLK>, 1784 <&gpucc GPU_CC_CX_GMU_CLK>, 1785 <&gpucc GPU_CC_CXO_CLK>, 1786 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1787 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1788 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 1789 clock-names = "ahb", 1790 "gmu", 1791 "cxo", 1792 "axi", 1793 "memnoc", 1794 "hub"; 1795 1796 power-domains = <&gpucc GPU_CX_GDSC>, 1797 <&gpucc GPU_GX_GDSC>; 1798 power-domain-names = "cx", 1799 "gx"; 1800 1801 iommus = <&adreno_smmu 5 0x400>; 1802 1803 qcom,qmp = <&aoss_qmp>; 1804 1805 operating-points-v2 = <&gmu_opp_table>; 1806 1807 gmu_opp_table: opp-table { 1808 compatible = "operating-points-v2"; 1809 1810 opp-220000000 { 1811 opp-hz = /bits/ 64 <220000000>; 1812 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1813 }; 1814 1815 opp-550000000 { 1816 opp-hz = /bits/ 64 <550000000>; 1817 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1818 }; 1819 }; 1820 }; 1821 1822 gpucc: clock-controller@3d90000 { 1823 compatible = "qcom,sar2130p-gpucc"; 1824 reg = <0x0 0x03d90000 0x0 0xa000>; 1825 1826 clocks = <&rpmhcc RPMH_CXO_CLK>, 1827 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1828 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1829 1830 #clock-cells = <1>; 1831 #reset-cells = <1>; 1832 #power-domain-cells = <1>; 1833 }; 1834 1835 adreno_smmu: iommu@3da0000 { 1836 compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu", 1837 "qcom,smmu-500", "arm,mmu-500"; 1838 reg = <0x0 0x03da0000 0x0 0x10000>; 1839 #iommu-cells = <2>; 1840 #global-interrupts = <1>; 1841 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 1850 1851 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1852 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1853 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1854 <&gpucc GPU_CC_AHB_CLK>; 1855 clock-names = "hlos", 1856 "bus", 1857 "iface", 1858 "ahb"; 1859 power-domains = <&gpucc GPU_CX_GDSC>; 1860 dma-coherent; 1861 }; 1862 1863 usb_1_hsphy: phy@88e3000 { 1864 compatible = "qcom,sar2130p-snps-eusb2-phy", 1865 "qcom,sm8550-snps-eusb2-phy"; 1866 reg = <0x0 0x088e3000 0x0 0x154>; 1867 #phy-cells = <0>; 1868 1869 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 1870 clock-names = "ref"; 1871 1872 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1873 1874 status = "disabled"; 1875 }; 1876 1877 usb_dp_qmpphy: phy@88e8000 { 1878 compatible = "qcom,sar2130p-qmp-usb3-dp-phy"; 1879 reg = <0x0 0x088e8000 0x0 0x3000>; 1880 1881 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1882 <&rpmhcc RPMH_CXO_CLK>, 1883 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1884 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1885 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1886 1887 power-domains = <&gcc USB3_PHY_GDSC>; 1888 1889 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1890 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1891 reset-names = "phy", "common"; 1892 1893 #clock-cells = <1>; 1894 #phy-cells = <1>; 1895 1896 orientation-switch; 1897 1898 status = "disabled"; 1899 1900 ports { 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 1904 port@0 { 1905 reg = <0>; 1906 1907 usb_dp_qmpphy_out: endpoint { 1908 }; 1909 }; 1910 1911 port@1 { 1912 reg = <1>; 1913 1914 usb_dp_qmpphy_usb_ss_in: endpoint { 1915 remote-endpoint = <&usb_1_dwc3_ss>; 1916 }; 1917 }; 1918 1919 port@2 { 1920 reg = <2>; 1921 1922 usb_dp_qmpphy_dp_in: endpoint { 1923 remote-endpoint = <&mdss_dp0_out>; 1924 }; 1925 }; 1926 }; 1927 }; 1928 1929 usb_1: usb@a6f8800 { 1930 compatible = "qcom,sar2130p-dwc3", "qcom,dwc3"; 1931 reg = <0x0 0x0a6f8800 0x0 0x400>; 1932 #address-cells = <2>; 1933 #size-cells = <2>; 1934 ranges; 1935 1936 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1937 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1938 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1939 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1940 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1941 <&tcsr TCSR_USB3_CLKREF_EN>; 1942 clock-names = "cfg_noc", 1943 "core", 1944 "iface", 1945 "sleep", 1946 "mock_utmi", 1947 "xo"; 1948 1949 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1950 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1951 assigned-clock-rates = <19200000>, <200000000>; 1952 1953 interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1954 <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1955 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1956 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1957 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1958 interrupt-names = "pwr_event", 1959 "hs_phy_irq", 1960 "dp_hs_phy_irq", 1961 "dm_hs_phy_irq", 1962 "ss_phy_irq"; 1963 1964 power-domains = <&gcc USB30_PRIM_GDSC>; 1965 required-opps = <&rpmhpd_opp_nom>; 1966 1967 resets = <&gcc GCC_USB30_PRIM_BCR>; 1968 1969 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 1970 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1971 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1972 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 1973 interconnect-names = "usb-ddr", "apps-usb"; 1974 1975 status = "disabled"; 1976 1977 usb_1_dwc3: usb@a600000 { 1978 compatible = "snps,dwc3"; 1979 reg = <0x0 0x0a600000 0x0 0xcd00>; 1980 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1981 iommus = <&apps_smmu 0x20 0x0>; 1982 phys = <&usb_1_hsphy>, 1983 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 1984 phy-names = "usb2-phy", "usb3-phy"; 1985 1986 snps,has-lpm-erratum; 1987 snps,hird-threshold = /bits/ 8 <0x0>; 1988 snps,is-utmi-l1-suspend; 1989 snps,dis-u1-entry-quirk; 1990 snps,dis-u2-entry-quirk; 1991 snps,dis_u2_susphy_quirk; 1992 snps,dis_u3_susphy_quirk; 1993 snps,parkmode-disable-ss-quirk; 1994 1995 tx-fifo-resize; 1996 dma-coherent; 1997 usb-role-switch; 1998 1999 ports { 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 2003 port@0 { 2004 reg = <0>; 2005 2006 usb_1_dwc3_hs: endpoint { 2007 }; 2008 }; 2009 2010 port@1 { 2011 reg = <1>; 2012 2013 usb_1_dwc3_ss: endpoint { 2014 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 2015 }; 2016 }; 2017 }; 2018 }; 2019 }; 2020 2021 mdss: display-subsystem@ae00000 { 2022 compatible = "qcom,sar2130p-mdss"; 2023 reg = <0x0 0x0ae00000 0x0 0x1000>; 2024 reg-names = "mdss"; 2025 2026 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2027 interrupt-controller; 2028 #interrupt-cells = <1>; 2029 2030 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2031 <&gcc GCC_DISP_AHB_CLK>, 2032 <&gcc GCC_DISP_HF_AXI_CLK>, 2033 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2034 2035 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2036 2037 power-domains = <&dispcc MDSS_GDSC>; 2038 2039 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ACTIVE_ONLY 2040 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2041 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2042 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2043 interconnect-names = "mdp0-mem", "cpu-cfg"; 2044 2045 iommus = <&apps_smmu 0x2000 0x402>; 2046 2047 #address-cells = <2>; 2048 #size-cells = <2>; 2049 ranges; 2050 2051 status = "disabled"; 2052 2053 mdss_mdp: display-controller@ae01000 { 2054 compatible = "qcom,sar2130p-dpu"; 2055 reg = <0x0 0x0ae01000 0x0 0x8f000>, 2056 <0x0 0x0aeb0000 0x0 0x2008>; 2057 reg-names = "mdp", 2058 "vbif"; 2059 2060 interrupt-parent = <&mdss>; 2061 interrupts = <0>; 2062 2063 clocks = <&gcc GCC_DISP_AHB_CLK>, 2064 <&gcc GCC_DISP_HF_AXI_CLK>, 2065 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2066 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2067 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2068 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2069 clock-names = "bus", 2070 "nrt_bus", 2071 "iface", 2072 "lut", 2073 "core", 2074 "vsync"; 2075 2076 power-domains = <&rpmhpd RPMHPD_MMCX>; 2077 2078 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2079 assigned-clock-rates = <19200000>; 2080 2081 operating-points-v2 = <&mdp_opp_table>; 2082 2083 ports { 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 2087 port@0 { 2088 reg = <0>; 2089 2090 dpu_intf1_out: endpoint { 2091 remote-endpoint = <&mdss_dsi0_in>; 2092 }; 2093 }; 2094 2095 port@1 { 2096 reg = <1>; 2097 2098 dpu_intf2_out: endpoint { 2099 remote-endpoint = <&mdss_dsi1_in>; 2100 }; 2101 }; 2102 2103 port@2 { 2104 reg = <2>; 2105 2106 dpu_intf0_out: endpoint { 2107 remote-endpoint = <&mdss_dp0_in>; 2108 }; 2109 }; 2110 }; 2111 2112 mdp_opp_table: opp-table { 2113 compatible = "operating-points-v2"; 2114 2115 opp-200000000 { 2116 opp-hz = /bits/ 64 <200000000>; 2117 required-opps = <&rpmhpd_opp_low_svs>; 2118 }; 2119 2120 opp-325000000 { 2121 opp-hz = /bits/ 64 <325000000>; 2122 required-opps = <&rpmhpd_opp_svs>; 2123 }; 2124 2125 opp-514000000 { 2126 opp-hz = /bits/ 64 <514000000>; 2127 required-opps = <&rpmhpd_opp_turbo>; 2128 }; 2129 }; 2130 }; 2131 2132 mdss_dp0: displayport-controller@ae90000 { 2133 compatible = "qcom,sar2130p-dp", 2134 "qcom,sm8350-dp"; 2135 reg = <0x0 0xae90000 0x0 0x200>, 2136 <0x0 0xae90200 0x0 0x200>, 2137 <0x0 0xae90400 0x0 0xc00>, 2138 <0x0 0xae91000 0x0 0x400>, 2139 <0x0 0xae91400 0x0 0x400>; 2140 interrupt-parent = <&mdss>; 2141 interrupts = <12>; 2142 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2143 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2144 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2145 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2146 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2147 clock-names = "core_iface", 2148 "core_aux", 2149 "ctrl_link", 2150 "ctrl_link_iface", 2151 "stream_pixel"; 2152 2153 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2154 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2155 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2156 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2157 2158 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2159 phy-names = "dp"; 2160 2161 #sound-dai-cells = <0>; 2162 2163 operating-points-v2 = <&dp_opp_table>; 2164 power-domains = <&rpmhpd RPMHPD_MMCX>; 2165 2166 status = "disabled"; 2167 2168 ports { 2169 #address-cells = <1>; 2170 #size-cells = <0>; 2171 2172 port@0 { 2173 reg = <0>; 2174 2175 mdss_dp0_in: endpoint { 2176 remote-endpoint = <&dpu_intf0_out>; 2177 }; 2178 }; 2179 2180 port@1 { 2181 reg = <1>; 2182 2183 mdss_dp0_out: endpoint { 2184 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 2185 }; 2186 }; 2187 }; 2188 2189 dp_opp_table: opp-table { 2190 compatible = "operating-points-v2"; 2191 2192 opp-162000000 { 2193 opp-hz = /bits/ 64 <162000000>; 2194 required-opps = <&rpmhpd_opp_low_svs_d1>; 2195 }; 2196 2197 opp-270000000 { 2198 opp-hz = /bits/ 64 <270000000>; 2199 required-opps = <&rpmhpd_opp_low_svs>; 2200 }; 2201 2202 opp-540000000 { 2203 opp-hz = /bits/ 64 <540000000>; 2204 required-opps = <&rpmhpd_opp_svs_l1>; 2205 }; 2206 2207 opp-810000000 { 2208 opp-hz = /bits/ 64 <810000000>; 2209 required-opps = <&rpmhpd_opp_nom>; 2210 }; 2211 }; 2212 }; 2213 2214 mdss_dsi0: dsi@ae94000 { 2215 compatible = "qcom,sar2130p-dsi-ctrl", 2216 "qcom,mdss-dsi-ctrl"; 2217 reg = <0x0 0x0ae94000 0x0 0x400>; 2218 reg-names = "dsi_ctrl"; 2219 2220 interrupt-parent = <&mdss>; 2221 interrupts = <4>; 2222 2223 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2224 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2225 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2226 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2227 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2228 <&gcc GCC_DISP_HF_AXI_CLK>; 2229 clock-names = "byte", 2230 "byte_intf", 2231 "pixel", 2232 "core", 2233 "iface", 2234 "bus"; 2235 2236 power-domains = <&rpmhpd RPMHPD_MMCX>; 2237 2238 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2239 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2240 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2241 <&mdss_dsi0_phy 1>; 2242 2243 operating-points-v2 = <&mdss_dsi_opp_table>; 2244 2245 phys = <&mdss_dsi0_phy>; 2246 phy-names = "dsi"; 2247 2248 #address-cells = <1>; 2249 #size-cells = <0>; 2250 2251 status = "disabled"; 2252 2253 ports { 2254 #address-cells = <1>; 2255 #size-cells = <0>; 2256 2257 port@0 { 2258 reg = <0>; 2259 mdss_dsi0_in: endpoint { 2260 remote-endpoint = <&dpu_intf1_out>; 2261 }; 2262 }; 2263 2264 port@1 { 2265 reg = <1>; 2266 mdss_dsi0_out: endpoint { 2267 }; 2268 }; 2269 }; 2270 2271 mdss_dsi_opp_table: opp-table { 2272 compatible = "operating-points-v2"; 2273 2274 opp-187500000 { 2275 opp-hz = /bits/ 64 <187500000>; 2276 required-opps = <&rpmhpd_opp_low_svs>; 2277 }; 2278 2279 opp-300000000 { 2280 opp-hz = /bits/ 64 <300000000>; 2281 required-opps = <&rpmhpd_opp_svs>; 2282 }; 2283 2284 opp-358000000 { 2285 opp-hz = /bits/ 64 <358000000>; 2286 required-opps = <&rpmhpd_opp_nom>; 2287 }; 2288 }; 2289 }; 2290 2291 mdss_dsi0_phy: phy@ae95000 { 2292 compatible = "qcom,sar2130p-dsi-phy-5nm"; 2293 reg = <0x0 0x0ae95000 0x0 0x200>, 2294 <0x0 0x0ae95200 0x0 0x280>, 2295 <0x0 0x0ae95500 0x0 0x400>; 2296 reg-names = "dsi_phy", 2297 "dsi_phy_lane", 2298 "dsi_pll"; 2299 2300 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2301 <&rpmhcc RPMH_CXO_CLK>; 2302 clock-names = "iface", "ref"; 2303 2304 #clock-cells = <1>; 2305 #phy-cells = <0>; 2306 2307 status = "disabled"; 2308 }; 2309 2310 mdss_dsi1: dsi@ae96000 { 2311 compatible = "qcom,sar2130p-dsi-ctrl", 2312 "qcom,mdss-dsi-ctrl"; 2313 reg = <0x0 0x0ae96000 0x0 0x400>; 2314 reg-names = "dsi_ctrl"; 2315 2316 interrupt-parent = <&mdss>; 2317 interrupts = <5>; 2318 2319 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2320 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2321 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2322 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2323 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2324 <&gcc GCC_DISP_HF_AXI_CLK>; 2325 clock-names = "byte", 2326 "byte_intf", 2327 "pixel", 2328 "core", 2329 "iface", 2330 "bus"; 2331 2332 power-domains = <&rpmhpd RPMHPD_MMCX>; 2333 2334 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2335 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2336 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2337 <&mdss_dsi1_phy 1>; 2338 2339 operating-points-v2 = <&mdss_dsi_opp_table>; 2340 2341 phys = <&mdss_dsi1_phy>; 2342 phy-names = "dsi"; 2343 2344 #address-cells = <1>; 2345 #size-cells = <0>; 2346 2347 status = "disabled"; 2348 2349 ports { 2350 #address-cells = <1>; 2351 #size-cells = <0>; 2352 2353 port@0 { 2354 reg = <0>; 2355 mdss_dsi1_in: endpoint { 2356 remote-endpoint = <&dpu_intf2_out>; 2357 }; 2358 }; 2359 2360 port@1 { 2361 reg = <1>; 2362 mdss_dsi1_out: endpoint { 2363 }; 2364 }; 2365 }; 2366 }; 2367 2368 mdss_dsi1_phy: phy@ae97000 { 2369 compatible = "qcom,sar2130p-dsi-phy-5nm"; 2370 reg = <0x0 0x0ae97000 0x0 0x200>, 2371 <0x0 0x0ae97200 0x0 0x280>, 2372 <0x0 0x0ae97500 0x0 0x400>; 2373 reg-names = "dsi_phy", 2374 "dsi_phy_lane", 2375 "dsi_pll"; 2376 2377 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2378 <&rpmhcc RPMH_CXO_CLK>; 2379 clock-names = "iface", "ref"; 2380 2381 #clock-cells = <1>; 2382 #phy-cells = <0>; 2383 2384 status = "disabled"; 2385 }; 2386 }; 2387 2388 dispcc: clock-controller@af00000 { 2389 compatible = "qcom,sar2130p-dispcc"; 2390 reg = <0x0 0x0af00000 0x0 0x20000>; 2391 clocks = <&rpmhcc RPMH_CXO_CLK>, 2392 <&rpmhcc RPMH_CXO_CLK_A>, 2393 <&gcc GCC_DISP_AHB_CLK>, 2394 <&sleep_clk>, 2395 <&mdss_dsi0_phy 0>, 2396 <&mdss_dsi0_phy 1>, 2397 <&mdss_dsi1_phy 0>, 2398 <&mdss_dsi1_phy 1>, 2399 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2400 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2401 <0>, /* dp1 */ 2402 <0>, 2403 <0>, /* dp2 */ 2404 <0>, 2405 <0>, /* dp3 */ 2406 <0>; 2407 power-domains = <&rpmhpd RPMHPD_MMCX>; 2408 #clock-cells = <1>; 2409 #reset-cells = <1>; 2410 #power-domain-cells = <1>; 2411 }; 2412 2413 pdc: interrupt-controller@b220000 { 2414 compatible = "qcom,sar2130p-pdc", "qcom,pdc"; 2415 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; 2416 qcom,pdc-ranges = <0 480 94>, 2417 <94 609 31>, 2418 <125 63 1>, 2419 <126 716 12>; 2420 #interrupt-cells = <2>; 2421 interrupt-parent = <&intc>; 2422 interrupt-controller; 2423 }; 2424 2425 aoss_qmp: power-management@c300000 { 2426 compatible = "qcom,sar2130p-aoss-qmp", "qcom,aoss-qmp"; 2427 reg = <0x0 0x0c300000 0x0 0x400>; 2428 interrupt-parent = <&ipcc>; 2429 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2430 IRQ_TYPE_EDGE_RISING>; 2431 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2432 2433 #clock-cells = <0>; 2434 }; 2435 2436 tsens0: thermal-sensor@c263000 { 2437 compatible = "qcom,sar2130p-tsens", "qcom,tsens-v2"; 2438 reg = <0x0 0x0c263000 0x0 0x1000>, /* TM */ 2439 <0x0 0x0c222000 0x0 0x1000>; /* SROT */ 2440 #qcom,sensors = <16>; 2441 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2443 interrupt-names = "uplow", "critical"; 2444 #thermal-sensor-cells = <1>; 2445 }; 2446 2447 sram@c3f0000 { 2448 compatible = "qcom,rpmh-stats"; 2449 reg = <0x0 0x0c3f0000 0x0 0x400>; 2450 }; 2451 2452 arbiter@c400000 { 2453 compatible = "qcom,sar2130p-spmi-pmic-arb", 2454 "qcom,x1e80100-spmi-pmic-arb"; 2455 reg = <0x0 0x0c400000 0x0 0x3000>, 2456 <0x0 0x0c500000 0x0 0x400000>, 2457 <0x0 0x0c440000 0x0 0x80000>; 2458 reg-names = "core", "chnls", "obsrvr"; 2459 2460 qcom,ee = <0>; 2461 qcom,channel = <0>; 2462 2463 #address-cells = <2>; 2464 #size-cells = <2>; 2465 ranges; 2466 2467 spmi_bus: spmi@c42d000 { 2468 reg = <0x0 0x0c42d000 0x0 0x4000>, 2469 <0x0 0x0c4c0000 0x0 0x10000>; 2470 reg-names = "cnfg", "intr"; 2471 2472 interrupt-names = "periph_irq"; 2473 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2474 interrupt-controller; 2475 #interrupt-cells = <4>; 2476 2477 #address-cells = <2>; 2478 #size-cells = <0>; 2479 }; 2480 }; 2481 2482 ipcc: mailbox@ed18000 { 2483 compatible = "qcom,sar2130p-ipcc", "qcom,ipcc"; 2484 reg = <0x0 0x0ed18000 0x0 0x1000>; 2485 2486 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 2487 interrupt-controller; 2488 #interrupt-cells = <3>; 2489 2490 #mbox-cells = <2>; 2491 }; 2492 2493 tlmm: pinctrl@f100000 { 2494 compatible = "qcom,sar2130p-tlmm"; 2495 reg = <0x0 0x0f100000 0x0 0x300000>; 2496 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2497 gpio-controller; 2498 #gpio-cells = <2>; 2499 interrupt-controller; 2500 #interrupt-cells = <2>; 2501 gpio-ranges = <&tlmm 0 0 156>; 2502 wakeup-parent = <&pdc>; 2503 2504 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2505 /* SDA, SCL */ 2506 pins = "gpio0", "gpio1"; 2507 function = "qup0"; 2508 drive-strength = <2>; 2509 bias-pull-up; 2510 }; 2511 2512 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2513 /* SDA, SCL */ 2514 pins = "gpio2", "gpio3"; 2515 function = "qup1"; 2516 drive-strength = <2>; 2517 bias-pull-up; 2518 }; 2519 2520 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2521 /* SDA, SCL */ 2522 pins = "gpio22", "gpio23"; 2523 function = "qup2"; 2524 drive-strength = <2>; 2525 bias-pull-up; 2526 }; 2527 2528 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2529 /* SDA, SCL */ 2530 pins = "gpio16", "gpio17"; 2531 function = "qup3"; 2532 drive-strength = <2>; 2533 bias-pull-up; 2534 }; 2535 2536 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2537 /* SDA, SCL */ 2538 pins = "gpio20", "gpio21"; 2539 function = "qup4"; 2540 drive-strength = <2>; 2541 bias-pull-up; 2542 }; 2543 2544 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2545 /* SDA, SCL */ 2546 pins = "gpio95", "gpio96"; 2547 function = "qup5"; 2548 drive-strength = <2>; 2549 bias-pull-up; 2550 }; 2551 2552 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2553 /* SDA, SCL */ 2554 pins = "gpio91", "gpio92"; 2555 function = "qup6"; 2556 drive-strength = <2>; 2557 bias-pull-up; 2558 }; 2559 2560 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 2561 /* SDA, SCL */ 2562 pins = "gpio8", "gpio9"; 2563 function = "qup7"; 2564 drive-strength = <2>; 2565 bias-pull-up; 2566 }; 2567 2568 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2569 /* SDA, SCL */ 2570 pins = "gpio8", "gpio9"; 2571 function = "qup8"; 2572 drive-strength = <2>; 2573 bias-pull-up; 2574 }; 2575 2576 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2577 /* SDA, SCL */ 2578 pins = "gpio109", "gpio110"; 2579 function = "qup9"; 2580 drive-strength = <2>; 2581 bias-pull-up; 2582 }; 2583 2584 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2585 /* SDA, SCL */ 2586 pins = "gpio4", "gpio5"; 2587 function = "qup10"; 2588 drive-strength = <2>; 2589 bias-pull-up; 2590 }; 2591 2592 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2593 /* SDA, SCL */ 2594 pins = "gpio28", "gpio30"; 2595 function = "qup11"; 2596 drive-strength = <2>; 2597 bias-pull-up; 2598 }; 2599 2600 qup_spi0_cs0: qup-spi0-cs0-state { 2601 pins = "gpio3"; 2602 function = "qup0"; 2603 drive-strength = <2>; 2604 bias-disable; 2605 }; 2606 2607 qup_spi0_cs1: qup-spi0-cs1-state { 2608 pins = "gpio93"; 2609 function = "qup0"; 2610 drive-strength = <2>; 2611 bias-disable; 2612 }; 2613 2614 qup_spi0_data_clk: qup-spi0-data-clk-state { 2615 /* MISO, MOSI, CLK */ 2616 pins = "gpio0", "gpio1", "gpio2"; 2617 function = "qup0"; 2618 drive-strength = <2>; 2619 bias-disable; 2620 }; 2621 2622 qup_spi1_cs: qup-spi1-cs-state { 2623 pins = "gpio62"; 2624 function = "qup1"; 2625 drive-strength = <2>; 2626 bias-disable; 2627 }; 2628 2629 qup_spi1_data_clk: qup-spi1-data-clk-state { 2630 /* MISO, MOSI, CLK */ 2631 pins = "gpio2", "gpio3", "gpio61"; 2632 function = "qup1"; 2633 drive-strength = <2>; 2634 bias-disable; 2635 }; 2636 2637 qup_spi2_cs: qup-spi2-cs-state { 2638 pins = "gpio13"; 2639 function = "qup2"; 2640 drive-strength = <2>; 2641 bias-disable; 2642 }; 2643 2644 qup_spi2_data_clk: qup-spi2-data-clk-state { 2645 /* MISO, MOSI, CLK */ 2646 pins = "gpio22", "gpio23", "gpio12"; 2647 function = "qup2"; 2648 drive-strength = <2>; 2649 bias-disable; 2650 }; 2651 2652 qup_spi3_cs0: qup-spi3-cs0-state { 2653 pins = "gpio19"; 2654 function = "qup3"; 2655 drive-strength = <2>; 2656 bias-disable; 2657 }; 2658 2659 qup_spi3_cs1: qup-spi3-cs1-state { 2660 pins = "gpio41"; 2661 function = "qup3"; 2662 drive-strength = <2>; 2663 bias-disable; 2664 }; 2665 2666 qup_spi3_data_clk: qup-spi3-data-clk-state { 2667 /* MISO, MOSI, CLK */ 2668 pins = "gpio16", "gpio17", "gpio18"; 2669 function = "qup3"; 2670 drive-strength = <2>; 2671 bias-disable; 2672 }; 2673 2674 qup_spi4_cs0: qup-spi4-cs0-state { 2675 pins = "gpio23"; 2676 function = "qup4"; 2677 drive-strength = <2>; 2678 bias-disable; 2679 }; 2680 2681 qup_spi4_cs1: qup-spi4-cs1-state { 2682 pins = "gpio94"; 2683 function = "qup4"; 2684 drive-strength = <2>; 2685 bias-disable; 2686 }; 2687 2688 qup_spi4_data_clk: qup-spi4-data-clk-state { 2689 /* MISO, MOSI, CLK */ 2690 pins = "gpio20", "gpio21", "gpio22"; 2691 function = "qup4"; 2692 drive-strength = <2>; 2693 bias-disable; 2694 }; 2695 2696 qup_spi5_cs: qup-spi5-cs-state { 2697 pins = "gpio98"; 2698 function = "qup5"; 2699 drive-strength = <2>; 2700 bias-disable; 2701 }; 2702 2703 qup_spi5_data_clk: qup-spi5-data-clk-state { 2704 /* MISO, MOSI, CLK */ 2705 pins = "gpio95", "gpio96", "gpio97"; 2706 function = "qup5"; 2707 drive-strength = <2>; 2708 bias-disable; 2709 }; 2710 2711 qup_spi6_cs: qup-spi6-cs-state { 2712 pins = "gpio63"; 2713 function = "qup6"; 2714 drive-strength = <2>; 2715 bias-disable; 2716 }; 2717 2718 qup_spi6_data_clk: qup-spi6-data-clk-state { 2719 /* MISO, MOSI, CLK */ 2720 pins = "gpio91", "gpio92", "gpio64"; 2721 function = "qup6"; 2722 drive-strength = <2>; 2723 bias-disable; 2724 }; 2725 2726 qup_spi7_cs: qup-spi7-cs-state { 2727 pins = "gpio27"; 2728 function = "qup7"; 2729 drive-strength = <2>; 2730 bias-disable; 2731 }; 2732 2733 qup_spi7_data_clk: qup-spi7-data-clk-state { 2734 /* MISO, MOSI, CLK */ 2735 pins = "gpio24", "gpio25", "gpio26"; 2736 function = "qup7"; 2737 drive-strength = <2>; 2738 bias-disable; 2739 }; 2740 2741 qup_spi8_cs: qup-spi8-cs-state { 2742 pins = "gpio11"; 2743 function = "qup8"; 2744 drive-strength = <2>; 2745 bias-disable; 2746 }; 2747 2748 qup_spi8_data_clk: qup-spi8-data-clk-state { 2749 /* MISO, MOSI, CLK */ 2750 pins = "gpio8", "gpio9", "gpio10"; 2751 function = "qup8"; 2752 drive-strength = <2>; 2753 bias-disable; 2754 }; 2755 2756 qup_spi9_cs: qup-spi9-cs-state { 2757 pins = "gpio35"; 2758 function = "qup9"; 2759 drive-strength = <2>; 2760 bias-disable; 2761 }; 2762 2763 qup_spi9_data_clk: qup-spi9-data-clk-state { 2764 /* MISO, MOSI, CLK */ 2765 pins = "gpio109", "gpio110", "gpio34"; 2766 function = "qup9"; 2767 drive-strength = <2>; 2768 bias-disable; 2769 }; 2770 2771 qup_spi10_cs: qup-spi10-cs-state { 2772 pins = "gpio7"; 2773 function = "qup10"; 2774 drive-strength = <2>; 2775 bias-disable; 2776 }; 2777 2778 qup_spi10_data_clk: qup-spi10-data-clk-state { 2779 /* MISO, MOSI, CLK */ 2780 pins = "gpio4", "gpio5", "gpio6"; 2781 function = "qup10"; 2782 drive-strength = <2>; 2783 bias-disable; 2784 }; 2785 2786 qup_spi11_cs: qup-spi11-cs-state { 2787 pins = "gpio15"; 2788 function = "qup11"; 2789 drive-strength = <2>; 2790 bias-disable; 2791 }; 2792 2793 qup_spi11_data_clk: qup-spi11-data-clk-state { 2794 /* MISO, MOSI, CLK */ 2795 pins = "gpio28", "gpio30", "gpio14"; 2796 function = "qup11"; 2797 drive-strength = <2>; 2798 bias-disable; 2799 }; 2800 2801 qup_uart7_default: qup-uart7-default-state { 2802 cts-pins { 2803 pins = "gpio24"; 2804 function = "qup7"; 2805 drive-strength = <2>; 2806 bias-disable; 2807 }; 2808 2809 rts-pins { 2810 pins = "gpio25"; 2811 function = "qup7"; 2812 drive-strength = <2>; 2813 bias-pull-down; 2814 }; 2815 2816 rx-pins { 2817 pins = "gpio27"; 2818 function = "qup7"; 2819 drive-strength = <2>; 2820 bias-pull-down; 2821 }; 2822 2823 tx-pins { 2824 pins = "gpio26"; 2825 function = "qup7"; 2826 drive-strength = <2>; 2827 bias-pull-up; 2828 }; 2829 }; 2830 2831 qup_uart11_default: qup-uart11-default-state { 2832 pins = "gpio14", "gpio15"; 2833 function = "qup11"; 2834 drive-strength = <2>; 2835 bias-disable; 2836 }; 2837 2838 sdc1_default: sdc1-default-state { 2839 clk-pins { 2840 pins = "sdc1_clk"; 2841 drive-strength = <16>; 2842 bias-disable; 2843 }; 2844 2845 cmd-pins { 2846 pins = "sdc1_cmd"; 2847 drive-strength = <10>; 2848 bias-pull-up; 2849 }; 2850 2851 data-pins { 2852 pins = "sdc1_data"; 2853 drive-strength = <10>; 2854 bias-pull-up; 2855 }; 2856 2857 rclk-pins { 2858 pins = "sdc1_rclk"; 2859 bias-pull-down; 2860 }; 2861 }; 2862 2863 sdc1_sleep: sdc1-sleep-state { 2864 clk-pins { 2865 pins = "sdc1_clk"; 2866 drive-strength = <2>; 2867 bias-disable; 2868 }; 2869 2870 cmd-pins { 2871 pins = "sdc1_cmd"; 2872 drive-strength = <2>; 2873 bias-pull-up; 2874 }; 2875 2876 data-pins { 2877 pins = "sdc1_data"; 2878 drive-strength = <2>; 2879 bias-pull-up; 2880 }; 2881 2882 rclk-pins { 2883 pins = "sdc1_rclk"; 2884 bias-pull-down; 2885 }; 2886 }; 2887 }; 2888 2889 apps_smmu: iommu@15000000 { 2890 compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2891 reg = <0x0 0x15000000 0x0 0x100000>; 2892 #iommu-cells = <2>; 2893 #global-interrupts = <1>; 2894 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2896 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2897 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2898 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2899 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2900 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2905 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2906 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2908 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2909 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2910 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2911 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2912 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2913 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2914 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2915 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2916 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2917 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2918 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2919 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2920 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2921 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2922 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2923 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2924 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2925 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2926 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2927 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2932 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2933 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2934 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2935 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2936 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2937 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2938 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2953 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2955 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2956 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2957 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2958 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2959 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2960 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2977 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2979 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2980 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2981 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2982 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2983 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2984 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2985 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2986 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2987 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2988 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2989 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2990 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 2991 dma-coherent; 2992 }; 2993 2994 intc: interrupt-controller@17200000 { 2995 compatible = "arm,gic-v3"; 2996 #interrupt-cells = <3>; 2997 interrupt-controller; 2998 #redistributor-regions = <1>; 2999 redistributor-stride = <0x0 0x20000>; 3000 reg = <0x0 0x17200000 0x0 0x10000>, 3001 <0x0 0x17260000 0x0 0x100000>; 3002 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3003 #address-cells = <2>; 3004 #size-cells = <2>; 3005 ranges; 3006 3007 gic_its: msi-controller@17240000 { 3008 compatible = "arm,gic-v3-its"; 3009 reg = <0x0 0x17240000 0x0 0x20000>; 3010 msi-controller; 3011 #msi-cells = <1>; 3012 }; 3013 }; 3014 3015 apps_rsc: rsc@17a00000 { 3016 label = "apps_rsc"; 3017 compatible = "qcom,rpmh-rsc"; 3018 reg = <0x0 0x17a00000 0x0 0x10000>, 3019 <0x0 0x17a10000 0x0 0x10000>, 3020 <0x0 0x17a20000 0x0 0x10000>; 3021 reg-names = "drv-0", "drv-1", "drv-2"; 3022 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3023 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3025 qcom,tcs-offset = <0xd00>; 3026 qcom,drv-id = <2>; 3027 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3028 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3029 power-domains = <&cluster_pd>; 3030 3031 apps_bcm_voter: bcm-voter { 3032 compatible = "qcom,bcm-voter"; 3033 }; 3034 3035 rpmhcc: clock-controller { 3036 compatible = "qcom,sar2130p-rpmh-clk"; 3037 #clock-cells = <1>; 3038 clock-names = "xo"; 3039 clocks = <&xo_board>; 3040 }; 3041 3042 rpmhpd: power-controller { 3043 compatible = "qcom,sar2130p-rpmhpd"; 3044 #power-domain-cells = <1>; 3045 operating-points-v2 = <&rpmhpd_opp_table>; 3046 3047 rpmhpd_opp_table: opp-table { 3048 compatible = "operating-points-v2"; 3049 3050 rpmhpd_opp_ret: opp1 { 3051 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3052 }; 3053 3054 rpmhpd_opp_min_svs: opp2 { 3055 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3056 }; 3057 3058 rpmhpd_opp_low_svs_d1: opp3 { 3059 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3060 }; 3061 3062 rpmhpd_opp_low_svs: opp4 { 3063 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3064 }; 3065 3066 rpmhpd_opp_svs: opp5 { 3067 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3068 }; 3069 3070 rpmhpd_opp_svs_l1: opp6 { 3071 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3072 }; 3073 3074 rpmhpd_opp_nom: opp7 { 3075 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3076 }; 3077 3078 rpmhpd_opp_turbo: opp8 { 3079 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3080 }; 3081 3082 rpmhpd_opp_turbo_l1: opp9 { 3083 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3084 }; 3085 }; 3086 }; 3087 }; 3088 3089 cpufreq_hw: cpufreq@17d91000 { 3090 compatible = "qcom,sar2130p-cpufreq-epss", "qcom,cpufreq-epss"; 3091 reg = <0x0 0x17d91000 0x0 0x1000>; 3092 reg-names = "freq-domain0"; 3093 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3094 clock-names = "xo", "alternate"; 3095 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3096 interrupt-names = "dcvsh-irq-0"; 3097 #freq-domain-cells = <1>; 3098 #clock-cells = <1>; 3099 }; 3100 3101 gem_noc: interconnect@19100000 { 3102 compatible = "qcom,sar2130p-gem-noc"; 3103 reg = <0x0 0x19100000 0x0 0xa2080>; 3104 #interconnect-cells = <2>; 3105 qcom,bcm-voters = <&apps_bcm_voter>; 3106 }; 3107 3108 /* 3109 * Bootloader expects just cache-controller node instead of 3110 * the typical system-cache-controller 3111 */ 3112 llcc: cache-controller@19200000 { 3113 compatible = "qcom,sar2130p-llcc"; 3114 reg = <0x0 0x19200000 0x0 0x80000>, 3115 <0x0 0x19300000 0x0 0x80000>, 3116 <0x0 0x19a00000 0x0 0x80000>, 3117 <0x0 0x19c00000 0x0 0x80000>, 3118 <0x0 0x19af0000 0x0 0x80000>, 3119 <0x0 0x19cf0000 0x0 0x80000>; 3120 reg-names = "llcc0_base", 3121 "llcc1_base", 3122 "llcc_broadcast_base", 3123 "llcc_broadcast_and_base", 3124 "llcc_scratchpad_broadcast_base", 3125 "llcc_scratchpad_broadcast_and_base"; 3126 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3127 }; 3128 3129 qfprom: qfprom@221c8000 { 3130 compatible = "qcom,sar2130p-qfprom", "qcom,qfprom"; 3131 reg = <0x0 0x221c8000 0x0 0x1000>; 3132 #address-cells = <1>; 3133 #size-cells = <1>; 3134 read-only; 3135 3136 gpu_speed_bin: gpu-speed-bin@119 { 3137 reg = <0x119 0x2>; 3138 bits = <5 8>; 3139 }; 3140 }; 3141 3142 nsp_noc: interconnect@320c0000 { 3143 compatible = "qcom,sar2130p-nsp-noc"; 3144 reg = <0x0 0x320c0000 0x0 0x10>; 3145 #interconnect-cells = <2>; 3146 qcom,bcm-voters = <&apps_bcm_voter>; 3147 }; 3148 3149 lpass_ag_noc: interconnect@3c40000 { 3150 compatible = "qcom,sar2130p-lpass-ag-noc"; 3151 reg = <0x0 0x3c40000 0x0 0x10>; 3152 #interconnect-cells = <1>; 3153 qcom,bcm-voters = <&apps_bcm_voter>; 3154 }; 3155 }; 3156 3157 timer { 3158 compatible = "arm,armv8-timer"; 3159 3160 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3161 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3162 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3163 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3164 }; 3165 3166 thermal-zones { 3167 aoss0-thermal { 3168 thermal-sensors = <&tsens0 0>; 3169 3170 trips { 3171 trip-point0 { 3172 temperature = <115000>; 3173 hysteresis = <5000>; 3174 type = "hot"; 3175 }; 3176 3177 aoss0-critical { 3178 temperature = <125000>; 3179 hysteresis = <0>; 3180 type = "critical"; 3181 }; 3182 3183 }; 3184 }; 3185 3186 cpu0-thermal { 3187 thermal-sensors = <&tsens0 1>; 3188 3189 trips { 3190 cpu0_alert0: trip-point0 { 3191 temperature = <110000>; 3192 hysteresis = <10000>; 3193 type = "passive"; 3194 }; 3195 3196 cpu0_alert1: trip-point1 { 3197 temperature = <115000>; 3198 hysteresis = <5000>; 3199 type = "passive"; 3200 }; 3201 3202 cpu0-critical { 3203 temperature = <125000>; 3204 hysteresis = <1000>; 3205 type = "critical"; 3206 }; 3207 }; 3208 3209 cooling-maps { 3210 map0 { 3211 trip = <&cpu0_alert0>; 3212 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3213 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3214 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3215 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3216 }; 3217 3218 map1 { 3219 trip = <&cpu0_alert1>; 3220 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3221 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3222 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3223 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3224 }; 3225 }; 3226 }; 3227 3228 cpu1-thermal { 3229 thermal-sensors = <&tsens0 2>; 3230 3231 trips { 3232 cpu1_alert0: trip-point0 { 3233 temperature = <110000>; 3234 hysteresis = <10000>; 3235 type = "passive"; 3236 }; 3237 3238 cpu1_alert1: trip-point1 { 3239 temperature = <115000>; 3240 hysteresis = <5000>; 3241 type = "passive"; 3242 }; 3243 3244 cpu1-critical { 3245 temperature = <125000>; 3246 hysteresis = <1000>; 3247 type = "critical"; 3248 }; 3249 }; 3250 3251 cooling-maps { 3252 map0 { 3253 trip = <&cpu1_alert0>; 3254 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3255 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3256 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3257 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3258 }; 3259 3260 map1 { 3261 trip = <&cpu1_alert1>; 3262 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3263 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3264 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3265 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3266 }; 3267 }; 3268 }; 3269 3270 cpu2-thermal { 3271 thermal-sensors = <&tsens0 3>; 3272 3273 trips { 3274 cpu2_alert0: trip-point0 { 3275 temperature = <110000>; 3276 hysteresis = <10000>; 3277 type = "passive"; 3278 }; 3279 3280 cpu2_alert1: trip-point1 { 3281 temperature = <115000>; 3282 hysteresis = <5000>; 3283 type = "passive"; 3284 }; 3285 3286 cpu2-critical { 3287 temperature = <125000>; 3288 hysteresis = <1000>; 3289 type = "critical"; 3290 }; 3291 }; 3292 3293 cooling-maps { 3294 map0 { 3295 trip = <&cpu2_alert0>; 3296 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3297 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3298 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3299 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3300 }; 3301 3302 map1 { 3303 trip = <&cpu2_alert1>; 3304 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3305 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3306 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3307 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3308 }; 3309 }; 3310 }; 3311 3312 cpu3-thermal { 3313 thermal-sensors = <&tsens0 4>; 3314 3315 trips { 3316 cpu3_alert0: trip-point0 { 3317 temperature = <110000>; 3318 hysteresis = <10000>; 3319 type = "passive"; 3320 }; 3321 3322 cpu3_alert1: rip-point1 { 3323 temperature = <115000>; 3324 hysteresis = <5000>; 3325 type = "passive"; 3326 }; 3327 3328 cpu3-critical { 3329 temperature = <125000>; 3330 hysteresis = <1000>; 3331 type = "critical"; 3332 }; 3333 }; 3334 3335 cooling-maps { 3336 map0 { 3337 trip = <&cpu3_alert0>; 3338 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3339 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3340 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3341 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3342 }; 3343 3344 map1 { 3345 trip = <&cpu3_alert1>; 3346 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3347 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3348 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3349 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3350 }; 3351 }; 3352 }; 3353 3354 gpuss0-thermal { 3355 polling-delay-passive = <250>; 3356 3357 thermal-sensors = <&tsens0 5>; 3358 3359 cooling-maps { 3360 map0 { 3361 trip = <&gpu0_alert0>; 3362 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3363 }; 3364 }; 3365 3366 trips { 3367 gpu0_alert0: trip-point0 { 3368 temperature = <85000>; 3369 hysteresis = <1000>; 3370 type = "passive"; 3371 }; 3372 3373 trip-point1 { 3374 temperature = <90000>; 3375 hysteresis = <1000>; 3376 type = "hot"; 3377 }; 3378 3379 trip-point2 { 3380 temperature = <115000>; 3381 hysteresis = <1000>; 3382 type = "critical"; 3383 }; 3384 }; 3385 }; 3386 3387 gpuss1-thermal { 3388 polling-delay-passive = <250>; 3389 3390 thermal-sensors = <&tsens0 6>; 3391 3392 cooling-maps { 3393 map0 { 3394 trip = <&gpu1_alert0>; 3395 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3396 }; 3397 }; 3398 3399 trips { 3400 gpu1_alert0: trip-point0 { 3401 temperature = <85000>; 3402 hysteresis = <1000>; 3403 type = "passive"; 3404 }; 3405 3406 trip-point1 { 3407 temperature = <90000>; 3408 hysteresis = <1000>; 3409 type = "hot"; 3410 }; 3411 3412 trip-point2 { 3413 temperature = <115000>; 3414 hysteresis = <1000>; 3415 type = "critical"; 3416 }; 3417 }; 3418 }; 3419 3420 nspss0-thermal { 3421 thermal-sensors = <&tsens0 7>; 3422 3423 trips { 3424 trip-point0 { 3425 temperature = <95000>; 3426 hysteresis = <5000>; 3427 type = "hot"; 3428 }; 3429 3430 trip-point1 { 3431 temperature = <115000>; 3432 hysteresis = <5000>; 3433 type = "hot"; 3434 }; 3435 3436 nspss1-critical { 3437 temperature = <125000>; 3438 hysteresis = <1000>; 3439 type = "critical"; 3440 }; 3441 }; 3442 }; 3443 3444 nspss1-thermal { 3445 thermal-sensors = <&tsens0 8>; 3446 3447 trips { 3448 trip-point0 { 3449 temperature = <95000>; 3450 hysteresis = <5000>; 3451 type = "hot"; 3452 }; 3453 3454 trip-point1 { 3455 temperature = <115000>; 3456 hysteresis = <5000>; 3457 type = "hot"; 3458 }; 3459 3460 nspss2-critical { 3461 temperature = <125000>; 3462 hysteresis = <1000>; 3463 type = "critical"; 3464 }; 3465 }; 3466 }; 3467 3468 nspss2-thermal { 3469 thermal-sensors = <&tsens0 9>; 3470 3471 trips { 3472 trip-point0 { 3473 temperature = <95000>; 3474 hysteresis = <5000>; 3475 type = "hot"; 3476 }; 3477 3478 trip-point1 { 3479 temperature = <115000>; 3480 hysteresis = <5000>; 3481 type = "hot"; 3482 }; 3483 3484 nspss2-critical { 3485 temperature = <125000>; 3486 hysteresis = <1000>; 3487 type = "critical"; 3488 }; 3489 }; 3490 }; 3491 3492 video-thermal { 3493 thermal-sensors = <&tsens0 10>; 3494 3495 trips { 3496 trip-point0 { 3497 temperature = <115000>; 3498 hysteresis = <5000>; 3499 type = "hot"; 3500 }; 3501 3502 video-critical { 3503 temperature = <125000>; 3504 hysteresis = <0>; 3505 type = "critical"; 3506 }; 3507 }; 3508 }; 3509 3510 ddr-thermal { 3511 thermal-sensors = <&tsens0 11>; 3512 3513 trips { 3514 trip-point0 { 3515 temperature = <115000>; 3516 hysteresis = <5000>; 3517 type = "hot"; 3518 }; 3519 3520 ddr-critical { 3521 temperature = <125000>; 3522 hysteresis = <0>; 3523 type = "critical"; 3524 }; 3525 }; 3526 }; 3527 3528 camera0-thermal { 3529 thermal-sensors = <&tsens0 12>; 3530 3531 trips { 3532 trip-point0 { 3533 temperature = <115000>; 3534 hysteresis = <5000>; 3535 type = "hot"; 3536 }; 3537 3538 camera0-critical { 3539 temperature = <125000>; 3540 hysteresis = <0>; 3541 type = "critical"; 3542 }; 3543 }; 3544 }; 3545 3546 camera1-thermal { 3547 thermal-sensors = <&tsens0 13>; 3548 3549 trips { 3550 trip-point0 { 3551 temperature = <115000>; 3552 hysteresis = <5000>; 3553 type = "hot"; 3554 }; 3555 3556 camera1-critical { 3557 temperature = <125000>; 3558 hysteresis = <0>; 3559 type = "critical"; 3560 }; 3561 }; 3562 }; 3563 3564 mdmss-thermal { 3565 thermal-sensors = <&tsens0 14>; 3566 3567 trips { 3568 trip-point0 { 3569 temperature = <115000>; 3570 hysteresis = <5000>; 3571 type = "hot"; 3572 }; 3573 3574 mdmss-critical { 3575 temperature = <125000>; 3576 hysteresis = <0>; 3577 type = "critical"; 3578 }; 3579 }; 3580 }; 3581 }; 3582}; 3583