1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 12#include "sa8540p.dtsi" 13#include "sa8540p-pmics.dtsi" 14 15/ { 16 model = "Qualcomm SA8540P Ride"; 17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p"; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c12 = &i2c12; 23 i2c15 = &i2c15; 24 i2c18 = &i2c18; 25 serial0 = &uart17; 26 }; 27 28 chosen { 29 stdout-path = "serial0:115200n8"; 30 }; 31}; 32 33&apps_rsc { 34 regulators-0 { 35 compatible = "qcom,pm8150-rpmh-regulators"; 36 qcom,pmic-id = "a"; 37 38 vreg_l3a: ldo3 { 39 regulator-name = "vreg_l3a"; 40 regulator-min-microvolt = <1200000>; 41 regulator-max-microvolt = <1208000>; 42 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 43 }; 44 45 vreg_l5a: ldo5 { 46 regulator-name = "vreg_l5a"; 47 regulator-min-microvolt = <912000>; 48 regulator-max-microvolt = <912000>; 49 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 50 }; 51 52 vreg_l7a: ldo7 { 53 regulator-name = "vreg_l7a"; 54 regulator-min-microvolt = <1800000>; 55 regulator-max-microvolt = <1800000>; 56 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 57 }; 58 59 vreg_l11a: ldo11 { 60 regulator-name = "vreg_l11a"; 61 regulator-min-microvolt = <880000>; 62 regulator-max-microvolt = <880000>; 63 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 64 }; 65 66 vreg_l13a: ldo13 { 67 regulator-name = "vreg_l13a"; 68 regulator-min-microvolt = <3072000>; 69 regulator-max-microvolt = <3072000>; 70 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 71 }; 72 }; 73 74 regulators-1 { 75 compatible = "qcom,pm8150-rpmh-regulators"; 76 qcom,pmic-id = "c"; 77 78 vreg_l1c: ldo1 { 79 regulator-name = "vreg_l1c"; 80 regulator-min-microvolt = <912000>; 81 regulator-max-microvolt = <912000>; 82 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 83 }; 84 85 vreg_l2c: ldo2 { 86 regulator-name = "vreg_l2c"; 87 regulator-min-microvolt = <3072000>; 88 regulator-max-microvolt = <3072000>; 89 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 90 }; 91 92 vreg_l4c: ldo4 { 93 regulator-name = "vreg_l4c"; 94 regulator-min-microvolt = <1200000>; 95 regulator-max-microvolt = <1208000>; 96 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 97 }; 98 99 vreg_l6c: ldo6 { 100 regulator-name = "vreg_l6c"; 101 regulator-min-microvolt = <1200000>; 102 regulator-max-microvolt = <1200000>; 103 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 104 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM 105 RPMH_REGULATOR_MODE_HPM>; 106 regulator-allow-set-load; 107 }; 108 109 vreg_l7c: ldo7 { 110 regulator-name = "vreg_l7c"; 111 regulator-min-microvolt = <1800000>; 112 regulator-max-microvolt = <1800000>; 113 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 114 }; 115 116 vreg_l17c: ldo17 { 117 regulator-name = "vreg_l17c"; 118 regulator-min-microvolt = <2504000>; 119 regulator-max-microvolt = <2504000>; 120 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 121 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM 122 RPMH_REGULATOR_MODE_HPM>; 123 regulator-allow-set-load; 124 }; 125 }; 126 127 regulators-2 { 128 compatible = "qcom,pm8150-rpmh-regulators"; 129 qcom,pmic-id = "g"; 130 131 vreg_l3g: ldo3 { 132 regulator-name = "vreg_l3g"; 133 regulator-min-microvolt = <1200000>; 134 regulator-max-microvolt = <1200000>; 135 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 136 }; 137 138 vreg_l7g: ldo7 { 139 regulator-name = "vreg_l7g"; 140 regulator-min-microvolt = <1800000>; 141 regulator-max-microvolt = <1800000>; 142 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 143 }; 144 145 vreg_l8g: ldo8 { 146 regulator-name = "vreg_l8g"; 147 regulator-min-microvolt = <880000>; 148 regulator-max-microvolt = <880000>; 149 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 150 }; 151 }; 152}; 153 154ðernet0 { 155 snps,mtl-rx-config = <ðernet0_mtl_rx_setup>; 156 snps,mtl-tx-config = <ðernet0_mtl_tx_setup>; 157 158 phy-handle = <&rgmii_phy>; 159 phy-mode = "rgmii-txid"; 160 161 pinctrl-names = "default"; 162 pinctrl-0 = <ðernet0_default>; 163 164 status = "okay"; 165 166 mdio { 167 compatible = "snps,dwmac-mdio"; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 /* Marvell 88EA1512 */ 172 rgmii_phy: phy@8 { 173 compatible = "ethernet-phy-id0141.0dd4"; 174 reg = <0x8>; 175 176 interrupts-extended = <&tlmm 127 IRQ_TYPE_EDGE_FALLING>; 177 178 reset-gpios = <&pmm8540c_gpios 1 GPIO_ACTIVE_LOW>; 179 reset-assert-us = <11000>; 180 reset-deassert-us = <70000>; 181 182 device_type = "ethernet-phy"; 183 184 /* Set to RGMII_SGMII mode and soft reset. Turn off auto-negotiation 185 * from userspace to talk to the switch on the SGMII side of things 186 */ 187 marvell,reg-init = 188 /* Set MODE[2:0] to RGMII_SGMII */ 189 <0x12 0x14 0xfff8 0x4>, 190 /* Soft reset required after changing MODE[2:0] */ 191 <0x12 0x14 0x7fff 0x8000>; 192 }; 193 }; 194 195 ethernet0_mtl_rx_setup: rx-queues-config { 196 snps,rx-queues-to-use = <1>; 197 snps,rx-sched-sp; 198 199 queue0 { 200 snps,dcb-algorithm; 201 snps,map-to-dma-channel = <0x0>; 202 snps,route-up; 203 snps,priority = <0x1>; 204 }; 205 206 queue1 { 207 snps,dcb-algorithm; 208 snps,map-to-dma-channel = <0x1>; 209 snps,route-ptp; 210 }; 211 212 queue2 { 213 snps,avb-algorithm; 214 snps,map-to-dma-channel = <0x2>; 215 snps,route-avcp; 216 }; 217 218 queue3 { 219 snps,avb-algorithm; 220 snps,map-to-dma-channel = <0x3>; 221 snps,priority = <0xc>; 222 }; 223 }; 224 225 ethernet0_mtl_tx_setup: tx-queues-config { 226 snps,tx-queues-to-use = <1>; 227 228 queue0 { 229 snps,dcb-algorithm; 230 }; 231 232 queue1 { 233 snps,dcb-algorithm; 234 }; 235 236 queue2 { 237 snps,avb-algorithm; 238 snps,send_slope = <0x1000>; 239 snps,idle_slope = <0x1000>; 240 snps,high_credit = <0x3e800>; 241 snps,low_credit = <0xffc18000>; 242 }; 243 244 queue3 { 245 snps,avb-algorithm; 246 snps,send_slope = <0x1000>; 247 snps,idle_slope = <0x1000>; 248 snps,high_credit = <0x3e800>; 249 snps,low_credit = <0xffc18000>; 250 }; 251 }; 252}; 253 254ðernet1 { 255 snps,mtl-rx-config = <ðernet1_mtl_rx_setup>; 256 snps,mtl-tx-config = <ðernet1_mtl_tx_setup>; 257 258 phy-mode = "rgmii-txid"; 259 260 pinctrl-names = "default"; 261 pinctrl-0 = <ðernet1_default>; 262 263 status = "okay"; 264 265 fixed-link { 266 speed = <1000>; 267 full-duplex; 268 }; 269 270 ethernet1_mtl_rx_setup: rx-queues-config { 271 snps,rx-queues-to-use = <1>; 272 snps,rx-sched-sp; 273 274 queue0 { 275 snps,dcb-algorithm; 276 snps,map-to-dma-channel = <0x0>; 277 snps,route-up; 278 snps,priority = <0x1>; 279 }; 280 281 queue1 { 282 snps,dcb-algorithm; 283 snps,map-to-dma-channel = <0x1>; 284 snps,route-ptp; 285 }; 286 287 queue2 { 288 snps,avb-algorithm; 289 snps,map-to-dma-channel = <0x2>; 290 snps,route-avcp; 291 }; 292 293 queue3 { 294 snps,avb-algorithm; 295 snps,map-to-dma-channel = <0x3>; 296 snps,priority = <0xc>; 297 }; 298 }; 299 300 ethernet1_mtl_tx_setup: tx-queues-config { 301 snps,tx-queues-to-use = <1>; 302 303 queue0 { 304 snps,dcb-algorithm; 305 }; 306 307 queue1 { 308 snps,dcb-algorithm; 309 }; 310 311 queue2 { 312 snps,avb-algorithm; 313 snps,send_slope = <0x1000>; 314 snps,idle_slope = <0x1000>; 315 snps,high_credit = <0x3e800>; 316 snps,low_credit = <0xffc18000>; 317 }; 318 319 queue3 { 320 snps,avb-algorithm; 321 snps,send_slope = <0x1000>; 322 snps,idle_slope = <0x1000>; 323 snps,high_credit = <0x3e800>; 324 snps,low_credit = <0xffc18000>; 325 }; 326 }; 327}; 328 329&i2c0 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&i2c0_default>; 332 333 status = "okay"; 334}; 335 336&i2c1 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&i2c1_default>; 339 340 status = "okay"; 341}; 342 343&i2c12 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&i2c12_default>; 346 347 status = "okay"; 348}; 349 350&i2c15 { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&i2c15_default>; 353 354 status = "okay"; 355}; 356 357&i2c18 { 358 pinctrl-names = "default"; 359 pinctrl-0 = <&i2c18_default>; 360 361 status = "okay"; 362}; 363 364&pcie2a { 365 ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, 366 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, 367 <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; 368 369 perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; 370 wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; 371 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pcie2a_default>; 374 375 status = "disabled"; 376}; 377 378&pcie2a_phy { 379 vdda-phy-supply = <&vreg_l11a>; 380 vdda-pll-supply = <&vreg_l3a>; 381 382 status = "disabled"; 383}; 384 385&pcie3a { 386 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 387 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, 388 <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; 389 390 perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; 391 wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; 392 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pcie3a_default>; 395 396 status = "okay"; 397}; 398 399&pcie3a_phy { 400 vdda-phy-supply = <&vreg_l11a>; 401 vdda-pll-supply = <&vreg_l3a>; 402 403 status = "okay"; 404}; 405 406&pmm8540a_rtc { 407 nvmem-cells = <&rtc_offset>; 408 nvmem-cell-names = "offset"; 409 410 status = "okay"; 411}; 412 413&pmm8540c_sdam_2 { 414 status = "okay"; 415 416 rtc_offset: rtc-offset@a0 { 417 reg = <0xa0 0x4>; 418 }; 419}; 420 421&qup0 { 422 status = "okay"; 423}; 424 425&qup1 { 426 status = "okay"; 427}; 428 429&qup2 { 430 status = "okay"; 431}; 432 433&remoteproc_nsp0 { 434 firmware-name = "qcom/sa8540p/cdsp0.mbn"; 435 status = "okay"; 436}; 437 438&remoteproc_nsp1 { 439 firmware-name = "qcom/sa8540p/cdsp1.mbn"; 440 status = "okay"; 441}; 442 443&uart17 { 444 compatible = "qcom,geni-debug-uart"; 445 status = "okay"; 446}; 447 448&ufs_mem_hc { 449 reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; 450 451 vcc-supply = <&vreg_l17c>; 452 vccq-supply = <&vreg_l6c>; 453 454 status = "okay"; 455}; 456 457&ufs_mem_phy { 458 vdda-phy-supply = <&vreg_l8g>; 459 vdda-pll-supply = <&vreg_l3g>; 460 461 status = "okay"; 462}; 463 464&usb_0 { 465 status = "okay"; 466}; 467 468&usb_0_dwc3 { 469 dr_mode = "peripheral"; 470}; 471 472&usb_0_hsphy { 473 vdda-pll-supply = <&vreg_l5a>; 474 vdda18-supply = <&vreg_l7a>; 475 vdda33-supply = <&vreg_l13a>; 476 477 status = "okay"; 478}; 479 480&usb_0_qmpphy { 481 vdda-phy-supply = <&vreg_l3a>; 482 vdda-pll-supply = <&vreg_l5a>; 483 484 status = "okay"; 485}; 486 487&usb_2_hsphy0 { 488 vdda-pll-supply = <&vreg_l5a>; 489 vdda18-supply = <&vreg_l7g>; 490 vdda33-supply = <&vreg_l13a>; 491 492 status = "okay"; 493}; 494 495&usb_2_qmpphy0 { 496 vdda-phy-supply = <&vreg_l3a>; 497 vdda-pll-supply = <&vreg_l5a>; 498 499 status = "okay"; 500}; 501 502&xo_board_clk { 503 clock-frequency = <38400000>; 504}; 505 506/* PINCTRL */ 507 508&tlmm { 509 ethernet0_default: ethernet0-default-state { 510 mdc-pins { 511 pins = "gpio175"; 512 function = "rgmii_0"; 513 drive-strength = <16>; 514 bias-pull-up; 515 }; 516 517 mdio-pins { 518 pins = "gpio176"; 519 function = "rgmii_0"; 520 drive-strength = <16>; 521 bias-pull-up; 522 }; 523 524 rgmii-tx-pins { 525 pins = "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188"; 526 function = "rgmii_0"; 527 drive-strength = <16>; 528 bias-pull-up; 529 }; 530 531 rgmii-rx-pins { 532 pins = "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182"; 533 function = "rgmii_0"; 534 drive-strength = <16>; 535 bias-disable; 536 }; 537 }; 538 539 ethernet1_default: ethernet1-default-state { 540 mdc-pins { 541 pins = "gpio97"; 542 function = "rgmii_1"; 543 drive-strength = <16>; 544 bias-pull-up; 545 }; 546 547 mdio-pins { 548 pins = "gpio98"; 549 function = "rgmii_1"; 550 drive-strength = <16>; 551 bias-pull-up; 552 }; 553 554 rgmii-tx-pins { 555 pins = "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110"; 556 function = "rgmii_1"; 557 drive-strength = <16>; 558 bias-pull-up; 559 }; 560 561 rgmii-rx-pins { 562 pins = "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104"; 563 function = "rgmii_1"; 564 drive-strength = <16>; 565 bias-disable; 566 }; 567 }; 568 569 i2c0_default: i2c0-default-state { 570 /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ 571 pins = "gpio135", "gpio136"; 572 function = "qup0"; 573 drive-strength = <2>; 574 bias-pull-up; 575 }; 576 577 i2c1_default: i2c1-default-state { 578 /* To PM40028B-F3EI PCIe switch */ 579 pins = "gpio158", "gpio159"; 580 function = "qup1"; 581 drive-strength = <2>; 582 bias-pull-up; 583 }; 584 585 i2c12_default: i2c12-default-state { 586 /* To Maxim max20411 */ 587 pins = "gpio0", "gpio1"; 588 function = "qup12"; 589 drive-strength = <2>; 590 bias-pull-up; 591 }; 592 593 i2c15_default: i2c15-default-state { 594 /* To display connector (SIP1 only) */ 595 pins = "gpio36", "gpio37"; 596 function = "qup15"; 597 drive-strength = <2>; 598 bias-pull-up; 599 }; 600 601 i2c18_default: i2c18-default-state { 602 /* To ASM330LHH IMU (SIP1 only) */ 603 pins = "gpio66", "gpio67"; 604 function = "qup18"; 605 drive-strength = <2>; 606 bias-pull-up; 607 }; 608 609 pcie2a_default: pcie2a-default-state { 610 perst-pins { 611 pins = "gpio143"; 612 function = "gpio"; 613 drive-strength = <2>; 614 bias-pull-down; 615 }; 616 617 clkreq-pins { 618 pins = "gpio142"; 619 function = "pcie2a_clkreq"; 620 drive-strength = <2>; 621 bias-pull-up; 622 }; 623 624 wake-pins { 625 pins = "gpio145"; 626 function = "gpio"; 627 drive-strength = <2>; 628 bias-pull-up; 629 }; 630 }; 631 632 pcie3a_default: pcie3a-default-state { 633 perst-pins { 634 pins = "gpio151"; 635 function = "gpio"; 636 drive-strength = <2>; 637 bias-pull-down; 638 }; 639 640 clkreq-pins { 641 pins = "gpio150"; 642 function = "pcie3a_clkreq"; 643 drive-strength = <2>; 644 bias-pull-up; 645 }; 646 647 wake-pins { 648 pins = "gpio56"; 649 function = "gpio"; 650 drive-strength = <2>; 651 bias-pull-up; 652 }; 653 }; 654}; 655