1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 9#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board_clk: xo-board-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32000>; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a78c"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 next-level-cache = <&l2_0>; 51 power-domains = <&cpu_pd0>; 52 power-domain-names = "psci"; 53 capacity-dmips-mhz = <1946>; 54 dynamic-power-coefficient = <472>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 57 l2_0: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 next-level-cache = <&l3_0>; 62 }; 63 }; 64 65 cpu1: cpu@100 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a78c"; 68 reg = <0x0 0x100>; 69 enable-method = "psci"; 70 next-level-cache = <&l2_1>; 71 power-domains = <&cpu_pd1>; 72 power-domain-names = "psci"; 73 capacity-dmips-mhz = <1946>; 74 dynamic-power-coefficient = <472>; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 77 l2_1: l2-cache { 78 compatible = "cache"; 79 cache-level = <2>; 80 cache-unified; 81 next-level-cache = <&l3_0>; 82 }; 83 }; 84 85 cpu2: cpu@200 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a78c"; 88 reg = <0x0 0x200>; 89 enable-method = "psci"; 90 next-level-cache = <&l2_2>; 91 power-domains = <&cpu_pd2>; 92 power-domain-names = "psci"; 93 capacity-dmips-mhz = <1946>; 94 dynamic-power-coefficient = <507>; 95 qcom,freq-domain = <&cpufreq_hw 2>; 96 97 l2_2: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&l3_0>; 102 }; 103 }; 104 105 cpu3: cpu@300 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a78c"; 108 reg = <0x0 0x300>; 109 enable-method = "psci"; 110 next-level-cache = <&l2_3>; 111 power-domains = <&cpu_pd3>; 112 power-domain-names = "psci"; 113 capacity-dmips-mhz = <1946>; 114 dynamic-power-coefficient = <507>; 115 qcom,freq-domain = <&cpufreq_hw 2>; 116 117 l2_3: l2-cache { 118 compatible = "cache"; 119 cache-level = <2>; 120 cache-unified; 121 next-level-cache = <&l3_0>; 122 }; 123 }; 124 125 cpu4: cpu@10000 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a55"; 128 reg = <0x0 0x10000>; 129 enable-method = "psci"; 130 next-level-cache = <&l2_4>; 131 power-domains = <&cpu_pd4>; 132 power-domain-names = "psci"; 133 capacity-dmips-mhz = <1024>; 134 dynamic-power-coefficient = <100>; 135 qcom,freq-domain = <&cpufreq_hw 1>; 136 137 l2_4: l2-cache { 138 compatible = "cache"; 139 cache-level = <2>; 140 cache-unified; 141 next-level-cache = <&l3_1>; 142 }; 143 }; 144 145 cpu5: cpu@10100 { 146 device_type = "cpu"; 147 compatible = "arm,cortex-a55"; 148 reg = <0x0 0x10100>; 149 enable-method = "psci"; 150 next-level-cache = <&l2_5>; 151 power-domains = <&cpu_pd5>; 152 power-domain-names = "psci"; 153 capacity-dmips-mhz = <1024>; 154 dynamic-power-coefficient = <100>; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 157 l2_5: l2-cache { 158 compatible = "cache"; 159 cache-level = <2>; 160 cache-unified; 161 next-level-cache = <&l3_1>; 162 }; 163 }; 164 165 cpu6: cpu@10200 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a55"; 168 reg = <0x0 0x10200>; 169 enable-method = "psci"; 170 next-level-cache = <&l2_6>; 171 power-domains = <&cpu_pd6>; 172 power-domain-names = "psci"; 173 capacity-dmips-mhz = <1024>; 174 dynamic-power-coefficient = <100>; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 177 l2_6: l2-cache { 178 compatible = "cache"; 179 cache-level = <2>; 180 cache-unified; 181 next-level-cache = <&l3_1>; 182 }; 183 }; 184 185 cpu7: cpu@10300 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a55"; 188 reg = <0x0 0x10300>; 189 enable-method = "psci"; 190 next-level-cache = <&l2_7>; 191 power-domains = <&cpu_pd7>; 192 power-domain-names = "psci"; 193 capacity-dmips-mhz = <1024>; 194 dynamic-power-coefficient = <100>; 195 qcom,freq-domain = <&cpufreq_hw 1>; 196 197 l2_7: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&l3_1>; 202 }; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 }; 223 224 cluster1 { 225 core0 { 226 cpu = <&cpu4>; 227 }; 228 229 core1 { 230 cpu = <&cpu5>; 231 }; 232 233 core2 { 234 cpu = <&cpu6>; 235 }; 236 237 core3 { 238 cpu = <&cpu7>; 239 }; 240 }; 241 }; 242 243 l3_0: l3-cache-0 { 244 compatible = "cache"; 245 cache-level = <3>; 246 cache-unified; 247 }; 248 249 l3_1: l3-cache-1 { 250 compatible = "cache"; 251 cache-level = <3>; 252 cache-unified; 253 }; 254 255 idle-states { 256 entry-method = "psci"; 257 258 little_cpu_sleep_0: cpu-sleep-0-0 { 259 compatible = "arm,idle-state"; 260 idle-state-name = "silver-power-collapse"; 261 arm,psci-suspend-param = <0x40000003>; 262 entry-latency-us = <449>; 263 exit-latency-us = <801>; 264 min-residency-us = <1574>; 265 local-timer-stop; 266 }; 267 268 little_cpu_sleep_1: cpu-sleep-0-1 { 269 compatible = "arm,idle-state"; 270 idle-state-name = "silver-rail-power-collapse"; 271 arm,psci-suspend-param = <0x40000004>; 272 entry-latency-us = <602>; 273 exit-latency-us = <961>; 274 min-residency-us = <4288>; 275 local-timer-stop; 276 }; 277 278 big_cpu_sleep_0: cpu-sleep-1-0 { 279 compatible = "arm,idle-state"; 280 idle-state-name = "gold-power-collapse"; 281 arm,psci-suspend-param = <0x40000003>; 282 entry-latency-us = <549>; 283 exit-latency-us = <901>; 284 min-residency-us = <1774>; 285 local-timer-stop; 286 }; 287 288 big_cpu_sleep_1: cpu-sleep-1-1 { 289 compatible = "arm,idle-state"; 290 idle-state-name = "gold-rail-power-collapse"; 291 arm,psci-suspend-param = <0x40000004>; 292 entry-latency-us = <702>; 293 exit-latency-us = <1061>; 294 min-residency-us = <4488>; 295 local-timer-stop; 296 }; 297 }; 298 299 domain-idle-states { 300 silver_cluster_sleep: cluster-sleep-0 { 301 compatible = "domain-idle-state"; 302 arm,psci-suspend-param = <0x41000044>; 303 entry-latency-us = <2552>; 304 exit-latency-us = <2848>; 305 min-residency-us = <5908>; 306 }; 307 308 gold_cluster_sleep: cluster-sleep-1 { 309 compatible = "domain-idle-state"; 310 arm,psci-suspend-param = <0x41000044>; 311 entry-latency-us = <2752>; 312 exit-latency-us = <3048>; 313 min-residency-us = <6118>; 314 }; 315 316 system_sleep: domain-sleep { 317 compatible = "domain-idle-state"; 318 arm,psci-suspend-param = <0x42000144>; 319 entry-latency-us = <3263>; 320 exit-latency-us = <6562>; 321 min-residency-us = <9987>; 322 }; 323 }; 324 }; 325 326 dummy_eud: dummy-sink { 327 compatible = "arm,coresight-dummy-sink"; 328 329 in-ports { 330 port { 331 eud_in: endpoint { 332 remote-endpoint = <&swao_rep_out1>; 333 }; 334 }; 335 }; 336 }; 337 338 firmware { 339 scm: scm { 340 compatible = "qcom,scm-qcs8300", "qcom,scm"; 341 qcom,dload-mode = <&tcsr 0x13000>; 342 }; 343 }; 344 345 memory@80000000 { 346 device_type = "memory"; 347 /* We expect the bootloader to fill in the size */ 348 reg = <0x0 0x80000000 0x0 0x0>; 349 }; 350 351 clk_virt: interconnect-0 { 352 compatible = "qcom,qcs8300-clk-virt"; 353 #interconnect-cells = <2>; 354 qcom,bcm-voters = <&apps_bcm_voter>; 355 }; 356 357 mc_virt: interconnect-1 { 358 compatible = "qcom,qcs8300-mc-virt"; 359 #interconnect-cells = <2>; 360 qcom,bcm-voters = <&apps_bcm_voter>; 361 }; 362 363 qup_opp_table: opp-table-qup { 364 compatible = "operating-points-v2"; 365 366 opp-120000000 { 367 opp-hz = /bits/ 64 <120000000>; 368 required-opps = <&rpmhpd_opp_svs_l1>; 369 }; 370 }; 371 372 pmu-a55 { 373 compatible = "arm,cortex-a55-pmu"; 374 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 375 }; 376 377 pmu-a78 { 378 compatible = "arm,cortex-a78-pmu"; 379 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 380 }; 381 382 psci { 383 compatible = "arm,psci-1.0"; 384 method = "smc"; 385 386 cpu_pd0: power-domain-cpu0 { 387 #power-domain-cells = <0>; 388 power-domains = <&cluster_pd0>; 389 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 390 }; 391 392 cpu_pd1: power-domain-cpu1 { 393 #power-domain-cells = <0>; 394 power-domains = <&cluster_pd0>; 395 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 396 }; 397 398 cpu_pd2: power-domain-cpu2 { 399 #power-domain-cells = <0>; 400 power-domains = <&cluster_pd0>; 401 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 402 }; 403 404 cpu_pd3: power-domain-cpu3 { 405 #power-domain-cells = <0>; 406 power-domains = <&cluster_pd0>; 407 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 408 }; 409 410 cpu_pd4: power-domain-cpu4 { 411 #power-domain-cells = <0>; 412 power-domains = <&cluster_pd1>; 413 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 414 }; 415 416 cpu_pd5: power-domain-cpu5 { 417 #power-domain-cells = <0>; 418 power-domains = <&cluster_pd1>; 419 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 420 }; 421 422 cpu_pd6: power-domain-cpu6 { 423 #power-domain-cells = <0>; 424 power-domains = <&cluster_pd1>; 425 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 426 }; 427 428 cpu_pd7: power-domain-cpu7 { 429 #power-domain-cells = <0>; 430 power-domains = <&cluster_pd1>; 431 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 432 }; 433 434 cluster_pd0: power-domain-cluster0 { 435 #power-domain-cells = <0>; 436 power-domains = <&system_pd>; 437 domain-idle-states = <&gold_cluster_sleep>; 438 }; 439 440 cluster_pd1: power-domain-cluster1 { 441 #power-domain-cells = <0>; 442 power-domains = <&system_pd>; 443 domain-idle-states = <&silver_cluster_sleep>; 444 }; 445 446 system_pd: power-domain-system { 447 #power-domain-cells = <0>; 448 domain-idle-states = <&system_sleep>; 449 }; 450 }; 451 452 reserved-memory { 453 #address-cells = <2>; 454 #size-cells = <2>; 455 ranges; 456 457 aop_image_mem: aop-image-region@90800000 { 458 reg = <0x0 0x90800000 0x0 0x60000>; 459 no-map; 460 }; 461 462 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 463 compatible = "qcom,cmd-db"; 464 reg = <0x0 0x90860000 0x0 0x20000>; 465 no-map; 466 }; 467 468 smem_mem: smem@90900000 { 469 compatible = "qcom,smem"; 470 reg = <0x0 0x90900000 0x0 0x200000>; 471 no-map; 472 hwlocks = <&tcsr_mutex 3>; 473 }; 474 475 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 476 reg = <0x0 0x93b00000 0x0 0xf00000>; 477 no-map; 478 }; 479 480 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 481 reg = <0x0 0x94a00000 0x0 0x800000>; 482 no-map; 483 }; 484 485 camera_mem: camera-region@95200000 { 486 reg = <0x0 0x95200000 0x0 0x500000>; 487 no-map; 488 }; 489 490 adsp_mem: adsp-region@95c00000 { 491 no-map; 492 reg = <0x0 0x95c00000 0x0 0x1e00000>; 493 }; 494 495 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 496 reg = <0x0 0x97a00000 0x0 0x80000>; 497 no-map; 498 }; 499 500 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 501 reg = <0x0 0x97a80000 0x0 0x80000>; 502 no-map; 503 }; 504 505 gpdsp_mem: gpdsp-region@97b00000 { 506 reg = <0x0 0x97b00000 0x0 0x1e00000>; 507 no-map; 508 }; 509 510 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 511 reg = <0x0 0x99900000 0x0 0x80000>; 512 no-map; 513 }; 514 515 cdsp_mem: cdsp-region@99980000 { 516 reg = <0x0 0x99980000 0x0 0x1e00000>; 517 no-map; 518 }; 519 520 gpu_microcode_mem: gpu-microcode-region@9b780000 { 521 reg = <0x0 0x9b780000 0x0 0x2000>; 522 no-map; 523 }; 524 525 cvp_mem: cvp-region@9b782000 { 526 reg = <0x0 0x9b782000 0x0 0x700000>; 527 no-map; 528 }; 529 530 video_mem: video-region@9be82000 { 531 reg = <0x0 0x9be82000 0x0 0x700000>; 532 no-map; 533 }; 534 }; 535 536 smp2p-adsp { 537 compatible = "qcom,smp2p"; 538 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 539 IPCC_MPROC_SIGNAL_SMP2P 540 IRQ_TYPE_EDGE_RISING>; 541 mboxes = <&ipcc IPCC_CLIENT_LPASS 542 IPCC_MPROC_SIGNAL_SMP2P>; 543 544 qcom,smem = <443>, <429>; 545 qcom,local-pid = <0>; 546 qcom,remote-pid = <2>; 547 548 smp2p_adsp_in: slave-kernel { 549 qcom,entry-name = "slave-kernel"; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 }; 553 554 smp2p_adsp_out: master-kernel { 555 qcom,entry-name = "master-kernel"; 556 #qcom,smem-state-cells = <1>; 557 }; 558 }; 559 560 smp2p-cdsp { 561 compatible = "qcom,smp2p"; 562 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 563 IPCC_MPROC_SIGNAL_SMP2P 564 IRQ_TYPE_EDGE_RISING>; 565 mboxes = <&ipcc IPCC_CLIENT_CDSP 566 IPCC_MPROC_SIGNAL_SMP2P>; 567 568 qcom,smem = <94>, <432>; 569 qcom,local-pid = <0>; 570 qcom,remote-pid = <5>; 571 572 smp2p_cdsp_in: slave-kernel { 573 qcom,entry-name = "slave-kernel"; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 }; 577 578 smp2p_cdsp_out: master-kernel { 579 qcom,entry-name = "master-kernel"; 580 #qcom,smem-state-cells = <1>; 581 }; 582 }; 583 584 smp2p-gpdsp { 585 compatible = "qcom,smp2p"; 586 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 587 IPCC_MPROC_SIGNAL_SMP2P 588 IRQ_TYPE_EDGE_RISING>; 589 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 590 IPCC_MPROC_SIGNAL_SMP2P>; 591 592 qcom,smem = <617>, <616>; 593 qcom,local-pid = <0>; 594 qcom,remote-pid = <17>; 595 596 smp2p_gpdsp_in: slave-kernel { 597 qcom,entry-name = "slave-kernel"; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 602 smp2p_gpdsp_out: master-kernel { 603 qcom,entry-name = "master-kernel"; 604 #qcom,smem-state-cells = <1>; 605 }; 606 }; 607 608 soc: soc@0 { 609 compatible = "simple-bus"; 610 ranges = <0 0 0 0 0x10 0>; 611 #address-cells = <2>; 612 #size-cells = <2>; 613 614 gcc: clock-controller@100000 { 615 compatible = "qcom,qcs8300-gcc"; 616 reg = <0x0 0x00100000 0x0 0xc7018>; 617 #clock-cells = <1>; 618 #reset-cells = <1>; 619 #power-domain-cells = <1>; 620 clocks = <&rpmhcc RPMH_CXO_CLK>, 621 <&sleep_clk>, 622 <0>, 623 <0>, 624 <0>, 625 <0>, 626 <0>, 627 <0>, 628 <0>, 629 <0>; 630 }; 631 632 ipcc: mailbox@408000 { 633 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 634 reg = <0x0 0x408000 0x0 0x1000>; 635 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-controller; 637 #interrupt-cells = <3>; 638 #mbox-cells = <2>; 639 }; 640 641 qfprom: efuse@784000 { 642 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 643 reg = <0x0 0x00784000 0x0 0x1200>; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 }; 647 648 gpi_dma0: dma-controller@900000 { 649 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 650 reg = <0x0 0x900000 0x0 0x60000>; 651 #dma-cells = <3>; 652 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 664 iommus = <&apps_smmu 0x416 0x0>; 665 dma-channels = <12>; 666 dma-channel-mask = <0xfff>; 667 dma-coherent; 668 status = "disabled"; 669 }; 670 671 qupv3_id_0: geniqup@9c0000 { 672 compatible = "qcom,geni-se-qup"; 673 reg = <0x0 0x9c0000 0x0 0x2000>; 674 ranges; 675 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 676 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 677 clock-names = "m-ahb", 678 "s-ahb"; 679 #address-cells = <2>; 680 #size-cells = <2>; 681 iommus = <&apps_smmu 0x403 0x0>; 682 dma-coherent; 683 status = "disabled"; 684 685 i2c0: i2c@980000 { 686 compatible = "qcom,geni-i2c"; 687 reg = <0x0 0x980000 0x0 0x4000>; 688 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 689 clock-names = "se"; 690 pinctrl-0 = <&qup_i2c0_data_clk>; 691 pinctrl-names = "default"; 692 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 696 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 697 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 698 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 699 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 700 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 701 interconnect-names = "qup-core", 702 "qup-config", 703 "qup-memory"; 704 power-domains = <&rpmhpd RPMHPD_CX>; 705 required-opps = <&rpmhpd_opp_low_svs>; 706 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 707 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 708 dma-names = "tx", 709 "rx"; 710 status = "disabled"; 711 }; 712 713 spi0: spi@980000 { 714 compatible = "qcom,geni-spi"; 715 reg = <0x0 0x980000 0x0 0x4000>; 716 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 717 clock-names = "se"; 718 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 719 pinctrl-names = "default"; 720 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 724 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 725 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 726 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 727 interconnect-names = "qup-core", 728 "qup-config"; 729 power-domains = <&rpmhpd RPMHPD_CX>; 730 operating-points-v2 = <&qup_opp_table>; 731 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 732 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 733 dma-names = "tx", 734 "rx"; 735 status = "disabled"; 736 }; 737 738 uart0: serial@980000 { 739 compatible = "qcom,geni-uart"; 740 reg = <0x0 0x980000 0x0 0x4000>; 741 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 742 clock-names = "se"; 743 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, 744 <&qup_uart0_tx>, <&qup_uart0_rx>; 745 pinctrl-names = "default"; 746 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 747 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 748 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 749 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 750 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 751 interconnect-names = "qup-core", 752 "qup-config"; 753 power-domains = <&rpmhpd RPMHPD_CX>; 754 operating-points-v2 = <&qup_opp_table>; 755 status = "disabled"; 756 }; 757 758 i2c1: i2c@984000 { 759 compatible = "qcom,geni-i2c"; 760 reg = <0x0 0x984000 0x0 0x4000>; 761 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 762 clock-names = "se"; 763 pinctrl-0 = <&qup_i2c1_data_clk>; 764 pinctrl-names = "default"; 765 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 769 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 770 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 771 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 772 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 773 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 774 interconnect-names = "qup-core", 775 "qup-config", 776 "qup-memory"; 777 power-domains = <&rpmhpd RPMHPD_CX>; 778 required-opps = <&rpmhpd_opp_low_svs>; 779 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 780 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 781 dma-names = "tx", 782 "rx"; 783 status = "disabled"; 784 }; 785 786 spi1: spi@984000 { 787 compatible = "qcom,geni-spi"; 788 reg = <0x0 0x984000 0x0 0x4000>; 789 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 790 clock-names = "se"; 791 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 792 pinctrl-names = "default"; 793 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 797 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 798 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 799 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 800 interconnect-names = "qup-core", 801 "qup-config"; 802 power-domains = <&rpmhpd RPMHPD_CX>; 803 operating-points-v2 = <&qup_opp_table>; 804 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 805 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 806 dma-names = "tx", 807 "rx"; 808 status = "disabled"; 809 }; 810 811 uart1: serial@984000 { 812 compatible = "qcom,geni-uart"; 813 reg = <0x0 0x984000 0x0 0x4000>; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 815 clock-names = "se"; 816 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, 817 <&qup_uart1_tx>, <&qup_uart1_rx>; 818 pinctrl-names = "default"; 819 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 820 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 821 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 822 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 823 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 824 interconnect-names = "qup-core", 825 "qup-config"; 826 power-domains = <&rpmhpd RPMHPD_CX>; 827 operating-points-v2 = <&qup_opp_table>; 828 status = "disabled"; 829 }; 830 831 i2c2: i2c@988000 { 832 compatible = "qcom,geni-i2c"; 833 reg = <0x0 0x988000 0x0 0x4000>; 834 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 835 clock-names = "se"; 836 pinctrl-0 = <&qup_i2c2_data_clk>; 837 pinctrl-names = "default"; 838 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 842 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 843 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 844 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 845 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 846 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 847 interconnect-names = "qup-core", 848 "qup-config", 849 "qup-memory"; 850 power-domains = <&rpmhpd RPMHPD_CX>; 851 required-opps = <&rpmhpd_opp_low_svs>; 852 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 853 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 854 dma-names = "tx", 855 "rx"; 856 status = "disabled"; 857 }; 858 859 spi2: spi@988000 { 860 compatible = "qcom,geni-spi"; 861 reg = <0x0 0x988000 0x0 0x4000>; 862 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 863 clock-names = "se"; 864 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 865 pinctrl-names = "default"; 866 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 870 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 871 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 872 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 873 interconnect-names = "qup-core", 874 "qup-config"; 875 power-domains = <&rpmhpd RPMHPD_CX>; 876 operating-points-v2 = <&qup_opp_table>; 877 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 878 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 879 dma-names = "tx", 880 "rx"; 881 status = "disabled"; 882 }; 883 884 uart2: serial@988000 { 885 compatible = "qcom,geni-uart"; 886 reg = <0x0 0x988000 0x0 0x4000>; 887 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 888 clock-names = "se"; 889 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 890 <&qup_uart2_tx>, <&qup_uart2_rx>; 891 pinctrl-names = "default"; 892 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 893 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 894 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 895 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 896 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 897 interconnect-names = "qup-core", 898 "qup-config"; 899 power-domains = <&rpmhpd RPMHPD_CX>; 900 operating-points-v2 = <&qup_opp_table>; 901 status = "disabled"; 902 }; 903 904 i2c3: i2c@98c000 { 905 compatible = "qcom,geni-i2c"; 906 reg = <0x0 0x98c000 0x0 0x4000>; 907 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 908 clock-names = "se"; 909 pinctrl-0 = <&qup_i2c3_data_clk>; 910 pinctrl-names = "default"; 911 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 915 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 917 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 918 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 920 interconnect-names = "qup-core", 921 "qup-config", 922 "qup-memory"; 923 power-domains = <&rpmhpd RPMHPD_CX>; 924 required-opps = <&rpmhpd_opp_low_svs>; 925 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 926 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 927 dma-names = "tx", 928 "rx"; 929 status = "disabled"; 930 }; 931 932 spi3: spi@98c000 { 933 compatible = "qcom,geni-spi"; 934 reg = <0x0 0x98c000 0x0 0x4000>; 935 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 936 clock-names = "se"; 937 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 938 pinctrl-names = "default"; 939 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 943 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 944 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 945 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 946 interconnect-names = "qup-core", 947 "qup-config"; 948 power-domains = <&rpmhpd RPMHPD_CX>; 949 operating-points-v2 = <&qup_opp_table>; 950 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 951 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 952 dma-names = "tx", 953 "rx"; 954 status = "disabled"; 955 }; 956 957 uart3: serial@98c000 { 958 compatible = "qcom,geni-uart"; 959 reg = <0x0 0x98c000 0x0 0x4000>; 960 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 961 clock-names = "se"; 962 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, 963 <&qup_uart3_tx>, <&qup_uart3_rx>; 964 pinctrl-names = "default"; 965 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 966 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 967 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 968 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 969 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 970 interconnect-names = "qup-core", 971 "qup-config"; 972 power-domains = <&rpmhpd RPMHPD_CX>; 973 operating-points-v2 = <&qup_opp_table>; 974 status = "disabled"; 975 }; 976 977 i2c4: i2c@990000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0x0 0x990000 0x0 0x4000>; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 981 clock-names = "se"; 982 pinctrl-0 = <&qup_i2c4_data_clk>; 983 pinctrl-names = "default"; 984 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 988 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 989 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 990 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 991 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 992 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 993 interconnect-names = "qup-core", 994 "qup-config", 995 "qup-memory"; 996 power-domains = <&rpmhpd RPMHPD_CX>; 997 required-opps = <&rpmhpd_opp_low_svs>; 998 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 999 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1000 dma-names = "tx", 1001 "rx"; 1002 status = "disabled"; 1003 }; 1004 1005 spi4: spi@990000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0x0 0x990000 0x0 0x4000>; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1009 clock-names = "se"; 1010 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1011 pinctrl-names = "default"; 1012 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1016 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1017 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1018 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1019 interconnect-names = "qup-core", 1020 "qup-config"; 1021 power-domains = <&rpmhpd RPMHPD_CX>; 1022 operating-points-v2 = <&qup_opp_table>; 1023 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1024 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1025 dma-names = "tx", 1026 "rx"; 1027 status = "disabled"; 1028 }; 1029 1030 uart4: serial@990000 { 1031 compatible = "qcom,geni-uart"; 1032 reg = <0x0 0x990000 0x0 0x4000>; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1034 clock-names = "se"; 1035 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1036 <&qup_uart4_tx>, <&qup_uart4_rx>; 1037 pinctrl-names = "default"; 1038 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1039 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1040 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1041 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1042 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1043 interconnect-names = "qup-core", 1044 "qup-config"; 1045 power-domains = <&rpmhpd RPMHPD_CX>; 1046 operating-points-v2 = <&qup_opp_table>; 1047 status = "disabled"; 1048 }; 1049 1050 i2c5: i2c@994000 { 1051 compatible = "qcom,geni-i2c"; 1052 reg = <0x0 0x994000 0x0 0x4000>; 1053 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1054 clock-names = "se"; 1055 pinctrl-0 = <&qup_i2c5_data_clk>; 1056 pinctrl-names = "default"; 1057 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1061 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1062 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1063 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1064 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1065 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1066 interconnect-names = "qup-core", 1067 "qup-config", 1068 "qup-memory"; 1069 power-domains = <&rpmhpd RPMHPD_CX>; 1070 required-opps = <&rpmhpd_opp_low_svs>; 1071 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1072 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1073 dma-names = "tx", 1074 "rx"; 1075 status = "disabled"; 1076 }; 1077 1078 spi5: spi@994000 { 1079 compatible = "qcom,geni-spi"; 1080 reg = <0x0 0x994000 0x0 0x4000>; 1081 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1082 clock-names = "se"; 1083 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1084 pinctrl-names = "default"; 1085 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1089 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1091 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1092 interconnect-names = "qup-core", 1093 "qup-config"; 1094 power-domains = <&rpmhpd RPMHPD_CX>; 1095 operating-points-v2 = <&qup_opp_table>; 1096 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1097 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1098 dma-names = "tx", 1099 "rx"; 1100 status = "disabled"; 1101 }; 1102 1103 uart5: serial@994000 { 1104 compatible = "qcom,geni-uart"; 1105 reg = <0x0 0x994000 0x0 0x4000>; 1106 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1107 clock-names = "se"; 1108 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, 1109 <&qup_uart5_tx>, <&qup_uart5_rx>; 1110 pinctrl-names = "default"; 1111 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1112 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1113 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1114 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1115 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1116 interconnect-names = "qup-core", 1117 "qup-config"; 1118 power-domains = <&rpmhpd RPMHPD_CX>; 1119 operating-points-v2 = <&qup_opp_table>; 1120 status = "disabled"; 1121 }; 1122 1123 i2c6: i2c@998000 { 1124 compatible = "qcom,geni-i2c"; 1125 reg = <0x0 0x998000 0x0 0x4000>; 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1127 clock-names = "se"; 1128 pinctrl-0 = <&qup_i2c6_data_clk>; 1129 pinctrl-names = "default"; 1130 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1134 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1135 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1136 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1137 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1138 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1139 interconnect-names = "qup-core", 1140 "qup-config", 1141 "qup-memory"; 1142 power-domains = <&rpmhpd RPMHPD_CX>; 1143 required-opps = <&rpmhpd_opp_low_svs>; 1144 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1145 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1146 dma-names = "tx", 1147 "rx"; 1148 status = "disabled"; 1149 }; 1150 1151 spi6: spi@998000 { 1152 compatible = "qcom,geni-spi"; 1153 reg = <0x0 0x998000 0x0 0x4000>; 1154 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1155 clock-names = "se"; 1156 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1157 pinctrl-names = "default"; 1158 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1162 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1163 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1164 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1165 interconnect-names = "qup-core", 1166 "qup-config"; 1167 power-domains = <&rpmhpd RPMHPD_CX>; 1168 operating-points-v2 = <&qup_opp_table>; 1169 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1170 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1171 dma-names = "tx", 1172 "rx"; 1173 status = "disabled"; 1174 }; 1175 1176 uart6: serial@998000 { 1177 compatible = "qcom,geni-uart"; 1178 reg = <0x0 0x998000 0x0 0x4000>; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1180 clock-names = "se"; 1181 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1182 <&qup_uart6_tx>, <&qup_uart6_rx>; 1183 pinctrl-names = "default"; 1184 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1185 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1186 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1187 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1188 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1189 interconnect-names = "qup-core", 1190 "qup-config"; 1191 power-domains = <&rpmhpd RPMHPD_CX>; 1192 operating-points-v2 = <&qup_opp_table>; 1193 status = "disabled"; 1194 }; 1195 1196 uart7: serial@99c000 { 1197 compatible = "qcom,geni-debug-uart"; 1198 reg = <0x0 0x0099c000 0x0 0x4000>; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1200 clock-names = "se"; 1201 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1202 pinctrl-names = "default"; 1203 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1205 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1206 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1207 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1208 interconnect-names = "qup-core", 1209 "qup-config"; 1210 power-domains = <&rpmhpd RPMHPD_CX>; 1211 operating-points-v2 = <&qup_opp_table>; 1212 status = "disabled"; 1213 }; 1214 }; 1215 1216 gpi_dma1: dma-controller@a00000 { 1217 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1218 reg = <0x0 0xa00000 0x0 0x60000>; 1219 #dma-cells = <3>; 1220 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1232 iommus = <&apps_smmu 0x456 0x0>; 1233 dma-channels = <12>; 1234 dma-channel-mask = <0xfff>; 1235 dma-coherent; 1236 status = "disabled"; 1237 }; 1238 1239 qupv3_id_1: geniqup@ac0000 { 1240 compatible = "qcom,geni-se-qup"; 1241 reg = <0x0 0xac0000 0x0 0x2000>; 1242 ranges; 1243 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1244 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1245 clock-names = "m-ahb", 1246 "s-ahb"; 1247 #address-cells = <2>; 1248 #size-cells = <2>; 1249 iommus = <&apps_smmu 0x443 0x0>; 1250 dma-coherent; 1251 status = "disabled"; 1252 1253 i2c8: i2c@a80000 { 1254 compatible = "qcom,geni-i2c"; 1255 reg = <0x0 0xa80000 0x0 0x4000>; 1256 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1257 clock-names = "se"; 1258 pinctrl-0 = <&qup_i2c8_data_clk>; 1259 pinctrl-names = "default"; 1260 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1264 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1265 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1266 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1267 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1268 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1269 interconnect-names = "qup-core", 1270 "qup-config", 1271 "qup-memory"; 1272 power-domains = <&rpmhpd RPMHPD_CX>; 1273 required-opps = <&rpmhpd_opp_low_svs>; 1274 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1275 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1276 dma-names = "tx", 1277 "rx"; 1278 status = "disabled"; 1279 }; 1280 1281 spi8: spi@a80000 { 1282 compatible = "qcom,geni-spi"; 1283 reg = <0x0 0xa80000 0x0 0x4000>; 1284 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1285 clock-names = "se"; 1286 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1287 pinctrl-names = "default"; 1288 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1292 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1293 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1294 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1295 interconnect-names = "qup-core", 1296 "qup-config"; 1297 power-domains = <&rpmhpd RPMHPD_CX>; 1298 operating-points-v2 = <&qup_opp_table>; 1299 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1300 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1301 dma-names = "tx", 1302 "rx"; 1303 status = "disabled"; 1304 }; 1305 1306 uart8: serial@a80000 { 1307 compatible = "qcom,geni-uart"; 1308 reg = <0x0 0xa80000 0x0 0x4000>; 1309 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1310 clock-names = "se"; 1311 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, 1312 <&qup_uart8_tx>, <&qup_uart8_rx>; 1313 pinctrl-names = "default"; 1314 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1316 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1317 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1318 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1319 interconnect-names = "qup-core", 1320 "qup-config"; 1321 power-domains = <&rpmhpd RPMHPD_CX>; 1322 operating-points-v2 = <&qup_opp_table>; 1323 status = "disabled"; 1324 }; 1325 1326 i2c9: i2c@a84000 { 1327 compatible = "qcom,geni-i2c"; 1328 reg = <0x0 0xa84000 0x0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1330 clock-names = "se"; 1331 pinctrl-0 = <&qup_i2c9_data_clk>; 1332 pinctrl-names = "default"; 1333 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1337 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1338 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1339 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1340 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1341 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1342 interconnect-names = "qup-core", 1343 "qup-config", 1344 "qup-memory"; 1345 power-domains = <&rpmhpd RPMHPD_CX>; 1346 required-opps = <&rpmhpd_opp_low_svs>; 1347 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1348 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1349 dma-names = "tx", 1350 "rx"; 1351 status = "disabled"; 1352 }; 1353 1354 spi9: spi@a84000 { 1355 compatible = "qcom,geni-spi"; 1356 reg = <0x0 0xa84000 0x0 0x4000>; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1358 clock-names = "se"; 1359 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1360 pinctrl-names = "default"; 1361 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1365 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1366 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1367 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1368 interconnect-names = "qup-core", 1369 "qup-config"; 1370 power-domains = <&rpmhpd RPMHPD_CX>; 1371 operating-points-v2 = <&qup_opp_table>; 1372 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1373 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1374 dma-names = "tx", 1375 "rx"; 1376 status = "disabled"; 1377 }; 1378 1379 uart9: serial@a84000 { 1380 compatible = "qcom,geni-uart"; 1381 reg = <0x0 0xa84000 0x0 0x4000>; 1382 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1383 clock-names = "se"; 1384 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, 1385 <&qup_uart9_tx>, <&qup_uart9_rx>; 1386 pinctrl-names = "default"; 1387 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1389 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1390 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1391 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1392 interconnect-names = "qup-core", 1393 "qup-config"; 1394 power-domains = <&rpmhpd RPMHPD_CX>; 1395 operating-points-v2 = <&qup_opp_table>; 1396 status = "disabled"; 1397 }; 1398 1399 i2c10: i2c@a88000 { 1400 compatible = "qcom,geni-i2c"; 1401 reg = <0x0 0xa88000 0x0 0x4000>; 1402 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1403 clock-names = "se"; 1404 pinctrl-0 = <&qup_i2c10_data_clk>; 1405 pinctrl-names = "default"; 1406 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1410 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1411 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1412 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1413 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1414 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1415 interconnect-names = "qup-core", 1416 "qup-config", 1417 "qup-memory"; 1418 power-domains = <&rpmhpd RPMHPD_CX>; 1419 required-opps = <&rpmhpd_opp_low_svs>; 1420 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1421 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1422 dma-names = "tx", 1423 "rx"; 1424 status = "disabled"; 1425 }; 1426 1427 spi10: spi@a88000 { 1428 compatible = "qcom,geni-spi"; 1429 reg = <0x0 0xa88000 0x0 0x4000>; 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1431 clock-names = "se"; 1432 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1433 pinctrl-names = "default"; 1434 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1438 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1439 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1440 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1441 interconnect-names = "qup-core", 1442 "qup-config"; 1443 power-domains = <&rpmhpd RPMHPD_CX>; 1444 operating-points-v2 = <&qup_opp_table>; 1445 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1446 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1447 dma-names = "tx", 1448 "rx"; 1449 status = "disabled"; 1450 }; 1451 1452 uart10: serial@a88000 { 1453 compatible = "qcom,geni-uart"; 1454 reg = <0x0 0xa88000 0x0 0x4000>; 1455 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1456 clock-names = "se"; 1457 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, 1458 <&qup_uart10_tx>, <&qup_uart10_rx>; 1459 pinctrl-names = "default"; 1460 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1461 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1462 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1463 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1464 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1465 interconnect-names = "qup-core", 1466 "qup-config"; 1467 power-domains = <&rpmhpd RPMHPD_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 status = "disabled"; 1470 }; 1471 1472 i2c11: i2c@a8c000 { 1473 compatible = "qcom,geni-i2c"; 1474 reg = <0x0 0xa8c000 0x0 0x4000>; 1475 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1476 clock-names = "se"; 1477 pinctrl-0 = <&qup_i2c11_data_clk>; 1478 pinctrl-names = "default"; 1479 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1483 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1484 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1485 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1486 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1487 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1488 interconnect-names = "qup-core", 1489 "qup-config", 1490 "qup-memory"; 1491 power-domains = <&rpmhpd RPMHPD_CX>; 1492 required-opps = <&rpmhpd_opp_low_svs>; 1493 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1494 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1495 dma-names = "tx", 1496 "rx"; 1497 status = "disabled"; 1498 }; 1499 1500 uart11: serial@a8c000 { 1501 compatible = "qcom,geni-uart"; 1502 reg = <0x0 0xa8c000 0x0 0x4000>; 1503 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1504 clock-names = "se"; 1505 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; 1506 pinctrl-names = "default"; 1507 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1509 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1510 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1511 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1512 interconnect-names = "qup-core", 1513 "qup-config"; 1514 power-domains = <&rpmhpd RPMHPD_CX>; 1515 operating-points-v2 = <&qup_opp_table>; 1516 status = "disabled"; 1517 }; 1518 1519 i2c12: i2c@a90000 { 1520 compatible = "qcom,geni-i2c"; 1521 reg = <0x0 0xa90000 0x0 0x4000>; 1522 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1523 clock-names = "se"; 1524 pinctrl-0 = <&qup_i2c12_data_clk>; 1525 pinctrl-names = "default"; 1526 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1530 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1531 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1532 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1533 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1534 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1535 interconnect-names = "qup-core", 1536 "qup-config", 1537 "qup-memory"; 1538 power-domains = <&rpmhpd RPMHPD_CX>; 1539 required-opps = <&rpmhpd_opp_low_svs>; 1540 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1541 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1542 dma-names = "tx", 1543 "rx"; 1544 status = "disabled"; 1545 }; 1546 1547 spi12: spi@a90000 { 1548 compatible = "qcom,geni-spi"; 1549 reg = <0x0 0xa90000 0x0 0x4000>; 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1551 clock-names = "se"; 1552 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1553 pinctrl-names = "default"; 1554 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1558 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1559 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1560 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1561 interconnect-names = "qup-core", 1562 "qup-config"; 1563 power-domains = <&rpmhpd RPMHPD_CX>; 1564 operating-points-v2 = <&qup_opp_table>; 1565 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1566 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1567 dma-names = "tx", 1568 "rx"; 1569 status = "disabled"; 1570 }; 1571 1572 uart12: serial@a90000 { 1573 compatible = "qcom,geni-uart"; 1574 reg = <0x0 0xa90000 0x0 0x4000>; 1575 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1576 clock-names = "se"; 1577 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, 1578 <&qup_uart12_tx>, <&qup_uart12_rx>; 1579 pinctrl-names = "default"; 1580 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1581 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1582 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1584 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1585 interconnect-names = "qup-core", 1586 "qup-config"; 1587 power-domains = <&rpmhpd RPMHPD_CX>; 1588 operating-points-v2 = <&qup_opp_table>; 1589 status = "disabled"; 1590 }; 1591 1592 i2c13: i2c@a94000 { 1593 compatible = "qcom,geni-i2c"; 1594 reg = <0x0 0xa94000 0x0 0x4000>; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1596 clock-names = "se"; 1597 pinctrl-0 = <&qup_i2c13_data_clk>; 1598 pinctrl-names = "default"; 1599 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1603 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1604 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1605 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1606 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1607 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1608 interconnect-names = "qup-core", 1609 "qup-config", 1610 "qup-memory"; 1611 power-domains = <&rpmhpd RPMHPD_CX>; 1612 required-opps = <&rpmhpd_opp_low_svs>; 1613 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1614 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1615 dma-names = "tx", 1616 "rx"; 1617 status = "disabled"; 1618 }; 1619 1620 spi13: spi@a94000 { 1621 compatible = "qcom,geni-spi"; 1622 reg = <0x0 0xa94000 0x0 0x4000>; 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1624 clock-names = "se"; 1625 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1626 pinctrl-names = "default"; 1627 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1631 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1632 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1633 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1634 interconnect-names = "qup-core", 1635 "qup-config"; 1636 power-domains = <&rpmhpd RPMHPD_CX>; 1637 operating-points-v2 = <&qup_opp_table>; 1638 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1639 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1640 dma-names = "tx", 1641 "rx"; 1642 status = "disabled"; 1643 }; 1644 1645 uart13: serial@a94000 { 1646 compatible = "qcom,geni-uart"; 1647 reg = <0x0 0xa94000 0x0 0x4000>; 1648 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1649 clock-names = "se"; 1650 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, 1651 <&qup_uart13_tx>, <&qup_uart13_rx>; 1652 pinctrl-names = "default"; 1653 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1655 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1656 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1657 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1658 interconnect-names = "qup-core", 1659 "qup-config"; 1660 power-domains = <&rpmhpd RPMHPD_CX>; 1661 operating-points-v2 = <&qup_opp_table>; 1662 status = "disabled"; 1663 }; 1664 1665 i2c14: i2c@a98000 { 1666 compatible = "qcom,geni-i2c"; 1667 reg = <0x0 0xa98000 0x0 0x4000>; 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1669 clock-names = "se"; 1670 pinctrl-0 = <&qup_i2c14_data_clk>; 1671 pinctrl-names = "default"; 1672 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1676 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1677 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1678 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1679 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1680 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1681 interconnect-names = "qup-core", 1682 "qup-config", 1683 "qup-memory"; 1684 power-domains = <&rpmhpd RPMHPD_CX>; 1685 required-opps = <&rpmhpd_opp_low_svs>; 1686 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1687 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1688 dma-names = "tx", 1689 "rx"; 1690 status = "disabled"; 1691 }; 1692 1693 spi14: spi@a98000 { 1694 compatible = "qcom,geni-spi"; 1695 reg = <0x0 0xa98000 0x0 0x4000>; 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1697 clock-names = "se"; 1698 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1699 pinctrl-names = "default"; 1700 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1704 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1705 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1706 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1707 interconnect-names = "qup-core", 1708 "qup-config"; 1709 power-domains = <&rpmhpd RPMHPD_CX>; 1710 operating-points-v2 = <&qup_opp_table>; 1711 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1712 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1713 dma-names = "tx", 1714 "rx"; 1715 status = "disabled"; 1716 }; 1717 1718 uart14: serial@a98000 { 1719 compatible = "qcom,geni-uart"; 1720 reg = <0x0 0xa98000 0x0 0x4000>; 1721 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1722 clock-names = "se"; 1723 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, 1724 <&qup_uart14_tx>, <&qup_uart14_rx>; 1725 pinctrl-names = "default"; 1726 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1727 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1728 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1729 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1730 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1731 interconnect-names = "qup-core", 1732 "qup-config"; 1733 power-domains = <&rpmhpd RPMHPD_CX>; 1734 operating-points-v2 = <&qup_opp_table>; 1735 status = "disabled"; 1736 }; 1737 1738 i2c15: i2c@a9c000 { 1739 compatible = "qcom,geni-i2c"; 1740 reg = <0x0 0xa9c000 0x0 0x4000>; 1741 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1742 clock-names = "se"; 1743 pinctrl-0 = <&qup_i2c15_data_clk>; 1744 pinctrl-names = "default"; 1745 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1749 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1750 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1751 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1752 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1753 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1754 interconnect-names = "qup-core", 1755 "qup-config", 1756 "qup-memory"; 1757 power-domains = <&rpmhpd RPMHPD_CX>; 1758 required-opps = <&rpmhpd_opp_low_svs>; 1759 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1760 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1761 dma-names = "tx", 1762 "rx"; 1763 status = "disabled"; 1764 }; 1765 1766 spi15: spi@a9c000 { 1767 compatible = "qcom,geni-spi"; 1768 reg = <0x0 0xa9c000 0x0 0x4000>; 1769 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1770 clock-names = "se"; 1771 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1772 pinctrl-names = "default"; 1773 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1777 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1778 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1779 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1780 interconnect-names = "qup-core", 1781 "qup-config"; 1782 power-domains = <&rpmhpd RPMHPD_CX>; 1783 operating-points-v2 = <&qup_opp_table>; 1784 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1785 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1786 dma-names = "tx", 1787 "rx"; 1788 status = "disabled"; 1789 }; 1790 1791 uart15: serial@a9c000 { 1792 compatible = "qcom,geni-uart"; 1793 reg = <0x0 0xa9c000 0x0 0x4000>; 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1795 clock-names = "se"; 1796 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, 1797 <&qup_uart15_tx>, <&qup_uart15_rx>; 1798 pinctrl-names = "default"; 1799 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1800 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1801 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1802 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1803 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1804 interconnect-names = "qup-core", 1805 "qup-config"; 1806 power-domains = <&rpmhpd RPMHPD_CX>; 1807 operating-points-v2 = <&qup_opp_table>; 1808 status = "disabled"; 1809 }; 1810 }; 1811 1812 gpi_dma3: dma-controller@b00000 { 1813 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1814 reg = <0x0 0xb00000 0x0 0x60000>; 1815 #dma-cells = <3>; 1816 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 1820 iommus = <&apps_smmu 0x56 0x0>; 1821 dma-channels = <4>; 1822 dma-channel-mask = <0xf>; 1823 dma-coherent; 1824 status = "disabled"; 1825 }; 1826 1827 qupv3_id_3: geniqup@bc0000 { 1828 compatible = "qcom,geni-se-qup"; 1829 reg = <0x0 0xbc0000 0x0 0x2000>; 1830 ranges; 1831 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 1832 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 1833 clock-names = "m-ahb", 1834 "s-ahb"; 1835 #address-cells = <2>; 1836 #size-cells = <2>; 1837 iommus = <&apps_smmu 0x43 0x0>; 1838 dma-coherent; 1839 status = "disabled"; 1840 1841 i2c16: i2c@b80000 { 1842 compatible = "qcom,geni-i2c"; 1843 reg = <0x0 0xb80000 0x0 0x4000>; 1844 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1845 clock-names = "se"; 1846 pinctrl-0 = <&qup_i2c16_data_clk>; 1847 pinctrl-names = "default"; 1848 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1852 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1853 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1854 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1855 <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1856 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1857 interconnect-names = "qup-core", 1858 "qup-config", 1859 "qup-memory"; 1860 power-domains = <&rpmhpd RPMHPD_CX>; 1861 required-opps = <&rpmhpd_opp_low_svs>; 1862 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 1863 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 1864 dma-names = "tx", 1865 "rx"; 1866 status = "disabled"; 1867 }; 1868 1869 spi16: spi@b80000 { 1870 compatible = "qcom,geni-spi"; 1871 reg = <0x0 0xb80000 0x0 0x4000>; 1872 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1873 clock-names = "se"; 1874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 1875 pinctrl-names = "default"; 1876 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1880 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1881 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1882 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 1883 interconnect-names = "qup-core", 1884 "qup-config"; 1885 power-domains = <&rpmhpd RPMHPD_CX>; 1886 operating-points-v2 = <&qup_opp_table>; 1887 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 1888 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 1889 dma-names = "tx", 1890 "rx"; 1891 status = "disabled"; 1892 }; 1893 1894 uart16: serial@b80000 { 1895 compatible = "qcom,geni-uart"; 1896 reg = <0x0 0xb80000 0x0 0x4000>; 1897 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1898 clock-names = "se"; 1899 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, 1900 <&qup_uart16_tx>, <&qup_uart16_rx>; 1901 pinctrl-names = "default"; 1902 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1904 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1905 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1906 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 1907 interconnect-names = "qup-core", 1908 "qup-config"; 1909 power-domains = <&rpmhpd RPMHPD_CX>; 1910 operating-points-v2 = <&qup_opp_table>; 1911 status = "disabled"; 1912 }; 1913 }; 1914 1915 rng: rng@10d2000 { 1916 compatible = "qcom,qcs8300-trng", "qcom,trng"; 1917 reg = <0x0 0x010d2000 0x0 0x1000>; 1918 }; 1919 1920 config_noc: interconnect@14c0000 { 1921 compatible = "qcom,qcs8300-config-noc"; 1922 reg = <0x0 0x014c0000 0x0 0x13080>; 1923 #interconnect-cells = <2>; 1924 qcom,bcm-voters = <&apps_bcm_voter>; 1925 }; 1926 1927 system_noc: interconnect@1680000 { 1928 compatible = "qcom,qcs8300-system-noc"; 1929 reg = <0x0 0x01680000 0x0 0x15080>; 1930 #interconnect-cells = <2>; 1931 qcom,bcm-voters = <&apps_bcm_voter>; 1932 }; 1933 1934 aggre1_noc: interconnect@16c0000 { 1935 compatible = "qcom,qcs8300-aggre1-noc"; 1936 reg = <0x0 0x016c0000 0x0 0x17080>; 1937 #interconnect-cells = <2>; 1938 qcom,bcm-voters = <&apps_bcm_voter>; 1939 }; 1940 1941 aggre2_noc: interconnect@1700000 { 1942 compatible = "qcom,qcs8300-aggre2-noc"; 1943 reg = <0x0 0x01700000 0x0 0x1a080>; 1944 #interconnect-cells = <2>; 1945 qcom,bcm-voters = <&apps_bcm_voter>; 1946 }; 1947 1948 pcie_anoc: interconnect@1760000 { 1949 compatible = "qcom,qcs8300-pcie-anoc"; 1950 reg = <0x0 0x01760000 0x0 0xc080>; 1951 #interconnect-cells = <2>; 1952 qcom,bcm-voters = <&apps_bcm_voter>; 1953 }; 1954 1955 gpdsp_anoc: interconnect@1780000 { 1956 compatible = "qcom,qcs8300-gpdsp-anoc"; 1957 reg = <0x0 0x01780000 0x0 0xd080>; 1958 #interconnect-cells = <2>; 1959 qcom,bcm-voters = <&apps_bcm_voter>; 1960 }; 1961 1962 mmss_noc: interconnect@17a0000 { 1963 compatible = "qcom,qcs8300-mmss-noc"; 1964 reg = <0x0 0x017a0000 0x0 0x40000>; 1965 #interconnect-cells = <2>; 1966 qcom,bcm-voters = <&apps_bcm_voter>; 1967 }; 1968 1969 ufs_mem_hc: ufs@1d84000 { 1970 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1971 reg = <0x0 0x01d84000 0x0 0x3000>; 1972 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1973 phys = <&ufs_mem_phy>; 1974 phy-names = "ufsphy"; 1975 lanes-per-direction = <2>; 1976 #reset-cells = <1>; 1977 resets = <&gcc GCC_UFS_PHY_BCR>; 1978 reset-names = "rst"; 1979 1980 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1981 required-opps = <&rpmhpd_opp_nom>; 1982 1983 iommus = <&apps_smmu 0x100 0x0>; 1984 dma-coherent; 1985 1986 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1987 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1988 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1989 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1990 interconnect-names = "ufs-ddr", 1991 "cpu-ufs"; 1992 1993 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1994 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1995 <&gcc GCC_UFS_PHY_AHB_CLK>, 1996 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1997 <&rpmhcc RPMH_CXO_CLK>, 1998 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1999 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2000 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2001 clock-names = "core_clk", 2002 "bus_aggr_clk", 2003 "iface_clk", 2004 "core_clk_unipro", 2005 "ref_clk", 2006 "tx_lane0_sync_clk", 2007 "rx_lane0_sync_clk", 2008 "rx_lane1_sync_clk"; 2009 freq-table-hz = <75000000 300000000>, 2010 <0 0>, 2011 <0 0>, 2012 <75000000 300000000>, 2013 <0 0>, 2014 <0 0>, 2015 <0 0>, 2016 <0 0>; 2017 qcom,ice = <&ice>; 2018 status = "disabled"; 2019 }; 2020 2021 ufs_mem_phy: phy@1d87000 { 2022 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 2023 reg = <0x0 0x01d87000 0x0 0xe10>; 2024 /* 2025 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2026 * enables the CXO clock to eDP *and* UFS PHY. 2027 */ 2028 clocks = <&rpmhcc RPMH_CXO_CLK>, 2029 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2030 <&gcc GCC_EDP_REF_CLKREF_EN>; 2031 clock-names = "ref", 2032 "ref_aux", 2033 "qref"; 2034 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2035 2036 resets = <&ufs_mem_hc 0>; 2037 reset-names = "ufsphy"; 2038 2039 #phy-cells = <0>; 2040 status = "disabled"; 2041 }; 2042 2043 cryptobam: dma-controller@1dc4000 { 2044 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2045 reg = <0x0 0x01dc4000 0x0 0x28000>; 2046 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2047 #dma-cells = <1>; 2048 qcom,ee = <0>; 2049 qcom,controlled-remotely; 2050 num-channels = <20>; 2051 qcom,num-ees = <4>; 2052 iommus = <&apps_smmu 0x480 0x00>, 2053 <&apps_smmu 0x481 0x00>; 2054 }; 2055 2056 ice: crypto@1d88000 { 2057 compatible = "qcom,qcs8300-inline-crypto-engine", 2058 "qcom,inline-crypto-engine"; 2059 reg = <0x0 0x01d88000 0x0 0x18000>; 2060 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2061 }; 2062 2063 tcsr_mutex: hwlock@1f40000 { 2064 compatible = "qcom,tcsr-mutex"; 2065 reg = <0x0 0x01f40000 0x0 0x20000>; 2066 #hwlock-cells = <1>; 2067 }; 2068 2069 tcsr: syscon@1fc0000 { 2070 compatible = "qcom,qcs8300-tcsr", "syscon"; 2071 reg = <0x0 0x1fc0000 0x0 0x30000>; 2072 }; 2073 2074 remoteproc_adsp: remoteproc@3000000 { 2075 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 2076 reg = <0x0 0x3000000 0x0 0x00100>; 2077 2078 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2079 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2080 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2081 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2082 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2083 interrupt-names = "wdog", 2084 "fatal", 2085 "ready", 2086 "handover", 2087 "stop-ack"; 2088 2089 clocks = <&rpmhcc RPMH_CXO_CLK>; 2090 clock-names = "xo"; 2091 2092 power-domains = <&rpmhpd RPMHPD_LCX>, 2093 <&rpmhpd RPMHPD_LMX>; 2094 power-domain-names = "lcx", 2095 "lmx"; 2096 2097 memory-region = <&adsp_mem>; 2098 2099 qcom,qmp = <&aoss_qmp>; 2100 2101 qcom,smem-states = <&smp2p_adsp_out 0>; 2102 qcom,smem-state-names = "stop"; 2103 2104 status = "disabled"; 2105 2106 remoteproc_adsp_glink: glink-edge { 2107 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2108 IPCC_MPROC_SIGNAL_GLINK_QMP 2109 IRQ_TYPE_EDGE_RISING>; 2110 mboxes = <&ipcc IPCC_CLIENT_LPASS 2111 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2112 2113 label = "lpass"; 2114 qcom,remote-pid = <2>; 2115 2116 fastrpc { 2117 compatible = "qcom,fastrpc"; 2118 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2119 label = "adsp"; 2120 memory-region = <&adsp_rpc_remote_heap_mem>; 2121 qcom,vmids = <QCOM_SCM_VMID_LPASS 2122 QCOM_SCM_VMID_ADSP_HEAP>; 2123 #address-cells = <1>; 2124 #size-cells = <0>; 2125 2126 compute-cb@3 { 2127 compatible = "qcom,fastrpc-compute-cb"; 2128 reg = <3>; 2129 iommus = <&apps_smmu 0x2003 0x0>; 2130 dma-coherent; 2131 }; 2132 2133 compute-cb@4 { 2134 compatible = "qcom,fastrpc-compute-cb"; 2135 reg = <4>; 2136 iommus = <&apps_smmu 0x2004 0x0>; 2137 dma-coherent; 2138 }; 2139 2140 compute-cb@5 { 2141 compatible = "qcom,fastrpc-compute-cb"; 2142 reg = <5>; 2143 iommus = <&apps_smmu 0x2005 0x0>; 2144 dma-coherent; 2145 }; 2146 }; 2147 }; 2148 }; 2149 2150 lpass_ag_noc: interconnect@3c40000 { 2151 compatible = "qcom,qcs8300-lpass-ag-noc"; 2152 reg = <0x0 0x03c40000 0x0 0x17200>; 2153 #interconnect-cells = <2>; 2154 qcom,bcm-voters = <&apps_bcm_voter>; 2155 }; 2156 2157 stm@4002000 { 2158 compatible = "arm,coresight-stm", "arm,primecell"; 2159 reg = <0x0 0x04002000 0x0 0x1000>, 2160 <0x0 0x16280000 0x0 0x180000>; 2161 reg-names = "stm-base", 2162 "stm-stimulus-base"; 2163 2164 clocks = <&aoss_qmp>; 2165 clock-names = "apb_pclk"; 2166 2167 out-ports { 2168 port { 2169 stm_out: endpoint { 2170 remote-endpoint = <&funnel0_in7>; 2171 }; 2172 }; 2173 }; 2174 }; 2175 2176 tpda@4004000 { 2177 compatible = "qcom,coresight-tpda", "arm,primecell"; 2178 reg = <0x0 0x04004000 0x0 0x1000>; 2179 2180 clocks = <&aoss_qmp>; 2181 clock-names = "apb_pclk"; 2182 2183 in-ports { 2184 #address-cells = <1>; 2185 #size-cells = <0>; 2186 2187 port@1 { 2188 reg = <1>; 2189 2190 qdss_tpda_in1: endpoint { 2191 remote-endpoint = <&qdss_tpdm1_out>; 2192 }; 2193 }; 2194 }; 2195 2196 out-ports { 2197 port { 2198 qdss_tpda_out: endpoint { 2199 remote-endpoint = <&funnel0_in6>; 2200 }; 2201 }; 2202 }; 2203 }; 2204 2205 tpdm@400f000 { 2206 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2207 reg = <0x0 0x0400f000 0x0 0x1000>; 2208 2209 clocks = <&aoss_qmp>; 2210 clock-names = "apb_pclk"; 2211 2212 qcom,cmb-element-bits = <32>; 2213 qcom,cmb-msrs-num = <32>; 2214 2215 out-ports { 2216 port { 2217 qdss_tpdm1_out: endpoint { 2218 remote-endpoint = <&qdss_tpda_in1>; 2219 }; 2220 }; 2221 }; 2222 }; 2223 2224 funnel@4041000 { 2225 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2226 reg = <0x0 0x04041000 0x0 0x1000>; 2227 2228 clocks = <&aoss_qmp>; 2229 clock-names = "apb_pclk"; 2230 2231 in-ports { 2232 #address-cells = <1>; 2233 #size-cells = <0>; 2234 2235 port@6 { 2236 reg = <6>; 2237 2238 funnel0_in6: endpoint { 2239 remote-endpoint = <&qdss_tpda_out>; 2240 }; 2241 }; 2242 2243 port@7 { 2244 reg = <7>; 2245 2246 funnel0_in7: endpoint { 2247 remote-endpoint = <&stm_out>; 2248 }; 2249 }; 2250 }; 2251 2252 out-ports { 2253 port { 2254 funnel0_out: endpoint { 2255 remote-endpoint = <&qdss_funnel_in0>; 2256 }; 2257 }; 2258 }; 2259 }; 2260 2261 funnel@4042000 { 2262 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2263 reg = <0x0 0x04042000 0x0 0x1000>; 2264 2265 clocks = <&aoss_qmp>; 2266 clock-names = "apb_pclk"; 2267 2268 in-ports { 2269 #address-cells = <1>; 2270 #size-cells = <0>; 2271 2272 port@4 { 2273 reg = <4>; 2274 2275 funnel1_in4: endpoint { 2276 remote-endpoint = <&apss_funnel1_out>; 2277 }; 2278 }; 2279 2280 port@5 { 2281 reg = <5>; 2282 2283 funnel1_in5: endpoint { 2284 remote-endpoint = <&dlct0_funnel_out>; 2285 }; 2286 }; 2287 2288 port@6 { 2289 reg = <6>; 2290 2291 funnel1_in6: endpoint { 2292 remote-endpoint = <&dlmm_funnel_out>; 2293 }; 2294 }; 2295 2296 port@7 { 2297 reg = <7>; 2298 2299 funnel1_in7: endpoint { 2300 remote-endpoint = <&dlst_ch_funnel_out>; 2301 }; 2302 }; 2303 }; 2304 2305 out-ports { 2306 port { 2307 funnel1_out: endpoint { 2308 remote-endpoint = <&qdss_funnel_in1>; 2309 }; 2310 }; 2311 }; 2312 }; 2313 2314 funnel@4045000 { 2315 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2316 reg = <0x0 0x04045000 0x0 0x1000>; 2317 2318 clocks = <&aoss_qmp>; 2319 clock-names = "apb_pclk"; 2320 2321 in-ports { 2322 #address-cells = <1>; 2323 #size-cells = <0>; 2324 2325 port@0 { 2326 reg = <0>; 2327 2328 qdss_funnel_in0: endpoint { 2329 remote-endpoint = <&funnel0_out>; 2330 }; 2331 }; 2332 2333 port@1 { 2334 reg = <1>; 2335 2336 qdss_funnel_in1: endpoint { 2337 remote-endpoint = <&funnel1_out>; 2338 }; 2339 }; 2340 }; 2341 2342 out-ports { 2343 port { 2344 qdss_funnel_out: endpoint { 2345 remote-endpoint = <&aoss_funnel_in7>; 2346 }; 2347 }; 2348 }; 2349 }; 2350 2351 tpdm@4841000 { 2352 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2353 reg = <0x0 0x04841000 0x0 0x1000>; 2354 2355 clocks = <&aoss_qmp>; 2356 clock-names = "apb_pclk"; 2357 2358 qcom,cmb-element-bits = <32>; 2359 qcom,cmb-msrs-num = <32>; 2360 2361 out-ports { 2362 port { 2363 prng_tpdm_out: endpoint { 2364 remote-endpoint = <&dlct0_tpda_in19>; 2365 }; 2366 }; 2367 }; 2368 }; 2369 2370 tpdm@4850000 { 2371 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2372 reg = <0x0 0x04850000 0x0 0x1000>; 2373 2374 clocks = <&aoss_qmp>; 2375 clock-names = "apb_pclk"; 2376 2377 qcom,cmb-element-bits = <64>; 2378 qcom,cmb-msrs-num = <32>; 2379 qcom,dsb-element-bits = <32>; 2380 qcom,dsb-msrs-num = <32>; 2381 2382 out-ports { 2383 port { 2384 pimem_tpdm_out: endpoint { 2385 remote-endpoint = <&dlct0_tpda_in25>; 2386 }; 2387 }; 2388 }; 2389 }; 2390 2391 tpdm@4860000 { 2392 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2393 reg = <0x0 0x04860000 0x0 0x1000>; 2394 2395 clocks = <&aoss_qmp>; 2396 clock-names = "apb_pclk"; 2397 2398 qcom,dsb-element-bits = <32>; 2399 qcom,dsb-msrs-num = <32>; 2400 2401 out-ports { 2402 port { 2403 dlst_ch_tpdm0_out: endpoint { 2404 remote-endpoint = <&dlst_ch_tpda_in8>; 2405 }; 2406 }; 2407 }; 2408 }; 2409 2410 tpda@4864000 { 2411 compatible = "qcom,coresight-tpda", "arm,primecell"; 2412 reg = <0x0 0x04864000 0x0 0x1000>; 2413 2414 clocks = <&aoss_qmp>; 2415 clock-names = "apb_pclk"; 2416 2417 in-ports { 2418 #address-cells = <1>; 2419 #size-cells = <0>; 2420 2421 port@8 { 2422 reg = <8>; 2423 2424 dlst_ch_tpda_in8: endpoint { 2425 remote-endpoint = <&dlst_ch_tpdm0_out>; 2426 }; 2427 }; 2428 }; 2429 2430 out-ports { 2431 port { 2432 dlst_ch_tpda_out: endpoint { 2433 remote-endpoint = <&dlst_ch_funnel_in0>; 2434 }; 2435 }; 2436 }; 2437 }; 2438 2439 funnel@4865000 { 2440 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2441 reg = <0x0 0x04865000 0x0 0x1000>; 2442 2443 clocks = <&aoss_qmp>; 2444 clock-names = "apb_pclk"; 2445 2446 in-ports { 2447 #address-cells = <1>; 2448 #size-cells = <0>; 2449 2450 port@0 { 2451 reg = <0>; 2452 2453 dlst_ch_funnel_in0: endpoint { 2454 remote-endpoint = <&dlst_ch_tpda_out>; 2455 }; 2456 }; 2457 2458 port@4 { 2459 reg = <4>; 2460 2461 dlst_ch_funnel_in4: endpoint { 2462 remote-endpoint = <&dlst_funnel_out>; 2463 }; 2464 }; 2465 2466 port@6 { 2467 reg = <6>; 2468 2469 dlst_ch_funnel_in6: endpoint { 2470 remote-endpoint = <&gdsp_funnel_out>; 2471 }; 2472 }; 2473 }; 2474 2475 out-ports { 2476 port { 2477 dlst_ch_funnel_out: endpoint { 2478 remote-endpoint = <&funnel1_in7>; 2479 }; 2480 }; 2481 }; 2482 }; 2483 2484 tpdm@4980000 { 2485 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2486 reg = <0x0 0x04980000 0x0 0x1000>; 2487 2488 clocks = <&aoss_qmp>; 2489 clock-names = "apb_pclk"; 2490 2491 qcom,dsb-element-bits = <32>; 2492 qcom,dsb-msrs-num = <32>; 2493 2494 out-ports { 2495 port { 2496 turing2_tpdm_out: endpoint { 2497 remote-endpoint = <&turing2_funnel_in0>; 2498 }; 2499 }; 2500 }; 2501 }; 2502 2503 funnel@4983000 { 2504 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2505 reg = <0x0 0x04983000 0x0 0x1000>; 2506 2507 clocks = <&aoss_qmp>; 2508 clock-names = "apb_pclk"; 2509 2510 in-ports { 2511 port { 2512 turing2_funnel_in0: endpoint { 2513 remote-endpoint = <&turing2_tpdm_out>; 2514 }; 2515 }; 2516 }; 2517 2518 out-ports { 2519 port { 2520 turing2_funnel_out0: endpoint { 2521 remote-endpoint = <&gdsp_tpda_in5>; 2522 }; 2523 }; 2524 }; 2525 }; 2526 2527 tpdm@4ac0000 { 2528 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2529 reg = <0x0 0x04ac0000 0x0 0x1000>; 2530 2531 clocks = <&aoss_qmp>; 2532 clock-names = "apb_pclk"; 2533 2534 qcom,dsb-element-bits = <32>; 2535 qcom,dsb-msrs-num = <32>; 2536 2537 out-ports { 2538 port { 2539 dlmm_tpdm0_out: endpoint { 2540 remote-endpoint = <&dlmm_tpda_in27>; 2541 }; 2542 }; 2543 }; 2544 }; 2545 2546 tpda@4ac4000 { 2547 compatible = "qcom,coresight-tpda", "arm,primecell"; 2548 reg = <0x0 0x04ac4000 0x0 0x1000>; 2549 2550 clocks = <&aoss_qmp>; 2551 clock-names = "apb_pclk"; 2552 2553 in-ports { 2554 #address-cells = <1>; 2555 #size-cells = <0>; 2556 2557 port@1b { 2558 reg = <27>; 2559 2560 dlmm_tpda_in27: endpoint { 2561 remote-endpoint = <&dlmm_tpdm0_out>; 2562 }; 2563 }; 2564 }; 2565 2566 out-ports { 2567 port { 2568 dlmm_tpda_out: endpoint { 2569 remote-endpoint = <&dlmm_funnel_in0>; 2570 }; 2571 }; 2572 }; 2573 }; 2574 2575 funnel@4ac5000 { 2576 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2577 reg = <0x0 0x04ac5000 0x0 0x1000>; 2578 2579 clocks = <&aoss_qmp>; 2580 clock-names = "apb_pclk"; 2581 2582 in-ports { 2583 port { 2584 dlmm_funnel_in0: endpoint { 2585 remote-endpoint = <&dlmm_tpda_out>; 2586 }; 2587 }; 2588 }; 2589 2590 out-ports { 2591 port { 2592 dlmm_funnel_out: endpoint { 2593 remote-endpoint = <&funnel1_in6>; 2594 }; 2595 }; 2596 }; 2597 }; 2598 2599 tpdm@4ad0000 { 2600 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2601 reg = <0x0 0x04ad0000 0x0 0x1000>; 2602 2603 clocks = <&aoss_qmp>; 2604 clock-names = "apb_pclk"; 2605 2606 qcom,dsb-element-bits = <32>; 2607 qcom,dsb-msrs-num = <32>; 2608 2609 out-ports { 2610 port { 2611 dlct0_tpdm0_out: endpoint { 2612 remote-endpoint = <&dlct0_tpda_in26>; 2613 }; 2614 }; 2615 }; 2616 }; 2617 2618 tpda@4ad3000 { 2619 compatible = "qcom,coresight-tpda", "arm,primecell"; 2620 reg = <0x0 0x04ad3000 0x0 0x1000>; 2621 2622 clocks = <&aoss_qmp>; 2623 clock-names = "apb_pclk"; 2624 2625 in-ports { 2626 #address-cells = <1>; 2627 #size-cells = <0>; 2628 2629 port@13 { 2630 reg = <19>; 2631 2632 dlct0_tpda_in19: endpoint { 2633 remote-endpoint = <&prng_tpdm_out>; 2634 }; 2635 }; 2636 2637 port@19 { 2638 reg = <25>; 2639 2640 dlct0_tpda_in25: endpoint { 2641 remote-endpoint = <&pimem_tpdm_out>; 2642 }; 2643 }; 2644 2645 port@1a { 2646 reg = <26>; 2647 2648 dlct0_tpda_in26: endpoint { 2649 remote-endpoint = <&dlct0_tpdm0_out>; 2650 }; 2651 }; 2652 }; 2653 2654 out-ports { 2655 port { 2656 dlct0_tpda_out: endpoint { 2657 remote-endpoint = <&dlct0_funnel_in0>; 2658 }; 2659 }; 2660 }; 2661 }; 2662 2663 funnel@4ad4000 { 2664 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2665 reg = <0x0 0x04ad4000 0x0 0x1000>; 2666 2667 clocks = <&aoss_qmp>; 2668 clock-names = "apb_pclk"; 2669 2670 in-ports { 2671 #address-cells = <1>; 2672 #size-cells = <0>; 2673 2674 port@0 { 2675 reg = <0>; 2676 2677 dlct0_funnel_in0: endpoint { 2678 remote-endpoint = <&dlct0_tpda_out>; 2679 }; 2680 }; 2681 2682 port@4 { 2683 reg = <4>; 2684 2685 dlct0_funnel_in4: endpoint { 2686 remote-endpoint = <&ddr_funnel5_out>; 2687 }; 2688 }; 2689 }; 2690 2691 out-ports { 2692 port { 2693 dlct0_funnel_out: endpoint { 2694 remote-endpoint = <&funnel1_in5>; 2695 }; 2696 }; 2697 }; 2698 }; 2699 2700 funnel@4b04000 { 2701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2702 reg = <0x0 0x04b04000 0x0 0x1000>; 2703 2704 clocks = <&aoss_qmp>; 2705 clock-names = "apb_pclk"; 2706 2707 in-ports { 2708 #address-cells = <1>; 2709 #size-cells = <0>; 2710 2711 port@6 { 2712 reg = <6>; 2713 2714 aoss_funnel_in6: endpoint { 2715 remote-endpoint = <&aoss_tpda_out>; 2716 }; 2717 }; 2718 2719 port@7 { 2720 reg = <7>; 2721 2722 aoss_funnel_in7: endpoint { 2723 remote-endpoint = <&qdss_funnel_out>; 2724 }; 2725 }; 2726 }; 2727 2728 out-ports { 2729 port { 2730 aoss_funnel_out: endpoint { 2731 remote-endpoint = <&etf0_in>; 2732 }; 2733 }; 2734 }; 2735 }; 2736 2737 tmc_etf: tmc@4b05000 { 2738 compatible = "arm,coresight-tmc", "arm,primecell"; 2739 reg = <0x0 0x04b05000 0x0 0x1000>; 2740 2741 clocks = <&aoss_qmp>; 2742 clock-names = "apb_pclk"; 2743 2744 in-ports { 2745 port { 2746 etf0_in: endpoint { 2747 remote-endpoint = <&aoss_funnel_out>; 2748 }; 2749 }; 2750 }; 2751 2752 out-ports { 2753 port { 2754 etf0_out: endpoint { 2755 remote-endpoint = <&swao_rep_in>; 2756 }; 2757 }; 2758 }; 2759 }; 2760 2761 replicator@4b06000 { 2762 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2763 reg = <0x0 0x04b06000 0x0 0x1000>; 2764 2765 clocks = <&aoss_qmp>; 2766 clock-names = "apb_pclk"; 2767 2768 in-ports { 2769 port { 2770 swao_rep_in: endpoint { 2771 remote-endpoint = <&etf0_out>; 2772 }; 2773 }; 2774 }; 2775 2776 out-ports { 2777 #address-cells = <1>; 2778 #size-cells = <0>; 2779 2780 port@1 { 2781 reg = <1>; 2782 2783 swao_rep_out1: endpoint { 2784 remote-endpoint = <&eud_in>; 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 tpda@4b08000 { 2791 compatible = "qcom,coresight-tpda", "arm,primecell"; 2792 reg = <0x0 0x04b08000 0x0 0x1000>; 2793 2794 clocks = <&aoss_qmp>; 2795 clock-names = "apb_pclk"; 2796 2797 in-ports { 2798 #address-cells = <1>; 2799 #size-cells = <0>; 2800 2801 port@0 { 2802 reg = <0>; 2803 2804 aoss_tpda_in0: endpoint { 2805 remote-endpoint = <&aoss_tpdm0_out>; 2806 }; 2807 }; 2808 2809 port@1 { 2810 reg = <1>; 2811 2812 aoss_tpda_in1: endpoint { 2813 remote-endpoint = <&aoss_tpdm1_out>; 2814 }; 2815 }; 2816 2817 port@2 { 2818 reg = <2>; 2819 2820 aoss_tpda_in2: endpoint { 2821 remote-endpoint = <&aoss_tpdm2_out>; 2822 }; 2823 }; 2824 2825 port@3 { 2826 reg = <3>; 2827 2828 aoss_tpda_in3: endpoint { 2829 remote-endpoint = <&aoss_tpdm3_out>; 2830 }; 2831 }; 2832 2833 port@4 { 2834 reg = <4>; 2835 2836 aoss_tpda_in4: endpoint { 2837 remote-endpoint = <&aoss_tpdm4_out>; 2838 }; 2839 }; 2840 }; 2841 2842 out-ports { 2843 port { 2844 aoss_tpda_out: endpoint { 2845 remote-endpoint = <&aoss_funnel_in6>; 2846 }; 2847 }; 2848 }; 2849 }; 2850 2851 tpdm@4b09000 { 2852 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2853 reg = <0x0 0x04b09000 0x0 0x1000>; 2854 2855 clocks = <&aoss_qmp>; 2856 clock-names = "apb_pclk"; 2857 2858 qcom,cmb-element-bits = <64>; 2859 qcom,cmb-msrs-num = <32>; 2860 2861 out-ports { 2862 port { 2863 aoss_tpdm0_out: endpoint { 2864 remote-endpoint = <&aoss_tpda_in0>; 2865 }; 2866 }; 2867 }; 2868 }; 2869 2870 tpdm@4b0a000 { 2871 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2872 reg = <0x0 0x04b0a000 0x0 0x1000>; 2873 2874 clocks = <&aoss_qmp>; 2875 clock-names = "apb_pclk"; 2876 2877 qcom,cmb-element-bits = <64>; 2878 qcom,cmb-msrs-num = <32>; 2879 2880 out-ports { 2881 port { 2882 aoss_tpdm1_out: endpoint { 2883 remote-endpoint = <&aoss_tpda_in1>; 2884 }; 2885 }; 2886 }; 2887 }; 2888 2889 tpdm@4b0b000 { 2890 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2891 reg = <0x0 0x04b0b000 0x0 0x1000>; 2892 2893 clocks = <&aoss_qmp>; 2894 clock-names = "apb_pclk"; 2895 2896 qcom,cmb-element-bits = <64>; 2897 qcom,cmb-msrs-num = <32>; 2898 2899 out-ports { 2900 port { 2901 aoss_tpdm2_out: endpoint { 2902 remote-endpoint = <&aoss_tpda_in2>; 2903 }; 2904 }; 2905 }; 2906 }; 2907 2908 tpdm@4b0c000 { 2909 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2910 reg = <0x0 0x04b0c000 0x0 0x1000>; 2911 2912 clocks = <&aoss_qmp>; 2913 clock-names = "apb_pclk"; 2914 2915 qcom,cmb-element-bits = <64>; 2916 qcom,cmb-msrs-num = <32>; 2917 2918 out-ports { 2919 port { 2920 aoss_tpdm3_out: endpoint { 2921 remote-endpoint = <&aoss_tpda_in3>; 2922 }; 2923 }; 2924 }; 2925 }; 2926 2927 tpdm@4b0d000 { 2928 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2929 reg = <0x0 0x04b0d000 0x0 0x1000>; 2930 2931 clocks = <&aoss_qmp>; 2932 clock-names = "apb_pclk"; 2933 2934 qcom,dsb-element-bits = <32>; 2935 qcom,dsb-msrs-num = <32>; 2936 2937 out-ports { 2938 port { 2939 aoss_tpdm4_out: endpoint { 2940 remote-endpoint = <&aoss_tpda_in4>; 2941 }; 2942 }; 2943 }; 2944 }; 2945 2946 cti@4b13000 { 2947 compatible = "arm,coresight-cti", "arm,primecell"; 2948 reg = <0x0 0x04b13000 0x0 0x1000>; 2949 2950 clocks = <&aoss_qmp>; 2951 clock-names = "apb_pclk"; 2952 }; 2953 2954 tpdm@4b80000 { 2955 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2956 reg = <0x0 0x04b80000 0x0 0x1000>; 2957 2958 clocks = <&aoss_qmp>; 2959 clock-names = "apb_pclk"; 2960 2961 qcom,dsb-element-bits = <32>; 2962 qcom,dsb-msrs-num = <32>; 2963 2964 out-ports { 2965 port { 2966 turing0_tpdm0_out: endpoint { 2967 remote-endpoint = <&turing0_tpda_in0>; 2968 }; 2969 }; 2970 }; 2971 }; 2972 2973 tpda@4b86000 { 2974 compatible = "qcom,coresight-tpda", "arm,primecell"; 2975 reg = <0x0 0x04b86000 0x0 0x1000>; 2976 2977 clocks = <&aoss_qmp>; 2978 clock-names = "apb_pclk"; 2979 2980 in-ports { 2981 port { 2982 turing0_tpda_in0: endpoint { 2983 remote-endpoint = <&turing0_tpdm0_out>; 2984 }; 2985 }; 2986 }; 2987 2988 out-ports { 2989 port { 2990 turing0_tpda_out: endpoint { 2991 remote-endpoint = <&turing0_funnel_in0>; 2992 }; 2993 }; 2994 }; 2995 }; 2996 2997 funnel@4b87000 { 2998 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2999 reg = <0x0 0x04b87000 0x0 0x1000>; 3000 3001 clocks = <&aoss_qmp>; 3002 clock-names = "apb_pclk"; 3003 3004 in-ports { 3005 port { 3006 turing0_funnel_in0: endpoint { 3007 remote-endpoint = <&turing0_tpda_out>; 3008 }; 3009 }; 3010 }; 3011 3012 out-ports { 3013 port { 3014 turing0_funnel_out: endpoint { 3015 remote-endpoint = <&gdsp_funnel_in4>; 3016 }; 3017 }; 3018 }; 3019 }; 3020 3021 cti@4b8b000 { 3022 compatible = "arm,coresight-cti", "arm,primecell"; 3023 reg = <0x0 0x04b8b000 0x0 0x1000>; 3024 3025 clocks = <&aoss_qmp>; 3026 clock-names = "apb_pclk"; 3027 }; 3028 3029 tpdm@4c40000 { 3030 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3031 reg = <0x0 0x04c40000 0x0 0x1000>; 3032 3033 clocks = <&aoss_qmp>; 3034 clock-names = "apb_pclk"; 3035 3036 qcom,dsb-element-bits = <32>; 3037 qcom,dsb-msrs-num = <32>; 3038 3039 out-ports { 3040 port { 3041 gdsp_tpdm0_out: endpoint { 3042 remote-endpoint = <&gdsp_tpda_in8>; 3043 }; 3044 }; 3045 }; 3046 }; 3047 3048 tpda@4c44000 { 3049 compatible = "qcom,coresight-tpda", "arm,primecell"; 3050 reg = <0x0 0x04c44000 0x0 0x1000>; 3051 3052 clocks = <&aoss_qmp>; 3053 clock-names = "apb_pclk"; 3054 3055 in-ports { 3056 #address-cells = <1>; 3057 #size-cells = <0>; 3058 3059 port@5 { 3060 reg = <5>; 3061 3062 gdsp_tpda_in5: endpoint { 3063 remote-endpoint = <&turing2_funnel_out0>; 3064 }; 3065 }; 3066 3067 port@8 { 3068 reg = <8>; 3069 3070 gdsp_tpda_in8: endpoint { 3071 remote-endpoint = <&gdsp_tpdm0_out>; 3072 }; 3073 }; 3074 }; 3075 3076 out-ports { 3077 port { 3078 gdsp_tpda_out: endpoint { 3079 remote-endpoint = <&gdsp_funnel_in0>; 3080 }; 3081 }; 3082 }; 3083 }; 3084 3085 funnel@4c45000 { 3086 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3087 reg = <0x0 0x04c45000 0x0 0x1000>; 3088 3089 clocks = <&aoss_qmp>; 3090 clock-names = "apb_pclk"; 3091 3092 in-ports { 3093 #address-cells = <1>; 3094 #size-cells = <0>; 3095 3096 port@0 { 3097 reg = <0>; 3098 3099 gdsp_funnel_in0: endpoint { 3100 remote-endpoint = <&gdsp_tpda_out>; 3101 }; 3102 }; 3103 3104 port@4 { 3105 reg = <4>; 3106 3107 gdsp_funnel_in4: endpoint { 3108 remote-endpoint = <&turing0_funnel_out>; 3109 }; 3110 }; 3111 }; 3112 3113 out-ports { 3114 port { 3115 gdsp_funnel_out: endpoint { 3116 remote-endpoint = <&dlst_ch_funnel_in6>; 3117 }; 3118 }; 3119 }; 3120 }; 3121 3122 tpdm@4c50000 { 3123 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3124 reg = <0x0 0x04c50000 0x0 0x1000>; 3125 3126 clocks = <&aoss_qmp>; 3127 clock-names = "apb_pclk"; 3128 3129 qcom,dsb-element-bits = <32>; 3130 qcom,dsb-msrs-num = <32>; 3131 3132 out-ports { 3133 port { 3134 dlst_tpdm0_out: endpoint { 3135 remote-endpoint = <&dlst_tpda_in8>; 3136 }; 3137 }; 3138 }; 3139 }; 3140 3141 tpda@4c54000 { 3142 compatible = "qcom,coresight-tpda", "arm,primecell"; 3143 reg = <0x0 0x04c54000 0x0 0x1000>; 3144 3145 clocks = <&aoss_qmp>; 3146 clock-names = "apb_pclk"; 3147 3148 in-ports { 3149 #address-cells = <1>; 3150 #size-cells = <0>; 3151 3152 port@8 { 3153 reg = <8>; 3154 3155 dlst_tpda_in8: endpoint { 3156 remote-endpoint = <&dlst_tpdm0_out>; 3157 }; 3158 }; 3159 }; 3160 3161 out-ports { 3162 port { 3163 dlst_tpda_out: endpoint { 3164 remote-endpoint = <&dlst_funnel_in0>; 3165 }; 3166 }; 3167 }; 3168 }; 3169 3170 funnel@4c55000 { 3171 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3172 reg = <0x0 0x04c55000 0x0 0x1000>; 3173 3174 clocks = <&aoss_qmp>; 3175 clock-names = "apb_pclk"; 3176 3177 in-ports { 3178 port { 3179 dlst_funnel_in0: endpoint { 3180 remote-endpoint = <&dlst_tpda_out>; 3181 }; 3182 }; 3183 }; 3184 3185 out-ports { 3186 port { 3187 dlst_funnel_out: endpoint { 3188 remote-endpoint = <&dlst_ch_funnel_in4>; 3189 }; 3190 }; 3191 }; 3192 }; 3193 3194 tpdm@4e00000 { 3195 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3196 reg = <0x0 0x04e00000 0x0 0x1000>; 3197 3198 clocks = <&aoss_qmp>; 3199 clock-names = "apb_pclk"; 3200 3201 qcom,dsb-element-bits = <32>; 3202 qcom,dsb-msrs-num = <32>; 3203 qcom,cmb-element-bits = <32>; 3204 qcom,cmb-msrs-num = <32>; 3205 3206 out-ports { 3207 port { 3208 ddr_tpdm3_out: endpoint { 3209 remote-endpoint = <&ddr_tpda_in4>; 3210 }; 3211 }; 3212 }; 3213 }; 3214 3215 tpda@4e03000 { 3216 compatible = "qcom,coresight-tpda", "arm,primecell"; 3217 reg = <0x0 0x04e03000 0x0 0x1000>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 3222 in-ports { 3223 #address-cells = <1>; 3224 #size-cells = <0>; 3225 3226 port@0 { 3227 reg = <0>; 3228 3229 ddr_tpda_in0: endpoint { 3230 remote-endpoint = <&ddr_funnel0_out0>; 3231 }; 3232 }; 3233 3234 port@1 { 3235 reg = <1>; 3236 3237 ddr_tpda_in1: endpoint { 3238 remote-endpoint = <&ddr_funnel1_out0>; 3239 }; 3240 }; 3241 3242 port@4 { 3243 reg = <4>; 3244 3245 ddr_tpda_in4: endpoint { 3246 remote-endpoint = <&ddr_tpdm3_out>; 3247 }; 3248 }; 3249 }; 3250 3251 out-ports { 3252 port { 3253 ddr_tpda_out: endpoint { 3254 remote-endpoint = <&ddr_funnel5_in0>; 3255 }; 3256 }; 3257 }; 3258 }; 3259 3260 funnel@4e04000 { 3261 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3262 reg = <0x0 0x04e04000 0x0 0x1000>; 3263 3264 clocks = <&aoss_qmp>; 3265 clock-names = "apb_pclk"; 3266 3267 in-ports { 3268 port { 3269 ddr_funnel5_in0: endpoint { 3270 remote-endpoint = <&ddr_tpda_out>; 3271 }; 3272 }; 3273 }; 3274 3275 out-ports { 3276 port { 3277 ddr_funnel5_out: endpoint { 3278 remote-endpoint = <&dlct0_funnel_in4>; 3279 }; 3280 }; 3281 }; 3282 }; 3283 3284 tpdm@4e10000 { 3285 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3286 reg = <0x0 0x04e10000 0x0 0x1000>; 3287 3288 clocks = <&aoss_qmp>; 3289 clock-names = "apb_pclk"; 3290 3291 qcom,dsb-element-bits = <32>; 3292 qcom,dsb-msrs-num = <32>; 3293 3294 out-ports { 3295 port { 3296 ddr_tpdm0_out: endpoint { 3297 remote-endpoint = <&ddr_funnel0_in0>; 3298 }; 3299 }; 3300 }; 3301 }; 3302 3303 funnel@4e12000 { 3304 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3305 reg = <0x0 0x04e12000 0x0 0x1000>; 3306 3307 clocks = <&aoss_qmp>; 3308 clock-names = "apb_pclk"; 3309 3310 in-ports { 3311 port { 3312 ddr_funnel0_in0: endpoint { 3313 remote-endpoint = <&ddr_tpdm0_out>; 3314 }; 3315 }; 3316 }; 3317 3318 out-ports { 3319 port { 3320 ddr_funnel0_out0: endpoint { 3321 remote-endpoint = <&ddr_tpda_in0>; 3322 }; 3323 }; 3324 }; 3325 }; 3326 3327 tpdm@4e20000 { 3328 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3329 reg = <0x0 0x04e20000 0x0 0x1000>; 3330 3331 clocks = <&aoss_qmp>; 3332 clock-names = "apb_pclk"; 3333 3334 qcom,dsb-element-bits = <32>; 3335 qcom,dsb-msrs-num = <32>; 3336 3337 out-ports { 3338 port { 3339 ddr_tpdm1_out: endpoint { 3340 remote-endpoint = <&ddr_funnel1_in0>; 3341 }; 3342 }; 3343 }; 3344 }; 3345 3346 funnel@4e22000 { 3347 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3348 reg = <0x0 0x04e22000 0x0 0x1000>; 3349 3350 clocks = <&aoss_qmp>; 3351 clock-names = "apb_pclk"; 3352 3353 in-ports { 3354 port { 3355 ddr_funnel1_in0: endpoint { 3356 remote-endpoint = <&ddr_tpdm1_out>; 3357 }; 3358 }; 3359 }; 3360 3361 out-ports { 3362 port { 3363 ddr_funnel1_out0: endpoint { 3364 remote-endpoint = <&ddr_tpda_in1>; 3365 }; 3366 }; 3367 }; 3368 }; 3369 3370 etm@6040000 { 3371 compatible = "arm,primecell"; 3372 reg = <0x0 0x06040000 0x0 0x1000>; 3373 cpu = <&cpu0>; 3374 3375 clocks = <&aoss_qmp>; 3376 clock-names = "apb_pclk"; 3377 3378 arm,coresight-loses-context-with-cpu; 3379 qcom,skip-power-up; 3380 3381 out-ports { 3382 port { 3383 etm0_out: endpoint { 3384 remote-endpoint = <&apss_funnel0_in0>; 3385 }; 3386 }; 3387 }; 3388 }; 3389 3390 etm@6140000 { 3391 compatible = "arm,primecell"; 3392 reg = <0x0 0x06140000 0x0 0x1000>; 3393 cpu = <&cpu1>; 3394 3395 clocks = <&aoss_qmp>; 3396 clock-names = "apb_pclk"; 3397 3398 arm,coresight-loses-context-with-cpu; 3399 qcom,skip-power-up; 3400 3401 out-ports { 3402 port { 3403 etm1_out: endpoint { 3404 remote-endpoint = <&apss_funnel0_in1>; 3405 }; 3406 }; 3407 }; 3408 }; 3409 3410 etm@6240000 { 3411 compatible = "arm,primecell"; 3412 reg = <0x0 0x06240000 0x0 0x1000>; 3413 cpu = <&cpu2>; 3414 3415 clocks = <&aoss_qmp>; 3416 clock-names = "apb_pclk"; 3417 3418 arm,coresight-loses-context-with-cpu; 3419 qcom,skip-power-up; 3420 3421 out-ports { 3422 port { 3423 etm2_out: endpoint { 3424 remote-endpoint = <&apss_funnel0_in2>; 3425 }; 3426 }; 3427 }; 3428 }; 3429 3430 etm@6340000 { 3431 compatible = "arm,primecell"; 3432 reg = <0x0 0x06340000 0x0 0x1000>; 3433 cpu = <&cpu3>; 3434 3435 clocks = <&aoss_qmp>; 3436 clock-names = "apb_pclk"; 3437 3438 arm,coresight-loses-context-with-cpu; 3439 qcom,skip-power-up; 3440 3441 out-ports { 3442 port { 3443 etm3_out: endpoint { 3444 remote-endpoint = <&apss_funnel0_in3>; 3445 }; 3446 }; 3447 }; 3448 }; 3449 3450 etm@6440000 { 3451 compatible = "arm,primecell"; 3452 reg = <0x0 0x06440000 0x0 0x1000>; 3453 cpu = <&cpu4>; 3454 3455 clocks = <&aoss_qmp>; 3456 clock-names = "apb_pclk"; 3457 3458 arm,coresight-loses-context-with-cpu; 3459 qcom,skip-power-up; 3460 3461 out-ports { 3462 port { 3463 etm4_out: endpoint { 3464 remote-endpoint = <&apss_funnel0_in4>; 3465 }; 3466 }; 3467 }; 3468 }; 3469 3470 etm@6540000 { 3471 compatible = "arm,primecell"; 3472 reg = <0x0 0x06540000 0x0 0x1000>; 3473 cpu = <&cpu5>; 3474 3475 clocks = <&aoss_qmp>; 3476 clock-names = "apb_pclk"; 3477 3478 arm,coresight-loses-context-with-cpu; 3479 qcom,skip-power-up; 3480 3481 out-ports { 3482 port { 3483 etm5_out: endpoint { 3484 remote-endpoint = <&apss_funnel0_in5>; 3485 }; 3486 }; 3487 }; 3488 }; 3489 3490 etm@6640000 { 3491 compatible = "arm,primecell"; 3492 reg = <0x0 0x06640000 0x0 0x1000>; 3493 cpu = <&cpu6>; 3494 3495 clocks = <&aoss_qmp>; 3496 clock-names = "apb_pclk"; 3497 3498 arm,coresight-loses-context-with-cpu; 3499 qcom,skip-power-up; 3500 3501 out-ports { 3502 port { 3503 etm6_out: endpoint { 3504 remote-endpoint = <&apss_funnel0_in6>; 3505 }; 3506 }; 3507 }; 3508 }; 3509 3510 etm@6740000 { 3511 compatible = "arm,primecell"; 3512 reg = <0x0 0x06740000 0x0 0x1000>; 3513 cpu = <&cpu7>; 3514 3515 clocks = <&aoss_qmp>; 3516 clock-names = "apb_pclk"; 3517 3518 arm,coresight-loses-context-with-cpu; 3519 qcom,skip-power-up; 3520 3521 out-ports { 3522 port { 3523 etm7_out: endpoint { 3524 remote-endpoint = <&apss_funnel0_in7>; 3525 }; 3526 }; 3527 }; 3528 }; 3529 3530 funnel@6800000 { 3531 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3532 reg = <0x0 0x06800000 0x0 0x1000>; 3533 3534 clocks = <&aoss_qmp>; 3535 clock-names = "apb_pclk"; 3536 3537 in-ports { 3538 #address-cells = <1>; 3539 #size-cells = <0>; 3540 3541 port@0 { 3542 reg = <0>; 3543 3544 apss_funnel0_in0: endpoint { 3545 remote-endpoint = <&etm0_out>; 3546 }; 3547 }; 3548 3549 port@1 { 3550 reg = <1>; 3551 3552 apss_funnel0_in1: endpoint { 3553 remote-endpoint = <&etm1_out>; 3554 }; 3555 }; 3556 3557 port@2 { 3558 reg = <2>; 3559 3560 apss_funnel0_in2: endpoint { 3561 remote-endpoint = <&etm2_out>; 3562 }; 3563 }; 3564 3565 port@3 { 3566 reg = <3>; 3567 3568 apss_funnel0_in3: endpoint { 3569 remote-endpoint = <&etm3_out>; 3570 }; 3571 }; 3572 3573 port@4 { 3574 reg = <4>; 3575 3576 apss_funnel0_in4: endpoint { 3577 remote-endpoint = <&etm4_out>; 3578 }; 3579 }; 3580 3581 port@5 { 3582 reg = <5>; 3583 3584 apss_funnel0_in5: endpoint { 3585 remote-endpoint = <&etm5_out>; 3586 }; 3587 }; 3588 3589 port@6 { 3590 reg = <6>; 3591 3592 apss_funnel0_in6: endpoint { 3593 remote-endpoint = <&etm6_out>; 3594 }; 3595 }; 3596 3597 port@7 { 3598 reg = <7>; 3599 3600 apss_funnel0_in7: endpoint { 3601 remote-endpoint = <&etm7_out>; 3602 }; 3603 }; 3604 }; 3605 3606 out-ports { 3607 port { 3608 apss_funnel0_out: endpoint { 3609 remote-endpoint = <&apss_funnel1_in0>; 3610 }; 3611 }; 3612 }; 3613 }; 3614 3615 funnel@6810000 { 3616 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3617 reg = <0x0 0x06810000 0x0 0x1000>; 3618 3619 clocks = <&aoss_qmp>; 3620 clock-names = "apb_pclk"; 3621 3622 in-ports { 3623 #address-cells = <1>; 3624 #size-cells = <0>; 3625 3626 port@0 { 3627 reg = <0>; 3628 3629 apss_funnel1_in0: endpoint { 3630 remote-endpoint = <&apss_funnel0_out>; 3631 }; 3632 }; 3633 3634 port@3 { 3635 reg = <3>; 3636 3637 apss_funnel1_in3: endpoint { 3638 remote-endpoint = <&apss_tpda_out>; 3639 }; 3640 }; 3641 }; 3642 3643 out-ports { 3644 port { 3645 apss_funnel1_out: endpoint { 3646 remote-endpoint = <&funnel1_in4>; 3647 }; 3648 }; 3649 }; 3650 }; 3651 3652 cti@682b000 { 3653 compatible = "arm,coresight-cti", "arm,primecell"; 3654 reg = <0x0 0x0682b000 0x0 0x1000>; 3655 3656 clocks = <&aoss_qmp>; 3657 clock-names = "apb_pclk"; 3658 }; 3659 3660 tpdm@6860000 { 3661 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3662 reg = <0x0 0x06860000 0x0 0x1000>; 3663 3664 clocks = <&aoss_qmp>; 3665 clock-names = "apb_pclk"; 3666 3667 qcom,cmb-element-bits = <64>; 3668 qcom,cmb-msrs-num = <32>; 3669 3670 out-ports { 3671 port { 3672 apss_tpdm3_out: endpoint { 3673 remote-endpoint = <&apss_tpda_in3>; 3674 }; 3675 }; 3676 }; 3677 }; 3678 3679 tpdm@6861000 { 3680 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3681 reg = <0x0 0x06861000 0x0 0x1000>; 3682 3683 clocks = <&aoss_qmp>; 3684 clock-names = "apb_pclk"; 3685 3686 qcom,dsb-element-bits = <32>; 3687 qcom,dsb-msrs-num = <32>; 3688 3689 out-ports { 3690 port { 3691 apss_tpdm4_out: endpoint { 3692 remote-endpoint = <&apss_tpda_in4>; 3693 }; 3694 }; 3695 }; 3696 }; 3697 3698 tpda@6863000 { 3699 compatible = "qcom,coresight-tpda", "arm,primecell"; 3700 reg = <0x0 0x06863000 0x0 0x1000>; 3701 3702 clocks = <&aoss_qmp>; 3703 clock-names = "apb_pclk"; 3704 3705 in-ports { 3706 #address-cells = <1>; 3707 #size-cells = <0>; 3708 3709 port@0 { 3710 reg = <0>; 3711 3712 apss_tpda_in0: endpoint { 3713 remote-endpoint = <&apss_tpdm0_out>; 3714 }; 3715 }; 3716 3717 port@1 { 3718 reg = <1>; 3719 3720 apss_tpda_in1: endpoint { 3721 remote-endpoint = <&apss_tpdm1_out>; 3722 }; 3723 }; 3724 3725 port@2 { 3726 reg = <2>; 3727 3728 apss_tpda_in2: endpoint { 3729 remote-endpoint = <&apss_tpdm2_out>; 3730 }; 3731 }; 3732 3733 port@3 { 3734 reg = <3>; 3735 3736 apss_tpda_in3: endpoint { 3737 remote-endpoint = <&apss_tpdm3_out>; 3738 }; 3739 }; 3740 3741 port@4 { 3742 reg = <4>; 3743 3744 apss_tpda_in4: endpoint { 3745 remote-endpoint = <&apss_tpdm4_out>; 3746 }; 3747 }; 3748 }; 3749 3750 out-ports { 3751 port { 3752 apss_tpda_out: endpoint { 3753 remote-endpoint = <&apss_funnel1_in3>; 3754 }; 3755 }; 3756 }; 3757 }; 3758 3759 tpdm@68a0000 { 3760 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3761 reg = <0x0 0x068a0000 0x0 0x1000>; 3762 3763 clocks = <&aoss_qmp>; 3764 clock-names = "apb_pclk"; 3765 3766 qcom,cmb-element-bits = <32>; 3767 qcom,cmb-msrs-num = <32>; 3768 3769 out-ports { 3770 port { 3771 apss_tpdm1_out: endpoint { 3772 remote-endpoint = <&apss_tpda_in1>; 3773 }; 3774 }; 3775 }; 3776 }; 3777 3778 tpdm@68b0000 { 3779 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3780 reg = <0x0 0x068b0000 0x0 0x1000>; 3781 3782 clocks = <&aoss_qmp>; 3783 clock-names = "apb_pclk"; 3784 3785 qcom,cmb-element-bits = <32>; 3786 qcom,cmb-msrs-num = <32>; 3787 3788 out-ports { 3789 port { 3790 apss_tpdm0_out: endpoint { 3791 remote-endpoint = <&apss_tpda_in0>; 3792 }; 3793 }; 3794 }; 3795 }; 3796 3797 tpdm@68c0000 { 3798 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3799 reg = <0x0 0x068c0000 0x0 0x1000>; 3800 3801 clocks = <&aoss_qmp>; 3802 clock-names = "apb_pclk"; 3803 3804 qcom,dsb-element-bits = <32>; 3805 qcom,dsb-msrs-num = <32>; 3806 3807 out-ports { 3808 port { 3809 apss_tpdm2_out: endpoint { 3810 remote-endpoint = <&apss_tpda_in2>; 3811 }; 3812 }; 3813 }; 3814 }; 3815 3816 cti@68e0000 { 3817 compatible = "arm,coresight-cti", "arm,primecell"; 3818 reg = <0x0 0x068e0000 0x0 0x1000>; 3819 3820 clocks = <&aoss_qmp>; 3821 clock-names = "apb_pclk"; 3822 }; 3823 3824 cti@68f0000 { 3825 compatible = "arm,coresight-cti", "arm,primecell"; 3826 reg = <0x0 0x068f0000 0x0 0x1000>; 3827 3828 clocks = <&aoss_qmp>; 3829 clock-names = "apb_pclk"; 3830 }; 3831 3832 cti@6900000 { 3833 compatible = "arm,coresight-cti", "arm,primecell"; 3834 reg = <0x0 0x06900000 0x0 0x1000>; 3835 3836 clocks = <&aoss_qmp>; 3837 clock-names = "apb_pclk"; 3838 }; 3839 3840 usb_1_hsphy: phy@8904000 { 3841 compatible = "qcom,qcs8300-usb-hs-phy", 3842 "qcom,usb-snps-hs-7nm-phy"; 3843 reg = <0x0 0x08904000 0x0 0x400>; 3844 3845 clocks = <&rpmhcc RPMH_CXO_CLK>; 3846 clock-names = "ref"; 3847 3848 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 3849 3850 #phy-cells = <0>; 3851 3852 status = "disabled"; 3853 }; 3854 3855 usb_2_hsphy: phy@8906000 { 3856 compatible = "qcom,qcs8300-usb-hs-phy", 3857 "qcom,usb-snps-hs-7nm-phy"; 3858 reg = <0x0 0x08906000 0x0 0x400>; 3859 3860 clocks = <&rpmhcc RPMH_CXO_CLK>; 3861 clock-names = "ref"; 3862 3863 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 3864 3865 #phy-cells = <0>; 3866 3867 status = "disabled"; 3868 }; 3869 3870 usb_qmpphy: phy@8907000 { 3871 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 3872 reg = <0x0 0x08907000 0x0 0x2000>; 3873 3874 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3875 <&gcc GCC_USB_CLKREF_EN>, 3876 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3877 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3878 clock-names = "aux", 3879 "ref", 3880 "com_aux", 3881 "pipe"; 3882 3883 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3884 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 3885 reset-names = "phy", "phy_phy"; 3886 3887 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3888 3889 #clock-cells = <0>; 3890 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 3891 3892 #phy-cells = <0>; 3893 3894 status = "disabled"; 3895 }; 3896 3897 serdes0: phy@8909000 { 3898 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 3899 reg = <0x0 0x08909000 0x0 0x00000e10>; 3900 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3901 clock-names = "sgmi_ref"; 3902 #phy-cells = <0>; 3903 status = "disabled"; 3904 }; 3905 3906 gpucc: clock-controller@3d90000 { 3907 compatible = "qcom,qcs8300-gpucc"; 3908 reg = <0x0 0x03d90000 0x0 0xa000>; 3909 clocks = <&rpmhcc RPMH_CXO_CLK>, 3910 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3911 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3912 clock-names = "bi_tcxo", 3913 "gcc_gpu_gpll0_clk_src", 3914 "gcc_gpu_gpll0_div_clk_src"; 3915 #clock-cells = <1>; 3916 #reset-cells = <1>; 3917 #power-domain-cells = <1>; 3918 }; 3919 3920 adreno_smmu: iommu@3da0000 { 3921 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", 3922 "qcom,smmu-500", "arm,mmu-500"; 3923 reg = <0x0 0x3da0000 0x0 0x20000>; 3924 #iommu-cells = <2>; 3925 #global-interrupts = <2>; 3926 3927 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3937 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3938 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3939 3940 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3941 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3942 <&gpucc GPU_CC_AHB_CLK>, 3943 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3944 <&gpucc GPU_CC_CX_GMU_CLK>, 3945 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3946 <&gpucc GPU_CC_HUB_AON_CLK>; 3947 3948 clock-names = "gcc_gpu_memnoc_gfx_clk", 3949 "gcc_gpu_snoc_dvm_gfx_clk", 3950 "gpu_cc_ahb_clk", 3951 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3952 "gpu_cc_cx_gmu_clk", 3953 "gpu_cc_hub_cx_int_clk", 3954 "gpu_cc_hub_aon_clk"; 3955 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3956 dma-coherent; 3957 }; 3958 3959 pmu@9091000 { 3960 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3961 reg = <0x0 0x9091000 0x0 0x1000>; 3962 3963 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 3964 3965 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3966 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3967 3968 operating-points-v2 = <&llcc_bwmon_opp_table>; 3969 3970 llcc_bwmon_opp_table: opp-table { 3971 compatible = "operating-points-v2"; 3972 3973 opp-0 { 3974 opp-peak-kBps = <762000>; 3975 }; 3976 3977 opp-1 { 3978 opp-peak-kBps = <1720000>; 3979 }; 3980 3981 opp-2 { 3982 opp-peak-kBps = <2086000>; 3983 }; 3984 3985 opp-3 { 3986 opp-peak-kBps = <2601000>; 3987 }; 3988 3989 opp-4 { 3990 opp-peak-kBps = <2929000>; 3991 }; 3992 3993 opp-5 { 3994 opp-peak-kBps = <5931000>; 3995 }; 3996 3997 opp-6 { 3998 opp-peak-kBps = <6515000>; 3999 }; 4000 4001 opp-7 { 4002 opp-peak-kBps = <7984000>; 4003 }; 4004 4005 opp-8 { 4006 opp-peak-kBps = <10437000>; 4007 }; 4008 4009 opp-9 { 4010 opp-peak-kBps = <12195000>; 4011 }; 4012 }; 4013 }; 4014 4015 pmu@90b5400 { 4016 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 4017 reg = <0x0 0x90b5400 0x0 0x600>; 4018 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4019 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4020 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4021 4022 operating-points-v2 = <&cpu_bwmon_opp_table>; 4023 4024 cpu_bwmon_opp_table: opp-table { 4025 compatible = "operating-points-v2"; 4026 4027 opp-0 { 4028 opp-peak-kBps = <9155000>; 4029 }; 4030 4031 opp-1 { 4032 opp-peak-kBps = <12298000>; 4033 }; 4034 4035 opp-2 { 4036 opp-peak-kBps = <14236000>; 4037 }; 4038 4039 opp-3 { 4040 opp-peak-kBps = <16265000>; 4041 }; 4042 }; 4043 }; 4044 4045 pmu@90b6400 { 4046 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 4047 reg = <0x0 0x90b6400 0x0 0x600>; 4048 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4049 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4050 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4051 4052 operating-points-v2 = <&cpu_bwmon_opp_table>; 4053 }; 4054 4055 dc_noc: interconnect@90e0000 { 4056 compatible = "qcom,qcs8300-dc-noc"; 4057 reg = <0x0 0x090e0000 0x0 0x5080>; 4058 #interconnect-cells = <2>; 4059 qcom,bcm-voters = <&apps_bcm_voter>; 4060 }; 4061 4062 gem_noc: interconnect@9100000 { 4063 compatible = "qcom,qcs8300-gem-noc"; 4064 reg = <0x0 0x9100000 0x0 0xf7080>; 4065 #interconnect-cells = <2>; 4066 qcom,bcm-voters = <&apps_bcm_voter>; 4067 }; 4068 4069 llcc: system-cache-controller@9200000 { 4070 compatible = "qcom,qcs8300-llcc"; 4071 reg = <0x0 0x09200000 0x0 0x80000>, 4072 <0x0 0x09300000 0x0 0x80000>, 4073 <0x0 0x09400000 0x0 0x80000>, 4074 <0x0 0x09500000 0x0 0x80000>, 4075 <0x0 0x09a00000 0x0 0x80000>; 4076 reg-names = "llcc0_base", 4077 "llcc1_base", 4078 "llcc2_base", 4079 "llcc3_base", 4080 "llcc_broadcast_base"; 4081 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4082 }; 4083 4084 usb_1: usb@a6f8800 { 4085 compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; 4086 reg = <0x0 0x0a6f8800 0x0 0x400>; 4087 4088 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4089 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4090 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4091 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4092 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4093 clock-names = "cfg_noc", 4094 "core", 4095 "iface", 4096 "sleep", 4097 "mock_utmi"; 4098 4099 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4100 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4101 assigned-clock-rates = <19200000>, <200000000>; 4102 4103 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 4104 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4105 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4106 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4107 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 4108 interrupt-names = "pwr_event", 4109 "hs_phy_irq", 4110 "dp_hs_phy_irq", 4111 "dm_hs_phy_irq", 4112 "ss_phy_irq"; 4113 4114 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4115 required-opps = <&rpmhpd_opp_nom>; 4116 4117 resets = <&gcc GCC_USB30_PRIM_BCR>; 4118 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 4119 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4120 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4121 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 4122 interconnect-names = "usb-ddr", "apps-usb"; 4123 4124 wakeup-source; 4125 4126 #address-cells = <2>; 4127 #size-cells = <2>; 4128 ranges; 4129 4130 status = "disabled"; 4131 4132 usb_1_dwc3: usb@a600000 { 4133 compatible = "snps,dwc3"; 4134 reg = <0x0 0x0a600000 0x0 0xe000>; 4135 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 4136 iommus = <&apps_smmu 0x80 0x0>; 4137 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 4138 phy-names = "usb2-phy", "usb3-phy"; 4139 snps,dis_enblslpm_quirk; 4140 snps,dis-u1-entry-quirk; 4141 snps,dis-u2-entry-quirk; 4142 snps,dis_u2_susphy_quirk; 4143 snps,dis_u3_susphy_quirk; 4144 }; 4145 }; 4146 4147 usb_2: usb@a4f8800 { 4148 compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; 4149 reg = <0x0 0x0a4f8800 0x0 0x400>; 4150 4151 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4152 <&gcc GCC_USB20_MASTER_CLK>, 4153 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4154 <&gcc GCC_USB20_SLEEP_CLK>, 4155 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4156 clock-names = "cfg_noc", 4157 "core", 4158 "iface", 4159 "sleep", 4160 "mock_utmi"; 4161 4162 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4163 <&gcc GCC_USB20_MASTER_CLK>; 4164 assigned-clock-rates = <19200000>, <120000000>; 4165 4166 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4167 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4168 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4169 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4170 interrupt-names = "pwr_event", 4171 "hs_phy_irq", 4172 "dp_hs_phy_irq", 4173 "dm_hs_phy_irq"; 4174 4175 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4176 required-opps = <&rpmhpd_opp_nom>; 4177 4178 resets = <&gcc GCC_USB20_PRIM_BCR>; 4179 4180 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4181 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4182 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4183 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 4184 interconnect-names = "usb-ddr", "apps-usb"; 4185 4186 qcom,select-utmi-as-pipe-clk; 4187 wakeup-source; 4188 4189 #address-cells = <2>; 4190 #size-cells = <2>; 4191 ranges; 4192 4193 status = "disabled"; 4194 4195 usb_2_dwc3: usb@a400000 { 4196 compatible = "snps,dwc3"; 4197 reg = <0x0 0x0a400000 0x0 0xe000>; 4198 4199 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 4200 iommus = <&apps_smmu 0x20 0x0>; 4201 4202 phys = <&usb_2_hsphy>; 4203 phy-names = "usb2-phy"; 4204 maximum-speed = "high-speed"; 4205 4206 snps,dis-u1-entry-quirk; 4207 snps,dis-u2-entry-quirk; 4208 snps,dis_u2_susphy_quirk; 4209 snps,dis_u3_susphy_quirk; 4210 snps,dis_enblslpm_quirk; 4211 }; 4212 }; 4213 4214 iris: video-codec@aa00000 { 4215 compatible = "qcom,qcs8300-iris"; 4216 4217 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4218 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4219 4220 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4221 <&videocc VIDEO_CC_MVS0_GDSC>, 4222 <&rpmhpd RPMHPD_MX>, 4223 <&rpmhpd RPMHPD_MMCX>; 4224 power-domain-names = "venus", 4225 "vcodec0", 4226 "mxc", 4227 "mmcx"; 4228 4229 operating-points-v2 = <&iris_opp_table>; 4230 4231 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4232 <&videocc VIDEO_CC_MVS0C_CLK>, 4233 <&videocc VIDEO_CC_MVS0_CLK>; 4234 clock-names = "iface", 4235 "core", 4236 "vcodec0_core"; 4237 4238 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4239 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4240 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4241 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4242 interconnect-names = "cpu-cfg", 4243 "video-mem"; 4244 4245 memory-region = <&video_mem>; 4246 4247 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4248 reset-names = "bus"; 4249 4250 iommus = <&apps_smmu 0x0880 0x0400>, 4251 <&apps_smmu 0x0887 0x0400>; 4252 dma-coherent; 4253 4254 status = "disabled"; 4255 4256 iris_opp_table: opp-table { 4257 compatible = "operating-points-v2"; 4258 4259 opp-366000000 { 4260 opp-hz = /bits/ 64 <366000000>; 4261 required-opps = <&rpmhpd_opp_svs_l1>, 4262 <&rpmhpd_opp_svs_l1>; 4263 }; 4264 4265 opp-444000000 { 4266 opp-hz = /bits/ 64 <444000000>; 4267 required-opps = <&rpmhpd_opp_nom>, 4268 <&rpmhpd_opp_nom>; 4269 }; 4270 4271 opp-533000000 { 4272 opp-hz = /bits/ 64 <533000000>; 4273 required-opps = <&rpmhpd_opp_turbo>, 4274 <&rpmhpd_opp_turbo>; 4275 }; 4276 4277 opp-560000000 { 4278 opp-hz = /bits/ 64 <560000000>; 4279 required-opps = <&rpmhpd_opp_turbo_l1>, 4280 <&rpmhpd_opp_turbo_l1>; 4281 }; 4282 }; 4283 }; 4284 4285 videocc: clock-controller@abf0000 { 4286 compatible = "qcom,qcs8300-videocc"; 4287 reg = <0x0 0x0abf0000 0x0 0x10000>; 4288 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4289 <&rpmhcc RPMH_CXO_CLK>, 4290 <&rpmhcc RPMH_CXO_CLK_A>, 4291 <&sleep_clk>; 4292 power-domains = <&rpmhpd RPMHPD_MMCX>; 4293 #clock-cells = <1>; 4294 #reset-cells = <1>; 4295 #power-domain-cells = <1>; 4296 }; 4297 4298 camcc: clock-controller@ade0000 { 4299 compatible = "qcom,qcs8300-camcc"; 4300 reg = <0x0 0x0ade0000 0x0 0x20000>; 4301 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4302 <&rpmhcc RPMH_CXO_CLK>, 4303 <&rpmhcc RPMH_CXO_CLK_A>, 4304 <&sleep_clk>; 4305 power-domains = <&rpmhpd RPMHPD_MMCX>; 4306 #clock-cells = <1>; 4307 #reset-cells = <1>; 4308 #power-domain-cells = <1>; 4309 }; 4310 4311 dispcc: clock-controller@af00000 { 4312 compatible = "qcom,sa8775p-dispcc0"; 4313 reg = <0x0 0x0af00000 0x0 0x20000>; 4314 clocks = <&gcc GCC_DISP_AHB_CLK>, 4315 <&rpmhcc RPMH_CXO_CLK>, 4316 <&rpmhcc RPMH_CXO_CLK_A>, 4317 <&sleep_clk>, 4318 <0>, <0>, <0>, <0>, 4319 <0>, <0>, <0>, <0>; 4320 power-domains = <&rpmhpd RPMHPD_MMCX>; 4321 #clock-cells = <1>; 4322 #reset-cells = <1>; 4323 #power-domain-cells = <1>; 4324 }; 4325 4326 pdc: interrupt-controller@b220000 { 4327 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 4328 reg = <0x0 0xb220000 0x0 0x30000>, 4329 <0x0 0x17c000f0 0x0 0x64>; 4330 interrupt-parent = <&intc>; 4331 #interrupt-cells = <2>; 4332 interrupt-controller; 4333 qcom,pdc-ranges = <0 480 40>, 4334 <40 140 14>, 4335 <54 263 1>, 4336 <55 306 4>, 4337 <59 312 3>, 4338 <62 374 2>, 4339 <64 434 2>, 4340 <66 438 2>, 4341 <70 520 1>, 4342 <73 523 1>, 4343 <118 568 6>, 4344 <124 609 3>, 4345 <159 638 1>, 4346 <160 720 3>, 4347 <169 728 30>, 4348 <199 416 2>, 4349 <201 449 1>, 4350 <202 89 1>, 4351 <203 451 1>, 4352 <204 462 1>, 4353 <205 264 1>, 4354 <206 579 1>, 4355 <207 653 1>, 4356 <208 656 1>, 4357 <209 659 1>, 4358 <210 122 1>, 4359 <211 699 1>, 4360 <212 705 1>, 4361 <213 450 1>, 4362 <214 643 2>, 4363 <216 646 5>, 4364 <221 390 5>, 4365 <226 700 2>, 4366 <228 440 1>, 4367 <229 663 1>, 4368 <230 524 2>, 4369 <232 612 3>, 4370 <235 723 5>; 4371 }; 4372 4373 aoss_qmp: power-management@c300000 { 4374 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 4375 reg = <0x0 0x0c300000 0x0 0x400>; 4376 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4377 IPCC_MPROC_SIGNAL_GLINK_QMP 4378 IRQ_TYPE_EDGE_RISING>; 4379 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4380 #clock-cells = <0>; 4381 }; 4382 4383 sram@c3f0000 { 4384 compatible = "qcom,rpmh-stats"; 4385 reg = <0x0 0x0c3f0000 0x0 0x400>; 4386 }; 4387 4388 spmi_bus: spmi@c440000 { 4389 compatible = "qcom,spmi-pmic-arb"; 4390 reg = <0x0 0x0c440000 0x0 0x1100>, 4391 <0x0 0x0c600000 0x0 0x2000000>, 4392 <0x0 0x0e600000 0x0 0x100000>, 4393 <0x0 0x0e700000 0x0 0xa0000>, 4394 <0x0 0x0c40a000 0x0 0x26000>; 4395 reg-names = "core", 4396 "chnls", 4397 "obsrvr", 4398 "intr", 4399 "cnfg"; 4400 qcom,channel = <0>; 4401 qcom,ee = <0>; 4402 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4403 interrupt-names = "periph_irq"; 4404 interrupt-controller; 4405 #interrupt-cells = <4>; 4406 #address-cells = <2>; 4407 #size-cells = <0>; 4408 }; 4409 4410 tlmm: pinctrl@f100000 { 4411 compatible = "qcom,qcs8300-tlmm"; 4412 reg = <0x0 0x0f100000 0x0 0x300000>; 4413 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4414 gpio-controller; 4415 #gpio-cells = <2>; 4416 gpio-ranges = <&tlmm 0 0 134>; 4417 interrupt-controller; 4418 #interrupt-cells = <2>; 4419 wakeup-parent = <&pdc>; 4420 4421 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4422 pins = "gpio17", "gpio18"; 4423 function = "qup0_se0"; 4424 }; 4425 4426 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4427 pins = "gpio19", "gpio20"; 4428 function = "qup0_se1"; 4429 }; 4430 4431 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4432 pins = "gpio33", "gpio34"; 4433 function = "qup0_se2"; 4434 }; 4435 4436 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4437 pins = "gpio25", "gpio26"; 4438 function = "qup0_se3"; 4439 }; 4440 4441 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4442 pins = "gpio29", "gpio30"; 4443 function = "qup0_se4"; 4444 }; 4445 4446 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4447 pins = "gpio21", "gpio22"; 4448 function = "qup0_se5"; 4449 }; 4450 4451 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4452 pins = "gpio80", "gpio81"; 4453 function = "qup0_se6"; 4454 }; 4455 4456 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4457 pins = "gpio37", "gpio38"; 4458 function = "qup1_se0"; 4459 }; 4460 4461 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4462 pins = "gpio39", "gpio40"; 4463 function = "qup1_se1"; 4464 }; 4465 4466 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4467 pins = "gpio84", "gpio85"; 4468 function = "qup1_se2"; 4469 }; 4470 4471 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4472 pins = "gpio41", "gpio42"; 4473 function = "qup1_se3"; 4474 }; 4475 4476 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4477 pins = "gpio45", "gpio46"; 4478 function = "qup1_se4"; 4479 }; 4480 4481 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4482 pins = "gpio49", "gpio50"; 4483 function = "qup1_se5"; 4484 }; 4485 4486 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4487 pins = "gpio89", "gpio90"; 4488 function = "qup1_se6"; 4489 }; 4490 4491 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4492 pins = "gpio91", "gpio92"; 4493 function = "qup1_se7"; 4494 }; 4495 4496 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 4497 pins = "gpio10", "gpio11"; 4498 function = "qup2_se0"; 4499 }; 4500 4501 qup_spi0_data_clk: qup-spi0-data-clk-state { 4502 pins = "gpio17", "gpio18", "gpio19"; 4503 function = "qup0_se0"; 4504 }; 4505 4506 qup_spi0_cs: qup-spi0-cs-state { 4507 pins = "gpio20"; 4508 function = "qup0_se0"; 4509 }; 4510 4511 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4512 pins = "gpio20"; 4513 function = "gpio"; 4514 }; 4515 4516 qup_spi1_data_clk: qup-spi1-data-clk-state { 4517 pins = "gpio19", "gpio20", "gpio17"; 4518 function = "qup0_se1"; 4519 }; 4520 4521 qup_spi1_cs: qup-spi1-cs-state { 4522 pins = "gpio18"; 4523 function = "qup0_se1"; 4524 }; 4525 4526 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4527 pins = "gpio18"; 4528 function = "gpio"; 4529 }; 4530 4531 qup_spi2_data_clk: qup-spi2-data-clk-state { 4532 pins = "gpio33", "gpio34", "gpio35"; 4533 function = "qup0_se2"; 4534 }; 4535 4536 qup_spi2_cs: qup-spi2-cs-state { 4537 pins = "gpio36"; 4538 function = "qup0_se2"; 4539 }; 4540 4541 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4542 pins = "gpio36"; 4543 function = "gpio"; 4544 }; 4545 4546 qup_spi3_data_clk: qup-spi3-data-clk-state { 4547 pins = "gpio25", "gpio26", "gpio27"; 4548 function = "qup0_se3"; 4549 }; 4550 4551 qup_spi3_cs: qup-spi3-cs-state { 4552 pins = "gpio28"; 4553 function = "qup0_se3"; 4554 }; 4555 4556 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4557 pins = "gpio28"; 4558 function = "gpio"; 4559 }; 4560 4561 qup_spi4_data_clk: qup-spi4-data-clk-state { 4562 pins = "gpio29", "gpio30", "gpio31"; 4563 function = "qup0_se4"; 4564 }; 4565 4566 qup_spi4_cs: qup-spi4-cs-state { 4567 pins = "gpio32"; 4568 function = "qup0_se4"; 4569 }; 4570 4571 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4572 pins = "gpio32"; 4573 function = "gpio"; 4574 }; 4575 4576 qup_spi5_data_clk: qup-spi5-data-clk-state { 4577 pins = "gpio21", "gpio22", "gpio23"; 4578 function = "qup0_se5"; 4579 }; 4580 4581 qup_spi5_cs: qup-spi5-cs-state { 4582 pins = "gpio24"; 4583 function = "qup0_se5"; 4584 }; 4585 4586 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4587 pins = "gpio24"; 4588 function = "gpio"; 4589 }; 4590 4591 qup_spi6_data_clk: qup-spi6-data-clk-state { 4592 pins = "gpio80", "gpio81", "gpio82"; 4593 function = "qup0_se6"; 4594 }; 4595 4596 qup_spi6_cs: qup-spi6-cs-state { 4597 pins = "gpio83"; 4598 function = "qup0_se6"; 4599 }; 4600 4601 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4602 pins = "gpio83"; 4603 function = "gpio"; 4604 }; 4605 4606 qup_spi8_data_clk: qup-spi8-data-clk-state { 4607 pins = "gpio37", "gpio38", "gpio39"; 4608 function = "qup1_se0"; 4609 }; 4610 4611 qup_spi8_cs: qup-spi8-cs-state { 4612 pins = "gpio40"; 4613 function = "qup1_se0"; 4614 }; 4615 4616 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4617 pins = "gpio40"; 4618 function = "gpio"; 4619 }; 4620 4621 qup_spi9_data_clk: qup-spi9-data-clk-state { 4622 pins = "gpio39", "gpio40", "gpio37"; 4623 function = "qup1_se1"; 4624 }; 4625 4626 qup_spi9_cs: qup-spi9-cs-state { 4627 pins = "gpio38"; 4628 function = "qup1_se1"; 4629 }; 4630 4631 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4632 pins = "gpio38"; 4633 function = "gpio"; 4634 }; 4635 4636 qup_spi10_data_clk: qup-spi10-data-clk-state { 4637 pins = "gpio84", "gpio85", "gpio86"; 4638 function = "qup1_se2"; 4639 }; 4640 4641 qup_spi10_cs: qup-spi10-cs-state { 4642 pins = "gpio87"; 4643 function = "qup1_se2"; 4644 }; 4645 4646 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4647 pins = "gpio87"; 4648 function = "gpio"; 4649 }; 4650 4651 qup_spi12_data_clk: qup-spi12-data-clk-state { 4652 pins = "gpio45", "gpio46", "gpio47"; 4653 function = "qup1_se4"; 4654 }; 4655 4656 qup_spi12_cs: qup-spi12-cs-state { 4657 pins = "gpio48"; 4658 function = "qup1_se4"; 4659 }; 4660 4661 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4662 pins = "gpio48"; 4663 function = "gpio"; 4664 }; 4665 4666 qup_spi13_data_clk: qup-spi13-data-clk-state { 4667 pins = "gpio49", "gpio50", "gpio51"; 4668 function = "qup1_se5"; 4669 }; 4670 4671 qup_spi13_cs: qup-spi13-cs-state { 4672 pins = "gpio52"; 4673 function = "qup1_se5"; 4674 }; 4675 4676 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4677 pins = "gpio52"; 4678 function = "gpio"; 4679 }; 4680 4681 qup_spi14_data_clk: qup-spi14-data-clk-state { 4682 pins = "gpio89", "gpio90", "gpio91"; 4683 function = "qup1_se6"; 4684 }; 4685 4686 qup_spi14_cs: qup-spi14-cs-state { 4687 pins = "gpio92"; 4688 function = "qup1_se6"; 4689 }; 4690 4691 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4692 pins = "gpio92"; 4693 function = "gpio"; 4694 }; 4695 4696 qup_spi15_data_clk: qup-spi15-data-clk-state { 4697 pins = "gpio91", "gpio92", "gpio89"; 4698 function = "qup1_se7"; 4699 }; 4700 4701 qup_spi15_cs: qup-spi15-cs-state { 4702 pins = "gpio90"; 4703 function = "qup1_se7"; 4704 }; 4705 4706 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4707 pins = "gpio90"; 4708 function = "gpio"; 4709 }; 4710 4711 qup_spi16_data_clk: qup-spi16-data-clk-state { 4712 pins = "gpio10", "gpio11", "gpio12"; 4713 function = "qup2_se0"; 4714 }; 4715 4716 qup_spi16_cs: qup-spi16-cs-state { 4717 pins = "gpio13"; 4718 function = "qup2_se0"; 4719 }; 4720 4721 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 4722 pins = "gpio13"; 4723 function = "gpio"; 4724 }; 4725 4726 qup_uart0_cts: qup-uart0-cts-state { 4727 pins = "gpio17"; 4728 function = "qup0_se0"; 4729 }; 4730 4731 qup_uart0_rts: qup-uart0-rts-state { 4732 pins = "gpio18"; 4733 function = "qup0_se0"; 4734 }; 4735 4736 qup_uart0_tx: qup-uart0-tx-state { 4737 pins = "gpio19"; 4738 function = "qup0_se0"; 4739 }; 4740 4741 qup_uart0_rx: qup-uart0-rx-state { 4742 pins = "gpio20"; 4743 function = "qup0_se0"; 4744 }; 4745 4746 qup_uart1_cts: qup-uart1-cts-state { 4747 pins = "gpio19"; 4748 function = "qup0_se1"; 4749 }; 4750 4751 qup_uart1_rts: qup-uart1-rts-state { 4752 pins = "gpio20"; 4753 function = "qup0_se1"; 4754 }; 4755 4756 qup_uart1_tx: qup-uart1-tx-state { 4757 pins = "gpio17"; 4758 function = "qup0_se1"; 4759 }; 4760 4761 qup_uart1_rx: qup-uart1-rx-state { 4762 pins = "gpio18"; 4763 function = "qup0_se1"; 4764 }; 4765 4766 qup_uart2_cts: qup-uart2-cts-state { 4767 pins = "gpio33"; 4768 function = "qup0_se2"; 4769 }; 4770 4771 qup_uart2_rts: qup-uart2-rts-state { 4772 pins = "gpio34"; 4773 function = "qup0_se2"; 4774 }; 4775 4776 qup_uart2_tx: qup-uart2-tx-state { 4777 pins = "gpio35"; 4778 function = "qup0_se2"; 4779 }; 4780 4781 qup_uart2_rx: qup-uart2-rx-state { 4782 pins = "gpio36"; 4783 function = "qup0_se2"; 4784 }; 4785 4786 qup_uart3_cts: qup-uart3-cts-state { 4787 pins = "gpio25"; 4788 function = "qup0_se3"; 4789 }; 4790 4791 qup_uart3_rts: qup-uart3-rts-state { 4792 pins = "gpio26"; 4793 function = "qup0_se3"; 4794 }; 4795 4796 qup_uart3_tx: qup-uart3-tx-state { 4797 pins = "gpio27"; 4798 function = "qup0_se3"; 4799 }; 4800 4801 qup_uart3_rx: qup-uart3-rx-state { 4802 pins = "gpio28"; 4803 function = "qup0_se3"; 4804 }; 4805 4806 qup_uart4_cts: qup-uart4-cts-state { 4807 pins = "gpio29"; 4808 function = "qup0_se4"; 4809 }; 4810 4811 qup_uart4_rts: qup-uart4-rts-state { 4812 pins = "gpio30"; 4813 function = "qup0_se4"; 4814 }; 4815 4816 qup_uart4_tx: qup-uart4-tx-state { 4817 pins = "gpio31"; 4818 function = "qup0_se4"; 4819 }; 4820 4821 qup_uart4_rx: qup-uart4-rx-state { 4822 pins = "gpio32"; 4823 function = "qup0_se4"; 4824 }; 4825 4826 qup_uart5_cts: qup-uart5-cts-state { 4827 pins = "gpio21"; 4828 function = "qup0_se5"; 4829 }; 4830 4831 qup_uart5_rts: qup-uart5-rts-state { 4832 pins = "gpio22"; 4833 function = "qup0_se5"; 4834 }; 4835 4836 qup_uart5_tx: qup-uart5-tx-state { 4837 pins = "gpio23"; 4838 function = "qup0_se5"; 4839 }; 4840 4841 qup_uart5_rx: qup-uart5-rx-state { 4842 pins = "gpio23"; 4843 function = "qup0_se5"; 4844 }; 4845 4846 qup_uart6_cts: qup-uart6-cts-state { 4847 pins = "gpio80"; 4848 function = "qup0_se6"; 4849 }; 4850 4851 qup_uart6_rts: qup-uart6-rts-state { 4852 pins = "gpio81"; 4853 function = "qup0_se6"; 4854 }; 4855 4856 qup_uart6_tx: qup-uart6-tx-state { 4857 pins = "gpio82"; 4858 function = "qup0_se6"; 4859 }; 4860 4861 qup_uart6_rx: qup-uart6-rx-state { 4862 pins = "gpio83"; 4863 function = "qup0_se6"; 4864 }; 4865 4866 qup_uart7_tx: qup-uart7-tx-state { 4867 pins = "gpio43"; 4868 function = "qup0_se7"; 4869 }; 4870 4871 qup_uart7_rx: qup-uart7-rx-state { 4872 pins = "gpio44"; 4873 function = "qup0_se7"; 4874 }; 4875 4876 qup_uart8_cts: qup-uart8-cts-state { 4877 pins = "gpio37"; 4878 function = "qup1_se0"; 4879 }; 4880 4881 qup_uart8_rts: qup-uart8-rts-state { 4882 pins = "gpio38"; 4883 function = "qup1_se0"; 4884 }; 4885 4886 qup_uart8_tx: qup-uart8-tx-state { 4887 pins = "gpio39"; 4888 function = "qup1_se0"; 4889 }; 4890 4891 qup_uart8_rx: qup-uart8-rx-state { 4892 pins = "gpio40"; 4893 function = "qup1_se0"; 4894 }; 4895 4896 qup_uart9_cts: qup-uart9-cts-state { 4897 pins = "gpio39"; 4898 function = "qup1_se1"; 4899 }; 4900 4901 qup_uart9_rts: qup-uart9-rts-state { 4902 pins = "gpio40"; 4903 function = "qup1_se1"; 4904 }; 4905 4906 qup_uart9_tx: qup-uart9-tx-state { 4907 pins = "gpio37"; 4908 function = "qup1_se1"; 4909 }; 4910 4911 qup_uart9_rx: qup-uart9-rx-state { 4912 pins = "gpio38"; 4913 function = "qup1_se1"; 4914 }; 4915 4916 qup_uart10_cts: qup-uart10-cts-state { 4917 pins = "gpio84"; 4918 function = "qup1_se2"; 4919 }; 4920 4921 qup_uart10_rts: qup-uart10-rts-state { 4922 pins = "gpio84"; 4923 function = "qup1_se2"; 4924 }; 4925 4926 qup_uart10_tx: qup-uart10-tx-state { 4927 pins = "gpio85"; 4928 function = "qup1_se2"; 4929 }; 4930 4931 qup_uart10_rx: qup-uart10-rx-state { 4932 pins = "gpio87"; 4933 function = "qup1_se2"; 4934 }; 4935 4936 qup_uart11_tx: qup-uart11-tx-state { 4937 pins = "gpio41"; 4938 function = "qup1_se3"; 4939 }; 4940 4941 qup_uart11_rx: qup-uart11-rx-state { 4942 pins = "gpio42"; 4943 function = "qup1_se3"; 4944 }; 4945 4946 qup_uart12_cts: qup-uart12-cts-state { 4947 pins = "gpio45"; 4948 function = "qup1_se4"; 4949 }; 4950 4951 qup_uart12_rts: qup-uart12-rts-state { 4952 pins = "gpio46"; 4953 function = "qup1_se4"; 4954 }; 4955 4956 qup_uart12_tx: qup-uart12-tx-state { 4957 pins = "gpio47"; 4958 function = "qup1_se4"; 4959 }; 4960 4961 qup_uart12_rx: qup-uart12-rx-state { 4962 pins = "gpio48"; 4963 function = "qup1_se4"; 4964 }; 4965 4966 qup_uart13_cts: qup-uart13-cts-state { 4967 pins = "gpio49"; 4968 function = "qup1_se5"; 4969 }; 4970 4971 qup_uart13_rts: qup-uart13-rts-state { 4972 pins = "gpio50"; 4973 function = "qup1_se5"; 4974 }; 4975 4976 qup_uart13_tx: qup-uart13-tx-state { 4977 pins = "gpio51"; 4978 function = "qup1_se5"; 4979 }; 4980 4981 qup_uart13_rx: qup-uart13-rx-state { 4982 pins = "gpio52"; 4983 function = "qup1_se5"; 4984 }; 4985 4986 qup_uart14_cts: qup-uart14-cts-state { 4987 pins = "gpio89"; 4988 function = "qup1_se6"; 4989 }; 4990 4991 qup_uart14_rts: qup-uart14-rts-state { 4992 pins = "gpio90"; 4993 function = "qup1_se6"; 4994 }; 4995 4996 qup_uart14_tx: qup-uart14-tx-state { 4997 pins = "gpio91"; 4998 function = "qup1_se6"; 4999 }; 5000 5001 qup_uart14_rx: qup-uart14-rx-state { 5002 pins = "gpio92"; 5003 function = "qup1_se6"; 5004 }; 5005 5006 qup_uart15_cts: qup-uart15-cts-state { 5007 pins = "gpio91"; 5008 function = "qup1_se7"; 5009 }; 5010 5011 qup_uart15_rts: qup-uart15-rts-state { 5012 pins = "gpio92"; 5013 function = "qup1_se7"; 5014 }; 5015 5016 qup_uart15_tx: qup-uart15-tx-state { 5017 pins = "gpio89"; 5018 function = "qup1_se7"; 5019 }; 5020 5021 qup_uart15_rx: qup-uart15-rx-state { 5022 pins = "gpio90"; 5023 function = "qup1_se7"; 5024 }; 5025 5026 qup_uart16_cts: qup-uart16-cts-state { 5027 pins = "gpio10"; 5028 function = "qup2_se0"; 5029 }; 5030 5031 qup_uart16_rts: qup-uart16-rts-state { 5032 pins = "gpio11"; 5033 function = "qup2_se0"; 5034 }; 5035 5036 qup_uart16_tx: qup-uart16-tx-state { 5037 pins = "gpio12"; 5038 function = "qup2_se0"; 5039 }; 5040 5041 qup_uart16_rx: qup-uart16-rx-state { 5042 pins = "gpio13"; 5043 function = "qup2_se0"; 5044 }; 5045 }; 5046 5047 sram: sram@146d8000 { 5048 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 5049 reg = <0x0 0x146d8000 0x0 0x1000>; 5050 ranges = <0x0 0x0 0x146d8000 0x1000>; 5051 5052 #address-cells = <1>; 5053 #size-cells = <1>; 5054 5055 pil-reloc@94c { 5056 compatible = "qcom,pil-reloc-info"; 5057 reg = <0x94c 0xc8>; 5058 }; 5059 }; 5060 5061 apps_smmu: iommu@15000000 { 5062 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5063 5064 reg = <0x0 0x15000000 0x0 0x100000>; 5065 #iommu-cells = <2>; 5066 #global-interrupts = <2>; 5067 dma-coherent; 5068 5069 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5195 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5196 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5197 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5198 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 5199 }; 5200 5201 pcie_smmu: iommu@15200000 { 5202 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5203 reg = <0x0 0x15200000 0x0 0x80000>; 5204 #iommu-cells = <2>; 5205 #global-interrupts = <2>; 5206 dma-coherent; 5207 5208 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 5209 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 5210 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 5211 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 5212 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 5213 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 5214 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 5215 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 5216 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 5217 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 5218 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 5219 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 5220 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 5221 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 5222 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 5223 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 5224 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 5225 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 5226 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 5227 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 5228 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 5229 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 5230 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 5231 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 5232 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 5233 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 5234 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 5235 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 5236 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 5237 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 5238 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 5239 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 5240 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 5241 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 5242 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 5243 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 5244 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 5245 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 5246 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 5247 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 5248 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 5249 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 5250 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 5251 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 5252 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 5253 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 5254 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 5255 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 5256 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 5257 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 5258 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 5259 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 5260 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 5261 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 5262 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 5263 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 5264 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 5265 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 5266 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 5267 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 5268 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 5269 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 5270 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 5271 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 5272 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 5273 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 5274 }; 5275 5276 intc: interrupt-controller@17a00000 { 5277 compatible = "arm,gic-v3"; 5278 reg = <0x0 0x17a00000 0x0 0x10000>, 5279 <0x0 0x17a60000 0x0 0x100000>; 5280 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5281 #interrupt-cells = <3>; 5282 interrupt-controller; 5283 #redistributor-regions = <1>; 5284 redistributor-stride = <0x0 0x20000>; 5285 }; 5286 5287 watchdog@17c10000 { 5288 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 5289 reg = <0x0 0x17c10000 0x0 0x1000>; 5290 clocks = <&sleep_clk>; 5291 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5292 }; 5293 5294 timer@17c20000 { 5295 compatible = "arm,armv7-timer-mem"; 5296 reg = <0x0 0x17c20000 0x0 0x1000>; 5297 ranges = <0x0 0x0 0x0 0x20000000>; 5298 #address-cells = <1>; 5299 #size-cells = <1>; 5300 5301 frame@17c21000 { 5302 reg = <0x17c21000 0x1000>, 5303 <0x17c22000 0x1000>; 5304 frame-number = <0>; 5305 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5306 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5307 }; 5308 5309 frame@17c23000 { 5310 reg = <0x17c23000 0x1000>; 5311 frame-number = <1>; 5312 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5313 status = "disabled"; 5314 }; 5315 5316 frame@17c25000 { 5317 reg = <0x17c25000 0x1000>; 5318 frame-number = <2>; 5319 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5320 status = "disabled"; 5321 }; 5322 5323 frame@17c27000 { 5324 reg = <0x17c27000 0x1000>; 5325 frame-number = <3>; 5326 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5327 status = "disabled"; 5328 }; 5329 5330 frame@17c29000 { 5331 reg = <0x17c29000 0x1000>; 5332 frame-number = <4>; 5333 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5334 status = "disabled"; 5335 }; 5336 5337 frame@17c2b000 { 5338 reg = <0x17c2b000 0x1000>; 5339 frame-number = <5>; 5340 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5341 status = "disabled"; 5342 }; 5343 5344 frame@17c2d000 { 5345 reg = <0x17c2d000 0x1000>; 5346 frame-number = <6>; 5347 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5348 status = "disabled"; 5349 }; 5350 }; 5351 5352 apps_rsc: rsc@18200000 { 5353 compatible = "qcom,rpmh-rsc"; 5354 reg = <0x0 0x18200000 0x0 0x10000>, 5355 <0x0 0x18210000 0x0 0x10000>, 5356 <0x0 0x18220000 0x0 0x10000>; 5357 reg-names = "drv-0", 5358 "drv-1", 5359 "drv-2"; 5360 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5361 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5362 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5363 5364 power-domains = <&system_pd>; 5365 label = "apps_rsc"; 5366 5367 qcom,tcs-offset = <0xd00>; 5368 qcom,drv-id = <2>; 5369 qcom,tcs-config = <ACTIVE_TCS 2>, 5370 <SLEEP_TCS 3>, 5371 <WAKE_TCS 3>, 5372 <CONTROL_TCS 0>; 5373 5374 apps_bcm_voter: bcm-voter { 5375 compatible = "qcom,bcm-voter"; 5376 }; 5377 5378 rpmhcc: clock-controller { 5379 compatible = "qcom,sa8775p-rpmh-clk"; 5380 #clock-cells = <1>; 5381 clocks = <&xo_board_clk>; 5382 clock-names = "xo"; 5383 }; 5384 5385 rpmhpd: power-controller { 5386 compatible = "qcom,qcs8300-rpmhpd"; 5387 #power-domain-cells = <1>; 5388 operating-points-v2 = <&rpmhpd_opp_table>; 5389 5390 rpmhpd_opp_table: opp-table { 5391 compatible = "operating-points-v2"; 5392 5393 rpmhpd_opp_ret: opp-0 { 5394 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5395 }; 5396 5397 rpmhpd_opp_min_svs: opp-1 { 5398 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5399 }; 5400 5401 rpmhpd_opp_low_svs: opp-2 { 5402 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5403 }; 5404 5405 rpmhpd_opp_svs: opp-3 { 5406 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5407 }; 5408 5409 rpmhpd_opp_svs_l1: opp-4 { 5410 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5411 }; 5412 5413 rpmhpd_opp_nom: opp-5 { 5414 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5415 }; 5416 5417 rpmhpd_opp_nom_l1: opp-6 { 5418 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5419 }; 5420 5421 rpmhpd_opp_nom_l2: opp-7 { 5422 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5423 }; 5424 5425 rpmhpd_opp_turbo: opp-8 { 5426 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5427 }; 5428 5429 rpmhpd_opp_turbo_l1: opp-9 { 5430 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5431 }; 5432 }; 5433 }; 5434 }; 5435 5436 cpufreq_hw: cpufreq@18591000 { 5437 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; 5438 reg = <0x0 0x18591000 0x0 0x1000>, 5439 <0x0 0x18593000 0x0 0x1000>, 5440 <0x0 0x18594000 0x0 0x1000>; 5441 reg-names = "freq-domain0", 5442 "freq-domain1", 5443 "freq-domain2"; 5444 5445 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5446 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 5447 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 5448 interrupt-names = "dcvsh-irq-0", 5449 "dcvsh-irq-1", 5450 "dcvsh-irq-2"; 5451 5452 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5453 clock-names = "xo", "alternate"; 5454 5455 #freq-domain-cells = <1>; 5456 }; 5457 5458 remoteproc_gpdsp: remoteproc@20c00000 { 5459 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 5460 reg = <0x0 0x20c00000 0x0 0x10000>; 5461 5462 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 5463 <&smp2p_gpdsp_in 0 0>, 5464 <&smp2p_gpdsp_in 1 0>, 5465 <&smp2p_gpdsp_in 2 0>, 5466 <&smp2p_gpdsp_in 3 0>; 5467 interrupt-names = "wdog", 5468 "fatal", 5469 "ready", 5470 "handover", 5471 "stop-ack"; 5472 5473 clocks = <&rpmhcc RPMH_CXO_CLK>; 5474 clock-names = "xo"; 5475 5476 power-domains = <&rpmhpd RPMHPD_CX>, 5477 <&rpmhpd RPMHPD_MXC>; 5478 power-domain-names = "cx", 5479 "mxc"; 5480 5481 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 5482 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 5483 5484 memory-region = <&gpdsp_mem>; 5485 5486 qcom,qmp = <&aoss_qmp>; 5487 5488 qcom,smem-states = <&smp2p_gpdsp_out 0>; 5489 qcom,smem-state-names = "stop"; 5490 5491 status = "disabled"; 5492 5493 glink-edge { 5494 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 5495 IPCC_MPROC_SIGNAL_GLINK_QMP 5496 IRQ_TYPE_EDGE_RISING>; 5497 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 5498 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5499 5500 label = "gpdsp"; 5501 qcom,remote-pid = <17>; 5502 }; 5503 }; 5504 5505 ethernet0: ethernet@23040000 { 5506 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 5507 reg = <0x0 0x23040000 0x0 0x00010000>, 5508 <0x0 0x23056000 0x0 0x00000100>; 5509 reg-names = "stmmaceth", "rgmii"; 5510 5511 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 5512 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 5513 interrupt-names = "macirq", "sfty"; 5514 5515 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 5516 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 5517 <&gcc GCC_EMAC0_PTP_CLK>, 5518 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 5519 clock-names = "stmmaceth", 5520 "pclk", 5521 "ptp_ref", 5522 "phyaux"; 5523 power-domains = <&gcc GCC_EMAC0_GDSC>; 5524 5525 phys = <&serdes0>; 5526 phy-names = "serdes"; 5527 5528 iommus = <&apps_smmu 0x120 0xf>; 5529 dma-coherent; 5530 5531 snps,tso; 5532 snps,pbl = <32>; 5533 rx-fifo-depth = <16384>; 5534 tx-fifo-depth = <20480>; 5535 5536 status = "disabled"; 5537 }; 5538 5539 nspa_noc: interconnect@260c0000 { 5540 compatible = "qcom,qcs8300-nspa-noc"; 5541 reg = <0x0 0x260c0000 0x0 0x16080>; 5542 #interconnect-cells = <2>; 5543 qcom,bcm-voters = <&apps_bcm_voter>; 5544 }; 5545 5546 remoteproc_cdsp: remoteproc@26300000 { 5547 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 5548 reg = <0x0 0x26300000 0x0 0x10000>; 5549 5550 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5551 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5552 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5553 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5554 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5555 interrupt-names = "wdog", 5556 "fatal", 5557 "ready", 5558 "handover", 5559 "stop-ack"; 5560 5561 clocks = <&rpmhcc RPMH_CXO_CLK>; 5562 clock-names = "xo"; 5563 5564 power-domains = <&rpmhpd RPMHPD_CX>, 5565 <&rpmhpd RPMHPD_MXC>, 5566 <&rpmhpd RPMHPD_NSP0>; 5567 5568 power-domain-names = "cx", 5569 "mxc", 5570 "nsp"; 5571 5572 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5573 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5574 5575 memory-region = <&cdsp_mem>; 5576 5577 qcom,qmp = <&aoss_qmp>; 5578 5579 qcom,smem-states = <&smp2p_cdsp_out 0>; 5580 qcom,smem-state-names = "stop"; 5581 5582 status = "disabled"; 5583 5584 glink-edge { 5585 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5586 IPCC_MPROC_SIGNAL_GLINK_QMP 5587 IRQ_TYPE_EDGE_RISING>; 5588 mboxes = <&ipcc IPCC_CLIENT_CDSP 5589 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5590 5591 label = "cdsp"; 5592 qcom,remote-pid = <5>; 5593 5594 fastrpc { 5595 compatible = "qcom,fastrpc"; 5596 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5597 label = "cdsp"; 5598 #address-cells = <1>; 5599 #size-cells = <0>; 5600 5601 compute-cb@1 { 5602 compatible = "qcom,fastrpc-compute-cb"; 5603 reg = <1>; 5604 iommus = <&apps_smmu 0x19c1 0x0440>, 5605 <&apps_smmu 0x1961 0x0400>; 5606 dma-coherent; 5607 }; 5608 5609 compute-cb@2 { 5610 compatible = "qcom,fastrpc-compute-cb"; 5611 reg = <2>; 5612 iommus = <&apps_smmu 0x19c2 0x0440>, 5613 <&apps_smmu 0x1962 0x0400>; 5614 dma-coherent; 5615 }; 5616 5617 compute-cb@3 { 5618 compatible = "qcom,fastrpc-compute-cb"; 5619 reg = <3>; 5620 iommus = <&apps_smmu 0x19c3 0x0440>, 5621 <&apps_smmu 0x1963 0x0400>; 5622 dma-coherent; 5623 }; 5624 5625 compute-cb@4 { 5626 compatible = "qcom,fastrpc-compute-cb"; 5627 reg = <4>; 5628 iommus = <&apps_smmu 0x19c4 0x0440>, 5629 <&apps_smmu 0x1964 0x0400>; 5630 dma-coherent; 5631 }; 5632 }; 5633 }; 5634 }; 5635 }; 5636 5637 timer { 5638 compatible = "arm,armv8-timer"; 5639 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5640 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5641 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5642 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5643 }; 5644}; 5645