1// SPDX-License-Identifier: BSD-3-Clause 2/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 5#include <dt-bindings/clock/qcom,gcc-msm8953.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interconnect/qcom,msm8953.h> 9#include <dt-bindings/interconnect/qcom,rpm-icc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,apr.h> 13#include <dt-bindings/sound/qcom,q6afe.h> 14#include <dt-bindings/sound/qcom,q6asm.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <32768>; 30 }; 31 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <19200000>; 36 clock-output-names = "xo"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0>; 48 enable-method = "psci"; 49 capacity-dmips-mhz = <1024>; 50 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 51 &bimc SLV_EBI RPM_ACTIVE_TAG>; 52 next-level-cache = <&l2_0>; 53 #cooling-cells = <2>; 54 }; 55 56 cpu1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x1>; 60 enable-method = "psci"; 61 capacity-dmips-mhz = <1024>; 62 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 63 &bimc SLV_EBI RPM_ACTIVE_TAG>; 64 next-level-cache = <&l2_0>; 65 #cooling-cells = <2>; 66 }; 67 68 cpu2: cpu@2 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x2>; 72 enable-method = "psci"; 73 capacity-dmips-mhz = <1024>; 74 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 75 &bimc SLV_EBI RPM_ACTIVE_TAG>; 76 next-level-cache = <&l2_0>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu3: cpu@3 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x3>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <1024>; 86 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 87 &bimc SLV_EBI RPM_ACTIVE_TAG>; 88 next-level-cache = <&l2_0>; 89 #cooling-cells = <2>; 90 }; 91 92 cpu4: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x100>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <1024>; 98 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 99 &bimc SLV_EBI RPM_ACTIVE_TAG>; 100 next-level-cache = <&l2_1>; 101 #cooling-cells = <2>; 102 }; 103 104 cpu5: cpu@101 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 reg = <0x101>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <1024>; 110 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 111 &bimc SLV_EBI RPM_ACTIVE_TAG>; 112 next-level-cache = <&l2_1>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu6: cpu@102 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x102>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 123 &bimc SLV_EBI RPM_ACTIVE_TAG>; 124 next-level-cache = <&l2_1>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu7: cpu@103 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a53"; 131 reg = <0x103>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <1024>; 134 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 135 &bimc SLV_EBI RPM_ACTIVE_TAG>; 136 next-level-cache = <&l2_1>; 137 #cooling-cells = <2>; 138 }; 139 140 cpu-map { 141 cluster0 { 142 core0 { 143 cpu = <&cpu0>; 144 }; 145 core1 { 146 cpu = <&cpu1>; 147 }; 148 core2 { 149 cpu = <&cpu2>; 150 }; 151 core3 { 152 cpu = <&cpu3>; 153 }; 154 }; 155 156 cluster1 { 157 core0 { 158 cpu = <&cpu4>; 159 }; 160 core1 { 161 cpu = <&cpu5>; 162 }; 163 core2 { 164 cpu = <&cpu6>; 165 }; 166 core3 { 167 cpu = <&cpu7>; 168 }; 169 }; 170 }; 171 172 l2_0: l2-cache-0 { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 }; 177 178 l2_1: l2-cache-1 { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-unified; 182 }; 183 }; 184 185 firmware { 186 scm: scm { 187 compatible = "qcom,scm-msm8953", "qcom,scm"; 188 clocks = <&gcc GCC_CRYPTO_CLK>, 189 <&gcc GCC_CRYPTO_AXI_CLK>, 190 <&gcc GCC_CRYPTO_AHB_CLK>; 191 clock-names = "core", "bus", "iface"; 192 #reset-cells = <1>; 193 }; 194 }; 195 196 memory@10000000 { 197 device_type = "memory"; 198 /* We expect the bootloader to fill in the reg */ 199 reg = <0 0x10000000 0 0>; 200 }; 201 202 pmu { 203 compatible = "arm,cortex-a53-pmu"; 204 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 205 }; 206 207 psci { 208 compatible = "arm,psci-1.0"; 209 method = "smc"; 210 }; 211 212 rpm: remoteproc { 213 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc"; 214 215 smd-edge { 216 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 217 mboxes = <&apcs 0>; 218 qcom,smd-edge = <15>; 219 220 rpm_requests: rpm-requests { 221 compatible = "qcom,rpm-msm8953", "qcom,smd-rpm"; 222 qcom,smd-channels = "rpm_requests"; 223 224 rpmcc: clock-controller { 225 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; 226 clocks = <&xo_board>; 227 clock-names = "xo"; 228 #clock-cells = <1>; 229 }; 230 231 rpmpd: power-controller { 232 compatible = "qcom,msm8953-rpmpd"; 233 #power-domain-cells = <1>; 234 operating-points-v2 = <&rpmpd_opp_table>; 235 236 rpmpd_opp_table: opp-table { 237 compatible = "operating-points-v2"; 238 239 rpmpd_opp_ret: opp1 { 240 opp-level = <RPM_SMD_LEVEL_RETENTION>; 241 }; 242 243 rpmpd_opp_ret_plus: opp2 { 244 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 245 }; 246 247 rpmpd_opp_min_svs: opp3 { 248 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 249 }; 250 251 rpmpd_opp_low_svs: opp4 { 252 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 253 }; 254 255 rpmpd_opp_svs: opp5 { 256 opp-level = <RPM_SMD_LEVEL_SVS>; 257 }; 258 259 rpmpd_opp_svs_plus: opp6 { 260 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 261 }; 262 263 rpmpd_opp_nom: opp7 { 264 opp-level = <RPM_SMD_LEVEL_NOM>; 265 }; 266 267 rpmpd_opp_nom_plus: opp8 { 268 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 269 }; 270 271 rpmpd_opp_turbo: opp9 { 272 opp-level = <RPM_SMD_LEVEL_TURBO>; 273 }; 274 }; 275 }; 276 }; 277 }; 278 }; 279 280 reserved-memory { 281 #address-cells = <2>; 282 #size-cells = <2>; 283 ranges; 284 285 zap_shader_region: zap@81800000 { 286 compatible = "shared-dma-pool"; 287 reg = <0x0 0x81800000 0x0 0x2000>; 288 no-map; 289 }; 290 291 qseecom_mem: qseecom@85b00000 { 292 reg = <0x0 0x85b00000 0x0 0x800000>; 293 no-map; 294 }; 295 296 smem_mem: smem@86300000 { 297 compatible = "qcom,smem"; 298 reg = <0x0 0x86300000 0x0 0x100000>; 299 qcom,rpm-msg-ram = <&rpm_msg_ram>; 300 hwlocks = <&tcsr_mutex 3>; 301 no-map; 302 }; 303 304 reserved@86400000 { 305 reg = <0x0 0x86400000 0x0 0x400000>; 306 no-map; 307 }; 308 309 mpss_mem: mpss@86c00000 { 310 reg = <0x0 0x86c00000 0x0 0x6a00000>; 311 no-map; 312 }; 313 314 adsp_fw_mem: adsp@8d600000 { 315 reg = <0x0 0x8d600000 0x0 0x1100000>; 316 no-map; 317 }; 318 319 wcnss_fw_mem: wcnss@8e700000 { 320 reg = <0x0 0x8e700000 0x0 0x700000>; 321 no-map; 322 }; 323 324 dfps_data_mem: dfps-data@90000000 { 325 reg = <0 0x90000000 0 0x1000>; 326 no-map; 327 }; 328 329 cont_splash_mem: cont-splash@90001000 { 330 reg = <0x0 0x90001000 0x0 0x13ff000>; 331 no-map; 332 }; 333 334 venus_mem: venus@91400000 { 335 reg = <0x0 0x91400000 0x0 0x700000>; 336 no-map; 337 }; 338 339 mba_mem: mba@92000000 { 340 reg = <0x0 0x92000000 0x0 0x100000>; 341 no-map; 342 }; 343 344 rmtfs@f2d00000 { 345 compatible = "qcom,rmtfs-mem"; 346 reg = <0x0 0xf2d00000 0x0 0x180000>; 347 no-map; 348 349 qcom,client-id = <1>; 350 }; 351 }; 352 353 smp2p-adsp { 354 compatible = "qcom,smp2p"; 355 qcom,smem = <443>, <429>; 356 357 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 358 359 mboxes = <&apcs 10>; 360 361 qcom,local-pid = <0>; 362 qcom,remote-pid = <2>; 363 364 smp2p_adsp_out: master-kernel { 365 qcom,entry-name = "master-kernel"; 366 #qcom,smem-state-cells = <1>; 367 }; 368 369 smp2p_adsp_in: slave-kernel { 370 qcom,entry-name = "slave-kernel"; 371 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 }; 375 }; 376 377 smp2p-modem { 378 compatible = "qcom,smp2p"; 379 qcom,smem = <435>, <428>; 380 381 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 382 383 mboxes = <&apcs 14>; 384 385 qcom,local-pid = <0>; 386 qcom,remote-pid = <1>; 387 388 smp2p_modem_out: master-kernel { 389 qcom,entry-name = "master-kernel"; 390 391 #qcom,smem-state-cells = <1>; 392 }; 393 394 smp2p_modem_in: slave-kernel { 395 qcom,entry-name = "slave-kernel"; 396 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 }; 400 }; 401 402 smp2p-wcnss { 403 compatible = "qcom,smp2p"; 404 qcom,smem = <451>, <431>; 405 406 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 407 408 mboxes = <&apcs 18>; 409 410 qcom,local-pid = <0>; 411 qcom,remote-pid = <4>; 412 413 smp2p_wcnss_out: master-kernel { 414 qcom,entry-name = "master-kernel"; 415 416 #qcom,smem-state-cells = <1>; 417 }; 418 419 smp2p_wcnss_in: slave-kernel { 420 qcom,entry-name = "slave-kernel"; 421 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 }; 425 }; 426 427 smsm { 428 compatible = "qcom,smsm"; 429 430 #address-cells = <1>; 431 #size-cells = <0>; 432 433 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; 434 435 apps_smsm: apps@0 { 436 reg = <0>; 437 438 #qcom,smem-state-cells = <1>; 439 }; 440 441 modem_smsm: modem@1 { 442 reg = <1>; 443 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 444 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 }; 448 449 wcnss_smsm: wcnss@6 { 450 reg = <6>; 451 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 452 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 }; 456 }; 457 458 soc: soc@0 { 459 #address-cells = <1>; 460 #size-cells = <1>; 461 ranges = <0 0 0 0xffffffff>; 462 compatible = "simple-bus"; 463 464 rpm_msg_ram: sram@60000 { 465 compatible = "qcom,rpm-msg-ram"; 466 reg = <0x00060000 0x8000>; 467 }; 468 469 hsusb_phy: phy@79000 { 470 compatible = "qcom,msm8953-qusb2-phy"; 471 reg = <0x00079000 0x180>; 472 #phy-cells = <0>; 473 474 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 475 <&gcc GCC_QUSB_REF_CLK>; 476 clock-names = "cfg_ahb", "ref"; 477 478 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; 479 480 resets = <&gcc GCC_QUSB2_PHY_BCR>; 481 482 status = "disabled"; 483 }; 484 485 rng@e3000 { 486 compatible = "qcom,prng"; 487 reg = <0x000e3000 0x1000>; 488 clocks = <&gcc GCC_PRNG_AHB_CLK>; 489 clock-names = "core"; 490 }; 491 492 bimc: interconnect@400000 { 493 compatible = "qcom,msm8953-bimc"; 494 reg = <0x00400000 0x5a000>; 495 496 #interconnect-cells = <2>; 497 }; 498 499 tsens0: thermal-sensor@4a9000 { 500 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; 501 reg = <0x004a9000 0x1000>, /* TM */ 502 <0x004a8000 0x1000>; /* SROT */ 503 #qcom,sensors = <16>; 504 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 506 interrupt-names = "uplow", "critical"; 507 #thermal-sensor-cells = <1>; 508 }; 509 510 restart@4ab000 { 511 compatible = "qcom,pshold"; 512 reg = <0x004ab000 0x4>; 513 }; 514 515 pcnoc: interconnect@500000 { 516 compatible = "qcom,msm8953-pcnoc"; 517 reg = <0x00500000 0x12080>; 518 519 clocks = <&gcc GCC_PCNOC_USB3_AXI_CLK>; 520 clock-names = "pcnoc_usb3_axi"; 521 522 #interconnect-cells = <2>; 523 }; 524 525 snoc: interconnect@580000 { 526 compatible = "qcom,msm8953-snoc"; 527 reg = <0x00580000 0x16080>; 528 529 #interconnect-cells = <2>; 530 531 snoc_mm: interconnect-snoc { 532 compatible = "qcom,msm8953-snoc-mm"; 533 534 #interconnect-cells = <2>; 535 }; 536 }; 537 538 tlmm: pinctrl@1000000 { 539 compatible = "qcom,msm8953-pinctrl"; 540 reg = <0x01000000 0x300000>; 541 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 542 gpio-controller; 543 gpio-ranges = <&tlmm 0 0 142>; 544 #gpio-cells = <2>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 548 uart_console_active: uart-console-active-state { 549 pins = "gpio4", "gpio5"; 550 function = "blsp_uart2"; 551 drive-strength = <2>; 552 bias-disable; 553 }; 554 555 uart_console_sleep: uart-console-sleep-state { 556 pins = "gpio4", "gpio5"; 557 function = "blsp_uart2"; 558 drive-strength = <2>; 559 bias-pull-down; 560 }; 561 562 sdc1_clk_on: sdc1-clk-on-state { 563 pins = "sdc1_clk"; 564 bias-disable; 565 drive-strength = <16>; 566 }; 567 568 sdc1_clk_off: sdc1-clk-off-state { 569 pins = "sdc1_clk"; 570 bias-disable; 571 drive-strength = <2>; 572 }; 573 574 sdc1_cmd_on: sdc1-cmd-on-state { 575 pins = "sdc1_cmd"; 576 bias-disable; 577 drive-strength = <10>; 578 }; 579 580 sdc1_cmd_off: sdc1-cmd-off-state { 581 pins = "sdc1_cmd"; 582 bias-disable; 583 drive-strength = <2>; 584 }; 585 586 sdc1_data_on: sdc1-data-on-state { 587 pins = "sdc1_data"; 588 bias-pull-up; 589 drive-strength = <10>; 590 }; 591 592 sdc1_data_off: sdc1-data-off-state { 593 pins = "sdc1_data"; 594 bias-pull-up; 595 drive-strength = <2>; 596 }; 597 598 sdc1_rclk_on: sdc1-rclk-on-state { 599 pins = "sdc1_rclk"; 600 bias-pull-down; 601 }; 602 603 sdc1_rclk_off: sdc1-rclk-off-state { 604 pins = "sdc1_rclk"; 605 bias-pull-down; 606 }; 607 608 sdc2_clk_on: sdc2-clk-on-state { 609 pins = "sdc2_clk"; 610 drive-strength = <16>; 611 bias-disable; 612 }; 613 614 sdc2_clk_off: sdc2-clk-off-state { 615 pins = "sdc2_clk"; 616 bias-disable; 617 drive-strength = <2>; 618 }; 619 620 sdc2_cmd_on: sdc2-cmd-on-state { 621 pins = "sdc2_cmd"; 622 bias-pull-up; 623 drive-strength = <10>; 624 }; 625 626 sdc2_cmd_off: sdc2-cmd-off-state { 627 pins = "sdc2_cmd"; 628 bias-pull-up; 629 drive-strength = <2>; 630 }; 631 632 sdc2_data_on: sdc2-data-on-state { 633 pins = "sdc2_data"; 634 bias-pull-up; 635 drive-strength = <10>; 636 }; 637 638 sdc2_data_off: sdc2-data-off-state { 639 pins = "sdc2_data"; 640 bias-pull-up; 641 drive-strength = <2>; 642 }; 643 644 sdc2_cd_on: cd-on-state { 645 pins = "gpio133"; 646 function = "gpio"; 647 drive-strength = <2>; 648 bias-pull-up; 649 }; 650 651 sdc2_cd_off: cd-off-state { 652 pins = "gpio133"; 653 function = "gpio"; 654 drive-strength = <2>; 655 bias-disable; 656 }; 657 658 gpio_key_default: gpio-key-default-state { 659 pins = "gpio85"; 660 function = "gpio"; 661 drive-strength = <2>; 662 bias-pull-up; 663 }; 664 665 i2c_1_default: i2c-1-default-state { 666 pins = "gpio2", "gpio3"; 667 function = "blsp_i2c1"; 668 drive-strength = <2>; 669 bias-disable; 670 }; 671 672 i2c_1_sleep: i2c-1-sleep-state { 673 pins = "gpio2", "gpio3"; 674 function = "gpio"; 675 drive-strength = <2>; 676 bias-disable; 677 }; 678 679 i2c_2_default: i2c-2-default-state { 680 pins = "gpio6", "gpio7"; 681 function = "blsp_i2c2"; 682 drive-strength = <2>; 683 bias-disable; 684 }; 685 686 i2c_2_sleep: i2c-2-sleep-state { 687 pins = "gpio6", "gpio7"; 688 function = "gpio"; 689 drive-strength = <2>; 690 bias-disable; 691 }; 692 693 i2c_3_default: i2c-3-default-state { 694 pins = "gpio10", "gpio11"; 695 function = "blsp_i2c3"; 696 drive-strength = <2>; 697 bias-disable; 698 }; 699 700 i2c_3_sleep: i2c-3-sleep-state { 701 pins = "gpio10", "gpio11"; 702 function = "gpio"; 703 drive-strength = <2>; 704 bias-disable; 705 }; 706 707 i2c_4_default: i2c-4-default-state { 708 pins = "gpio14", "gpio15"; 709 function = "blsp_i2c4"; 710 drive-strength = <2>; 711 bias-disable; 712 }; 713 714 i2c_4_sleep: i2c-4-sleep-state { 715 pins = "gpio14", "gpio15"; 716 function = "gpio"; 717 drive-strength = <2>; 718 bias-disable; 719 }; 720 721 i2c_5_default: i2c-5-default-state { 722 pins = "gpio18", "gpio19"; 723 function = "blsp_i2c5"; 724 drive-strength = <2>; 725 bias-disable; 726 }; 727 728 i2c_5_sleep: i2c-5-sleep-state { 729 pins = "gpio18", "gpio19"; 730 function = "gpio"; 731 drive-strength = <2>; 732 bias-disable; 733 }; 734 735 i2c_6_default: i2c-6-default-state { 736 pins = "gpio22", "gpio23"; 737 function = "blsp_i2c6"; 738 drive-strength = <2>; 739 bias-disable; 740 }; 741 742 i2c_6_sleep: i2c-6-sleep-state { 743 pins = "gpio22", "gpio23"; 744 function = "gpio"; 745 drive-strength = <2>; 746 bias-disable; 747 }; 748 749 i2c_7_default: i2c-7-default-state { 750 pins = "gpio135", "gpio136"; 751 function = "blsp_i2c7"; 752 drive-strength = <2>; 753 bias-disable; 754 }; 755 756 i2c_7_sleep: i2c-7-sleep-state { 757 pins = "gpio135", "gpio136"; 758 function = "gpio"; 759 drive-strength = <2>; 760 bias-disable; 761 }; 762 763 i2c_8_default: i2c-8-default-state { 764 pins = "gpio98", "gpio99"; 765 function = "blsp_i2c8"; 766 drive-strength = <2>; 767 bias-disable; 768 }; 769 770 i2c_8_sleep: i2c-8-sleep-state { 771 pins = "gpio98", "gpio99"; 772 function = "gpio"; 773 drive-strength = <2>; 774 bias-disable; 775 }; 776 777 spi_3_default: spi-3-default-state { 778 pins = "gpio10", "gpio11"; 779 function = "blsp_spi3"; 780 drive-strength = <2>; 781 bias-disable; 782 }; 783 784 spi_3_sleep: spi-3-sleep-state { 785 pins = "gpio10", "gpio11"; 786 function = "gpio"; 787 drive-strength = <2>; 788 bias-disable; 789 }; 790 791 spi_5_default: spi-5-default-state { 792 pins = "gpio18", "gpio19"; 793 function = "blsp_spi5"; 794 drive-strength = <2>; 795 bias-disable; 796 }; 797 798 spi_5_sleep: spi-5-sleep-state { 799 pins = "gpio18", "gpio19"; 800 function = "gpio"; 801 drive-strength = <2>; 802 bias-disable; 803 }; 804 805 spi_6_default: spi-6-default-state { 806 pins = "gpio22", "gpio23"; 807 function = "blsp_spi6"; 808 drive-strength = <2>; 809 bias-disable; 810 }; 811 812 spi_6_sleep: spi-6-sleep-state { 813 pins = "gpio22", "gpio23"; 814 function = "gpio"; 815 drive-strength = <2>; 816 bias-disable; 817 }; 818 819 uart_5_default: uart-5-default-state { 820 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 821 function = "blsp_uart5"; 822 drive-strength = <16>; 823 bias-disable; 824 }; 825 826 uart_5_sleep: uart-5-sleep-state { 827 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 828 function = "gpio"; 829 drive-strength = <2>; 830 bias-disable; 831 }; 832 833 wcnss_pin_a: wcnss-active-state { 834 835 wcss-wlan2-pins { 836 pins = "gpio76"; 837 function = "wcss_wlan2"; 838 drive-strength = <6>; 839 bias-pull-up; 840 }; 841 842 wcss-wlan1-pins { 843 pins = "gpio77"; 844 function = "wcss_wlan1"; 845 drive-strength = <6>; 846 bias-pull-up; 847 }; 848 849 wcss-wlan0-pins { 850 pins = "gpio78"; 851 function = "wcss_wlan0"; 852 drive-strength = <6>; 853 bias-pull-up; 854 }; 855 856 wcss-wlan-pins { 857 pins = "gpio79", "gpio80"; 858 function = "wcss_wlan"; 859 drive-strength = <6>; 860 bias-pull-up; 861 }; 862 }; 863 }; 864 865 gcc: clock-controller@1800000 { 866 compatible = "qcom,gcc-msm8953"; 867 reg = <0x01800000 0x80000>; 868 #clock-cells = <1>; 869 #reset-cells = <1>; 870 #power-domain-cells = <1>; 871 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 872 <&sleep_clk>, 873 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 874 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 875 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 876 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; 877 clock-names = "xo", 878 "sleep", 879 "dsi0pll", 880 "dsi0pllbyte", 881 "dsi1pll", 882 "dsi1pllbyte"; 883 }; 884 885 tcsr_mutex: hwlock@1905000 { 886 compatible = "qcom,tcsr-mutex"; 887 reg = <0x01905000 0x20000>; 888 #hwlock-cells = <1>; 889 }; 890 891 tcsr: syscon@1937000 { 892 compatible = "qcom,tcsr-msm8953", "syscon"; 893 reg = <0x01937000 0x30000>; 894 }; 895 896 tcsr_phy_clk_scheme_sel: syscon@193f044 { 897 compatible = "qcom,tcsr-msm8953", "syscon"; 898 reg = <0x0193f044 0x4>; 899 }; 900 901 mdss: display-subsystem@1a00000 { 902 compatible = "qcom,mdss"; 903 904 reg = <0x01a00000 0x1000>, 905 <0x01ab0000 0x1040>; 906 reg-names = "mdss_phys", 907 "vbif_phys"; 908 909 power-domains = <&gcc MDSS_GDSC>; 910 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 911 912 interrupt-controller; 913 #interrupt-cells = <1>; 914 915 interconnects = <&snoc_mm MAS_MDP RPM_ALWAYS_TAG 916 &bimc SLV_EBI RPM_ALWAYS_TAG>, 917 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 918 &pcnoc SLV_DISP_SS_CFG RPM_ACTIVE_TAG>; 919 interconnect-names = "mdp0-mem", 920 "cpu-cfg"; 921 922 clocks = <&gcc GCC_MDSS_AHB_CLK>, 923 <&gcc GCC_MDSS_AXI_CLK>, 924 <&gcc GCC_MDSS_VSYNC_CLK>, 925 <&gcc GCC_MDSS_MDP_CLK>; 926 clock-names = "iface", 927 "bus", 928 "vsync", 929 "core"; 930 931 resets = <&gcc GCC_MDSS_BCR>; 932 933 #address-cells = <1>; 934 #size-cells = <1>; 935 ranges; 936 937 status = "disabled"; 938 939 mdp: display-controller@1a01000 { 940 compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; 941 reg = <0x01a01000 0x89000>; 942 reg-names = "mdp_phys"; 943 944 interrupt-parent = <&mdss>; 945 interrupts = <0>; 946 947 power-domains = <&gcc MDSS_GDSC>; 948 949 clocks = <&gcc GCC_MDSS_AHB_CLK>, 950 <&gcc GCC_MDSS_AXI_CLK>, 951 <&gcc GCC_MDSS_MDP_CLK>, 952 <&gcc GCC_MDSS_VSYNC_CLK>; 953 clock-names = "iface", 954 "bus", 955 "core", 956 "vsync"; 957 958 iommus = <&apps_iommu 0x15>; 959 960 ports { 961 #address-cells = <1>; 962 #size-cells = <0>; 963 964 port@0 { 965 reg = <0>; 966 mdp5_intf1_out: endpoint { 967 remote-endpoint = <&mdss_dsi0_in>; 968 }; 969 }; 970 971 port@1 { 972 reg = <1>; 973 mdp5_intf2_out: endpoint { 974 remote-endpoint = <&mdss_dsi1_in>; 975 }; 976 }; 977 }; 978 }; 979 980 mdss_dsi0: dsi@1a94000 { 981 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 982 reg = <0x01a94000 0x400>; 983 reg-names = "dsi_ctrl"; 984 985 interrupt-parent = <&mdss>; 986 interrupts = <4>; 987 988 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 989 <&gcc PCLK0_CLK_SRC>; 990 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 991 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 992 993 clocks = <&gcc GCC_MDSS_MDP_CLK>, 994 <&gcc GCC_MDSS_AHB_CLK>, 995 <&gcc GCC_MDSS_AXI_CLK>, 996 <&gcc GCC_MDSS_BYTE0_CLK>, 997 <&gcc GCC_MDSS_PCLK0_CLK>, 998 <&gcc GCC_MDSS_ESC0_CLK>; 999 clock-names = "mdp_core", 1000 "iface", 1001 "bus", 1002 "byte", 1003 "pixel", 1004 "core"; 1005 1006 phys = <&mdss_dsi0_phy>; 1007 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 1011 status = "disabled"; 1012 1013 ports { 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 1017 port@0 { 1018 reg = <0>; 1019 mdss_dsi0_in: endpoint { 1020 remote-endpoint = <&mdp5_intf1_out>; 1021 }; 1022 }; 1023 1024 port@1 { 1025 reg = <1>; 1026 mdss_dsi0_out: endpoint { 1027 }; 1028 }; 1029 }; 1030 }; 1031 1032 mdss_dsi0_phy: phy@1a94400 { 1033 compatible = "qcom,dsi-phy-14nm-8953"; 1034 reg = <0x01a94400 0x100>, 1035 <0x01a94500 0x300>, 1036 <0x01a94800 0x188>; 1037 reg-names = "dsi_phy", 1038 "dsi_phy_lane", 1039 "dsi_pll"; 1040 1041 #clock-cells = <1>; 1042 #phy-cells = <0>; 1043 1044 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1045 clock-names = "iface", "ref"; 1046 1047 status = "disabled"; 1048 }; 1049 1050 mdss_dsi1: dsi@1a96000 { 1051 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1052 reg = <0x01a96000 0x400>; 1053 reg-names = "dsi_ctrl"; 1054 1055 interrupt-parent = <&mdss>; 1056 interrupts = <5>; 1057 1058 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 1059 <&gcc PCLK1_CLK_SRC>; 1060 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1061 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 1062 1063 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1064 <&gcc GCC_MDSS_AHB_CLK>, 1065 <&gcc GCC_MDSS_AXI_CLK>, 1066 <&gcc GCC_MDSS_BYTE1_CLK>, 1067 <&gcc GCC_MDSS_PCLK1_CLK>, 1068 <&gcc GCC_MDSS_ESC1_CLK>; 1069 clock-names = "mdp_core", 1070 "iface", 1071 "bus", 1072 "byte", 1073 "pixel", 1074 "core"; 1075 1076 phys = <&mdss_dsi1_phy>; 1077 1078 status = "disabled"; 1079 1080 ports { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 port@0 { 1085 reg = <0>; 1086 mdss_dsi1_in: endpoint { 1087 remote-endpoint = <&mdp5_intf2_out>; 1088 }; 1089 }; 1090 1091 port@1 { 1092 reg = <1>; 1093 mdss_dsi1_out: endpoint { 1094 }; 1095 }; 1096 }; 1097 }; 1098 1099 mdss_dsi1_phy: phy@1a96400 { 1100 compatible = "qcom,dsi-phy-14nm-8953"; 1101 reg = <0x01a96400 0x100>, 1102 <0x01a96500 0x300>, 1103 <0x01a96800 0x188>; 1104 reg-names = "dsi_phy", 1105 "dsi_phy_lane", 1106 "dsi_pll"; 1107 1108 #clock-cells = <1>; 1109 #phy-cells = <0>; 1110 1111 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1112 clock-names = "iface", "ref"; 1113 1114 status = "disabled"; 1115 }; 1116 }; 1117 1118 gpu: gpu@1c00000 { 1119 compatible = "qcom,adreno-506.0", "qcom,adreno"; 1120 reg = <0x01c00000 0x40000>; 1121 reg-names = "kgsl_3d0_reg_memory"; 1122 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1123 1124 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1125 <&gcc GCC_OXILI_AHB_CLK>, 1126 <&gcc GCC_BIMC_GFX_CLK>, 1127 <&gcc GCC_BIMC_GPU_CLK>, 1128 <&gcc GCC_OXILI_TIMER_CLK>, 1129 <&gcc GCC_OXILI_AON_CLK>; 1130 clock-names = "core", 1131 "iface", 1132 "mem_iface", 1133 "alt_mem_iface", 1134 "rbbmtimer", 1135 "alwayson"; 1136 power-domains = <&gcc OXILI_GX_GDSC>; 1137 1138 interconnects = <&bimc MAS_OXILI RPM_ALWAYS_TAG 1139 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1140 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1141 &pcnoc SLV_GPU_CFG RPM_ACTIVE_TAG>; 1142 1143 iommus = <&gpu_iommu 0>; 1144 operating-points-v2 = <&gpu_opp_table>; 1145 1146 #cooling-cells = <2>; 1147 1148 status = "disabled"; 1149 1150 zap-shader { 1151 memory-region = <&zap_shader_region>; 1152 }; 1153 1154 gpu_opp_table: opp-table { 1155 compatible = "operating-points-v2"; 1156 1157 opp-19200000 { 1158 opp-hz = /bits/ 64 <19200000>; 1159 opp-supported-hw = <0xff>; 1160 required-opps = <&rpmpd_opp_min_svs>; 1161 }; 1162 1163 opp-133300000 { 1164 opp-hz = /bits/ 64 <133300000>; 1165 opp-supported-hw = <0xff>; 1166 required-opps = <&rpmpd_opp_min_svs>; 1167 }; 1168 1169 opp-216000000 { 1170 opp-hz = /bits/ 64 <216000000>; 1171 opp-supported-hw = <0xff>; 1172 required-opps = <&rpmpd_opp_low_svs>; 1173 }; 1174 1175 opp-320000000 { 1176 opp-hz = /bits/ 64 <320000000>; 1177 opp-supported-hw = <0xff>; 1178 required-opps = <&rpmpd_opp_svs>; 1179 }; 1180 1181 opp-400000000 { 1182 opp-hz = /bits/ 64 <400000000>; 1183 opp-supported-hw = <0xff>; 1184 required-opps = <&rpmpd_opp_svs_plus>; 1185 }; 1186 1187 opp-510000000 { 1188 opp-hz = /bits/ 64 <510000000>; 1189 opp-supported-hw = <0xff>; 1190 required-opps = <&rpmpd_opp_nom>; 1191 }; 1192 1193 opp-560000000 { 1194 opp-hz = /bits/ 64 <560000000>; 1195 opp-supported-hw = <0xff>; 1196 required-opps = <&rpmpd_opp_nom_plus>; 1197 }; 1198 1199 /* 1200 * This opp is only available on msm8953 and 1201 * sdm632, the max for sdm450 is 600MHz. 1202 */ 1203 opp-650000000 { 1204 opp-hz = /bits/ 64 <650000000>; 1205 opp-supported-hw = <0xff>; 1206 required-opps = <&rpmpd_opp_turbo>; 1207 }; 1208 }; 1209 }; 1210 1211 gpu_iommu: iommu@1c48000 { 1212 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2"; 1213 ranges = <0 0x01c48000 0x8000>; 1214 1215 clocks = <&gcc GCC_OXILI_AHB_CLK>, 1216 <&gcc GCC_BIMC_GFX_CLK>; 1217 clock-names = "iface", "bus"; 1218 1219 power-domains = <&gcc OXILI_CX_GDSC>; 1220 1221 qcom,iommu-secure-id = <18>; 1222 1223 #address-cells = <1>; 1224 #iommu-cells = <1>; 1225 #size-cells = <1>; 1226 1227 /* gfx3d_user */ 1228 iommu-ctx@0 { 1229 compatible = "qcom,msm-iommu-v2-ns"; 1230 reg = <0x0000 0x1000>; 1231 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1232 }; 1233 1234 /* gfx3d_secure */ 1235 iommu-ctx@2000 { 1236 compatible = "qcom,msm-iommu-v2-sec"; 1237 reg = <0x2000 0x1000>; 1238 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1239 }; 1240 }; 1241 1242 apps_iommu: iommu@1e20000 { 1243 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; 1244 ranges = <0 0x01e20000 0x20000>; 1245 1246 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1247 <&gcc GCC_APSS_TCU_ASYNC_CLK>; 1248 clock-names = "iface", "bus"; 1249 1250 qcom,iommu-secure-id = <17>; 1251 1252 #address-cells = <1>; 1253 #iommu-cells = <1>; 1254 #size-cells = <1>; 1255 1256 /* VFE */ 1257 iommu-ctx@14000 { 1258 compatible = "qcom,msm-iommu-v1-ns"; 1259 reg = <0x14000 0x1000>; 1260 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1261 }; 1262 1263 /* MDP_0 */ 1264 iommu-ctx@15000 { 1265 compatible = "qcom,msm-iommu-v1-ns"; 1266 reg = <0x15000 0x1000>; 1267 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1268 }; 1269 1270 /* VENUS_NS */ 1271 iommu-ctx@16000 { 1272 compatible = "qcom,msm-iommu-v1-ns"; 1273 reg = <0x16000 0x1000>; 1274 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1275 }; 1276 }; 1277 1278 spmi_bus: spmi@200f000 { 1279 compatible = "qcom,spmi-pmic-arb"; 1280 reg = <0x0200f000 0x1000>, 1281 <0x02400000 0x800000>, 1282 <0x02c00000 0x800000>, 1283 <0x03800000 0x200000>, 1284 <0x0200a000 0x2100>; 1285 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1286 interrupt-names = "periph_irq"; 1287 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1288 qcom,ee = <0>; 1289 qcom,channel = <0>; 1290 interrupt-controller; 1291 1292 #interrupt-cells = <4>; 1293 #address-cells = <2>; 1294 #size-cells = <0>; 1295 }; 1296 1297 mpss: remoteproc@4080000 { 1298 compatible = "qcom,msm8953-mss-pil"; 1299 reg = <0x04080000 0x100>, 1300 <0x04020000 0x040>; 1301 reg-names = "qdsp6", "rmb"; 1302 1303 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1304 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1305 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1306 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1307 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>; 1308 interrupt-names = "wdog", "fatal", "ready", 1309 "handover", "stop-ack"; 1310 1311 power-domains = <&rpmpd MSM8953_VDDCX>, 1312 <&rpmpd MSM8953_VDDMX>, 1313 <&rpmpd MSM8953_VDDMD>; 1314 power-domain-names = "cx", "mx","mss"; 1315 1316 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1317 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1318 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1319 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1320 clock-names = "iface", "bus", "mem", "xo"; 1321 1322 qcom,smem-states = <&smp2p_modem_out 0>; 1323 qcom,smem-state-names = "stop"; 1324 1325 resets = <&gcc GCC_MSS_BCR>; 1326 reset-names = "mss_restart"; 1327 1328 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1329 1330 status = "disabled"; 1331 1332 mba { 1333 memory-region = <&mba_mem>; 1334 }; 1335 1336 mpss { 1337 memory-region = <&mpss_mem>; 1338 }; 1339 1340 smd-edge { 1341 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1342 1343 qcom,smd-edge = <0>; 1344 mboxes = <&apcs 12>; 1345 qcom,remote-pid = <1>; 1346 1347 label = "modem"; 1348 }; 1349 }; 1350 1351 usb3: usb@70f8800 { 1352 compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; 1353 reg = <0x070f8800 0x400>; 1354 #address-cells = <1>; 1355 #size-cells = <1>; 1356 ranges; 1357 1358 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1361 interrupt-names = "pwr_event", 1362 "qusb2_phy", 1363 "ss_phy_irq"; 1364 1365 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 1366 <&gcc GCC_USB30_MASTER_CLK>, 1367 <&gcc GCC_PCNOC_USB3_AXI_CLK>, 1368 <&gcc GCC_USB30_SLEEP_CLK>, 1369 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1370 clock-names = "cfg_noc", 1371 "core", 1372 "iface", 1373 "sleep", 1374 "mock_utmi"; 1375 1376 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1377 <&gcc GCC_USB30_MASTER_CLK>; 1378 assigned-clock-rates = <19200000>, <133330000>; 1379 1380 interconnects = <&pcnoc MAS_USB3 RPM_ALWAYS_TAG 1381 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1382 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1383 &pcnoc SLV_USB3 RPM_ACTIVE_TAG>; 1384 interconnect-names = "usb-ddr", 1385 "apps-usb"; 1386 1387 power-domains = <&gcc USB30_GDSC>; 1388 1389 qcom,select-utmi-as-pipe-clk; 1390 1391 status = "disabled"; 1392 1393 usb3_dwc3: usb@7000000 { 1394 compatible = "snps,dwc3"; 1395 reg = <0x07000000 0xcc00>; 1396 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1397 phys = <&hsusb_phy>; 1398 phy-names = "usb2-phy"; 1399 1400 snps,usb2-gadget-lpm-disable; 1401 snps,dis-u1-entry-quirk; 1402 snps,dis-u2-entry-quirk; 1403 snps,is-utmi-l1-suspend; 1404 snps,hird-threshold = /bits/ 8 <0x00>; 1405 1406 maximum-speed = "high-speed"; 1407 1408 usb-role-switch; 1409 1410 ports { 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 1414 port@0 { 1415 reg = <0>; 1416 1417 usb_dwc3_hs: endpoint { 1418 }; 1419 }; 1420 }; 1421 }; 1422 }; 1423 1424 sdhc_1: mmc@7824900 { 1425 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1426 1427 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1428 reg-names = "hc", "core"; 1429 1430 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1432 interrupt-names = "hc_irq", "pwr_irq"; 1433 1434 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1435 <&gcc GCC_SDCC1_APPS_CLK>, 1436 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1437 clock-names = "iface", "core", "xo"; 1438 1439 interconnects = <&pcnoc MAS_SDCC_1 RPM_ALWAYS_TAG 1440 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1441 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1442 &pcnoc SLV_SDCC_1 RPM_ACTIVE_TAG>; 1443 interconnect-names = "sdhc-ddr", 1444 "cpu-sdhc"; 1445 1446 power-domains = <&rpmpd MSM8953_VDDCX>; 1447 operating-points-v2 = <&sdhc1_opp_table>; 1448 1449 pinctrl-names = "default", "sleep"; 1450 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 1451 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 1452 1453 mmc-hs400-1_8v; 1454 mmc-hs200-1_8v; 1455 mmc-ddr-1_8v; 1456 bus-width = <8>; 1457 non-removable; 1458 1459 status = "disabled"; 1460 1461 sdhc1_opp_table: opp-table-sdhc1 { 1462 compatible = "operating-points-v2"; 1463 1464 opp-25000000 { 1465 opp-hz = /bits/ 64 <25000000>; 1466 opp-peak-kBps = <200000>, <100000>; 1467 opp-avg-kBps = <65360>, <32768>; 1468 required-opps = <&rpmpd_opp_low_svs>; 1469 }; 1470 1471 opp-50000000 { 1472 opp-hz = /bits/ 64 <50000000>; 1473 opp-peak-kBps = <400000>, <200000>; 1474 opp-avg-kBps = <130718>, <65360>; 1475 required-opps = <&rpmpd_opp_svs>; 1476 }; 1477 1478 opp-100000000 { 1479 opp-hz = /bits/ 64 <100000000>; 1480 opp-peak-kBps = <400000>, <400000>; 1481 opp-avg-kBps = <130718>, <65360>; 1482 required-opps = <&rpmpd_opp_svs>; 1483 }; 1484 1485 opp-192000000 { 1486 opp-hz = /bits/ 64 <192000000>; 1487 opp-peak-kBps = <800000>, <600000>; 1488 opp-avg-kBps = <261438>, <130718>; 1489 required-opps = <&rpmpd_opp_nom>; 1490 }; 1491 1492 opp-384000000 { 1493 opp-hz = /bits/ 64 <384000000>; 1494 opp-peak-kBps = <800000>, <800000>; 1495 opp-avg-kBps = <261438>, <300000>; 1496 required-opps = <&rpmpd_opp_nom>; 1497 }; 1498 }; 1499 }; 1500 1501 sdhc_2: mmc@7864900 { 1502 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1503 1504 reg = <0x07864900 0x500>, <0x07864000 0x800>; 1505 reg-names = "hc", "core"; 1506 1507 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1509 interrupt-names = "hc_irq", "pwr_irq"; 1510 1511 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1512 <&gcc GCC_SDCC2_APPS_CLK>, 1513 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1514 clock-names = "iface", "core", "xo"; 1515 1516 interconnects = <&pcnoc MAS_SDCC_2 RPM_ALWAYS_TAG 1517 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1518 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1519 &pcnoc SLV_SDCC_2 RPM_ACTIVE_TAG>; 1520 interconnect-names = "sdhc-ddr", 1521 "cpu-sdhc"; 1522 1523 power-domains = <&rpmpd MSM8953_VDDCX>; 1524 operating-points-v2 = <&sdhc2_opp_table>; 1525 1526 pinctrl-names = "default", "sleep"; 1527 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 1528 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 1529 1530 bus-width = <4>; 1531 1532 status = "disabled"; 1533 1534 sdhc2_opp_table: opp-table-sdhc2 { 1535 compatible = "operating-points-v2"; 1536 1537 opp-25000000 { 1538 opp-hz = /bits/ 64 <25000000>; 1539 opp-peak-kBps = <200000>, <100000>; 1540 opp-avg-kBps = <65360>, <32768>; 1541 required-opps = <&rpmpd_opp_low_svs>; 1542 }; 1543 1544 opp-50000000 { 1545 opp-hz = /bits/ 64 <50000000>; 1546 opp-peak-kBps = <400000>, <400000>; 1547 opp-avg-kBps = <130718>, <65360>; 1548 required-opps = <&rpmpd_opp_svs>; 1549 }; 1550 1551 opp-100000000 { 1552 opp-hz = /bits/ 64 <100000000>; 1553 opp-peak-kBps = <800000>, <400000>; 1554 opp-avg-kBps = <130718>, <130718>; 1555 required-opps = <&rpmpd_opp_svs>; 1556 }; 1557 1558 opp-177770000 { 1559 opp-hz = /bits/ 64 <177770000>; 1560 opp-peak-kBps = <600000>, <600000>; 1561 opp-avg-kBps = <261438>, <130718>; 1562 required-opps = <&rpmpd_opp_nom>; 1563 }; 1564 1565 opp-200000000 { 1566 opp-hz = /bits/ 64 <200000000>; 1567 opp-peak-kBps = <800000>, <800000>; 1568 opp-avg-kBps = <261438>, <130718>; 1569 required-opps = <&rpmpd_opp_nom>; 1570 }; 1571 }; 1572 }; 1573 1574 blsp1_dma: dma-controller@7884000 { 1575 compatible = "qcom,bam-v1.7.0"; 1576 reg = <0x07884000 0x1f000>; 1577 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1578 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1579 clock-names = "bam_clk"; 1580 num-channels = <12>; 1581 #dma-cells = <1>; 1582 qcom,ee = <0>; 1583 qcom,num-ees = <4>; 1584 qcom,controlled-remotely; 1585 }; 1586 1587 uart_0: serial@78af000 { 1588 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1589 reg = <0x078af000 0x200>; 1590 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1591 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1592 <&gcc GCC_BLSP1_AHB_CLK>; 1593 clock-names = "core", "iface"; 1594 1595 status = "disabled"; 1596 }; 1597 1598 i2c_1: i2c@78b5000 { 1599 compatible = "qcom,i2c-qup-v2.2.1"; 1600 reg = <0x078b5000 0x600>; 1601 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1602 clock-names = "core", "iface"; 1603 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1604 <&gcc GCC_BLSP1_AHB_CLK>; 1605 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1606 dma-names = "tx", "rx"; 1607 1608 pinctrl-names = "default", "sleep"; 1609 pinctrl-0 = <&i2c_1_default>; 1610 pinctrl-1 = <&i2c_1_sleep>; 1611 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 1615 status = "disabled"; 1616 }; 1617 1618 i2c_2: i2c@78b6000 { 1619 compatible = "qcom,i2c-qup-v2.2.1"; 1620 reg = <0x078b6000 0x600>; 1621 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1622 clock-names = "core", "iface"; 1623 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1624 <&gcc GCC_BLSP1_AHB_CLK>; 1625 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1626 dma-names = "tx", "rx"; 1627 1628 pinctrl-names = "default", "sleep"; 1629 pinctrl-0 = <&i2c_2_default>; 1630 pinctrl-1 = <&i2c_2_sleep>; 1631 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 1635 status = "disabled"; 1636 }; 1637 1638 i2c_3: i2c@78b7000 { 1639 compatible = "qcom,i2c-qup-v2.2.1"; 1640 reg = <0x078b7000 0x600>; 1641 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1642 clock-names = "core", "iface"; 1643 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1644 <&gcc GCC_BLSP1_AHB_CLK>; 1645 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1646 dma-names = "tx", "rx"; 1647 1648 pinctrl-names = "default", "sleep"; 1649 pinctrl-0 = <&i2c_3_default>; 1650 pinctrl-1 = <&i2c_3_sleep>; 1651 1652 #address-cells = <1>; 1653 #size-cells = <0>; 1654 1655 status = "disabled"; 1656 }; 1657 1658 spi_3: spi@78b7000 { 1659 compatible = "qcom,spi-qup-v2.2.1"; 1660 reg = <0x078b7000 0x600>; 1661 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1662 clock-names = "core", "iface"; 1663 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1664 <&gcc GCC_BLSP1_AHB_CLK>; 1665 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1666 dma-names = "tx", "rx"; 1667 1668 pinctrl-names = "default", "sleep"; 1669 pinctrl-0 = <&spi_3_default>; 1670 pinctrl-1 = <&spi_3_sleep>; 1671 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 1675 status = "disabled"; 1676 }; 1677 1678 i2c_4: i2c@78b8000 { 1679 compatible = "qcom,i2c-qup-v2.2.1"; 1680 reg = <0x078b8000 0x600>; 1681 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1682 clock-names = "core", "iface"; 1683 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1684 <&gcc GCC_BLSP1_AHB_CLK>; 1685 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1686 dma-names = "tx", "rx"; 1687 1688 pinctrl-names = "default", "sleep"; 1689 pinctrl-0 = <&i2c_4_default>; 1690 pinctrl-1 = <&i2c_4_sleep>; 1691 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 1695 status = "disabled"; 1696 }; 1697 1698 blsp2_dma: dma-controller@7ac4000 { 1699 compatible = "qcom,bam-v1.7.0"; 1700 reg = <0x07ac4000 0x1f000>; 1701 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1702 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1703 clock-names = "bam_clk"; 1704 num-channels = <12>; 1705 #dma-cells = <1>; 1706 qcom,ee = <0>; 1707 qcom,num-ees = <4>; 1708 qcom,controlled-remotely; 1709 }; 1710 1711 uart_5: serial@7aef000 { 1712 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1713 reg = <0x07aef000 0x200>; 1714 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1715 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1716 <&gcc GCC_BLSP2_AHB_CLK>; 1717 clock-names = "core", 1718 "iface"; 1719 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1720 dma-names = "tx", "rx"; 1721 1722 pinctrl-0 = <&uart_5_default>; 1723 pinctrl-1 = <&uart_5_sleep>; 1724 pinctrl-names = "default", "sleep"; 1725 1726 status = "disabled"; 1727 }; 1728 1729 i2c_5: i2c@7af5000 { 1730 compatible = "qcom,i2c-qup-v2.2.1"; 1731 reg = <0x07af5000 0x600>; 1732 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1733 clock-names = "core", "iface"; 1734 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1735 <&gcc GCC_BLSP2_AHB_CLK>; 1736 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1737 dma-names = "tx", "rx"; 1738 1739 pinctrl-names = "default", "sleep"; 1740 pinctrl-0 = <&i2c_5_default>; 1741 pinctrl-1 = <&i2c_5_sleep>; 1742 1743 #address-cells = <1>; 1744 #size-cells = <0>; 1745 1746 status = "disabled"; 1747 }; 1748 1749 spi_5: spi@7af5000 { 1750 compatible = "qcom,spi-qup-v2.2.1"; 1751 reg = <0x07af5000 0x600>; 1752 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1753 clock-names = "core", "iface"; 1754 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1755 <&gcc GCC_BLSP2_AHB_CLK>; 1756 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1757 dma-names = "tx", "rx"; 1758 1759 pinctrl-names = "default", "sleep"; 1760 pinctrl-0 = <&spi_5_default>; 1761 pinctrl-1 = <&spi_5_sleep>; 1762 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 1766 status = "disabled"; 1767 }; 1768 1769 i2c_6: i2c@7af6000 { 1770 compatible = "qcom,i2c-qup-v2.2.1"; 1771 reg = <0x07af6000 0x600>; 1772 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1773 clock-names = "core", "iface"; 1774 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1775 <&gcc GCC_BLSP2_AHB_CLK>; 1776 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1777 dma-names = "tx", "rx"; 1778 1779 pinctrl-names = "default", "sleep"; 1780 pinctrl-0 = <&i2c_6_default>; 1781 pinctrl-1 = <&i2c_6_sleep>; 1782 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 1786 status = "disabled"; 1787 }; 1788 1789 spi_6: spi@7af6000 { 1790 compatible = "qcom,spi-qup-v2.2.1"; 1791 reg = <0x07af6000 0x600>; 1792 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1793 clock-names = "core", "iface"; 1794 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1795 <&gcc GCC_BLSP2_AHB_CLK>; 1796 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1797 dma-names = "tx", "rx"; 1798 1799 pinctrl-names = "default", "sleep"; 1800 pinctrl-0 = <&spi_6_default>; 1801 pinctrl-1 = <&spi_6_sleep>; 1802 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 1806 status = "disabled"; 1807 }; 1808 1809 i2c_7: i2c@7af7000 { 1810 compatible = "qcom,i2c-qup-v2.2.1"; 1811 reg = <0x07af7000 0x600>; 1812 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1813 clock-names = "core", "iface"; 1814 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1815 <&gcc GCC_BLSP2_AHB_CLK>; 1816 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1817 dma-names = "tx", "rx"; 1818 1819 pinctrl-names = "default", "sleep"; 1820 pinctrl-0 = <&i2c_7_default>; 1821 pinctrl-1 = <&i2c_7_sleep>; 1822 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 1826 status = "disabled"; 1827 }; 1828 1829 i2c_8: i2c@7af8000 { 1830 compatible = "qcom,i2c-qup-v2.2.1"; 1831 reg = <0x07af8000 0x600>; 1832 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1833 clock-names = "core", "iface"; 1834 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1835 <&gcc GCC_BLSP2_AHB_CLK>; 1836 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1837 dma-names = "tx", "rx"; 1838 1839 pinctrl-names = "default", "sleep"; 1840 pinctrl-0 = <&i2c_8_default>; 1841 pinctrl-1 = <&i2c_8_sleep>; 1842 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 1846 status = "disabled"; 1847 }; 1848 1849 wcnss: remoteproc@a204000 { 1850 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1851 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1852 reg-names = "ccu", "dxe", "pmu"; 1853 1854 memory-region = <&wcnss_fw_mem>; 1855 1856 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1857 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>, 1858 <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>, 1859 <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>, 1860 <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>; 1861 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1862 1863 power-domains = <&rpmpd MSM8953_VDDCX>, 1864 <&rpmpd MSM8953_VDDMX>; 1865 power-domain-names = "cx", "mx"; 1866 1867 qcom,smem-states = <&smp2p_wcnss_out 0>; 1868 qcom,smem-state-names = "stop"; 1869 1870 pinctrl-names = "default"; 1871 pinctrl-0 = <&wcnss_pin_a>; 1872 1873 status = "disabled"; 1874 1875 wcnss_iris: iris { 1876 /* Separate chip, compatible is board-specific */ 1877 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1878 clock-names = "xo"; 1879 }; 1880 1881 smd-edge { 1882 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1883 1884 mboxes = <&apcs 17>; 1885 qcom,smd-edge = <6>; 1886 qcom,remote-pid = <4>; 1887 1888 label = "pronto"; 1889 1890 wcnss_ctrl: wcnss { 1891 compatible = "qcom,wcnss"; 1892 qcom,smd-channels = "WCNSS_CTRL"; 1893 1894 qcom,mmio = <&wcnss>; 1895 1896 wcnss_bt: bluetooth { 1897 compatible = "qcom,wcnss-bt"; 1898 }; 1899 1900 wcnss_wifi: wifi { 1901 compatible = "qcom,wcnss-wlan"; 1902 1903 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1905 interrupt-names = "tx", "rx"; 1906 1907 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1908 qcom,smem-state-names = "tx-enable", 1909 "tx-rings-empty"; 1910 }; 1911 }; 1912 }; 1913 }; 1914 1915 intc: interrupt-controller@b000000 { 1916 compatible = "qcom,msm-qgic2"; 1917 interrupt-controller; 1918 #interrupt-cells = <3>; 1919 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1920 }; 1921 1922 apcs: mailbox@b011000 { 1923 compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; 1924 reg = <0x0b011000 0x1000>; 1925 #mbox-cells = <1>; 1926 }; 1927 1928 timer@b120000 { 1929 compatible = "arm,armv7-timer-mem"; 1930 reg = <0x0b120000 0x1000>; 1931 #address-cells = <1>; 1932 #size-cells = <1>; 1933 ranges; 1934 1935 frame@b121000 { 1936 frame-number = <0>; 1937 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1939 reg = <0x0b121000 0x1000>, 1940 <0x0b122000 0x1000>; 1941 }; 1942 1943 frame@b123000 { 1944 frame-number = <1>; 1945 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1946 reg = <0x0b123000 0x1000>; 1947 status = "disabled"; 1948 }; 1949 1950 frame@b124000 { 1951 frame-number = <2>; 1952 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1953 reg = <0x0b124000 0x1000>; 1954 status = "disabled"; 1955 }; 1956 1957 frame@b125000 { 1958 frame-number = <3>; 1959 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1960 reg = <0x0b125000 0x1000>; 1961 status = "disabled"; 1962 }; 1963 1964 frame@b126000 { 1965 frame-number = <4>; 1966 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1967 reg = <0x0b126000 0x1000>; 1968 status = "disabled"; 1969 }; 1970 1971 frame@b127000 { 1972 frame-number = <5>; 1973 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1974 reg = <0x0b127000 0x1000>; 1975 status = "disabled"; 1976 }; 1977 1978 frame@b128000 { 1979 frame-number = <6>; 1980 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1981 reg = <0x0b128000 0x1000>; 1982 status = "disabled"; 1983 }; 1984 }; 1985 1986 lpass: remoteproc@c200000 { 1987 compatible = "qcom,msm8953-adsp-pil"; 1988 reg = <0x0c200000 0x100>; 1989 1990 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>, 1991 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1992 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1993 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1994 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1995 interrupt-names = "wdog", "fatal", "ready", 1996 "handover", "stop-ack"; 1997 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1998 clock-names = "xo"; 1999 2000 power-domains = <&rpmpd MSM8953_VDDCX>; 2001 power-domain-names = "cx"; 2002 2003 memory-region = <&adsp_fw_mem>; 2004 2005 qcom,smem-states = <&smp2p_adsp_out 0>; 2006 qcom,smem-state-names = "stop"; 2007 2008 status = "disabled"; 2009 2010 smd-edge { 2011 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 2012 2013 label = "lpass"; 2014 mboxes = <&apcs 8>; 2015 qcom,smd-edge = <1>; 2016 qcom,remote-pid = <2>; 2017 2018 apr { 2019 compatible = "qcom,apr-v2"; 2020 qcom,smd-channels = "apr_audio_svc"; 2021 qcom,domain = <APR_DOMAIN_ADSP>; 2022 #address-cells = <1>; 2023 #size-cells = <0>; 2024 2025 q6core: service@3 { 2026 reg = <APR_SVC_ADSP_CORE>; 2027 compatible = "qcom,q6core"; 2028 }; 2029 2030 q6afe: service@4 { 2031 compatible = "qcom,q6afe"; 2032 reg = <APR_SVC_AFE>; 2033 q6afedai: dais { 2034 compatible = "qcom,q6afe-dais"; 2035 #address-cells = <1>; 2036 #size-cells = <0>; 2037 #sound-dai-cells = <1>; 2038 2039 dai@16 { 2040 reg = <PRIMARY_MI2S_RX>; 2041 qcom,sd-lines = <0 1>; 2042 }; 2043 dai@20 { 2044 reg = <TERTIARY_MI2S_TX>; 2045 qcom,sd-lines = <0 1>; 2046 }; 2047 dai@127 { 2048 reg = <QUINARY_MI2S_RX>; 2049 qcom,sd-lines = <0>; 2050 }; 2051 }; 2052 2053 q6afecc: clock-controller { 2054 compatible = "qcom,q6afe-clocks"; 2055 #clock-cells = <2>; 2056 }; 2057 }; 2058 2059 q6asm: service@7 { 2060 compatible = "qcom,q6asm"; 2061 reg = <APR_SVC_ASM>; 2062 q6asmdai: dais { 2063 compatible = "qcom,q6asm-dais"; 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 #sound-dai-cells = <1>; 2067 2068 dai@0 { 2069 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 2070 direction = <Q6ASM_DAI_RX>; 2071 }; 2072 dai@1 { 2073 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 2074 direction = <Q6ASM_DAI_TX>; 2075 }; 2076 dai@2 { 2077 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 2078 direction = <Q6ASM_DAI_RX>; 2079 }; 2080 dai@3 { 2081 reg = <MSM_FRONTEND_DAI_MULTIMEDIA4>; 2082 direction = <Q6ASM_DAI_RX>; 2083 is-compress-dai; 2084 }; 2085 }; 2086 }; 2087 2088 q6adm: service@8 { 2089 compatible = "qcom,q6adm"; 2090 reg = <APR_SVC_ADM>; 2091 q6routing: routing { 2092 compatible = "qcom,q6adm-routing"; 2093 #sound-dai-cells = <0>; 2094 }; 2095 }; 2096 }; 2097 }; 2098 }; 2099 }; 2100 2101 thermal-zones { 2102 cpu0-thermal { 2103 polling-delay-passive = <250>; 2104 2105 thermal-sensors = <&tsens0 9>; 2106 2107 trips { 2108 cpu0_alert: trip-point0 { 2109 temperature = <80000>; 2110 hysteresis = <2000>; 2111 type = "passive"; 2112 }; 2113 cpu0_crit: crit { 2114 temperature = <100000>; 2115 hysteresis = <2000>; 2116 type = "critical"; 2117 }; 2118 }; 2119 cooling-maps { 2120 map0 { 2121 trip = <&cpu0_alert>; 2122 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2123 }; 2124 }; 2125 }; 2126 cpu1-thermal { 2127 polling-delay-passive = <250>; 2128 2129 thermal-sensors = <&tsens0 10>; 2130 2131 trips { 2132 cpu1_alert: trip-point0 { 2133 temperature = <80000>; 2134 hysteresis = <2000>; 2135 type = "passive"; 2136 }; 2137 cpu1_crit: crit { 2138 temperature = <100000>; 2139 hysteresis = <2000>; 2140 type = "critical"; 2141 }; 2142 }; 2143 cooling-maps { 2144 map0 { 2145 trip = <&cpu1_alert>; 2146 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2147 }; 2148 }; 2149 }; 2150 cpu2-thermal { 2151 polling-delay-passive = <250>; 2152 2153 thermal-sensors = <&tsens0 11>; 2154 2155 trips { 2156 cpu2_alert: trip-point0 { 2157 temperature = <80000>; 2158 hysteresis = <2000>; 2159 type = "passive"; 2160 }; 2161 cpu2_crit: crit { 2162 temperature = <100000>; 2163 hysteresis = <2000>; 2164 type = "critical"; 2165 }; 2166 }; 2167 cooling-maps { 2168 map0 { 2169 trip = <&cpu2_alert>; 2170 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2171 }; 2172 }; 2173 }; 2174 cpu3-thermal { 2175 polling-delay-passive = <250>; 2176 2177 thermal-sensors = <&tsens0 12>; 2178 2179 trips { 2180 cpu3_alert: trip-point0 { 2181 temperature = <80000>; 2182 hysteresis = <2000>; 2183 type = "passive"; 2184 }; 2185 cpu3_crit: crit { 2186 temperature = <100000>; 2187 hysteresis = <2000>; 2188 type = "critical"; 2189 }; 2190 }; 2191 cooling-maps { 2192 map0 { 2193 trip = <&cpu3_alert>; 2194 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2195 }; 2196 }; 2197 }; 2198 cpu4-thermal { 2199 polling-delay-passive = <250>; 2200 thermal-sensors = <&tsens0 4>; 2201 trips { 2202 cpu4_alert: trip-point0 { 2203 temperature = <80000>; 2204 hysteresis = <2000>; 2205 type = "passive"; 2206 }; 2207 cpu4_crit: crit { 2208 temperature = <100000>; 2209 hysteresis = <2000>; 2210 type = "critical"; 2211 }; 2212 }; 2213 cooling-maps { 2214 map0 { 2215 trip = <&cpu4_alert>; 2216 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2217 }; 2218 }; 2219 }; 2220 cpu5-thermal { 2221 polling-delay-passive = <250>; 2222 thermal-sensors = <&tsens0 5>; 2223 trips { 2224 cpu5_alert: trip-point0 { 2225 temperature = <80000>; 2226 hysteresis = <2000>; 2227 type = "passive"; 2228 }; 2229 cpu5_crit: crit { 2230 temperature = <100000>; 2231 hysteresis = <2000>; 2232 type = "critical"; 2233 }; 2234 }; 2235 cooling-maps { 2236 map0 { 2237 trip = <&cpu5_alert>; 2238 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2239 }; 2240 }; 2241 }; 2242 cpu6-thermal { 2243 polling-delay-passive = <250>; 2244 thermal-sensors = <&tsens0 6>; 2245 trips { 2246 cpu6_alert: trip-point0 { 2247 temperature = <80000>; 2248 hysteresis = <2000>; 2249 type = "passive"; 2250 }; 2251 cpu6_crit: crit { 2252 temperature = <100000>; 2253 hysteresis = <2000>; 2254 type = "critical"; 2255 }; 2256 }; 2257 cooling-maps { 2258 map0 { 2259 trip = <&cpu6_alert>; 2260 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2261 }; 2262 }; 2263 }; 2264 cpu7-thermal { 2265 polling-delay-passive = <250>; 2266 thermal-sensors = <&tsens0 7>; 2267 trips { 2268 cpu7_alert: trip-point0 { 2269 temperature = <80000>; 2270 hysteresis = <2000>; 2271 type = "passive"; 2272 }; 2273 cpu7_crit: crit { 2274 temperature = <100000>; 2275 hysteresis = <2000>; 2276 type = "critical"; 2277 }; 2278 }; 2279 cooling-maps { 2280 map0 { 2281 trip = <&cpu7_alert>; 2282 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2283 }; 2284 }; 2285 }; 2286 2287 gpu-thermal { 2288 polling-delay-passive = <250>; 2289 thermal-sensors = <&tsens0 15>; 2290 2291 trips { 2292 gpu_alert: trip-point0 { 2293 temperature = <70000>; 2294 hysteresis = <2000>; 2295 type = "passive"; 2296 }; 2297 2298 gpu_crit: crit { 2299 temperature = <90000>; 2300 hysteresis = <2000>; 2301 type = "critical"; 2302 }; 2303 }; 2304 2305 cooling-maps { 2306 map0 { 2307 trip = <&gpu_alert>; 2308 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2309 }; 2310 }; 2311 }; 2312 }; 2313 2314 timer { 2315 compatible = "arm,armv8-timer"; 2316 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2317 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2318 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2319 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2320 }; 2321}; 2322