1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 7 8#include "monaco.dtsi" 9#include "monaco-pmics.dtsi" 10 11/ { 12 /* This comes from a PMIC handled within the SAIL domain */ 13 vreg_s2s: vreg-s2s { 14 compatible = "regulator-fixed"; 15 regulator-name = "vreg_s2s"; 16 17 regulator-min-microvolt = <1800000>; 18 regulator-max-microvolt = <1800000>; 19 }; 20}; 21 22&apps_rsc { 23 regulators-0 { 24 compatible = "qcom,pmm8654au-rpmh-regulators"; 25 qcom,pmic-id = "a"; 26 27 vreg_l3a: ldo3 { 28 regulator-name = "vreg_l3a"; 29 regulator-min-microvolt = <1200000>; 30 regulator-max-microvolt = <1200000>; 31 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 32 regulator-allow-set-load; 33 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 34 regulator-always-on; 35 }; 36 37 vreg_l4a: ldo4 { 38 regulator-name = "vreg_l4a"; 39 regulator-min-microvolt = <880000>; 40 regulator-max-microvolt = <912000>; 41 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 42 regulator-allow-set-load; 43 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 44 }; 45 46 vreg_l5a: ldo5 { 47 regulator-name = "vreg_l5a"; 48 regulator-min-microvolt = <1200000>; 49 regulator-max-microvolt = <1200000>; 50 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 51 regulator-allow-set-load; 52 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 53 }; 54 55 vreg_l6a: ldo6 { 56 regulator-name = "vreg_l6a"; 57 regulator-min-microvolt = <880000>; 58 regulator-max-microvolt = <912000>; 59 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 60 regulator-allow-set-load; 61 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 62 }; 63 64 vreg_l7a: ldo7 { 65 regulator-name = "vreg_l7a"; 66 regulator-min-microvolt = <880000>; 67 regulator-max-microvolt = <912000>; 68 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 69 regulator-allow-set-load; 70 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 71 }; 72 73 vreg_l8a: ldo8 { 74 regulator-name = "vreg_l8a"; 75 regulator-min-microvolt = <2504000>; 76 regulator-max-microvolt = <2960000>; 77 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 78 regulator-allow-set-load; 79 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 80 }; 81 82 vreg_l9a: ldo9 { 83 regulator-name = "vreg_l9a"; 84 regulator-min-microvolt = <2970000>; 85 regulator-max-microvolt = <3072000>; 86 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 87 regulator-allow-set-load; 88 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 89 }; 90 }; 91 92 regulators-1 { 93 compatible = "qcom,pmm8654au-rpmh-regulators"; 94 qcom,pmic-id = "c"; 95 96 vreg_s5c: smps5 { /* LPDDR VDD2H */ 97 regulator-name = "vreg_s5c"; 98 regulator-min-microvolt = <1104000>; 99 regulator-max-microvolt = <1104000>; 100 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 101 }; 102 103 vreg_l1c: ldo1 { /* LPDDR VDDQ */ 104 regulator-name = "vreg_l1c"; 105 regulator-min-microvolt = <300000>; 106 regulator-max-microvolt = <512000>; 107 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 108 regulator-allow-set-load; 109 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 110 }; 111 112 vreg_l2c: ldo2 { /* LPDDR VDD2L */ 113 regulator-name = "vreg_l2c"; 114 regulator-min-microvolt = <900000>; 115 regulator-max-microvolt = <904000>; 116 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 117 regulator-allow-set-load; 118 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 119 }; 120 121 vreg_l4c: ldo4 { 122 regulator-name = "vreg_l4c"; 123 regulator-min-microvolt = <1200000>; 124 regulator-max-microvolt = <1200000>; 125 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 126 regulator-allow-set-load; 127 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 128 }; 129 130 vreg_l7c: ldo7 { 131 regulator-name = "vreg_l7c"; 132 regulator-min-microvolt = <1800000>; 133 regulator-max-microvolt = <1800000>; 134 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 135 regulator-allow-set-load; 136 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 137 }; 138 139 vreg_l8c: ldo8 { /* LPDDR VDD1 */ 140 regulator-name = "vreg_l8c"; 141 regulator-min-microvolt = <1800000>; 142 regulator-max-microvolt = <1800000>; 143 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 144 regulator-allow-set-load; 145 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 146 }; 147 148 vreg_l9c: ldo9 { /* QFPROM */ 149 regulator-name = "vreg_l9c"; 150 regulator-min-microvolt = <1800000>; 151 regulator-max-microvolt = <1800000>; 152 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 153 regulator-allow-set-load; 154 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 155 }; 156 }; 157}; 158 159&mdss_dp0 { 160 pinctrl-0 = <&dp_hpd>; 161 pinctrl-names = "default"; 162}; 163 164&mdss_dp0_phy { 165 vdda-phy-supply = <&vreg_l5a>; 166 vdda-pll-supply = <&vreg_l4a>; 167}; 168 169&mdss_dsi0 { 170 vdda-supply = <&vreg_l5a>; 171}; 172 173&mdss_dsi0_phy { 174 vdds-supply = <&vreg_l4a>; 175}; 176 177&gpi_dma0 { 178 status = "okay"; 179}; 180 181&gpi_dma1 { 182 status = "okay"; 183}; 184 185&gpu { 186 status = "okay"; 187}; 188 189&gpu_zap_shader { 190 firmware-name = "qcom/qcs8300/a623_zap.mbn"; 191}; 192 193&iris { 194 status = "okay"; 195}; 196 197/* PCIe0 Gen4 x2 */ 198&pcie0 { 199 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 200 <0x100 &pcie_smmu 0x0001 0x1>, 201 <0x200 &pcie_smmu 0x0007 0x1>, 202 <0x208 &pcie_smmu 0x0002 0x1>, 203 <0x210 &pcie_smmu 0x0003 0x1>, 204 <0x218 &pcie_smmu 0x0004 0x1>, 205 <0x300 &pcie_smmu 0x0005 0x1>, 206 <0x400 &pcie_smmu 0x0006 0x1>; 207 208 status = "okay"; 209}; 210 211&pcie0_phy { 212 vdda-phy-supply = <&vreg_l6a>; 213 vdda-pll-supply = <&vreg_l5a>; 214 215 status = "okay"; 216}; 217 218/* PCIe1 Gen4 x4 */ 219&pcie1 { 220 status = "okay"; 221}; 222 223&pcie1_phy { 224 vdda-phy-supply = <&vreg_l6a>; 225 vdda-pll-supply = <&vreg_l5a>; 226 227 status = "okay"; 228}; 229 230&qupv3_id_0 { 231 firmware-name = "qcom/qcs8300/qupv3fw.elf"; 232 233 status = "okay"; 234}; 235 236&qupv3_id_1 { 237 firmware-name = "qcom/qcs8300/qupv3fw.elf"; 238 status = "okay"; 239}; 240 241/* There is a HW/FW issue preventing proper REFGEN hardware voting 242 * for the USB2 HS PHY. As a workaround, we force REFGEN to stay 243 * always‑on in software, matching initial bootloader config. 244 */ 245&refgen { 246 regulator-always-on; 247}; 248 249&remoteproc_adsp { 250 firmware-name = "qcom/qcs8300/adsp.mbn"; 251 252 status = "okay"; 253}; 254 255&remoteproc_cdsp { 256 firmware-name = "qcom/qcs8300/cdsp0.mbn"; 257 258 status = "okay"; 259}; 260 261&remoteproc_gpdsp { 262 firmware-name = "qcom/qcs8300/gpdsp0.mbn"; 263 264 status = "okay"; 265}; 266 267/* OnSom eMMC */ 268&sdhc_1 { 269 vmmc-supply = <&vreg_l8a>; 270 vqmmc-supply = <&vreg_s2s>; 271 272 bus-width = <8>; 273 mmc-ddr-1_8v; 274 mmc-hs200-1_8v; 275 mmc-hs400-1_8v; 276 mmc-hs400-enhanced-strobe; 277 278 no-sd; 279 no-sdio; 280 non-removable; 281 282 status = "okay"; 283}; 284 285/* Ethernet/SGMII */ 286&serdes0 { 287 phy-supply = <&vreg_l5a>; 288 289 status = "okay"; 290}; 291 292&tlmm { 293 dp_hpd: dp-hpd-state { 294 pins = "gpio94"; 295 function = "edp0_hot"; 296 bias-disable; 297 }; 298}; 299 300/* USB0 HS + SS */ 301&usb_1_hsphy { 302 vdda-pll-supply = <&vreg_l7a>; 303 vdda18-supply = <&vreg_l7c>; 304 vdda33-supply = <&vreg_l9a>; 305 306 status = "okay"; 307}; 308 309&usb_qmpphy { 310 vdda-phy-supply = <&vreg_l7a>; 311 vdda-pll-supply = <&vreg_l5a>; 312 313 status = "okay"; 314}; 315 316/* USB1 HS */ 317&usb_2_hsphy { 318 vdda-pll-supply = <&vreg_l7a>; 319 vdda18-supply = <&vreg_l7c>; 320 vdda33-supply = <&vreg_l9a>; 321 322 status = "okay"; 323}; 324