1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6/dts-v1/; 7/plugin/; 8 9#include <dt-bindings/gpio/gpio.h> 10 11&{/} { 12 model = "Qualcomm Technologies, Inc. Monaco-EVK IFP Mezzanine"; 13 14 vreg_0p9: regulator-0v9 { 15 compatible = "regulator-fixed"; 16 regulator-name = "VREG_0P9"; 17 18 regulator-min-microvolt = <900000>; 19 regulator-max-microvolt = <900000>; 20 regulator-always-on; 21 regulator-boot-on; 22 }; 23 24 vreg_1p8: regulator-1v8 { 25 compatible = "regulator-fixed"; 26 regulator-name = "VREG_1P8"; 27 28 regulator-min-microvolt = <1800000>; 29 regulator-max-microvolt = <1800000>; 30 regulator-always-on; 31 regulator-boot-on; 32 }; 33}; 34 35&i2c15 { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 eeprom1: eeprom@52 { 40 compatible = "giantec,gt24c256c", "atmel,24c256"; 41 reg = <0x52>; 42 pagesize = <64>; 43 44 nvmem-layout { 45 compatible = "fixed-layout"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 }; 49 }; 50}; 51 52&pcie0 { 53 iommu-map = <0x0 &pcie_smmu 0x0 0x1>, 54 <0x100 &pcie_smmu 0x1 0x1>, 55 <0x208 &pcie_smmu 0x2 0x1>, 56 <0x210 &pcie_smmu 0x3 0x1>, 57 <0x218 &pcie_smmu 0x4 0x1>, 58 <0x300 &pcie_smmu 0x5 0x1>, 59 <0x400 &pcie_smmu 0x6 0x1>, 60 <0x500 &pcie_smmu 0x7 0x1>, 61 <0x501 &pcie_smmu 0x8 0x1>; 62}; 63 64&pcieport0 { 65 #address-cells = <3>; 66 #size-cells = <2>; 67 68 pcie@0,0 { 69 compatible = "pci1179,0623"; 70 reg = <0x10000 0x0 0x0 0x0 0x0>; 71 #address-cells = <3>; 72 #size-cells = <2>; 73 74 device_type = "pci"; 75 ranges; 76 bus-range = <0x2 0xff>; 77 78 vddc-supply = <&vreg_0p9>; 79 vdd18-supply = <&vreg_1p8>; 80 vdd09-supply = <&vreg_0p9>; 81 vddio1-supply = <&vreg_1p8>; 82 vddio2-supply = <&vreg_1p8>; 83 vddio18-supply = <&vreg_1p8>; 84 85 i2c-parent = <&i2c15 0x77>; 86 87 resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; 88 89 pinctrl-0 = <&tc9563_resx_n>; 90 pinctrl-names = "default"; 91 92 pcie@1,0 { 93 reg = <0x20800 0x0 0x0 0x0 0x0>; 94 #address-cells = <3>; 95 #size-cells = <2>; 96 97 device_type = "pci"; 98 ranges; 99 bus-range = <0x3 0xff>; 100 }; 101 102 pcie@2,0 { 103 reg = <0x21000 0x0 0x0 0x0 0x0>; 104 #address-cells = <3>; 105 #size-cells = <2>; 106 107 device_type = "pci"; 108 ranges; 109 bus-range = <0x4 0xff>; 110 }; 111 112 pcie@3,0 { 113 reg = <0x21800 0x0 0x0 0x0 0x0>; 114 #address-cells = <3>; 115 #size-cells = <2>; 116 device_type = "pci"; 117 ranges; 118 bus-range = <0x5 0xff>; 119 120 pci@0,0 { 121 reg = <0x50000 0x0 0x0 0x0 0x0>; 122 #address-cells = <3>; 123 #size-cells = <2>; 124 device_type = "pci"; 125 ranges; 126 }; 127 128 pci@0,1 { 129 reg = <0x50100 0x0 0x0 0x0 0x0>; 130 #address-cells = <3>; 131 #size-cells = <2>; 132 device_type = "pci"; 133 ranges; 134 }; 135 }; 136 }; 137}; 138 139&tlmm { 140 tc9563_resx_n: tc9563-resx-state { 141 pins = "gpio124"; 142 function = "gpio"; 143 bias-disable; 144 /* Reset pin of tc9563 is active low hence set default 145 * state of this pin to output-high. 146 */ 147 output-high; 148 }; 149}; 150