1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 4 */ 5 6#include <dt-bindings/clock/qcom,milos-camcc.h> 7#include <dt-bindings/clock/qcom,milos-dispcc.h> 8#include <dt-bindings/clock/qcom,milos-gcc.h> 9#include <dt-bindings/clock/qcom,milos-gpucc.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,milos-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <76800000>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a520"; 52 reg = <0x0 0x0>; 53 54 clocks = <&cpufreq_hw 0>; 55 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 59 enable-method = "psci"; 60 next-level-cache = <&l2_0>; 61 capacity-dmips-mhz = <1024>; 62 dynamic-power-coefficient = <100>; 63 64 qcom,freq-domain = <&cpufreq_hw 0>; 65 66 #cooling-cells = <2>; 67 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 74 l3_0: l3-cache { 75 compatible = "cache"; 76 cache-level = <3>; 77 cache-unified; 78 }; 79 }; 80 }; 81 82 cpu1: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a520"; 85 reg = <0x0 0x100>; 86 87 clocks = <&cpufreq_hw 0>; 88 89 power-domains = <&cpu_pd1>; 90 power-domain-names = "psci"; 91 92 enable-method = "psci"; 93 next-level-cache = <&l2_0>; 94 capacity-dmips-mhz = <1024>; 95 dynamic-power-coefficient = <100>; 96 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 99 #cooling-cells = <2>; 100 }; 101 102 cpu2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a520"; 105 reg = <0x0 0x200>; 106 107 clocks = <&cpufreq_hw 0>; 108 109 power-domains = <&cpu_pd2>; 110 power-domain-names = "psci"; 111 112 enable-method = "psci"; 113 next-level-cache = <&l2_2>; 114 capacity-dmips-mhz = <1024>; 115 dynamic-power-coefficient = <100>; 116 117 qcom,freq-domain = <&cpufreq_hw 0>; 118 119 #cooling-cells = <2>; 120 121 l2_2: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 cache-unified; 125 next-level-cache = <&l3_0>; 126 }; 127 }; 128 129 cpu3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a520"; 132 reg = <0x0 0x300>; 133 134 clocks = <&cpufreq_hw 0>; 135 136 power-domains = <&cpu_pd3>; 137 power-domain-names = "psci"; 138 139 enable-method = "psci"; 140 next-level-cache = <&l2_2>; 141 capacity-dmips-mhz = <1024>; 142 dynamic-power-coefficient = <100>; 143 144 qcom,freq-domain = <&cpufreq_hw 0>; 145 146 #cooling-cells = <2>; 147 }; 148 149 cpu4: cpu@400 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a720"; 152 reg = <0x0 0x400>; 153 154 clocks = <&cpufreq_hw 1>; 155 156 power-domains = <&cpu_pd4>; 157 power-domain-names = "psci"; 158 159 enable-method = "psci"; 160 next-level-cache = <&l2_4>; 161 capacity-dmips-mhz = <1670>; 162 dynamic-power-coefficient = <264>; 163 164 qcom,freq-domain = <&cpufreq_hw 1>; 165 166 #cooling-cells = <2>; 167 168 l2_4: l2-cache { 169 compatible = "cache"; 170 cache-level = <2>; 171 cache-unified; 172 next-level-cache = <&l3_0>; 173 }; 174 }; 175 176 cpu5: cpu@500 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-a720"; 179 reg = <0x0 0x500>; 180 181 clocks = <&cpufreq_hw 1>; 182 183 power-domains = <&cpu_pd5>; 184 power-domain-names = "psci"; 185 186 enable-method = "psci"; 187 next-level-cache = <&l2_5>; 188 capacity-dmips-mhz = <1670>; 189 dynamic-power-coefficient = <264>; 190 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 193 #cooling-cells = <2>; 194 195 l2_5: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-unified; 199 next-level-cache = <&l3_0>; 200 }; 201 }; 202 203 cpu6: cpu@600 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a720"; 206 reg = <0x0 0x600>; 207 208 clocks = <&cpufreq_hw 1>; 209 210 power-domains = <&cpu_pd6>; 211 power-domain-names = "psci"; 212 213 enable-method = "psci"; 214 next-level-cache = <&l2_6>; 215 capacity-dmips-mhz = <1670>; 216 dynamic-power-coefficient = <264>; 217 218 qcom,freq-domain = <&cpufreq_hw 1>; 219 220 #cooling-cells = <2>; 221 222 l2_6: l2-cache { 223 compatible = "cache"; 224 cache-level = <2>; 225 cache-unified; 226 next-level-cache = <&l3_0>; 227 }; 228 }; 229 230 cpu7: cpu@700 { 231 device_type = "cpu"; 232 compatible = "arm,cortex-a720"; 233 reg = <0x0 0x700>; 234 235 clocks = <&cpufreq_hw 2>; 236 237 power-domains = <&cpu_pd7>; 238 power-domain-names = "psci"; 239 240 enable-method = "psci"; 241 next-level-cache = <&l2_7>; 242 capacity-dmips-mhz = <1670>; 243 dynamic-power-coefficient = <287>; 244 245 qcom,freq-domain = <&cpufreq_hw 2>; 246 247 #cooling-cells = <2>; 248 249 l2_7: l2-cache { 250 compatible = "cache"; 251 cache-level = <2>; 252 cache-unified; 253 next-level-cache = <&l3_0>; 254 }; 255 }; 256 257 cpu-map { 258 cluster0 { 259 core0 { 260 cpu = <&cpu0>; 261 }; 262 263 core1 { 264 cpu = <&cpu1>; 265 }; 266 267 core2 { 268 cpu = <&cpu2>; 269 }; 270 271 core3 { 272 cpu = <&cpu3>; 273 }; 274 }; 275 276 cluster1 { 277 core0 { 278 cpu = <&cpu4>; 279 }; 280 281 core1 { 282 cpu = <&cpu5>; 283 }; 284 285 core2 { 286 cpu = <&cpu6>; 287 }; 288 }; 289 290 cluster2 { 291 core0 { 292 cpu = <&cpu7>; 293 }; 294 }; 295 }; 296 297 idle-states { 298 entry-method = "psci"; 299 300 silver_cpu_sleep_0: cpu-sleep-0-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "pc"; 303 arm,psci-suspend-param = <0x40000003>; 304 entry-latency-us = <250>; 305 exit-latency-us = <700>; 306 min-residency-us = <5200>; 307 local-timer-stop; 308 }; 309 310 silver_cpu_sleep_1: cpu-sleep-0-1 { 311 compatible = "arm,idle-state"; 312 idle-state-name = "silver-rail-power-collapse"; 313 arm,psci-suspend-param = <0x40000004>; 314 entry-latency-us = <550>; 315 exit-latency-us = <750>; 316 min-residency-us = <6700>; 317 local-timer-stop; 318 }; 319 320 gold_cpu_sleep_0: cpu-sleep-1-0 { 321 compatible = "arm,idle-state"; 322 idle-state-name = "silver-power-collapse"; 323 arm,psci-suspend-param = <0x40000003>; 324 entry-latency-us = <400>; 325 exit-latency-us = <900>; 326 min-residency-us = <5511>; 327 local-timer-stop; 328 }; 329 330 gold_cpu_sleep_1: cpu-sleep-1-1 { 331 compatible = "arm,idle-state"; 332 idle-state-name = "gold-rail-power-collapse"; 333 arm,psci-suspend-param = <0x40000004>; 334 entry-latency-us = <600>; 335 exit-latency-us = <1300>; 336 min-residency-us = <8136>; 337 local-timer-stop; 338 }; 339 340 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 341 compatible = "arm,idle-state"; 342 idle-state-name = "gold-plus-rail-power-collapse"; 343 arm,psci-suspend-param = <0x40000004>; 344 entry-latency-us = <600>; 345 exit-latency-us = <1500>; 346 min-residency-us = <8551>; 347 local-timer-stop; 348 }; 349 }; 350 351 domain-idle-states { 352 cluster_sleep_0: cluster-sleep-0 { 353 compatible = "domain-idle-state"; 354 arm,psci-suspend-param = <0x41000044>; 355 entry-latency-us = <750>; 356 exit-latency-us = <2350>; 357 min-residency-us = <9144>; 358 }; 359 360 cluster_sleep_1: cluster-sleep-1 { 361 compatible = "domain-idle-state"; 362 arm,psci-suspend-param = <0x41003344>; 363 entry-latency-us = <2800>; 364 exit-latency-us = <4400>; 365 min-residency-us = <10150>; 366 }; 367 }; 368 }; 369 370 firmware { 371 scm: scm { 372 compatible = "qcom,scm-milos", "qcom,scm"; 373 qcom,dload-mode = <&tcsr 0x19000>; 374 }; 375 }; 376 377 clk_virt: interconnect-0 { 378 compatible = "qcom,milos-clk-virt"; 379 #interconnect-cells = <2>; 380 qcom,bcm-voters = <&apps_bcm_voter>; 381 }; 382 383 mc_virt: interconnect-1 { 384 compatible = "qcom,milos-mc-virt"; 385 #interconnect-cells = <2>; 386 qcom,bcm-voters = <&apps_bcm_voter>; 387 }; 388 389 memory@0 { 390 device_type = "memory"; 391 /* We expect the bootloader to fill in the size */ 392 reg = <0 0 0 0>; 393 }; 394 395 pmu-a520 { 396 compatible = "arm,cortex-a520-pmu"; 397 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 398 }; 399 400 pmu-a720 { 401 compatible = "arm,cortex-a720-pmu"; 402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 403 }; 404 405 psci { 406 compatible = "arm,psci-1.0"; 407 method = "smc"; 408 409 cpu_pd0: power-domain-cpu0 { 410 #power-domain-cells = <0>; 411 power-domains = <&cluster_pd>; 412 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 413 }; 414 415 cpu_pd1: power-domain-cpu1 { 416 #power-domain-cells = <0>; 417 power-domains = <&cluster_pd>; 418 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 419 }; 420 421 cpu_pd2: power-domain-cpu2 { 422 #power-domain-cells = <0>; 423 power-domains = <&cluster_pd>; 424 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 425 }; 426 427 cpu_pd3: power-domain-cpu3 { 428 #power-domain-cells = <0>; 429 power-domains = <&cluster_pd>; 430 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 431 }; 432 433 cpu_pd4: power-domain-cpu4 { 434 #power-domain-cells = <0>; 435 power-domains = <&cluster_pd>; 436 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 437 }; 438 439 cpu_pd5: power-domain-cpu5 { 440 #power-domain-cells = <0>; 441 power-domains = <&cluster_pd>; 442 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 443 }; 444 445 cpu_pd6: power-domain-cpu6 { 446 #power-domain-cells = <0>; 447 power-domains = <&cluster_pd>; 448 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 449 }; 450 451 cpu_pd7: power-domain-cpu7 { 452 #power-domain-cells = <0>; 453 power-domains = <&cluster_pd>; 454 domain-idle-states = <&gold_plus_cpu_sleep_0>; 455 }; 456 457 cluster_pd: power-domain-cluster { 458 #power-domain-cells = <0>; 459 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 460 }; 461 }; 462 463 reserved-memory { 464 #address-cells = <2>; 465 #size-cells = <2>; 466 ranges; 467 468 gunyah_hyp_mem: gunyah-hyp-region@80000000 { 469 reg = <0x0 0x80000000 0x0 0xe00000>; 470 no-map; 471 }; 472 473 xbl_sc_mem: xbl-sc-region@81800000 { 474 reg = <0x0 0x81800000 0x0 0x40000>; 475 no-map; 476 }; 477 478 cpucp_fw_mem: cpucp-fw-region@81840000 { 479 reg = <0x0 0x81840000 0x0 0x1c0000>; 480 no-map; 481 }; 482 483 xbl_dtlog_mem: xbl-dtlog-region@81a00000 { 484 reg = <0x0 0x81a00000 0x0 0x40000>; 485 no-map; 486 }; 487 488 xbl_ramdump_mem: xbl-ramdump-region@81a40000 { 489 reg = <0x0 0x81a40000 0x0 0x1c0000>; 490 no-map; 491 }; 492 493 aop_image_mem: aop-image-region@81c00000 { 494 reg = <0x0 0x81c00000 0x0 0x60000>; 495 no-map; 496 }; 497 498 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 499 compatible = "qcom,cmd-db"; 500 reg = <0x0 0x81c60000 0x0 0x20000>; 501 no-map; 502 }; 503 504 aop_config_mem: aop-config-region@81c80000 { 505 reg = <0x0 0x81c80000 0x0 0x20000>; 506 no-map; 507 }; 508 509 tme_crash_dump_mem: tme-crash-dump-region@81ca0000 { 510 reg = <0x0 0x81ca0000 0x0 0x40000>; 511 no-map; 512 }; 513 514 tme_log_mem: tme-log-region@81ce0000 { 515 reg = <0x0 0x81ce0000 0x0 0x4000>; 516 no-map; 517 }; 518 519 uefi_log_mem: uefi-log-region@81ce4000 { 520 reg = <0x0 0x81ce4000 0x0 0x10000>; 521 no-map; 522 }; 523 524 chipinfo_mem: chipinfo-region@81cf4000 { 525 reg = <0x0 0x81cf4000 0x0 0x1000>; 526 no-map; 527 }; 528 529 secdata_apss_mem: secdata-apss-region@81cff000 { 530 reg = <0x0 0x81cff000 0x0 0x1000>; 531 no-map; 532 }; 533 534 smem_mem: smem-region@81d00000 { 535 compatible = "qcom,smem"; 536 reg = <0x0 0x81d00000 0x0 0x200000>; 537 hwlocks = <&tcsr_mutex 3>; 538 no-map; 539 }; 540 541 adsp_mhi_mem: adsp-mhi-region@81f00000 { 542 reg = <0x0 0x81f00000 0x0 0x20000>; 543 no-map; 544 }; 545 546 pvm_fw_mem: pvm-fw-region@824a0000 { 547 reg = <0x0 0x824a0000 0x0 0x100000>; 548 no-map; 549 }; 550 551 hyp_mem_database_mem: hyp-mem-database-region@825a0000 { 552 reg = <0x0 0x825a0000 0x0 0x60000>; 553 no-map; 554 }; 555 556 global_sync_mem: global-sync-region@82600000 { 557 reg = <0x0 0x82600000 0x0 0x100000>; 558 no-map; 559 }; 560 561 tz_stat_mem: tz-stat-region@82700000 { 562 reg = <0x0 0x82700000 0x0 0x100000>; 563 no-map; 564 }; 565 566 qdss_apps_mem: qdss-apps-region@82800000 { 567 reg = <0x0 0x82800000 0x0 0x2000000>; 568 reusable; 569 }; 570 571 mpss_mem: mpss-region@8ac00000 { 572 reg = <0x0 0x8ac00000 0x0 0xe600000>; 573 no-map; 574 }; 575 576 q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 { 577 reg = <0x0 0x99200000 0x0 0x80000>; 578 no-map; 579 }; 580 581 q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 { 582 reg = <0x0 0x99280000 0x0 0x80000>; 583 no-map; 584 }; 585 586 adspslpi_mem: adspslpi-region@99300000 { 587 reg = <0x0 0x99300000 0x0 0x2800000>; 588 no-map; 589 }; 590 591 wpss_mem: wpss-region@9bb00000 { 592 reg = <0x0 0x9bb00000 0x0 0x1900000>; 593 no-map; 594 }; 595 596 video_mem: video-region@9d400000 { 597 reg = <0x0 0x9d400000 0x0 0x700000>; 598 no-map; 599 }; 600 601 cdsp_mem: cdsp-region@9db00000 { 602 reg = <0x0 0x9db00000 0x0 0xf00000>; 603 no-map; 604 }; 605 606 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 { 607 reg = <0x0 0x9ea00000 0x0 0x80000>; 608 no-map; 609 }; 610 611 ipa_fw_mem: ipa-fw-region@9ea80000 { 612 reg = <0x0 0x9ea80000 0x0 0x10000>; 613 no-map; 614 }; 615 616 ipa_gsi_mem: ipa-gsi-region@9ea90000 { 617 reg = <0x0 0x9ea90000 0x0 0xa000>; 618 no-map; 619 }; 620 621 gpu_microcode_mem: gpu-microcode-region@9ea9a000 { 622 reg = <0x0 0x9ea9a000 0x0 0x2000>; 623 no-map; 624 }; 625 626 camera_mem: camera-region@9eb00000 { 627 reg = <0x0 0x9eb00000 0x0 0x800000>; 628 no-map; 629 }; 630 631 wlan_msa_mem: wlan-msa-region@a6400000 { 632 reg = <0x0 0xa6400000 0x0 0xc00000>; 633 no-map; 634 }; 635 636 cpusys_vm_mem: cpusys-vm-region@e0600000 { 637 reg = <0x0 0xe0600000 0x0 0x400000>; 638 no-map; 639 }; 640 641 rmtfs_mem: rmtfs@e1f00000 { 642 compatible = "qcom,rmtfs-mem"; 643 reg = <0x0 0xe1f00000 0x0 0x600000>; 644 no-map; 645 646 qcom,client-id = <1>; 647 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 648 }; 649 650 qtee_mem: qtee-region@e8900000 { 651 reg = <0x0 0xe8900000 0x0 0x500000>; 652 no-map; 653 }; 654 655 tags_mem: tags-region@e8e00000 { 656 reg = <0x0 0xe8e00000 0x0 0x700000>; 657 no-map; 658 }; 659 660 trusted_apps_mem: trusted-apps-region@e9500000 { 661 reg = <0x0 0xe9500000 0x0 0x1200000>; 662 no-map; 663 }; 664 }; 665 666 smp2p-adsp { 667 compatible = "qcom,smp2p"; 668 qcom,smem = <443>, <429>; 669 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 670 IPCC_MPROC_SIGNAL_SMP2P 671 IRQ_TYPE_EDGE_RISING>; 672 mboxes = <&ipcc IPCC_CLIENT_LPASS 673 IPCC_MPROC_SIGNAL_SMP2P>; 674 675 qcom,local-pid = <0>; 676 qcom,remote-pid = <2>; 677 678 smp2p_adsp_out: master-kernel { 679 qcom,entry-name = "master-kernel"; 680 #qcom,smem-state-cells = <1>; 681 }; 682 683 smp2p_adsp_in: slave-kernel { 684 qcom,entry-name = "slave-kernel"; 685 interrupt-controller; 686 #interrupt-cells = <2>; 687 }; 688 }; 689 690 smp2p-cdsp { 691 compatible = "qcom,smp2p"; 692 qcom,smem = <94>, <432>; 693 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 694 IPCC_MPROC_SIGNAL_SMP2P 695 IRQ_TYPE_EDGE_RISING>; 696 mboxes = <&ipcc IPCC_CLIENT_CDSP 697 IPCC_MPROC_SIGNAL_SMP2P>; 698 699 qcom,local-pid = <0>; 700 qcom,remote-pid = <5>; 701 702 smp2p_cdsp_out: master-kernel { 703 qcom,entry-name = "master-kernel"; 704 #qcom,smem-state-cells = <1>; 705 }; 706 707 smp2p_cdsp_in: slave-kernel { 708 qcom,entry-name = "slave-kernel"; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 }; 712 }; 713 714 smp2p-modem { 715 compatible = "qcom,smp2p"; 716 qcom,smem = <435>, <428>; 717 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 718 IPCC_MPROC_SIGNAL_SMP2P 719 IRQ_TYPE_EDGE_RISING>; 720 mboxes = <&ipcc IPCC_CLIENT_MPSS 721 IPCC_MPROC_SIGNAL_SMP2P>; 722 723 qcom,local-pid = <0>; 724 qcom,remote-pid = <1>; 725 726 smp2p_modem_out: master-kernel { 727 qcom,entry-name = "master-kernel"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 smp2p_modem_in: slave-kernel { 732 qcom,entry-name = "slave-kernel"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 737 smp2p_ipa_out: ipa-ap-to-modem { 738 qcom,entry-name = "ipa"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_ipa_in: ipa-modem-to-ap { 743 qcom,entry-name = "ipa"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-wpss { 750 compatible = "qcom,smp2p"; 751 qcom,smem = <617>, <616>; 752 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 753 IPCC_MPROC_SIGNAL_SMP2P 754 IRQ_TYPE_EDGE_RISING>; 755 mboxes = <&ipcc IPCC_CLIENT_WPSS 756 IPCC_MPROC_SIGNAL_SMP2P>; 757 758 qcom,local-pid = <0>; 759 qcom,remote-pid = <13>; 760 761 smp2p_wpss_out: master-kernel { 762 qcom,entry-name = "master-kernel"; 763 #qcom,smem-state-cells = <1>; 764 }; 765 766 smp2p_wpss_in: slave-kernel { 767 qcom,entry-name = "slave-kernel"; 768 interrupt-controller; 769 #interrupt-cells = <2>; 770 }; 771 772 smp2p_wlan_out: wlan-ap-to-wpss { 773 qcom,entry-name = "wlan"; 774 #qcom,smem-state-cells = <1>; 775 }; 776 777 smp2p_wlan_in: wlan-wpss-to-ap { 778 qcom,entry-name = "wlan"; 779 interrupt-controller; 780 #interrupt-cells = <2>; 781 }; 782 }; 783 784 soc: soc@0 { 785 compatible = "simple-bus"; 786 787 #address-cells = <2>; 788 #size-cells = <2>; 789 dma-ranges = <0 0 0 0 0x10 0>; 790 ranges = <0 0 0 0 0x10 0>; 791 792 gcc: clock-controller@100000 { 793 compatible = "qcom,milos-gcc"; 794 reg = <0x0 0x00100000 0x0 0x1f4200>; 795 796 clocks = <&rpmhcc RPMH_CXO_CLK>, 797 <&sleep_clk>, 798 <0>, /* pcie_0_pipe_clk */ 799 <0>, /* pcie_1_pipe_clk */ 800 <0>, /* ufs_phy_rx_symbol_0_clk */ 801 <0>, /* ufs_phy_rx_symbol_1_clk */ 802 <0>, /* ufs_phy_tx_symbol_0_clk */ 803 <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ 804 805 #clock-cells = <1>; 806 #reset-cells = <1>; 807 #power-domain-cells = <1>; 808 }; 809 810 ipcc: mailbox@405000 { 811 compatible = "qcom,milos-ipcc", "qcom,ipcc"; 812 reg = <0x0 0x00405000 0x0 0x1000>; 813 814 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 815 interrupt-controller; 816 #interrupt-cells = <3>; 817 818 #mbox-cells = <2>; 819 }; 820 821 gpi_dma1: dma-controller@800000 { 822 compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; 823 reg = <0x0 0x00800000 0x0 0x60000>; 824 825 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 826 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 827 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 828 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 829 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 830 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 831 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 832 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>, 833 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>, 834 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>, 835 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>, 836 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 837 838 dma-channels = <12>; 839 dma-channel-mask = <0x3f>; 840 #dma-cells = <3>; 841 842 iommus = <&apps_smmu 0x36 0x0>; 843 dma-coherent; 844 }; 845 846 qupv3_id_1: geniqup@8c0000 { 847 compatible = "qcom,geni-se-qup"; 848 reg = <0x0 0x008c0000 0x0 0x2000>; 849 850 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 851 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 852 clock-names = "m-ahb", 853 "s-ahb"; 854 855 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 856 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 857 interconnect-names = "qup-core"; 858 859 iommus = <&apps_smmu 0x23 0>; 860 861 dma-coherent; 862 863 #address-cells = <2>; 864 #size-cells = <2>; 865 ranges; 866 867 status = "disabled"; 868 869 i2c7: i2c@880000 { 870 compatible = "qcom,geni-i2c"; 871 reg = <0x0 0x00880000 0x0 0x4000>; 872 873 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 874 875 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 876 clock-names = "se"; 877 878 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 879 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 880 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 881 &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 882 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 883 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 884 interconnect-names = "qup-core", 885 "qup-config", 886 "qup-memory"; 887 888 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 889 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 890 dma-names = "tx", 891 "rx"; 892 893 pinctrl-0 = <&qup_i2c7_data_clk>; 894 pinctrl-names = "default"; 895 896 #address-cells = <1>; 897 #size-cells = <0>; 898 899 status = "disabled"; 900 }; 901 902 uart11: serial@890000 { 903 compatible = "qcom,geni-uart"; 904 reg = <0x0 0x00890000 0x0 0x4000>; 905 906 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 907 908 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 909 clock-names = "se"; 910 911 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 912 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 914 &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 915 interconnect-names = "qup-core", 916 "qup-config"; 917 918 pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>; 919 pinctrl-names = "default"; 920 921 status = "disabled"; 922 }; 923 }; 924 925 gpi_dma0: dma-controller@a00000 { 926 compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; 927 reg = <0x0 0x00a00000 0x0 0x60000>; 928 929 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>, 930 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, 931 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, 932 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, 933 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, 934 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 935 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>, 936 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 937 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 938 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 939 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 940 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 941 942 dma-channels = <12>; 943 dma-channel-mask = <0x3e>; 944 #dma-cells = <3>; 945 946 iommus = <&apps_smmu 0x576 0x0>; 947 dma-coherent; 948 }; 949 950 qupv3_id_0: geniqup@ac0000 { 951 compatible = "qcom,geni-se-qup"; 952 reg = <0x0 0x00ac0000 0x0 0x2000>; 953 954 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 955 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 956 clock-names = "m-ahb", 957 "s-ahb"; 958 959 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 960 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; 961 interconnect-names = "qup-core"; 962 963 iommus = <&apps_smmu 0x563 0>; 964 965 dma-coherent; 966 967 #address-cells = <2>; 968 #size-cells = <2>; 969 ranges; 970 971 status = "disabled"; 972 973 spi0: spi@a80000 { 974 compatible = "qcom,geni-spi"; 975 reg = <0x0 0x00a80000 0x0 0x4000>; 976 977 interrupts = <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 978 979 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 980 clock-names = "se"; 981 982 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 983 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 984 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 985 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 986 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 987 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 988 interconnect-names = "qup-core", 989 "qup-config", 990 "qup-memory"; 991 992 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 993 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 994 dma-names = "tx", 995 "rx"; 996 997 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 998 pinctrl-names = "default"; 999 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 1003 status = "disabled"; 1004 }; 1005 1006 i2c1: i2c@a84000 { 1007 compatible = "qcom,geni-i2c"; 1008 reg = <0x0 0x00a84000 0x0 0x4000>; 1009 1010 interrupts = <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>; 1011 1012 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1013 clock-names = "se"; 1014 1015 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1016 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1017 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1018 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 1019 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1020 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1021 interconnect-names = "qup-core", 1022 "qup-config", 1023 "qup-memory"; 1024 1025 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1026 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1027 dma-names = "tx", 1028 "rx"; 1029 1030 pinctrl-0 = <&qup_i2c1_data_clk>; 1031 pinctrl-names = "default"; 1032 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 1036 status = "disabled"; 1037 }; 1038 1039 i2c3: i2c@a8c000 { 1040 compatible = "qcom,geni-i2c"; 1041 reg = <0x0 0x00a8c000 0x0 0x4000>; 1042 1043 interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>; 1044 1045 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1046 clock-names = "se"; 1047 1048 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1049 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1050 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1051 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 1052 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1053 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1054 interconnect-names = "qup-core", 1055 "qup-config", 1056 "qup-memory"; 1057 1058 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1059 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1060 dma-names = "tx", 1061 "rx"; 1062 1063 pinctrl-0 = <&qup_i2c3_data_clk>; 1064 pinctrl-names = "default"; 1065 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 1069 status = "disabled"; 1070 }; 1071 1072 uart5: serial@a94000 { 1073 compatible = "qcom,geni-debug-uart"; 1074 reg = <0x0 0x00a94000 0x0 0x4000>; 1075 1076 interrupts = <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>; 1077 1078 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1079 clock-names = "se"; 1080 1081 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1082 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1083 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1084 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1085 interconnect-names = "qup-core", 1086 "qup-config"; 1087 1088 pinctrl-0 = <&qup_uart5_default>; 1089 pinctrl-names = "default"; 1090 1091 status = "disabled"; 1092 }; 1093 }; 1094 1095 rng: rng@10c3000 { 1096 compatible = "qcom,milos-trng", "qcom,trng"; 1097 reg = <0x0 0x010c3000 0x0 0x1000>; 1098 }; 1099 1100 mmss_noc: interconnect@1400000 { 1101 compatible = "qcom,milos-mmss-noc"; 1102 reg = <0x0 0x01400000 0x0 0xdb800>; 1103 #interconnect-cells = <2>; 1104 qcom,bcm-voters = <&apps_bcm_voter>; 1105 }; 1106 1107 cnoc_main: interconnect@1500000 { 1108 compatible = "qcom,milos-cnoc-main"; 1109 reg = <0x0 0x01500000 0x0 0x14400>; 1110 #interconnect-cells = <2>; 1111 qcom,bcm-voters = <&apps_bcm_voter>; 1112 }; 1113 1114 cnoc_cfg: interconnect@1600000 { 1115 compatible = "qcom,milos-cnoc-cfg"; 1116 reg = <0x0 0x01600000 0x0 0x6e00>; 1117 #interconnect-cells = <2>; 1118 qcom,bcm-voters = <&apps_bcm_voter>; 1119 }; 1120 1121 system_noc: interconnect@1680000 { 1122 compatible = "qcom,milos-system-noc"; 1123 reg = <0x0 0x01680000 0x0 0x40000>; 1124 #interconnect-cells = <2>; 1125 qcom,bcm-voters = <&apps_bcm_voter>; 1126 }; 1127 1128 pcie_anoc: interconnect@16c0000 { 1129 compatible = "qcom,milos-pcie-anoc"; 1130 reg = <0x0 0x016c0000 0x0 0x12400>; 1131 #interconnect-cells = <2>; 1132 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1133 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1134 qcom,bcm-voters = <&apps_bcm_voter>; 1135 }; 1136 1137 aggre1_noc: interconnect@16e0000 { 1138 compatible = "qcom,milos-aggre1-noc"; 1139 reg = <0x0 0x016e0000 0x0 0x16400>; 1140 #interconnect-cells = <2>; 1141 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1142 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 1143 qcom,bcm-voters = <&apps_bcm_voter>; 1144 }; 1145 1146 aggre2_noc: interconnect@1700000 { 1147 compatible = "qcom,milos-aggre2-noc"; 1148 reg = <0x0 0x01700000 0x0 0x1f400>; 1149 #interconnect-cells = <2>; 1150 clocks = <&rpmhcc RPMH_IPA_CLK>; 1151 qcom,bcm-voters = <&apps_bcm_voter>; 1152 }; 1153 1154 tcsr_mutex: hwlock@1f40000 { 1155 compatible = "qcom,tcsr-mutex"; 1156 reg = <0x0 0x01f40000 0x0 0x20000>; 1157 1158 #hwlock-cells = <1>; 1159 }; 1160 1161 tcsr: clock-controller@1fc0000 { 1162 compatible = "qcom,milos-tcsr", "syscon"; 1163 reg = <0x0 0x01fc0000 0x0 0xa0000>; 1164 1165 clocks = <&rpmhcc RPMH_CXO_CLK>; 1166 1167 #clock-cells = <1>; 1168 #reset-cells = <1>; 1169 }; 1170 1171 remoteproc_adsp: remoteproc@3000000 { 1172 compatible = "qcom,milos-adsp-pas"; 1173 reg = <0x0 0x03000000 0x0 0x10000>; 1174 1175 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1176 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1177 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1178 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1179 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 1180 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 1181 interrupt-names = "wdog", 1182 "fatal", 1183 "ready", 1184 "handover", 1185 "stop-ack", 1186 "shutdown-ack"; 1187 1188 clocks = <&rpmhcc RPMH_CXO_CLK>; 1189 clock-names = "xo"; 1190 1191 power-domains = <&rpmhpd RPMHPD_LCX>, 1192 <&rpmhpd RPMHPD_LMX>; 1193 power-domain-names = "lcx", 1194 "lmx"; 1195 1196 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 1197 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1198 1199 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 1200 1201 qcom,qmp = <&aoss_qmp>; 1202 1203 qcom,smem-states = <&smp2p_adsp_out 0>; 1204 qcom,smem-state-names = "stop"; 1205 1206 status = "disabled"; 1207 1208 glink-edge { 1209 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1210 IPCC_MPROC_SIGNAL_GLINK_QMP 1211 IRQ_TYPE_EDGE_RISING>; 1212 mboxes = <&ipcc IPCC_CLIENT_LPASS 1213 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1214 1215 label = "lpass"; 1216 qcom,remote-pid = <2>; 1217 }; 1218 }; 1219 1220 lpass_ag_noc: interconnect@3c40000 { 1221 compatible = "qcom,milos-lpass-ag-noc"; 1222 reg = <0x0 0x03c40000 0x0 0x17200>; 1223 #interconnect-cells = <2>; 1224 qcom,bcm-voters = <&apps_bcm_voter>; 1225 }; 1226 1227 gpucc: clock-controller@3d90000 { 1228 compatible = "qcom,milos-gpucc"; 1229 reg = <0x0 0x03d90000 0x0 0x9800>; 1230 1231 clocks = <&rpmhcc RPMH_CXO_CLK>, 1232 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1233 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1234 1235 #clock-cells = <1>; 1236 #reset-cells = <1>; 1237 #power-domain-cells = <1>; 1238 }; 1239 1240 adreno_smmu: iommu@3da0000 { 1241 compatible = "qcom,milos-smmu-500", "qcom,adreno-smmu", 1242 "qcom,smmu-500", "arm,mmu-500"; 1243 reg = <0x0 0x03da0000 0x0 0x40000>; 1244 #iommu-cells = <2>; 1245 #global-interrupts = <1>; 1246 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 1247 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 1248 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 1249 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 1250 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 1251 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 1252 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 1253 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 1254 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 1255 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 1256 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 1257 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 1258 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 1259 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 1260 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 1261 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 1262 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 1263 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 1264 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 1265 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 1266 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 1267 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 1268 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 1269 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 1270 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 1271 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 1272 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1273 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1274 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1275 <&gpucc GPU_CC_AHB_CLK>; 1276 clock-names = "hlos", 1277 "bus", 1278 "iface", 1279 "ahb"; 1280 power-domains = <&gpucc GPU_CC_CX_GDSC>; 1281 dma-coherent; 1282 }; 1283 1284 remoteproc_mpss: remoteproc@4080000 { 1285 compatible = "qcom,milos-mpss-pas"; 1286 reg = <0x0 0x04080000 0x0 0x10000>; 1287 1288 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 1289 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1290 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1291 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1292 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1293 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1294 interrupt-names = "wdog", 1295 "fatal", 1296 "ready", 1297 "handover", 1298 "stop-ack", 1299 "shutdown-ack"; 1300 1301 clocks = <&rpmhcc RPMH_CXO_CLK>; 1302 clock-names = "xo"; 1303 1304 power-domains = <&rpmhpd RPMHPD_CX>, 1305 <&rpmhpd RPMHPD_MSS>; 1306 power-domain-names = "cx", 1307 "mss"; 1308 1309 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 1310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1311 1312 memory-region = <&mpss_mem>; 1313 1314 qcom,qmp = <&aoss_qmp>; 1315 1316 qcom,smem-states = <&smp2p_modem_out 0>; 1317 qcom,smem-state-names = "stop"; 1318 1319 status = "disabled"; 1320 1321 glink-edge { 1322 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1323 IPCC_MPROC_SIGNAL_GLINK_QMP 1324 IRQ_TYPE_EDGE_RISING>; 1325 mboxes = <&ipcc IPCC_CLIENT_MPSS 1326 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1327 1328 label = "mpss"; 1329 qcom,remote-pid = <1>; 1330 }; 1331 }; 1332 1333 sdhc_2: mmc@8804000 { 1334 compatible = "qcom,milos-sdhci", "qcom,sdhci-msm-v5"; 1335 reg = <0x0 0x08804000 0x0 0x1000>; 1336 1337 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, 1338 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1339 interrupt-names = "hc_irq", 1340 "pwr_irq"; 1341 1342 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1343 <&gcc GCC_SDCC2_APPS_CLK>, 1344 <&rpmhcc RPMH_CXO_CLK>; 1345 clock-names = "iface", 1346 "core", 1347 "xo"; 1348 1349 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 1350 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1351 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1352 &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1353 interconnect-names = "sdhc-ddr", 1354 "cpu-sdhc"; 1355 1356 power-domains = <&rpmhpd RPMHPD_CX>; 1357 operating-points-v2 = <&sdhc2_opp_table>; 1358 1359 iommus = <&apps_smmu 0x540 0>; 1360 1361 bus-width = <4>; 1362 1363 qcom,dll-config = <0x0007442c>; 1364 qcom,ddr-config = <0x80040868>; 1365 1366 dma-coherent; 1367 1368 status = "disabled"; 1369 1370 sdhc2_opp_table: opp-table { 1371 compatible = "operating-points-v2"; 1372 1373 opp-100000000 { 1374 opp-hz = /bits/ 64 <100000000>; 1375 required-opps = <&rpmhpd_opp_low_svs>; 1376 }; 1377 1378 opp-202000000 { 1379 opp-hz = /bits/ 64 <202000000>; 1380 required-opps = <&rpmhpd_opp_svs_l1>; 1381 }; 1382 }; 1383 }; 1384 1385 usb_1_hsphy: phy@88e3000 { 1386 compatible = "qcom,milos-snps-eusb2-phy", 1387 "qcom,sm8550-snps-eusb2-phy"; 1388 reg = <0x0 0x088e3000 0x0 0x154>; 1389 #phy-cells = <0>; 1390 1391 clocks = <&rpmhcc RPMH_CXO_CLK>; 1392 clock-names = "ref"; 1393 1394 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1395 1396 status = "disabled"; 1397 }; 1398 1399 remoteproc_wpss: remoteproc@8a00000 { 1400 compatible = "qcom,milos-wpss-pas"; 1401 reg = <0x0 0x08a00000 0x0 0x10000>; 1402 1403 interrupts-extended = <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING 0>, 1404 <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>, 1405 <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>, 1406 <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>, 1407 <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>, 1408 <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>; 1409 interrupt-names = "wdog", 1410 "fatal", 1411 "ready", 1412 "handover", 1413 "stop-ack", 1414 "shutdown-ack"; 1415 1416 clocks = <&rpmhcc RPMH_CXO_CLK>; 1417 clock-names = "xo"; 1418 1419 power-domains = <&rpmhpd RPMHPD_CX>, 1420 <&rpmhpd RPMHPD_MX>; 1421 power-domain-names = "cx", 1422 "mx"; 1423 1424 memory-region = <&wpss_mem>; 1425 1426 qcom,qmp = <&aoss_qmp>; 1427 1428 qcom,smem-states = <&smp2p_wpss_out 0>; 1429 qcom,smem-state-names = "stop"; 1430 1431 status = "disabled"; 1432 1433 glink-edge { 1434 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 1435 IPCC_MPROC_SIGNAL_GLINK_QMP 1436 IRQ_TYPE_EDGE_RISING>; 1437 mboxes = <&ipcc IPCC_CLIENT_WPSS 1438 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1439 1440 label = "wpss"; 1441 qcom,remote-pid = <13>; 1442 }; 1443 }; 1444 1445 usb_1: usb@a600000 { 1446 compatible = "qcom,milos-dwc3", "qcom,snps-dwc3"; 1447 reg = <0x0 0x0a600000 0x0 0xfc000>; 1448 1449 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1450 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1451 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1452 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1453 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1454 <&rpmhcc RPMH_CXO_CLK>; 1455 clock-names = "cfg_noc", 1456 "core", 1457 "iface", 1458 "sleep", 1459 "mock_utmi", 1460 "xo"; 1461 1462 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1463 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1464 assigned-clock-rates = <19200000>, <200000000>; 1465 1466 interrupts-extended = <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>, 1467 <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>, 1468 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1469 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1470 <&pdc 25 IRQ_TYPE_LEVEL_HIGH>; 1471 interrupt-names = "dwc_usb3", 1472 "pwr_event", 1473 "dp_hs_phy_irq", 1474 "dm_hs_phy_irq", 1475 "ss_phy_irq"; 1476 1477 iommus = <&apps_smmu 0x40 0x0>; 1478 power-domains = <&gcc USB30_PRIM_GDSC>; 1479 required-opps = <&rpmhpd_opp_nom>; 1480 1481 resets = <&gcc GCC_USB30_PRIM_BCR>; 1482 1483 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 1484 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1485 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1486 &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1487 interconnect-names = "usb-ddr", "apps-usb"; 1488 1489 phys = <&usb_1_hsphy>; 1490 phy-names = "usb2-phy"; 1491 1492 snps,dis-u1-entry-quirk; 1493 snps,dis-u2-entry-quirk; 1494 snps,dis_enblslpm_quirk; 1495 snps,dis_u2_susphy_quirk; 1496 snps,dis_u3_susphy_quirk; 1497 snps,has-lpm-erratum; 1498 snps,hird-threshold = /bits/ 8 <0x0>; 1499 snps,is-utmi-l1-suspend; 1500 snps,parkmode-disable-ss-quirk; 1501 tx-fifo-resize; 1502 dma-coherent; 1503 usb-role-switch; 1504 1505 status = "disabled"; 1506 1507 ports { 1508 #address-cells = <1>; 1509 #size-cells = <0>; 1510 1511 port@0 { 1512 reg = <0>; 1513 1514 usb_1_dwc3_hs: endpoint { 1515 }; 1516 }; 1517 }; 1518 }; 1519 1520 videocc: clock-controller@aaf0000 { 1521 compatible = "qcom,milos-videocc"; 1522 reg = <0x0 0x0aaf0000 0x0 0x10000>; 1523 1524 clocks = <&rpmhcc RPMH_CXO_CLK>, 1525 <&rpmhcc RPMH_CXO_CLK_A>, 1526 <&sleep_clk>, 1527 <&gcc GCC_VIDEO_AHB_CLK>; 1528 1529 #clock-cells = <1>; 1530 #reset-cells = <1>; 1531 #power-domain-cells = <1>; 1532 }; 1533 1534 camcc: clock-controller@adb0000 { 1535 compatible = "qcom,milos-camcc"; 1536 reg = <0x0 0x0adb0000 0x0 0x40000>; 1537 1538 clocks = <&rpmhcc RPMH_CXO_CLK>, 1539 <&sleep_clk>, 1540 <&gcc GCC_CAMERA_AHB_CLK>; 1541 1542 #clock-cells = <1>; 1543 #reset-cells = <1>; 1544 #power-domain-cells = <1>; 1545 }; 1546 1547 dispcc: clock-controller@af00000 { 1548 compatible = "qcom,milos-dispcc"; 1549 reg = <0x0 0x0af00000 0x0 0x20000>; 1550 1551 clocks = <&rpmhcc RPMH_CXO_CLK>, 1552 <&sleep_clk>, 1553 <&gcc GCC_DISP_AHB_CLK>, 1554 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1555 <0>, /* dsi0_phy_pll_out_byteclk */ 1556 <0>, /* dsi0_phy_pll_out_dsiclk */ 1557 <0>, /* dp0_phy_pll_link_clk */ 1558 <0>; /* dp0_phy_pll_vco_div_clk */ 1559 1560 #clock-cells = <1>; 1561 #reset-cells = <1>; 1562 #power-domain-cells = <1>; 1563 }; 1564 1565 pdc: interrupt-controller@b220000 { 1566 compatible = "qcom,milos-pdc", "qcom,pdc"; 1567 reg = <0x0 0x0b220000 0x0 0x30000>, 1568 <0x0 0x174000f0 0x0 0x64>; 1569 interrupt-parent = <&intc>; 1570 1571 qcom,pdc-ranges = <0 480 40>, <40 140 11>, <51 527 47>, 1572 <98 609 31>, <129 63 1>, <130 716 12>, 1573 <142 251 5>; 1574 1575 #interrupt-cells = <2>; 1576 interrupt-controller; 1577 }; 1578 1579 tsens0: thermal-sensor@c228000 { 1580 compatible = "qcom,milos-tsens", "qcom,tsens-v2"; 1581 reg = <0x0 0x0c228000 0x0 0x1000>, 1582 <0x0 0x0c222000 0x0 0x1000>; 1583 1584 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1585 <&intc GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 1586 interrupt-names = "uplow", 1587 "critical"; 1588 1589 #qcom,sensors = <15>; 1590 1591 #thermal-sensor-cells = <1>; 1592 }; 1593 1594 tsens1: thermal-sensor@c229000 { 1595 compatible = "qcom,milos-tsens", "qcom,tsens-v2"; 1596 reg = <0x0 0x0c229000 0x0 0x1000>, 1597 <0x0 0x0c223000 0x0 0x1000>; 1598 1599 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1600 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 1601 interrupt-names = "uplow", 1602 "critical"; 1603 1604 #qcom,sensors = <14>; 1605 1606 #thermal-sensor-cells = <1>; 1607 }; 1608 1609 aoss_qmp: power-management@c300000 { 1610 compatible = "qcom,milos-aoss-qmp", "qcom,aoss-qmp"; 1611 reg = <0x0 0x0c300000 0x0 0x400>; 1612 1613 interrupt-parent = <&ipcc>; 1614 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1615 IRQ_TYPE_EDGE_RISING>; 1616 1617 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1618 1619 #clock-cells = <0>; 1620 }; 1621 1622 sram@c3f0000 { 1623 compatible = "qcom,rpmh-stats"; 1624 reg = <0x0 0x0c3f0000 0x0 0x400>; 1625 }; 1626 1627 spmi_bus: spmi@c400000 { 1628 compatible = "qcom,spmi-pmic-arb"; 1629 reg = <0x0 0x0c400000 0x0 0x3000>, 1630 <0x0 0x0c500000 0x0 0x400000>, 1631 <0x0 0x0c440000 0x0 0x80000>, 1632 <0x0 0x0c4c0000 0x0 0x10000>, 1633 <0x0 0x0c42d000 0x0 0x4000>; 1634 reg-names = "core", 1635 "chnls", 1636 "obsrvr", 1637 "intr", 1638 "cnfg"; 1639 1640 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1641 interrupt-names = "periph_irq"; 1642 1643 qcom,ee = <0>; 1644 qcom,channel = <0>; 1645 qcom,bus-id = <0>; 1646 1647 interrupt-controller; 1648 #interrupt-cells = <4>; 1649 1650 #address-cells = <2>; 1651 #size-cells = <0>; 1652 }; 1653 1654 tlmm: pinctrl@f100000 { 1655 compatible = "qcom,milos-tlmm"; 1656 reg = <0x0 0x0f100000 0x0 0x300000>; 1657 1658 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 1659 1660 gpio-controller; 1661 #gpio-cells = <2>; 1662 1663 interrupt-controller; 1664 #interrupt-cells = <2>; 1665 1666 gpio-ranges = <&tlmm 0 0 168>; 1667 1668 wakeup-parent = <&pdc>; 1669 1670 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1671 /* SDA, SCL */ 1672 pins = "gpio4", "gpio5"; 1673 function = "qup0_se1"; 1674 drive-strength = <2>; 1675 bias-pull-up; 1676 }; 1677 1678 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1679 /* SDA, SCL */ 1680 pins = "gpio15", "gpio16"; 1681 function = "qup0_se3"; 1682 drive-strength = <2>; 1683 bias-pull-up = <2200>; 1684 }; 1685 1686 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1687 /* SDA, SCL */ 1688 pins = "gpio32", "gpio33"; 1689 function = "qup1_se0"; 1690 drive-strength = <2>; 1691 bias-pull-up; 1692 }; 1693 1694 qup_spi0_cs: qup-spi0-cs-state { 1695 pins = "gpio3"; 1696 function = "qup0_se0"; 1697 drive-strength = <6>; 1698 bias-disable; 1699 }; 1700 1701 qup_spi0_data_clk: qup-spi0-data-clk-state { 1702 /* MISO, MOSI, CLK */ 1703 pins = "gpio0", "gpio1", "gpio2"; 1704 function = "qup0_se0"; 1705 drive-strength = <6>; 1706 bias-disable; 1707 }; 1708 1709 qup_uart5_default: qup-uart5-default-state { 1710 /* TX, RX */ 1711 pins = "gpio25", "gpio26"; 1712 function = "qup0_se5"; 1713 drive-strength = <2>; 1714 bias-disable; 1715 }; 1716 1717 qup_uart11_default: qup-uart11-default-state { 1718 /* TX, RX */ 1719 pins = "gpio50", "gpio51"; 1720 function = "qup1_se4"; 1721 drive-strength = <2>; 1722 bias-pull-up; 1723 }; 1724 1725 qup_uart11_cts_rts: qup-uart11-cts-rts-state { 1726 /* CTS, RTS */ 1727 pins = "gpio48", "gpio49"; 1728 function = "qup1_se4"; 1729 drive-strength = <2>; 1730 bias-pull-down; 1731 }; 1732 1733 sdc2_default: sdc2-default-state { 1734 clk-pins { 1735 pins = "gpio62"; 1736 function = "sdc2_clk"; 1737 drive-strength = <16>; 1738 bias-disable; 1739 }; 1740 1741 cmd-pins { 1742 pins = "gpio61"; 1743 function = "sdc2_cmd"; 1744 drive-strength = <10>; 1745 bias-pull-up; 1746 }; 1747 1748 data-pins { 1749 pins = "gpio58", "gpio57", "gpio35", "gpio34"; 1750 function = "sdc2_data"; 1751 drive-strength = <10>; 1752 bias-pull-up; 1753 }; 1754 }; 1755 1756 sdc2_sleep: sdc2-sleep-state { 1757 clk-pins { 1758 pins = "gpio62"; 1759 function = "gpio"; 1760 drive-strength = <2>; 1761 bias-disable; 1762 }; 1763 1764 cmd-pins { 1765 pins = "gpio61"; 1766 function = "gpio"; 1767 drive-strength = <2>; 1768 bias-pull-up; 1769 }; 1770 1771 data-pins { 1772 pins = "gpio58", "gpio57", "gpio35", "gpio34"; 1773 function = "gpio"; 1774 drive-strength = <2>; 1775 bias-pull-up; 1776 }; 1777 }; 1778 }; 1779 1780 apps_smmu: iommu@15000000 { 1781 compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1782 reg = <0x0 0x15000000 0x0 0x100000>; 1783 #iommu-cells = <2>; 1784 #global-interrupts = <1>; 1785 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 1786 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 1787 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 1788 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 1789 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 1790 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 1791 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 1792 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1793 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1794 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 1795 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 1796 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 1797 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1798 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1799 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 1800 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 1801 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 1802 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 1803 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1804 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 1805 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 1806 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 1807 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 1808 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 1809 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 1810 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 1811 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 1812 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 1813 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 1814 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 1815 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 1816 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 1817 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 1818 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 1819 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 1820 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 1821 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 1822 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 1823 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 1824 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 1825 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 1826 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 1827 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 1828 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 1829 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 1830 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 1831 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 1832 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 1833 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 1834 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 1835 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 1836 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 1837 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 1838 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 1839 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 1840 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 1841 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 1842 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 1843 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 1844 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 1845 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 1846 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 1847 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 1848 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 1849 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 1850 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 1851 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 1852 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 1853 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 1854 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 1855 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 1856 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 1857 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 1858 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 1859 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 1860 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 1861 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 1862 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 1863 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 1864 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 1865 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 1866 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 1867 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 1868 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 1869 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 1870 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 1871 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 1872 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 1873 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 1874 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 1875 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 1876 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 1877 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 1878 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 1879 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 1880 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 1881 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 1882 dma-coherent; 1883 }; 1884 1885 intc: interrupt-controller@17100000 { 1886 compatible = "arm,gic-v3"; 1887 reg = <0x0 0x17100000 0x0 0x10000>, 1888 <0x0 0x17180000 0x0 0x200000>; 1889 1890 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1891 1892 #interrupt-cells = <4>; 1893 interrupt-controller; 1894 1895 #redistributor-regions = <1>; 1896 redistributor-stride = <0 0x40000>; 1897 1898 #address-cells = <2>; 1899 #size-cells = <2>; 1900 ranges; 1901 1902 ppi-partitions { 1903 ppi_cluster0: interrupt-partition-0 { 1904 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 1905 }; 1906 1907 ppi_cluster1: interrupt-partition-1 { 1908 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 1909 }; 1910 }; 1911 1912 gic_its: msi-controller@17140000 { 1913 compatible = "arm,gic-v3-its"; 1914 reg = <0x0 0x17140000 0x0 0x20000>; 1915 1916 msi-controller; 1917 #msi-cells = <1>; 1918 }; 1919 }; 1920 1921 timer@17420000 { 1922 compatible = "arm,armv7-timer-mem"; 1923 reg = <0x0 0x17420000 0x0 0x1000>; 1924 1925 ranges = <0 0 0 0x20000000>; 1926 #address-cells = <1>; 1927 #size-cells = <1>; 1928 1929 frame@17421000 { 1930 reg = <0x17421000 0x1000>, 1931 <0x17422000 0x1000>; 1932 1933 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 1934 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1935 1936 frame-number = <0>; 1937 }; 1938 1939 frame@17423000 { 1940 reg = <0x17423000 0x1000>; 1941 1942 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1943 1944 frame-number = <1>; 1945 1946 status = "disabled"; 1947 }; 1948 1949 frame@17425000 { 1950 reg = <0x17425000 0x1000>; 1951 1952 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1953 1954 frame-number = <2>; 1955 1956 status = "disabled"; 1957 }; 1958 1959 frame@17427000 { 1960 reg = <0x17427000 0x1000>; 1961 1962 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 1963 1964 frame-number = <3>; 1965 1966 status = "disabled"; 1967 }; 1968 1969 frame@17429000 { 1970 reg = <0x17429000 0x1000>; 1971 1972 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 1973 1974 frame-number = <4>; 1975 1976 status = "disabled"; 1977 }; 1978 1979 frame@1742b000 { 1980 reg = <0x1742b000 0x1000>; 1981 1982 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 1983 1984 frame-number = <5>; 1985 1986 status = "disabled"; 1987 }; 1988 1989 frame@1742d000 { 1990 reg = <0x1742d000 0x1000>; 1991 1992 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1993 1994 frame-number = <6>; 1995 1996 status = "disabled"; 1997 }; 1998 }; 1999 2000 apps_rsc: rsc@17a00000 { 2001 compatible = "qcom,rpmh-rsc"; 2002 reg = <0x0 0x17a00000 0x0 0x10000>, 2003 <0x0 0x17a10000 0x0 0x10000>, 2004 <0x0 0x17a20000 0x0 0x10000>; 2005 reg-names = "drv-0", 2006 "drv-1", 2007 "drv-2"; 2008 2009 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 2010 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 2011 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 2012 2013 power-domains = <&cluster_pd>; 2014 2015 qcom,tcs-offset = <0xd00>; 2016 qcom,drv-id = <2>; 2017 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 2018 <WAKE_TCS 2>, <CONTROL_TCS 0>; 2019 2020 label = "apps_rsc"; 2021 2022 apps_bcm_voter: bcm-voter { 2023 compatible = "qcom,bcm-voter"; 2024 }; 2025 2026 rpmhcc: clock-controller { 2027 compatible = "qcom,milos-rpmh-clk"; 2028 2029 clocks = <&xo_board>; 2030 clock-names = "xo"; 2031 2032 #clock-cells = <1>; 2033 }; 2034 2035 rpmhpd: power-controller { 2036 compatible = "qcom,milos-rpmhpd"; 2037 #power-domain-cells = <1>; 2038 operating-points-v2 = <&rpmhpd_opp_table>; 2039 2040 rpmhpd_opp_table: opp-table { 2041 compatible = "operating-points-v2"; 2042 2043 rpmhpd_opp_ret: opp-16 { 2044 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2045 }; 2046 2047 rpmhpd_opp_low_svs_d1: opp-56 { 2048 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2049 }; 2050 2051 rpmhpd_opp_low_svs: opp-64 { 2052 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2053 }; 2054 2055 rpmhpd_opp_svs: opp-128 { 2056 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2057 }; 2058 2059 rpmhpd_opp_svs_l1: opp-192 { 2060 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2061 }; 2062 2063 rpmhpd_opp_nom: opp-256 { 2064 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2065 }; 2066 2067 rpmhpd_opp_nom_l1: opp-320 { 2068 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2069 }; 2070 2071 rpmhpd_opp_turbo: opp-384 { 2072 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2073 }; 2074 2075 rpmhpd_opp_turbo_l1: opp-416 { 2076 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2077 }; 2078 }; 2079 }; 2080 }; 2081 2082 cpufreq_hw: cpufreq@17d91000 { 2083 compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; 2084 reg = <0x0 0x17d91000 0x0 0x1000>, 2085 <0x0 0x17d92000 0x0 0x1000>, 2086 <0x0 0x17d93000 0x0 0x1000>; 2087 reg-names = "freq-domain0", 2088 "freq-domain1", 2089 "freq-domain2"; 2090 2091 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 2092 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 2093 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2094 interrupt-names = "dcvsh-irq-0", 2095 "dcvsh-irq-1", 2096 "dcvsh-irq-2"; 2097 2098 clocks = <&rpmhcc RPMH_CXO_CLK>, 2099 <&gcc GCC_GPLL0>; 2100 clock-names = "xo", 2101 "alternate"; 2102 2103 #freq-domain-cells = <1>; 2104 #clock-cells = <1>; 2105 }; 2106 2107 gem_noc: interconnect@24100000 { 2108 compatible = "qcom,milos-gem-noc"; 2109 reg = <0x0 0x24100000 0x0 0xff080>; 2110 #interconnect-cells = <2>; 2111 qcom,bcm-voters = <&apps_bcm_voter>; 2112 }; 2113 2114 nsp_noc: interconnect@320c0000 { 2115 compatible = "qcom,milos-nsp-noc"; 2116 reg = <0x0 0x320c0000 0x0 0xe080>; 2117 #interconnect-cells = <2>; 2118 qcom,bcm-voters = <&apps_bcm_voter>; 2119 }; 2120 2121 remoteproc_cdsp: remoteproc@32300000 { 2122 compatible = "qcom,milos-cdsp-pas"; 2123 reg = <0x0 0x32300000 0x0 0x10000>; 2124 2125 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 2126 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2127 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2128 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2129 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 2130 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 2131 interrupt-names = "wdog", 2132 "fatal", 2133 "ready", 2134 "handover", 2135 "stop-ack", 2136 "shutdown-ack"; 2137 2138 clocks = <&rpmhcc RPMH_CXO_CLK>; 2139 clock-names = "xo"; 2140 2141 power-domains = <&rpmhpd RPMHPD_CX>, 2142 <&rpmhpd RPMHPD_MX>; 2143 power-domain-names = "cx", 2144 "mx"; 2145 2146 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 2147 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2148 2149 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 2150 2151 qcom,qmp = <&aoss_qmp>; 2152 2153 qcom,smem-states = <&smp2p_cdsp_out 0>; 2154 qcom,smem-state-names = "stop"; 2155 2156 status = "disabled"; 2157 2158 glink-edge { 2159 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2160 IPCC_MPROC_SIGNAL_GLINK_QMP 2161 IRQ_TYPE_EDGE_RISING>; 2162 mboxes = <&ipcc IPCC_CLIENT_CDSP 2163 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2164 2165 label = "cdsp"; 2166 qcom,remote-pid = <5>; 2167 }; 2168 }; 2169 }; 2170 2171 thermal-zones { 2172 aoss0-thermal { 2173 thermal-sensors = <&tsens0 0>; 2174 2175 trips { 2176 aoss0-hot { 2177 temperature = <110000>; 2178 hysteresis = <1000>; 2179 type = "hot"; 2180 }; 2181 2182 aoss0-critical { 2183 temperature = <115000>; 2184 hysteresis = <0>; 2185 type = "critical"; 2186 }; 2187 }; 2188 }; 2189 2190 cpuss0-thermal { 2191 thermal-sensors = <&tsens0 1>; 2192 2193 trips { 2194 cpuss0-critical { 2195 temperature = <115000>; 2196 hysteresis = <0>; 2197 type = "critical"; 2198 }; 2199 }; 2200 }; 2201 2202 cpuss1-thermal { 2203 thermal-sensors = <&tsens0 2>; 2204 2205 trips { 2206 cpuss1-critical { 2207 temperature = <115000>; 2208 hysteresis = <0>; 2209 type = "critical"; 2210 }; 2211 }; 2212 }; 2213 2214 cpu4-left-thermal { 2215 thermal-sensors = <&tsens0 3>; 2216 2217 trips { 2218 cpu4-left-critical { 2219 temperature = <110000>; 2220 hysteresis = <1000>; 2221 type = "critical"; 2222 }; 2223 }; 2224 }; 2225 2226 cpu4-right-thermal { 2227 thermal-sensors = <&tsens0 4>; 2228 2229 trips { 2230 cpu4-right-critical { 2231 temperature = <110000>; 2232 hysteresis = <1000>; 2233 type = "critical"; 2234 }; 2235 }; 2236 }; 2237 2238 cpu5-left-thermal { 2239 thermal-sensors = <&tsens0 5>; 2240 2241 trips { 2242 cpu5-left-critical { 2243 temperature = <110000>; 2244 hysteresis = <1000>; 2245 type = "critical"; 2246 }; 2247 }; 2248 }; 2249 2250 cpu5-right-thermal { 2251 thermal-sensors = <&tsens0 6>; 2252 2253 trips { 2254 cpu5-right-critical { 2255 temperature = <110000>; 2256 hysteresis = <1000>; 2257 type = "critical"; 2258 }; 2259 }; 2260 }; 2261 2262 cpu6-left-thermal { 2263 thermal-sensors = <&tsens0 7>; 2264 2265 trips { 2266 cpu6-left-critical { 2267 temperature = <110000>; 2268 hysteresis = <1000>; 2269 type = "critical"; 2270 }; 2271 }; 2272 }; 2273 2274 cpu6-right-thermal { 2275 thermal-sensors = <&tsens0 8>; 2276 2277 trips { 2278 cpu6-right-critical { 2279 temperature = <110000>; 2280 hysteresis = <1000>; 2281 type = "critical"; 2282 }; 2283 }; 2284 }; 2285 2286 cpu7-left-thermal { 2287 thermal-sensors = <&tsens0 9>; 2288 2289 trips { 2290 cpu7-left-critical { 2291 temperature = <110000>; 2292 hysteresis = <1000>; 2293 type = "critical"; 2294 }; 2295 }; 2296 }; 2297 2298 cpu7-right-thermal { 2299 thermal-sensors = <&tsens0 10>; 2300 2301 trips { 2302 cpu7-right-critical { 2303 temperature = <110000>; 2304 hysteresis = <1000>; 2305 type = "critical"; 2306 }; 2307 }; 2308 }; 2309 2310 cpu0-thermal { 2311 thermal-sensors = <&tsens0 11>; 2312 2313 trips { 2314 cpu0-critical { 2315 temperature = <110000>; 2316 hysteresis = <1000>; 2317 type = "critical"; 2318 }; 2319 }; 2320 }; 2321 2322 cpu1-thermal { 2323 thermal-sensors = <&tsens0 12>; 2324 2325 trips { 2326 cpu1-critical { 2327 temperature = <110000>; 2328 hysteresis = <1000>; 2329 type = "critical"; 2330 }; 2331 }; 2332 }; 2333 2334 cpu2-thermal { 2335 thermal-sensors = <&tsens0 13>; 2336 2337 trips { 2338 cpu2-critical { 2339 temperature = <110000>; 2340 hysteresis = <1000>; 2341 type = "critical"; 2342 }; 2343 }; 2344 }; 2345 2346 cpu3-thermal { 2347 thermal-sensors = <&tsens0 14>; 2348 2349 trips { 2350 cpu3-critical { 2351 temperature = <110000>; 2352 hysteresis = <1000>; 2353 type = "critical"; 2354 }; 2355 }; 2356 }; 2357 2358 aoss1-thermal { 2359 thermal-sensors = <&tsens1 0>; 2360 2361 trips { 2362 aoss1-hot { 2363 temperature = <110000>; 2364 hysteresis = <1000>; 2365 type = "hot"; 2366 }; 2367 2368 aoss1-critical { 2369 temperature = <115000>; 2370 hysteresis = <0>; 2371 type = "critical"; 2372 }; 2373 }; 2374 }; 2375 2376 nsphvx0-thermal { 2377 polling-delay-passive = <10>; 2378 2379 thermal-sensors = <&tsens1 1>; 2380 2381 trips { 2382 nsphvx0-hot { 2383 temperature = <110000>; 2384 hysteresis = <1000>; 2385 type = "hot"; 2386 }; 2387 2388 nsphvx0-critical { 2389 temperature = <115000>; 2390 hysteresis = <0>; 2391 type = "critical"; 2392 }; 2393 }; 2394 }; 2395 2396 nsphmx1-thermal { 2397 polling-delay-passive = <10>; 2398 2399 thermal-sensors = <&tsens1 2>; 2400 2401 trips { 2402 nsphmx1-hot { 2403 temperature = <110000>; 2404 hysteresis = <1000>; 2405 type = "hot"; 2406 }; 2407 2408 nsphmx1-critical { 2409 temperature = <115000>; 2410 hysteresis = <0>; 2411 type = "critical"; 2412 }; 2413 }; 2414 }; 2415 2416 nsphmx0-thermal { 2417 polling-delay-passive = <10>; 2418 2419 thermal-sensors = <&tsens1 3>; 2420 2421 trips { 2422 nsphmx0-hot { 2423 temperature = <110000>; 2424 hysteresis = <1000>; 2425 type = "hot"; 2426 }; 2427 2428 nsphmx0-critical { 2429 temperature = <115000>; 2430 hysteresis = <0>; 2431 type = "critical"; 2432 }; 2433 }; 2434 }; 2435 2436 gpuss0-thermal { 2437 polling-delay-passive = <10>; 2438 2439 thermal-sensors = <&tsens1 4>; 2440 2441 trips { 2442 gpu0_alert0: trip-point0 { 2443 temperature = <85000>; 2444 hysteresis = <1000>; 2445 type = "passive"; 2446 }; 2447 2448 trip-point1 { 2449 temperature = <90000>; 2450 hysteresis = <1000>; 2451 type = "hot"; 2452 }; 2453 2454 gpuss0-critical { 2455 temperature = <110000>; 2456 hysteresis = <1000>; 2457 type = "critical"; 2458 }; 2459 }; 2460 }; 2461 2462 gpuss1-thermal { 2463 polling-delay-passive = <10>; 2464 2465 thermal-sensors = <&tsens1 5>; 2466 2467 trips { 2468 gpu1_alert0: trip-point0 { 2469 temperature = <85000>; 2470 hysteresis = <1000>; 2471 type = "passive"; 2472 }; 2473 2474 trip-point1 { 2475 temperature = <90000>; 2476 hysteresis = <1000>; 2477 type = "hot"; 2478 }; 2479 2480 gpuss1-critical { 2481 temperature = <110000>; 2482 hysteresis = <1000>; 2483 type = "critical"; 2484 }; 2485 }; 2486 }; 2487 2488 video-thermal { 2489 thermal-sensors = <&tsens1 7>; 2490 2491 trips { 2492 video-hot { 2493 temperature = <110000>; 2494 hysteresis = <1000>; 2495 type = "hot"; 2496 }; 2497 2498 video-critical { 2499 temperature = <115000>; 2500 hysteresis = <0>; 2501 type = "critical"; 2502 }; 2503 }; 2504 }; 2505 2506 ddr-thermal { 2507 polling-delay-passive = <10>; 2508 2509 thermal-sensors = <&tsens1 8>; 2510 2511 trips { 2512 ddr-hot { 2513 temperature = <110000>; 2514 hysteresis = <1000>; 2515 type = "hot"; 2516 }; 2517 2518 ddr-critical { 2519 temperature = <115000>; 2520 hysteresis = <0>; 2521 type = "critical"; 2522 }; 2523 }; 2524 }; 2525 2526 camera0-thermal { 2527 thermal-sensors = <&tsens1 9>; 2528 2529 trips { 2530 camera0-hot { 2531 temperature = <110000>; 2532 hysteresis = <1000>; 2533 type = "hot"; 2534 }; 2535 2536 camera0-critical { 2537 temperature = <115000>; 2538 hysteresis = <0>; 2539 type = "critical"; 2540 }; 2541 }; 2542 }; 2543 2544 modem0-thermal { 2545 polling-delay-passive = <100>; 2546 2547 thermal-sensors = <&tsens1 10>; 2548 2549 trips { 2550 modem0-hot { 2551 temperature = <110000>; 2552 hysteresis = <1000>; 2553 type = "hot"; 2554 }; 2555 2556 modem0-critical { 2557 temperature = <115000>; 2558 hysteresis = <0>; 2559 type = "critical"; 2560 }; 2561 }; 2562 }; 2563 2564 modem1-thermal { 2565 polling-delay-passive = <100>; 2566 2567 thermal-sensors = <&tsens1 11>; 2568 2569 trips { 2570 modem1-hot { 2571 temperature = <110000>; 2572 hysteresis = <1000>; 2573 type = "hot"; 2574 }; 2575 2576 modem1-critical { 2577 temperature = <115000>; 2578 hysteresis = <0>; 2579 type = "critical"; 2580 }; 2581 }; 2582 }; 2583 2584 modem2-thermal { 2585 polling-delay-passive = <100>; 2586 2587 thermal-sensors = <&tsens1 12>; 2588 2589 trips { 2590 modem2-hot { 2591 temperature = <110000>; 2592 hysteresis = <1000>; 2593 type = "hot"; 2594 }; 2595 2596 modem2-critical { 2597 temperature = <115000>; 2598 hysteresis = <0>; 2599 type = "critical"; 2600 }; 2601 }; 2602 }; 2603 2604 modem3-thermal { 2605 polling-delay-passive = <100>; 2606 2607 thermal-sensors = <&tsens1 13>; 2608 2609 trips { 2610 modem3-hot { 2611 temperature = <110000>; 2612 hysteresis = <1000>; 2613 type = "hot"; 2614 }; 2615 2616 modem3-critical { 2617 temperature = <115000>; 2618 hysteresis = <0>; 2619 type = "critical"; 2620 }; 2621 }; 2622 }; 2623 }; 2624 2625 timer { 2626 compatible = "arm,armv8-timer"; 2627 2628 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 2629 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 2630 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 2631 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; 2632 }; 2633}; 2634