1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,kaanapali-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8750-tcsr.h> 9#include <dt-bindings/firmware/qcom,scm.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 20#include "kaanapali-ipcc.h" 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "qcom,oryon"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 next-level-cache = <&l2_0>; 38 power-domains = <&cpu_pd0>; 39 power-domain-names = "psci"; 40 clocks = <&pdp_scmi_perf 0>; 41 42 l2_0: l2-cache { 43 compatible = "cache"; 44 cache-level = <2>; 45 cache-unified; 46 }; 47 }; 48 49 cpu1: cpu@100 { 50 device_type = "cpu"; 51 compatible = "qcom,oryon"; 52 reg = <0x0 0x100>; 53 enable-method = "psci"; 54 next-level-cache = <&l2_0>; 55 power-domains = <&cpu_pd1>; 56 power-domain-names = "psci"; 57 clocks = <&pdp_scmi_perf 0>; 58 }; 59 60 cpu2: cpu@200 { 61 device_type = "cpu"; 62 compatible = "qcom,oryon"; 63 reg = <0x0 0x200>; 64 enable-method = "psci"; 65 next-level-cache = <&l2_0>; 66 power-domains = <&cpu_pd2>; 67 power-domain-names = "psci"; 68 clocks = <&pdp_scmi_perf 0>; 69 }; 70 71 cpu3: cpu@300 { 72 device_type = "cpu"; 73 compatible = "qcom,oryon"; 74 reg = <0x0 0x300>; 75 enable-method = "psci"; 76 next-level-cache = <&l2_0>; 77 power-domains = <&cpu_pd3>; 78 power-domain-names = "psci"; 79 clocks = <&pdp_scmi_perf 0>; 80 }; 81 82 cpu4: cpu@400 { 83 device_type = "cpu"; 84 compatible = "qcom,oryon"; 85 reg = <0x0 0x400>; 86 enable-method = "psci"; 87 next-level-cache = <&l2_0>; 88 power-domains = <&cpu_pd4>; 89 power-domain-names = "psci"; 90 clocks = <&pdp_scmi_perf 0>; 91 }; 92 93 cpu5: cpu@500 { 94 device_type = "cpu"; 95 compatible = "qcom,oryon"; 96 reg = <0x0 0x500>; 97 enable-method = "psci"; 98 next-level-cache = <&l2_0>; 99 power-domains = <&cpu_pd5>; 100 power-domain-names = "psci"; 101 clocks = <&pdp_scmi_perf 0>; 102 }; 103 104 cpu6: cpu@10000 { 105 device_type = "cpu"; 106 compatible = "qcom,oryon"; 107 reg = <0x0 0x10000>; 108 enable-method = "psci"; 109 next-level-cache = <&l2_1>; 110 power-domains = <&cpu_pd6>; 111 power-domain-names = "psci"; 112 clocks = <&pdp_scmi_perf 1>; 113 114 l2_1: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 }; 119 }; 120 121 cpu7: cpu@10100 { 122 device_type = "cpu"; 123 compatible = "qcom,oryon"; 124 reg = <0x0 0x10100>; 125 enable-method = "psci"; 126 next-level-cache = <&l2_1>; 127 power-domains = <&cpu_pd7>; 128 power-domain-names = "psci"; 129 clocks = <&pdp_scmi_perf 1>; 130 }; 131 132 cpu-map { 133 cluster0 { 134 core0 { 135 cpu = <&cpu0>; 136 }; 137 138 core1 { 139 cpu = <&cpu1>; 140 }; 141 142 core2 { 143 cpu = <&cpu2>; 144 }; 145 146 core3 { 147 cpu = <&cpu3>; 148 }; 149 150 core4 { 151 cpu = <&cpu4>; 152 }; 153 154 core5 { 155 cpu = <&cpu5>; 156 }; 157 }; 158 159 cluster1 { 160 core0 { 161 cpu = <&cpu6>; 162 }; 163 164 core1 { 165 cpu = <&cpu7>; 166 }; 167 }; 168 }; 169 170 idle-states { 171 entry-method = "psci"; 172 173 cluster0_c4: cpu-sleep-0 { 174 compatible = "arm,idle-state"; 175 idle-state-name = "retention"; 176 arm,psci-suspend-param = <0x00000004>; 177 entry-latency-us = <93>; 178 exit-latency-us = <129>; 179 min-residency-us = <560>; 180 }; 181 182 cluster1_c4: cpu-sleep-1 { 183 compatible = "arm,idle-state"; 184 idle-state-name = "retention"; 185 arm,psci-suspend-param = <0x00000004>; 186 entry-latency-us = <172>; 187 exit-latency-us = <130>; 188 min-residency-us = <686>; 189 }; 190 }; 191 192 domain-idle-states { 193 cluster_cl5: cluster-sleep-0 { 194 compatible = "domain-idle-state"; 195 arm,psci-suspend-param = <0x01000054>; 196 entry-latency-us = <2150>; 197 exit-latency-us = <1983>; 198 min-residency-us = <9144>; 199 }; 200 201 domain_ss3: domain-sleep-0 { 202 compatible = "domain-idle-state"; 203 arm,psci-suspend-param = <0x0200c354>; 204 entry-latency-us = <2800>; 205 exit-latency-us = <4400>; 206 min-residency-us = <10150>; 207 }; 208 }; 209 }; 210 211 firmware { 212 scm: scm { 213 compatible = "qcom,scm-kaanapali", "qcom,scm"; 214 qcom,dload-mode = <&tcsr 0x19000>; 215 interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 217 }; 218 219 scmi: scmi { 220 compatible = "arm,scmi"; 221 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 222 mbox-names = "tx", "rx"; 223 shmem = <&pdp_tx>, <&pdp_rx>; 224 225 #address-cells = <1>; 226 #size-cells = <0>; 227 228 pdp_scmi_perf: protocol@13 { 229 reg = <0x13>; 230 #clock-cells = <1>; 231 }; 232 }; 233 }; 234 235 clk_virt: interconnect-0 { 236 compatible = "qcom,kaanapali-clk-virt"; 237 #interconnect-cells = <2>; 238 qcom,bcm-voters = <&apps_bcm_voter>; 239 }; 240 241 mc_virt: interconnect-1 { 242 compatible = "qcom,kaanapali-mc-virt"; 243 #interconnect-cells = <2>; 244 qcom,bcm-voters = <&apps_bcm_voter>; 245 }; 246 247 memory@a0000000 { 248 device_type = "memory"; 249 /* We expect the bootloader to fill in the size */ 250 reg = <0x0 0xa0000000 0x0 0x0>; 251 }; 252 253 pmu { 254 compatible = "arm,armv8-pmuv3"; 255 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 256 }; 257 258 psci { 259 compatible = "arm,psci-1.0"; 260 method = "smc"; 261 262 cpu_pd0: power-domain-cpu0 { 263 #power-domain-cells = <0>; 264 power-domains = <&cluster_pd>; 265 domain-idle-states = <&cluster0_c4>; 266 }; 267 268 cpu_pd1: power-domain-cpu1 { 269 #power-domain-cells = <0>; 270 power-domains = <&cluster_pd>; 271 domain-idle-states = <&cluster0_c4>; 272 }; 273 274 cpu_pd2: power-domain-cpu2 { 275 #power-domain-cells = <0>; 276 power-domains = <&cluster_pd>; 277 domain-idle-states = <&cluster0_c4>; 278 }; 279 280 cpu_pd3: power-domain-cpu3 { 281 #power-domain-cells = <0>; 282 power-domains = <&cluster_pd>; 283 domain-idle-states = <&cluster0_c4>; 284 }; 285 286 cpu_pd4: power-domain-cpu4 { 287 #power-domain-cells = <0>; 288 power-domains = <&cluster_pd>; 289 domain-idle-states = <&cluster0_c4>; 290 }; 291 292 cpu_pd5: power-domain-cpu5 { 293 #power-domain-cells = <0>; 294 power-domains = <&cluster_pd>; 295 domain-idle-states = <&cluster0_c4>; 296 }; 297 298 cpu_pd6: power-domain-cpu6 { 299 #power-domain-cells = <0>; 300 power-domains = <&cluster_pd>; 301 domain-idle-states = <&cluster1_c4>; 302 }; 303 304 cpu_pd7: power-domain-cpu7 { 305 #power-domain-cells = <0>; 306 power-domains = <&cluster_pd>; 307 domain-idle-states = <&cluster1_c4>; 308 }; 309 310 cluster_pd: power-domain-cluster { 311 #power-domain-cells = <0>; 312 domain-idle-states = <&cluster_cl5>; 313 power-domains = <&system_pd>; 314 }; 315 316 system_pd: power-domain-system { 317 #power-domain-cells = <0>; 318 domain-idle-states = <&domain_ss3>; 319 }; 320 }; 321 322 reserved-memory { 323 #address-cells = <2>; 324 #size-cells = <2>; 325 ranges; 326 327 pdp_mem: pdp@81300000 { 328 reg = <0x0 0x81300000 0x0 0x100000>; 329 no-map; 330 }; 331 332 aop_cmd_db_mem: aop-cmd-db@81c60000 { 333 compatible = "qcom,cmd-db"; 334 reg = <0x0 0x81c60000 0x0 0x20000>; 335 no-map; 336 }; 337 338 smem_mem: smem@81d00000 { 339 compatible = "qcom,smem"; 340 reg = <0x0 0x81d00000 0x0 0x200000>; 341 hwlocks = <&tcsr_mutex 3>; 342 no-map; 343 }; 344 345 pdp_ns_shared_mem: pdp-ns-shared@81f00000 { 346 reg = <0x0 0x81f00000 0x0 0x100000>; 347 no-map; 348 }; 349 350 dsm_partition_1_mem: dsm-partition-1@84a00000 { 351 reg = <0x0 0x84a00000 0x0 0x5500000>; 352 no-map; 353 }; 354 355 dsm_partition_2_mem: dsm-partition-2@89f00000 { 356 reg = <0x0 0x89f00000 0x0 0xa80000>; 357 no-map; 358 }; 359 360 mpss_mem: mpss@8aa00000 { 361 reg = <0x0 0x8aa00000 0x0 0xeb00000>; 362 no-map; 363 }; 364 365 q6_mpss_dtb_mem: q6-mpss-dtb@99500000 { 366 reg = <0x0 0x99500000 0x0 0x80000>; 367 no-map; 368 }; 369 370 ipa_fw_mem: ipa-fw@99580000 { 371 reg = <0x0 0x99580000 0x0 0x10000>; 372 no-map; 373 }; 374 375 ipa_gsi_mem: ipa-gsi@99590000 { 376 reg = <0x0 0x99590000 0x0 0xa000>; 377 no-map; 378 }; 379 380 gpu_microcode_mem: gpu-microcode@9959a000 { 381 reg = <0x0 0x9959a000 0x0 0x2000>; 382 no-map; 383 }; 384 385 camera_mem: camera@99600000 { 386 reg = <0x0 0x99600000 0x0 0x800000>; 387 no-map; 388 }; 389 390 camera_2_mem: camera-2@99e00000 { 391 reg = <0x0 0x99e00000 0x0 0x800000>; 392 no-map; 393 }; 394 395 video_mem: video@9a600000 { 396 reg = <0x0 0x9a600000 0x0 0x800000>; 397 no-map; 398 }; 399 400 cvp_mem: cvp@9ae00000 { 401 reg = <0x0 0x9ae00000 0x0 0x700000>; 402 no-map; 403 }; 404 405 cdsp_mem: cdsp@9b500000 { 406 reg = <0x0 0x9b500000 0x0 0x1900000>; 407 no-map; 408 }; 409 410 q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 { 411 reg = <0x0 0x9ce00000 0x0 0x80000>; 412 no-map; 413 }; 414 415 soccp_mem: soccp@a03d0000 { 416 reg = <0x0 0xa03d0000 0x0 0x500000>; 417 no-map; 418 }; 419 420 soccp_dtb_mem: soccp-dtb@a08d0000 { 421 reg = <0x0 0xa08d0000 0x0 0x40000>; 422 no-map; 423 }; 424 425 q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 { 426 reg = <0x0 0xa1380000 0x0 0x80000>; 427 no-map; 428 }; 429 430 adspslpi_mem: adspslpi@a1400000 { 431 reg = <0x0 0xa1400000 0x0 0x4c00000>; 432 no-map; 433 }; 434 435 rmtfs_mem: rmtfs@d7c00000 { 436 compatible = "qcom,rmtfs-mem"; 437 reg = <0x0 0xd7c00000 0x0 0x400000>; 438 no-map; 439 440 qcom,client-id = <1>; 441 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 442 }; 443 }; 444 445 soc: soc@0 { 446 compatible = "simple-bus"; 447 448 #address-cells = <2>; 449 #size-cells = <2>; 450 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 451 ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 452 453 gcc: clock-controller@100000 { 454 compatible = "qcom,kaanapali-gcc"; 455 reg = <0x0 0x00100000 0x0 0x1f4200>; 456 457 clocks = <&bi_tcxo_div2>, 458 <&bi_tcxo_ao_div2>, 459 <&sleep_clk>, 460 <&pcie0_phy>, 461 <&ufs_mem_phy 0>, 462 <&ufs_mem_phy 1>, 463 <&ufs_mem_phy 2>, 464 <0>; 465 466 #clock-cells = <1>; 467 #reset-cells = <1>; 468 #power-domain-cells = <1>; 469 }; 470 471 qupv3_1: geniqup@ac0000 { 472 compatible = "qcom,geni-se-qup"; 473 reg = <0x0 0x00ac0000 0x0 0x2000>; 474 475 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, 476 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 477 clock-names = "m-ahb", 478 "s-ahb"; 479 480 iommus = <&apps_smmu 0xa3 0x0>; 481 482 dma-coherent; 483 484 #address-cells = <2>; 485 #size-cells = <2>; 486 ranges; 487 488 uart7: serial@a9c000 { 489 compatible = "qcom,geni-debug-uart"; 490 reg = <0x0 0x00a9c000 0x0 0x4000>; 491 492 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 493 494 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 495 clock-names = "se"; 496 497 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 498 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 499 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 500 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 501 interconnect-names = "qup-core", 502 "qup-config"; 503 504 pinctrl-0 = <&qup_uart7_default>; 505 pinctrl-names = "default"; 506 507 status = "disabled"; 508 }; 509 }; 510 511 ipcc: mailbox@1106000 { 512 compatible = "qcom,kaanapali-ipcc", "qcom,ipcc"; 513 reg = <0x0 0x01106000 0x0 0x1000>; 514 515 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-controller; 517 #interrupt-cells = <3>; 518 519 #mbox-cells = <2>; 520 }; 521 522 cnoc_main: interconnect@1500000 { 523 compatible = "qcom,kaanapali-cnoc-main"; 524 reg = <0x0 0x01500000 0x0 0x1a080>; 525 qcom,bcm-voters = <&apps_bcm_voter>; 526 #interconnect-cells = <2>; 527 }; 528 529 config_noc: interconnect@1600000 { 530 compatible = "qcom,kaanapali-cnoc-cfg"; 531 reg = <0x0 0x01600000 0x0 0x6200>; 532 qcom,bcm-voters = <&apps_bcm_voter>; 533 #interconnect-cells = <2>; 534 }; 535 536 system_noc: interconnect@1680000 { 537 compatible = "qcom,kaanapali-system-noc"; 538 reg = <0x0 0x01680000 0x0 0x1f080>; 539 qcom,bcm-voters = <&apps_bcm_voter>; 540 #interconnect-cells = <2>; 541 }; 542 543 pcie_noc: interconnect@16c0000 { 544 compatible = "qcom,kaanapali-pcie-anoc"; 545 reg = <0x0 0x016c0000 0x0 0x11400>; 546 qcom,bcm-voters = <&apps_bcm_voter>; 547 #interconnect-cells = <2>; 548 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 549 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 550 }; 551 552 aggre_noc: interconnect@16e0000 { 553 compatible = "qcom,kaanapali-aggre-noc"; 554 reg = <0x0 0x016e0000 0x0 0x42400>; 555 qcom,bcm-voters = <&apps_bcm_voter>; 556 #interconnect-cells = <2>; 557 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 558 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 559 <&rpmhcc RPMH_IPA_CLK>; 560 }; 561 562 mmss_noc: interconnect@1780000 { 563 compatible = "qcom,kaanapali-mmss-noc"; 564 reg = <0x0 0x01780000 0x0 0x5b800>; 565 qcom,bcm-voters = <&apps_bcm_voter>; 566 #interconnect-cells = <2>; 567 }; 568 569 pcie0: pcie@1c00000 { 570 device_type = "pci"; 571 compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; 572 reg = <0x0 0x01c00000 0x0 0x3000>, 573 <0x0 0x40000000 0x0 0xf1d>, 574 <0x0 0x40000f20 0x0 0xa8>, 575 <0x0 0x40001000 0x0 0x1000>, 576 <0x0 0x40100000 0x0 0x100000>, 577 <0x0 0x01c03000 0x0 0x1000>; 578 reg-names = "parf", 579 "dbi", 580 "elbi", 581 "atu", 582 "config", 583 "mhi"; 584 #address-cells = <3>; 585 #size-cells = <2>; 586 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 587 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>; 588 589 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 598 interrupt-names = "msi0", 599 "msi1", 600 "msi2", 601 "msi3", 602 "msi4", 603 "msi5", 604 "msi6", 605 "msi7", 606 "global"; 607 608 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 609 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 610 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 611 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 612 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 613 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 614 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 615 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 616 clock-names = "aux", 617 "cfg", 618 "bus_master", 619 "bus_slave", 620 "slave_q2a", 621 "ddrss_sf_tbu", 622 "noc_aggr", 623 "cnoc_sf_axi"; 624 625 resets = <&gcc GCC_PCIE_0_BCR>, 626 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 627 reset-names = "pci", 628 "link_down"; 629 630 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 632 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 633 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 634 interconnect-names = "pcie-mem", 635 "cpu-pcie"; 636 637 power-domains = <&gcc GCC_PCIE_0_GDSC>; 638 639 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 640 641 operating-points-v2 = <&pcie0_opp_table>; 642 643 iommu-map = <0 &apps_smmu 0x1400 0x1>, 644 <0x100 &apps_smmu 0x1401 0x1>; 645 646 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 647 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 648 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 649 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 650 interrupt-map-mask = <0 0 0 0x7>; 651 #interrupt-cells = <1>; 652 653 msi-map = <0x0 &gic_its 0x1400 0x1>, 654 <0x100 &gic_its 0x1401 0x1>; 655 msi-map-mask = <0xff00>; 656 max-link-speed = <3>; 657 linux,pci-domain = <0>; 658 num-lanes = <2>; 659 bus-range = <0x00 0xff>; 660 661 dma-coherent; 662 663 status = "disabled"; 664 665 pcie0_opp_table: opp-table { 666 compatible = "operating-points-v2"; 667 668 /* GEN 1 x1 */ 669 opp-2500000 { 670 opp-hz = /bits/ 64 <2500000>; 671 required-opps = <&rpmhpd_opp_low_svs>; 672 opp-peak-kBps = <250000 1>; 673 }; 674 675 /* GEN 1 x2 and GEN 2 x1 */ 676 opp-5000000 { 677 opp-hz = /bits/ 64 <5000000>; 678 required-opps = <&rpmhpd_opp_low_svs>; 679 opp-peak-kBps = <500000 1>; 680 }; 681 682 /* GEN 2 x2 */ 683 opp-10000000 { 684 opp-hz = /bits/ 64 <10000000>; 685 required-opps = <&rpmhpd_opp_low_svs>; 686 opp-peak-kBps = <1000000 1>; 687 }; 688 689 /* GEN 3 x1 */ 690 opp-8000000 { 691 opp-hz = /bits/ 64 <8000000>; 692 required-opps = <&rpmhpd_opp_nom>; 693 opp-peak-kBps = <984500 1>; 694 }; 695 696 /* GEN 3 x2 */ 697 opp-16000000 { 698 opp-hz = /bits/ 64 <16000000>; 699 required-opps = <&rpmhpd_opp_nom>; 700 opp-peak-kBps = <1969000 1>; 701 }; 702 }; 703 704 pcie_port0: pcie@0 { 705 device_type = "pci"; 706 reg = <0x0 0x0 0x0 0x0 0x0>; 707 bus-range = <0x01 0xff>; 708 709 #address-cells = <3>; 710 #size-cells = <2>; 711 ranges; 712 phys = <&pcie0_phy>; 713 }; 714 }; 715 716 pcie0_phy: phy@1c06000 { 717 compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy"; 718 reg = <0x0 0x01c06000 0x0 0x2000>; 719 720 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 721 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 722 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 723 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 724 <&gcc GCC_PCIE_0_PIPE_CLK>; 725 clock-names = "aux", 726 "cfg_ahb", 727 "ref", 728 "rchng", 729 "pipe"; 730 731 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 732 assigned-clock-rates = <100000000>; 733 734 resets = <&gcc GCC_PCIE_0_PHY_BCR>, 735 <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; 736 reset-names = "phy", 737 "phy_nocsr"; 738 739 power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; 740 741 #clock-cells = <0>; 742 clock-output-names = "pcie0_pipe_clk"; 743 744 #phy-cells = <0>; 745 746 status = "disabled"; 747 }; 748 749 ufs_mem_phy: phy@1d80000 { 750 compatible = "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy"; 751 reg = <0x0 0x01d80000 0x0 0x2000>; 752 753 clocks = <&rpmhcc RPMH_CXO_CLK>, 754 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 755 <&tcsr TCSR_UFS_CLKREF_EN>; 756 757 clock-names = "ref", 758 "ref_aux", 759 "qref"; 760 761 resets = <&ufs_mem_hc 0>; 762 reset-names = "ufsphy"; 763 764 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 765 766 #clock-cells = <1>; 767 #phy-cells = <0>; 768 769 status = "disabled"; 770 }; 771 772 ufs_mem_hc: ufs@1d84000 { 773 compatible = "qcom,kaanapali-ufshc", 774 "qcom,ufshc", 775 "jedec,ufs-2.0"; 776 reg = <0x0 0x01d84000 0x0 0x3000>; 777 778 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 779 780 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 781 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 782 <&gcc GCC_UFS_PHY_AHB_CLK>, 783 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 784 <&rpmhcc RPMH_LN_BB_CLK3>, 785 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 786 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 787 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 788 clock-names = "core_clk", 789 "bus_aggr_clk", 790 "iface_clk", 791 "core_clk_unipro", 792 "ref_clk", 793 "tx_lane0_sync_clk", 794 "rx_lane0_sync_clk", 795 "rx_lane1_sync_clk"; 796 797 operating-points-v2 = <&ufs_opp_table>; 798 799 resets = <&gcc GCC_UFS_PHY_BCR>; 800 reset-names = "rst"; 801 802 interconnects = <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 803 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 804 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 805 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 806 interconnect-names = "ufs-ddr", 807 "cpu-ufs"; 808 809 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 810 required-opps = <&rpmhpd_opp_nom>; 811 812 iommus = <&apps_smmu 0x60 0x0>; 813 dma-coherent; 814 815 lanes-per-direction = <2>; 816 qcom,ice = <&ice>; 817 818 phys = <&ufs_mem_phy>; 819 phy-names = "ufsphy"; 820 821 #reset-cells = <1>; 822 823 status = "disabled"; 824 825 ufs_opp_table: opp-table { 826 compatible = "operating-points-v2"; 827 828 opp-75000000 { 829 opp-hz = /bits/ 64 <75000000>, 830 /bits/ 64 <0>, 831 /bits/ 64 <0>, 832 /bits/ 64 <75000000>, 833 /bits/ 64 <0>, 834 /bits/ 64 <0>, 835 /bits/ 64 <0>, 836 /bits/ 64 <0>; 837 required-opps = <&rpmhpd_opp_low_svs_d1>; 838 }; 839 840 opp-100000000 { 841 opp-hz = /bits/ 64 <100000000>, 842 /bits/ 64 <0>, 843 /bits/ 64 <0>, 844 /bits/ 64 <100000000>, 845 /bits/ 64 <0>, 846 /bits/ 64 <0>, 847 /bits/ 64 <0>, 848 /bits/ 64 <0>; 849 required-opps = <&rpmhpd_opp_low_svs>; 850 }; 851 852 opp-403000000 { 853 opp-hz = /bits/ 64 <403000000>, 854 /bits/ 64 <0>, 855 /bits/ 64 <0>, 856 /bits/ 64 <403000000>, 857 /bits/ 64 <0>, 858 /bits/ 64 <0>, 859 /bits/ 64 <0>, 860 /bits/ 64 <0>; 861 required-opps = <&rpmhpd_opp_nom>; 862 }; 863 }; 864 }; 865 866 ice: crypto@1d88000 { 867 compatible = "qcom,kaanapali-inline-crypto-engine", 868 "qcom,inline-crypto-engine"; 869 reg = <0x0 0x01d88000 0x0 0x18000>; 870 871 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 872 }; 873 874 tcsr_mutex: hwlock@1f40000 { 875 compatible = "qcom,tcsr-mutex"; 876 reg = <0x0 0x01f40000 0x0 0x20000>; 877 #hwlock-cells = <1>; 878 }; 879 880 tcsr: clock-controller@1fc0000 { 881 compatible = "qcom,kaanapali-tcsr", "syscon"; 882 reg = <0x0 0x01fc0000 0x0 0x30000>; 883 884 clocks = <&rpmhcc RPMH_CXO_CLK>; 885 886 #clock-cells = <1>; 887 #reset-cells = <1>; 888 }; 889 890 lpass_lpiaon_noc: interconnect@7400000 { 891 compatible = "qcom,kaanapali-lpass-lpiaon-noc"; 892 reg = <0x0 0x07400000 0x0 0x19080>; 893 qcom,bcm-voters = <&apps_bcm_voter>; 894 #interconnect-cells = <2>; 895 }; 896 897 lpass_lpicx_noc: interconnect@7420000 { 898 compatible = "qcom,kaanapali-lpass-lpicx-noc"; 899 reg = <0x0 0x07420000 0x0 0x44080>; 900 qcom,bcm-voters = <&apps_bcm_voter>; 901 #interconnect-cells = <2>; 902 }; 903 904 lpass_ag_noc: interconnect@7f40000 { 905 compatible = "qcom,kaanapali-lpass-ag-noc"; 906 reg = <0x0 0x07f40000 0x0 0xe080>; 907 qcom,bcm-voters = <&apps_bcm_voter>; 908 #interconnect-cells = <2>; 909 }; 910 911 sdhc_2: mmc@8804000 { 912 compatible = "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5"; 913 reg = <0x0 0x08804000 0x0 0x1000>; 914 915 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "hc_irq", "pwr_irq"; 918 919 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 920 <&gcc GCC_SDCC2_APPS_CLK>, 921 <&rpmhcc RPMH_CXO_CLK>; 922 clock-names = "iface", "core", "xo"; 923 924 interconnects = <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 926 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 927 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 928 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 929 930 power-domains = <&rpmhpd RPMHPD_CX>; 931 operating-points-v2 = <&sdhc2_opp_table>; 932 933 qcom,dll-config = <0x0007442c>; 934 qcom,ddr-config = <0x80040868>; 935 936 iommus = <&apps_smmu 0x540 0x0>; 937 dma-coherent; 938 939 resets = <&gcc GCC_SDCC2_BCR>; 940 status = "disabled"; 941 942 sdhc2_opp_table: opp-table { 943 compatible = "operating-points-v2"; 944 945 opp-100000000 { 946 opp-hz = /bits/ 64 <100000000>; 947 opp-peak-kBps = <160000 100000>; 948 opp-avg-kBps = <50000 0>; 949 required-opps = <&rpmhpd_opp_nom>; 950 }; 951 952 opp-202000000 { 953 opp-hz = /bits/ 64 <202000000>; 954 opp-peak-kBps = <200000 120000>; 955 opp-avg-kBps = <104000 0>; 956 required-opps = <&rpmhpd_opp_nom>; 957 }; 958 }; 959 }; 960 961 pdc: interrupt-controller@b220000 { 962 compatible = "qcom,kaanapali-pdc", "qcom,pdc"; 963 reg = <0x0 0x0b220000 0x0 0x10000>, 964 <0x0 0x179600f0 0x0 0xf4>; 965 966 qcom,pdc-ranges = <0 745 38>, 967 <40 785 11>, 968 <51 527 4>, 969 <58 534 2>, 970 <61 537 20>, 971 <84 559 14>, 972 <98 609 32>, 973 <130 717 12>, 974 <142 251 5>, 975 <147 796 16>, 976 <163 783 2>, 977 <165 531 2>, 978 <167 536 1>, 979 <168 557 2>, 980 <170 415 1>, 981 <171 438 1>, 982 <172 579 1>, 983 <173 703 1>, 984 <174 708 1>, 985 <175 714 1>, 986 <176 68 1>, 987 <177 86 1>, 988 <178 96 1>, 989 <179 249 1>; 990 #interrupt-cells = <2>; 991 interrupt-parent = <&intc>; 992 interrupt-controller; 993 }; 994 995 aoss_qmp: power-management@c300000 { 996 compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; 997 reg = <0x0 0x0c300000 0x0 0x400>; 998 999 interrupts-extended = <&ipcc IPCC_MPROC_AOP 1000 IPCC_MPROC_SIGNAL_GLINK_QMP 1001 IRQ_TYPE_EDGE_RISING>; 1002 1003 mboxes = <&ipcc IPCC_MPROC_AOP 1004 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1005 1006 #clock-cells = <0>; 1007 }; 1008 1009 tlmm: pinctrl@f100000 { 1010 compatible = "qcom,kaanapali-tlmm"; 1011 reg = <0x0 0x0f100000 0x0 0x300000>; 1012 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1013 gpio-controller; 1014 #gpio-cells = <2>; 1015 gpio-ranges = <&tlmm 0 0 218>; 1016 interrupt-controller; 1017 #interrupt-cells = <2>; 1018 wakeup-parent = <&pdc>; 1019 1020 qup_uart7_default: qup-uart7-state { 1021 /* TX, RX */ 1022 pins = "gpio62", "gpio63"; 1023 function = "qup1_se7"; 1024 drive-strength = <2>; 1025 bias-disable; 1026 }; 1027 1028 sdc2_default: sdc2-default-state { 1029 clk-pins { 1030 pins = "sdc2_clk"; 1031 drive-strength = <16>; 1032 bias-disable; 1033 }; 1034 1035 cmd-pins { 1036 pins = "sdc2_cmd"; 1037 drive-strength = <10>; 1038 bias-pull-up; 1039 }; 1040 1041 data-pins { 1042 pins = "sdc2_data"; 1043 drive-strength = <10>; 1044 bias-pull-up; 1045 }; 1046 1047 card-detect-pins { 1048 pins = "gpio55"; 1049 function = "gpio"; 1050 drive-strength = <2>; 1051 bias-pull-up; 1052 }; 1053 }; 1054 1055 sdc2_sleep: sdc2-sleep-state { 1056 clk-pins { 1057 pins = "sdc2_clk"; 1058 drive-strength = <2>; 1059 bias-disable; 1060 }; 1061 1062 cmd-pins { 1063 pins = "sdc2_cmd"; 1064 drive-strength = <2>; 1065 bias-pull-up; 1066 }; 1067 1068 data-pins { 1069 pins = "sdc2_data"; 1070 drive-strength = <2>; 1071 bias-pull-up; 1072 }; 1073 1074 card-detect-pins { 1075 pins = "gpio55"; 1076 function = "gpio"; 1077 drive-strength = <2>; 1078 bias-pull-up; 1079 }; 1080 }; 1081 }; 1082 1083 sram@14680000 { 1084 compatible = "qcom,kaanapali-imem", "mmio-sram"; 1085 reg = <0x0 0x14680000 0x0 0x1000>; 1086 ranges = <0x0 0x0 0x14680000 0x1000>; 1087 1088 no-memory-wc; 1089 1090 #address-cells = <1>; 1091 #size-cells = <1>; 1092 1093 pil-sram@94c { 1094 compatible = "qcom,pil-reloc-info"; 1095 reg = <0x94c 0xc8>; 1096 }; 1097 }; 1098 1099 apps_smmu: iommu@15000000 { 1100 compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1101 reg = <0x0 0x15000000 0x0 0x100000>; 1102 1103 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 1216 1217 #iommu-cells = <2>; 1218 #global-interrupts = <1>; 1219 1220 dma-coherent; 1221 }; 1222 1223 intc: interrupt-controller@17000000 { 1224 compatible = "arm,gic-v3"; 1225 reg = <0x0 0x17000000 0x0 0x10000>, 1226 <0x0 0x17080000 0x0 0x200000>; 1227 1228 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1229 1230 #interrupt-cells = <3>; 1231 interrupt-controller; 1232 1233 #redistributor-regions = <1>; 1234 redistributor-stride = <0x0 0x40000>; 1235 1236 #address-cells = <2>; 1237 #size-cells = <2>; 1238 ranges; 1239 1240 gic_its: msi-controller@17040000 { 1241 compatible = "arm,gic-v3-its"; 1242 reg = <0x0 0x17040000 0x0 0x20000>; 1243 1244 msi-controller; 1245 #msi-cells = <1>; 1246 }; 1247 }; 1248 1249 watchdog@17600000 { 1250 compatible = "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt"; 1251 reg = <0x0 0x17600000 0x0 0x1000>; 1252 clocks = <&sleep_clk>; 1253 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 1254 }; 1255 1256 pdp0_mbox: mailbox@17610000 { 1257 compatible = "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 1258 reg = <0x0 0x17610000 0x0 0x8000>, <0x0 0x19980000 0x0 0x8000>; 1259 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1260 #mbox-cells = <1>; 1261 }; 1262 1263 timer@17810000 { 1264 compatible = "arm,armv7-timer-mem"; 1265 reg = <0x0 0x17810000 0x0 0x1000>; 1266 1267 #address-cells = <2>; 1268 #size-cells = <1>; 1269 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 1270 1271 frame@17811000 { 1272 reg = <0x0 0x17811000 0x1000>, 1273 <0x0 0x17812000 0x1000>; 1274 frame-number = <0>; 1275 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1277 }; 1278 1279 frame@17813000 { 1280 reg = <0x0 0x17813000 0x1000>; 1281 frame-number = <1>; 1282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1283 status = "disabled"; 1284 }; 1285 1286 frame@17815000 { 1287 reg = <0x0 0x17815000 0x1000>; 1288 frame-number = <2>; 1289 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1290 status = "disabled"; 1291 }; 1292 1293 frame@17817000 { 1294 reg = <0x0 0x17817000 0x1000>; 1295 frame-number = <3>; 1296 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1297 status = "disabled"; 1298 }; 1299 1300 frame@17819000 { 1301 reg = <0x0 0x17819000 0x1000>; 1302 frame-number = <4>; 1303 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1304 status = "disabled"; 1305 }; 1306 1307 frame@1781b000 { 1308 reg = <0x0 0x1781b000 0x1000>; 1309 frame-number = <5>; 1310 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1311 status = "disabled"; 1312 }; 1313 1314 frame@1781d000 { 1315 reg = <0x0 0x1781d000 0x1000>; 1316 frame-number = <6>; 1317 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1318 status = "disabled"; 1319 }; 1320 }; 1321 1322 apps_rsc: rsc@18900000 { 1323 compatible = "qcom,rpmh-rsc"; 1324 reg = <0x0 0x18900000 0x0 0x10000>, 1325 <0x0 0x18910000 0x0 0x10000>, 1326 <0x0 0x18920000 0x0 0x10000>; 1327 reg-names = "drv-0", 1328 "drv-1", 1329 "drv-2"; 1330 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1333 1334 power-domains = <&system_pd>; 1335 label = "apps_rsc"; 1336 1337 qcom,tcs-offset = <0xd00>; 1338 qcom,drv-id = <2>; 1339 qcom,tcs-config = <ACTIVE_TCS 3>, 1340 <SLEEP_TCS 2>, 1341 <WAKE_TCS 2>, 1342 <CONTROL_TCS 0>; 1343 1344 apps_bcm_voter: bcm-voter { 1345 compatible = "qcom,bcm-voter"; 1346 }; 1347 1348 rpmhcc: clock-controller { 1349 compatible = "qcom,kaanapali-rpmh-clk"; 1350 #clock-cells = <1>; 1351 clocks = <&xo_board>; 1352 clock-names = "xo"; 1353 }; 1354 1355 rpmhpd: power-controller { 1356 compatible = "qcom,kaanapali-rpmhpd"; 1357 1358 operating-points-v2 = <&rpmhpd_opp_table>; 1359 1360 #power-domain-cells = <1>; 1361 1362 rpmhpd_opp_table: opp-table { 1363 compatible = "operating-points-v2"; 1364 1365 rpmhpd_opp_ret: opp-16 { 1366 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1367 }; 1368 1369 rpmhpd_opp_low_svs_d3: opp-50 { 1370 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 1371 }; 1372 1373 rpmhpd_opp_low_svs_d2_1: opp-51 { 1374 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1>; 1375 }; 1376 1377 rpmhpd_opp_low_svs_d2: opp-52 { 1378 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 1379 }; 1380 1381 rpmhpd_opp_low_svs_d1_1: opp-54 { 1382 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>; 1383 }; 1384 1385 rpmhpd_opp_low_svs_d1: opp-56 { 1386 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 1387 }; 1388 1389 rpmhpd_opp_low_svs_d0: opp-60 { 1390 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 1391 }; 1392 1393 rpmhpd_opp_low_svs: opp-64 { 1394 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1395 }; 1396 1397 rpmhpd_opp_low_svs_l0: opp-76 { 1398 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>; 1399 }; 1400 1401 rpmhpd_opp_low_svs_l1: opp-80 { 1402 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 1403 }; 1404 1405 rpmhpd_opp_low_svs_l2: opp-96 { 1406 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>; 1407 }; 1408 1409 rpmhpd_opp_svs: opp-128 { 1410 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1411 }; 1412 1413 rpmhpd_opp_svs_l0: opp-144 { 1414 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1415 }; 1416 1417 rpmhpd_opp_svs_l1: opp-192 { 1418 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1419 }; 1420 1421 rpmhpd_opp_svs_l2: opp-224 { 1422 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1423 }; 1424 1425 rpmhpd_opp_nom: opp-256 { 1426 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1427 }; 1428 1429 rpmhpd_opp_nom_l1: opp-320 { 1430 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1431 }; 1432 1433 rpmhpd_opp_nom_l2: opp-336 { 1434 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1435 }; 1436 1437 rpmhpd_opp_turbo: opp-384 { 1438 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1439 }; 1440 1441 rpmhpd_opp_turbo_l0: opp-400 { 1442 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L0>; 1443 }; 1444 1445 rpmhpd_opp_turbo_l1: opp-416 { 1446 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1447 }; 1448 1449 rpmhpd_opp_turbo_l2: opp-432 { 1450 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 1451 }; 1452 1453 rpmhpd_opp_turbo_l3: opp-448 { 1454 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 1455 }; 1456 1457 rpmhpd_opp_turbo_l4: opp-452 { 1458 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 1459 }; 1460 1461 rpmhpd_opp_turbo_l5: opp-456 { 1462 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 1463 }; 1464 1465 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 1466 opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 1467 }; 1468 }; 1469 }; 1470 }; 1471 1472 nsp_noc: interconnect@260c0000 { 1473 compatible = "qcom,kaanapali-nsp-noc"; 1474 reg = <0x0 0x260c0000 0x0 0x21280>; 1475 qcom,bcm-voters = <&apps_bcm_voter>; 1476 #interconnect-cells = <2>; 1477 }; 1478 1479 /* Cluster 0 */ 1480 pmu@310b3400 { 1481 compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; 1482 reg = <0x0 0x310b3400 0x0 0x600>; 1483 1484 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1485 1486 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1487 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1488 1489 operating-points-v2 = <&cpu_bwmon_opp_table>; 1490 1491 cpu_bwmon_opp_table: opp-table { 1492 compatible = "operating-points-v2"; 1493 1494 opp-0 { 1495 opp-peak-kBps = <2188000>; 1496 }; 1497 1498 opp-1 { 1499 opp-peak-kBps = <5412000>; 1500 }; 1501 1502 opp-2 { 1503 opp-peak-kBps = <6220000>; 1504 }; 1505 1506 opp-3 { 1507 opp-peak-kBps = <6832000>; 1508 }; 1509 1510 opp-4 { 1511 opp-peak-kBps = <8368000>; 1512 }; 1513 1514 opp-5 { 1515 opp-peak-kBps = <10944000>; 1516 }; 1517 1518 opp-6 { 1519 opp-peak-kBps = <12748000>; 1520 }; 1521 1522 opp-7 { 1523 opp-peak-kBps = <14744000>; 1524 }; 1525 1526 opp-8 { 1527 opp-peak-kBps = <16896000>; 1528 }; 1529 1530 opp-9 { 1531 opp-peak-kBps = <19120000>; 1532 }; 1533 1534 opp-10 { 1535 opp-peak-kBps = <21332000>; 1536 }; 1537 }; 1538 }; 1539 1540 /* Cluster 1 */ 1541 pmu@310b7400 { 1542 compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; 1543 reg = <0x0 0x310b7400 0x0 0x600>; 1544 1545 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1546 1547 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1548 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1549 1550 operating-points-v2 = <&cpu_bwmon_opp_table>; 1551 }; 1552 1553 gem_noc: interconnect@31100000 { 1554 compatible = "qcom,kaanapali-gem-noc"; 1555 reg = <0x0 0x31100000 0x0 0x153080>; 1556 qcom,bcm-voters = <&apps_bcm_voter>; 1557 #interconnect-cells = <2>; 1558 }; 1559 1560 system-cache-controller@31800000 { 1561 compatible = "qcom,kaanapali-llcc"; 1562 reg = <0x0 0x31800000 0x0 0x200000>, 1563 <0x0 0x32800000 0x0 0x200000>, 1564 <0x0 0x31c00000 0x0 0x200000>, 1565 <0x0 0x32c00000 0x0 0x200000>, 1566 <0x0 0x34800000 0x0 0x200000>, 1567 <0x0 0x34c00000 0x0 0x200000>; 1568 reg-names = "llcc0_base", 1569 "llcc1_base", 1570 "llcc2_base", 1571 "llcc3_base", 1572 "llcc_broadcast_base", 1573 "llcc_broadcast_and_base"; 1574 1575 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1576 }; 1577 1578 sram: sram@81f08000 { 1579 compatible = "mmio-sram"; 1580 reg = <0x0 0x81f08000 0x0 0x200>; 1581 1582 #address-cells = <1>; 1583 #size-cells = <1>; 1584 ranges = <0x0 0x0 0x81f08000 0x200>; 1585 1586 pdp_rx: scp-sram-section@0 { 1587 compatible = "arm,scmi-shmem"; 1588 reg = <0x0 0x80>; 1589 }; 1590 1591 pdp_tx: scp-sram-section@100 { 1592 compatible = "arm,scmi-shmem"; 1593 reg = <0x100 0x80>; 1594 }; 1595 }; 1596 }; 1597 1598 timer { 1599 compatible = "arm,armv8-timer"; 1600 1601 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1602 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1603 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1604 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1605 }; 1606}; 1607