1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ5424 device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/qcom,ipq5424-gcc.h> 11#include <dt-bindings/reset/qcom,ipq5424-gcc.h> 12#include <dt-bindings/interconnect/qcom,ipq5424.h> 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&intc>; 19 20 clocks { 21 sleep_clk: sleep-clk { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 }; 25 26 xo_board: xo-board-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a55"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&l2_0>; 42 l2_0: l2-cache { 43 compatible = "cache"; 44 cache-level = <2>; 45 cache-unified; 46 next-level-cache = <&l3_0>; 47 48 l3_0: l3-cache { 49 compatible = "cache"; 50 cache-level = <3>; 51 cache-unified; 52 }; 53 }; 54 }; 55 56 cpu1: cpu@100 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 enable-method = "psci"; 60 reg = <0x100>; 61 next-level-cache = <&l2_100>; 62 63 l2_100: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&l3_0>; 68 }; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 enable-method = "psci"; 75 reg = <0x200>; 76 next-level-cache = <&l2_200>; 77 78 l2_200: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 next-level-cache = <&l3_0>; 83 }; 84 }; 85 86 cpu3: cpu@300 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a55"; 89 enable-method = "psci"; 90 reg = <0x300>; 91 next-level-cache = <&l2_300>; 92 93 l2_300: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&l3_0>; 98 }; 99 }; 100 }; 101 102 firmware { 103 scm { 104 compatible = "qcom,scm-ipq5424", "qcom,scm"; 105 qcom,dload-mode = <&tcsr 0x25100>; 106 }; 107 }; 108 109 memory@80000000 { 110 device_type = "memory"; 111 /* We expect the bootloader to fill in the size */ 112 reg = <0x0 0x80000000 0x0 0x0>; 113 }; 114 115 pmu-a55 { 116 compatible = "arm,cortex-a55-pmu"; 117 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 118 }; 119 120 pmu-dsu { 121 compatible = "arm,dsu-pmu"; 122 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 123 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 124 }; 125 126 psci { 127 compatible = "arm,psci-1.0"; 128 method = "smc"; 129 }; 130 131 reserved-memory { 132 #address-cells = <2>; 133 #size-cells = <2>; 134 ranges; 135 136 bootloader@8a200000 { 137 reg = <0x0 0x8a200000 0x0 0x400000>; 138 no-map; 139 }; 140 141 tz@8a600000 { 142 reg = <0x0 0x8a600000 0x0 0x200000>; 143 no-map; 144 }; 145 146 smem@8a800000 { 147 compatible = "qcom,smem"; 148 reg = <0x0 0x8a800000 0x0 0x32000>; 149 no-map; 150 151 hwlocks = <&tcsr_mutex 3>; 152 }; 153 }; 154 155 soc@0 { 156 compatible = "simple-bus"; 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges = <0 0 0 0 0x10 0>; 160 161 pcie0_phy: phy@84000 { 162 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", 163 "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 164 reg = <0x0 0x00084000 0x0 0x1000>; 165 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 166 <&gcc GCC_PCIE0_AHB_CLK>, 167 <&gcc GCC_PCIE0_PIPE_CLK>; 168 clock-names = "aux", 169 "cfg_ahb", 170 "pipe"; 171 172 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; 173 assigned-clock-rates = <20000000>; 174 175 resets = <&gcc GCC_PCIE0_PHY_BCR>, 176 <&gcc GCC_PCIE0PHY_PHY_BCR>; 177 reset-names = "phy", 178 "common"; 179 180 #clock-cells = <0>; 181 clock-output-names = "gcc_pcie0_pipe_clk_src"; 182 183 #phy-cells = <0>; 184 status = "disabled"; 185 }; 186 187 pcie1_phy: phy@8c000 { 188 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", 189 "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 190 reg = <0x0 0x0008c000 0x0 0x1000>; 191 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 192 <&gcc GCC_PCIE1_AHB_CLK>, 193 <&gcc GCC_PCIE1_PIPE_CLK>; 194 clock-names = "aux", 195 "cfg_ahb", 196 "pipe"; 197 198 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; 199 assigned-clock-rates = <20000000>; 200 201 resets = <&gcc GCC_PCIE1_PHY_BCR>, 202 <&gcc GCC_PCIE1PHY_PHY_BCR>; 203 reset-names = "phy", 204 "common"; 205 206 #clock-cells = <0>; 207 clock-output-names = "gcc_pcie1_pipe_clk_src"; 208 209 #phy-cells = <0>; 210 status = "disabled"; 211 }; 212 213 efuse@a4000 { 214 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; 215 reg = <0 0x000a4000 0 0x741>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 219 tsens_sens9_off: s9@3dc { 220 reg = <0x3dc 0x1>; 221 bits = <4 4>; 222 }; 223 224 tsens_sens10_off: s10@3dd { 225 reg = <0x3dd 0x1>; 226 bits = <0 4>; 227 }; 228 229 tsens_sens11_off: s11@3dd { 230 reg = <0x3dd 0x1>; 231 bits = <4 4>; 232 }; 233 234 tsens_sens12_off: s12@3de { 235 reg = <0x3de 0x1>; 236 bits = <0 4>; 237 }; 238 239 tsens_sens13_off: s13@3de { 240 reg = <0x3de 0x1>; 241 bits = <4 4>; 242 }; 243 244 tsens_sens14_off: s14@3e5 { 245 reg = <0x3e5 0x2>; 246 bits = <7 4>; 247 }; 248 249 tsens_sens15_off: s15@3e6 { 250 reg = <0x3e6 0x1>; 251 bits = <3 4>; 252 }; 253 254 tsens_mode: mode@419 { 255 reg = <0x419 0x1>; 256 bits = <0 3>; 257 }; 258 259 tsens_base0: base0@419 { 260 reg = <0x419 0x2>; 261 bits = <3 10>; 262 }; 263 264 tsens_base1: base1@41a { 265 reg = <0x41a 0x2>; 266 bits = <5 10>; 267 }; 268 }; 269 270 pcie2_phy: phy@f4000 { 271 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", 272 "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 273 reg = <0x0 0x000f4000 0x0 0x2000>; 274 clocks = <&gcc GCC_PCIE2_AUX_CLK>, 275 <&gcc GCC_PCIE2_AHB_CLK>, 276 <&gcc GCC_PCIE2_PIPE_CLK>; 277 clock-names = "aux", 278 "cfg_ahb", 279 "pipe"; 280 281 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; 282 assigned-clock-rates = <20000000>; 283 284 resets = <&gcc GCC_PCIE2_PHY_BCR>, 285 <&gcc GCC_PCIE2PHY_PHY_BCR>; 286 reset-names = "phy", 287 "common"; 288 289 #clock-cells = <0>; 290 clock-output-names = "gcc_pcie2_pipe_clk_src"; 291 292 #phy-cells = <0>; 293 status = "disabled"; 294 }; 295 296 pcie3_phy: phy@fc000 { 297 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", 298 "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 299 reg = <0x0 0x000fc000 0x0 0x2000>; 300 clocks = <&gcc GCC_PCIE3_AUX_CLK>, 301 <&gcc GCC_PCIE3_AHB_CLK>, 302 <&gcc GCC_PCIE3_PIPE_CLK>; 303 clock-names = "aux", 304 "cfg_ahb", 305 "pipe"; 306 307 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; 308 assigned-clock-rates = <20000000>; 309 310 resets = <&gcc GCC_PCIE3_PHY_BCR>, 311 <&gcc GCC_PCIE3PHY_PHY_BCR>; 312 reset-names = "phy", 313 "common"; 314 315 #clock-cells = <0>; 316 clock-output-names = "gcc_pcie3_pipe_clk_src"; 317 318 #phy-cells = <0>; 319 status = "disabled"; 320 }; 321 322 tsens: thermal-sensor@4a9000 { 323 compatible = "qcom,ipq5424-tsens"; 324 reg = <0 0x004a9000 0 0x1000>, 325 <0 0x004a8000 0 0x1000>; 326 interrupts = <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>; 327 interrupt-names = "combined"; 328 nvmem-cells = <&tsens_mode>, 329 <&tsens_base0>, 330 <&tsens_base1>, 331 <&tsens_sens9_off>, 332 <&tsens_sens10_off>, 333 <&tsens_sens11_off>, 334 <&tsens_sens12_off>, 335 <&tsens_sens13_off>, 336 <&tsens_sens14_off>, 337 <&tsens_sens15_off>; 338 nvmem-cell-names = "mode", 339 "base0", 340 "base1", 341 "tsens_sens9_off", 342 "tsens_sens10_off", 343 "tsens_sens11_off", 344 "tsens_sens12_off", 345 "tsens_sens13_off", 346 "tsens_sens14_off", 347 "tsens_sens15_off"; 348 #qcom,sensors = <7>; 349 #thermal-sensor-cells = <1>; 350 }; 351 352 rng: rng@4c3000 { 353 compatible = "qcom,ipq5424-trng", "qcom,trng"; 354 reg = <0 0x004c3000 0 0x1000>; 355 clocks = <&gcc GCC_PRNG_AHB_CLK>; 356 clock-names = "core"; 357 }; 358 359 system-cache-controller@800000 { 360 compatible = "qcom,ipq5424-llcc"; 361 reg = <0 0x00800000 0 0x200000>; 362 reg-names = "llcc0_base"; 363 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 364 }; 365 366 tlmm: pinctrl@1000000 { 367 compatible = "qcom,ipq5424-tlmm"; 368 reg = <0 0x01000000 0 0x300000>; 369 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 370 gpio-controller; 371 #gpio-cells = <2>; 372 gpio-ranges = <&tlmm 0 0 50>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 376 uart1_pins: uart1-state { 377 pins = "gpio43", "gpio44"; 378 function = "uart1"; 379 drive-strength = <8>; 380 bias-pull-up; 381 }; 382 }; 383 384 gcc: clock-controller@1800000 { 385 compatible = "qcom,ipq5424-gcc"; 386 reg = <0 0x01800000 0 0x40000>; 387 clocks = <&xo_board>, 388 <&sleep_clk>, 389 <&pcie0_phy>, 390 <&pcie1_phy>, 391 <&pcie2_phy>, 392 <&pcie3_phy>, 393 <0>; 394 #clock-cells = <1>; 395 #reset-cells = <1>; 396 #interconnect-cells = <1>; 397 }; 398 399 tcsr_mutex: hwlock@1905000 { 400 compatible = "qcom,tcsr-mutex"; 401 reg = <0 0x01905000 0 0x20000>; 402 #hwlock-cells = <1>; 403 }; 404 405 tcsr: syscon@1937000 { 406 compatible = "qcom,tcsr-ipq5424", "syscon"; 407 reg = <0 0x01937000 0 0x2a000>; 408 }; 409 410 qupv3: geniqup@1ac0000 { 411 compatible = "qcom,geni-se-qup"; 412 reg = <0 0x01ac0000 0 0x2000>; 413 ranges; 414 clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, 415 <&gcc GCC_QUPV3_AHB_SLV_CLK>; 416 clock-names = "m-ahb", "s-ahb"; 417 #address-cells = <2>; 418 #size-cells = <2>; 419 420 uart1: serial@1a84000 { 421 compatible = "qcom,geni-debug-uart"; 422 reg = <0 0x01a84000 0 0x4000>; 423 clocks = <&gcc GCC_QUPV3_UART1_CLK>; 424 clock-names = "se"; 425 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 426 }; 427 428 spi0: spi@1a90000 { 429 compatible = "qcom,geni-spi"; 430 reg = <0 0x01a90000 0 0x4000>; 431 clocks = <&gcc GCC_QUPV3_SPI0_CLK>; 432 clock-names = "se"; 433 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 status = "disabled"; 437 }; 438 439 spi1: spi@1a94000 { 440 compatible = "qcom,geni-spi"; 441 reg = <0 0x01a94000 0 0x4000>; 442 clocks = <&gcc GCC_QUPV3_SPI1_CLK>; 443 clock-names = "se"; 444 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 status = "disabled"; 448 }; 449 }; 450 451 sdhc: mmc@7804000 { 452 compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5"; 453 reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>; 454 reg-names = "hc", "cqhci"; 455 456 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "hc_irq", "pwr_irq"; 459 460 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 461 <&gcc GCC_SDCC1_APPS_CLK>, 462 <&xo_board>; 463 clock-names = "iface", "core", "xo"; 464 465 supports-cqe; 466 467 status = "disabled"; 468 }; 469 470 intc: interrupt-controller@f200000 { 471 compatible = "arm,gic-v3"; 472 reg = <0 0xf200000 0 0x10000>, /* GICD */ 473 <0 0xf240000 0 0x80000>; /* GICR * 4 regions */ 474 #interrupt-cells = <0x3>; 475 interrupt-controller; 476 #redistributor-regions = <1>; 477 redistributor-stride = <0x0 0x20000>; 478 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 479 mbi-ranges = <672 128>; 480 msi-controller; 481 }; 482 483 watchdog@f410000 { 484 compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt"; 485 reg = <0 0x0f410000 0 0x1000>; 486 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 487 clocks = <&sleep_clk>; 488 }; 489 490 qusb_phy_1: phy@71000 { 491 compatible = "qcom,ipq5424-qusb2-phy"; 492 reg = <0 0x00071000 0 0x180>; 493 #phy-cells = <0>; 494 495 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 496 <&xo_board>; 497 clock-names = "cfg_ahb", "ref"; 498 499 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 500 status = "disabled"; 501 }; 502 503 usb2: usb2@1e00000 { 504 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; 505 reg = <0 0x01ef8800 0 0x400>; 506 #address-cells = <2>; 507 #size-cells = <2>; 508 ranges; 509 510 clocks = <&gcc GCC_USB1_MASTER_CLK>, 511 <&gcc GCC_USB1_SLEEP_CLK>, 512 <&gcc GCC_USB1_MOCK_UTMI_CLK>, 513 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 514 <&gcc GCC_CNOC_USB_CLK>; 515 516 clock-names = "core", 517 "sleep", 518 "mock_utmi", 519 "iface", 520 "cfg_noc"; 521 522 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 523 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 524 assigned-clock-rates = <200000000>, 525 <24000000>; 526 527 interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 528 <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 529 <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 530 <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; 531 interrupt-names = "pwr_event", 532 "qusb2_phy", 533 "dm_hs_phy_irq", 534 "dp_hs_phy_irq"; 535 536 resets = <&gcc GCC_USB1_BCR>; 537 qcom,select-utmi-as-pipe-clk; 538 status = "disabled"; 539 540 dwc_1: usb@1e00000 { 541 compatible = "snps,dwc3"; 542 reg = <0 0x01e00000 0 0xe000>; 543 clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; 544 clock-names = "ref"; 545 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 546 phys = <&qusb_phy_1>; 547 phy-names = "usb2-phy"; 548 tx-fifo-resize; 549 snps,is-utmi-l1-suspend; 550 snps,hird-threshold = /bits/ 8 <0x0>; 551 snps,dis_u2_susphy_quirk; 552 snps,dis_u3_susphy_quirk; 553 }; 554 }; 555 556 qusb_phy_0: phy@7b000 { 557 compatible = "qcom,ipq5424-qusb2-phy"; 558 reg = <0 0x0007b000 0 0x180>; 559 #phy-cells = <0>; 560 561 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 562 <&xo_board>; 563 clock-names = "cfg_ahb", "ref"; 564 565 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 566 status = "disabled"; 567 }; 568 569 ssphy_0: phy@7d000 { 570 compatible = "qcom,ipq5424-qmp-usb3-phy"; 571 reg = <0 0x0007d000 0 0xa00>; 572 #phy-cells = <0>; 573 574 clocks = <&gcc GCC_USB0_AUX_CLK>, 575 <&xo_board>, 576 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 577 <&gcc GCC_USB0_PIPE_CLK>; 578 clock-names = "aux", 579 "ref", 580 "cfg_ahb", 581 "pipe"; 582 583 resets = <&gcc GCC_USB0_PHY_BCR>, 584 <&gcc GCC_USB3PHY_0_PHY_BCR>; 585 reset-names = "phy", 586 "phy_phy"; 587 588 #clock-cells = <0>; 589 clock-output-names = "usb0_pipe_clk"; 590 591 status = "disabled"; 592 }; 593 594 usb3: usb3@8a00000 { 595 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; 596 reg = <0 0x08af8800 0 0x400>; 597 598 #address-cells = <2>; 599 #size-cells = <2>; 600 ranges; 601 602 clocks = <&gcc GCC_USB0_MASTER_CLK>, 603 <&gcc GCC_USB0_SLEEP_CLK>, 604 <&gcc GCC_USB0_MOCK_UTMI_CLK>, 605 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 606 <&gcc GCC_CNOC_USB_CLK>; 607 608 clock-names = "core", 609 "sleep", 610 "mock_utmi", 611 "iface", 612 "cfg_noc"; 613 614 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 615 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 616 assigned-clock-rates = <200000000>, 617 <24000000>; 618 619 interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 620 <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 621 <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 622 <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "pwr_event", 624 "qusb2_phy", 625 "dm_hs_phy_irq", 626 "dp_hs_phy_irq"; 627 628 resets = <&gcc GCC_USB_BCR>; 629 status = "disabled"; 630 631 dwc_0: usb@8a00000 { 632 compatible = "snps,dwc3"; 633 reg = <0 0x08a00000 0 0xcd00>; 634 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 635 clock-names = "ref"; 636 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 637 phys = <&qusb_phy_0>, <&ssphy_0>; 638 phy-names = "usb2-phy", "usb3-phy"; 639 tx-fifo-resize; 640 snps,is-utmi-l1-suspend; 641 snps,hird-threshold = /bits/ 8 <0x0>; 642 snps,dis_u2_susphy_quirk; 643 snps,dis_u3_susphy_quirk; 644 snps,dis-u1-entry-quirk; 645 snps,dis-u2-entry-quirk; 646 }; 647 }; 648 649 timer@f420000 { 650 compatible = "arm,armv7-timer-mem"; 651 reg = <0 0xf420000 0 0x1000>; 652 ranges = <0 0 0 0x10000000>; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 656 frame@f421000 { 657 reg = <0xf421000 0x1000>, 658 <0xf422000 0x1000>; 659 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 661 frame-number = <0>; 662 }; 663 664 frame@f423000 { 665 reg = <0xf423000 0x1000>; 666 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 667 frame-number = <1>; 668 status = "disabled"; 669 }; 670 671 frame@f425000 { 672 reg = <0xf425000 0x1000>, 673 <0xf426000 0x1000>; 674 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 675 frame-number = <2>; 676 status = "disabled"; 677 }; 678 679 frame@f427000 { 680 reg = <0xf427000 0x1000>; 681 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 682 frame-number = <3>; 683 status = "disabled"; 684 }; 685 686 frame@f429000 { 687 reg = <0xf429000 0x1000>; 688 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 689 frame-number = <4>; 690 status = "disabled"; 691 }; 692 693 frame@f42b000 { 694 reg = <0xf42b000 0x1000>; 695 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 696 frame-number = <5>; 697 status = "disabled"; 698 }; 699 700 frame@f42d000 { 701 reg = <0xf42d000 0x1000>; 702 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 703 frame-number = <6>; 704 status = "disabled"; 705 }; 706 }; 707 708 pcie3: pcie@40000000 { 709 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 710 reg = <0x0 0x40000000 0x0 0xf1c>, 711 <0x0 0x40000f20 0x0 0xa8>, 712 <0x0 0x40001000 0x0 0x1000>, 713 <0x0 0x000f8000 0x0 0x3000>, 714 <0x0 0x40100000 0x0 0x1000>, 715 <0x0 0x000fe000 0x0 0x1000>; 716 reg-names = "dbi", 717 "elbi", 718 "atu", 719 "parf", 720 "config", 721 "mhi"; 722 device_type = "pci"; 723 linux,pci-domain = <3>; 724 num-lanes = <2>; 725 #address-cells = <3>; 726 #size-cells = <2>; 727 728 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>, 729 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>; 730 731 msi-map = <0x0 &intc 0x0 0x1000>; 732 733 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>; 742 743 interrupt-names = "msi0", 744 "msi1", 745 "msi2", 746 "msi3", 747 "msi4", 748 "msi5", 749 "msi6", 750 "msi7", 751 "global"; 752 753 #interrupt-cells = <1>; 754 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 755 interrupt-map = <0 0 0 1 &intc 0 479 IRQ_TYPE_LEVEL_HIGH>, 756 <0 0 0 2 &intc 0 480 IRQ_TYPE_LEVEL_HIGH>, 757 <0 0 0 3 &intc 0 481 IRQ_TYPE_LEVEL_HIGH>, 758 <0 0 0 4 &intc 0 482 IRQ_TYPE_LEVEL_HIGH>; 759 760 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, 761 <&gcc GCC_PCIE3_AXI_S_CLK>, 762 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, 763 <&gcc GCC_PCIE3_RCHNG_CLK>, 764 <&gcc GCC_PCIE3_AHB_CLK>, 765 <&gcc GCC_PCIE3_AUX_CLK>; 766 clock-names = "axi_m", 767 "axi_s", 768 "axi_bridge", 769 "rchng", 770 "ahb", 771 "aux"; 772 773 assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>; 774 assigned-clock-rates = <100000000>; 775 776 resets = <&gcc GCC_PCIE3_PIPE_ARES>, 777 <&gcc GCC_PCIE3_CORE_STICKY_RESET>, 778 <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>, 779 <&gcc GCC_PCIE3_AXI_S_ARES>, 780 <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>, 781 <&gcc GCC_PCIE3_AXI_M_ARES>, 782 <&gcc GCC_PCIE3_AUX_ARES>, 783 <&gcc GCC_PCIE3_AHB_ARES>; 784 reset-names = "pipe", 785 "sticky", 786 "axi_s_sticky", 787 "axi_s", 788 "axi_m_sticky", 789 "axi_m", 790 "aux", 791 "ahb"; 792 793 phys = <&pcie3_phy>; 794 phy-names = "pciephy"; 795 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, 796 <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>; 797 interconnect-names = "pcie-mem", "cpu-pcie"; 798 799 status = "disabled"; 800 801 pcie@0 { 802 device_type = "pci"; 803 reg = <0x0 0x0 0x0 0x0 0x0>; 804 bus-range = <0x01 0xff>; 805 806 #address-cells = <3>; 807 #size-cells = <2>; 808 ranges; 809 }; 810 }; 811 812 pcie2: pcie@50000000 { 813 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 814 reg = <0x0 0x50000000 0x0 0xf1c>, 815 <0x0 0x50000f20 0x0 0xa8>, 816 <0x0 0x50001000 0x0 0x1000>, 817 <0x0 0x000f0000 0x0 0x3000>, 818 <0x0 0x50100000 0x0 0x1000>, 819 <0x0 0x000f6000 0x0 0x1000>; 820 reg-names = "dbi", 821 "elbi", 822 "atu", 823 "parf", 824 "config", 825 "mhi"; 826 device_type = "pci"; 827 linux,pci-domain = <2>; 828 num-lanes = <2>; 829 #address-cells = <3>; 830 #size-cells = <2>; 831 832 ranges = <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000>, 833 <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>; 834 835 msi-map = <0x0 &intc 0x0 0x1000>; 836 837 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "msi0", 847 "msi1", 848 "msi2", 849 "msi3", 850 "msi4", 851 "msi5", 852 "msi6", 853 "msi7", 854 "global"; 855 856 #interrupt-cells = <1>; 857 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 858 interrupt-map = <0 0 0 1 &intc 0 464 IRQ_TYPE_LEVEL_HIGH>, 859 <0 0 0 2 &intc 0 465 IRQ_TYPE_LEVEL_HIGH>, 860 <0 0 0 3 &intc 0 466 IRQ_TYPE_LEVEL_HIGH>, 861 <0 0 0 4 &intc 0 467 IRQ_TYPE_LEVEL_HIGH>; 862 863 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, 864 <&gcc GCC_PCIE2_AXI_S_CLK>, 865 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, 866 <&gcc GCC_PCIE2_RCHNG_CLK>, 867 <&gcc GCC_PCIE2_AHB_CLK>, 868 <&gcc GCC_PCIE2_AUX_CLK>; 869 clock-names = "axi_m", 870 "axi_s", 871 "axi_bridge", 872 "rchng", 873 "ahb", 874 "aux"; 875 876 assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>; 877 assigned-clock-rates = <100000000>; 878 879 resets = <&gcc GCC_PCIE2_PIPE_ARES>, 880 <&gcc GCC_PCIE2_CORE_STICKY_RESET>, 881 <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>, 882 <&gcc GCC_PCIE2_AXI_S_ARES>, 883 <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>, 884 <&gcc GCC_PCIE2_AXI_M_ARES>, 885 <&gcc GCC_PCIE2_AUX_ARES>, 886 <&gcc GCC_PCIE2_AHB_ARES>; 887 reset-names = "pipe", 888 "sticky", 889 "axi_s_sticky", 890 "axi_s", 891 "axi_m_sticky", 892 "axi_m", 893 "aux", 894 "ahb"; 895 896 phys = <&pcie2_phy>; 897 phy-names = "pciephy"; 898 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, 899 <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>; 900 interconnect-names = "pcie-mem", "cpu-pcie"; 901 902 status = "disabled"; 903 904 pcie@0 { 905 device_type = "pci"; 906 reg = <0x0 0x0 0x0 0x0 0x0>; 907 bus-range = <0x01 0xff>; 908 909 #address-cells = <3>; 910 #size-cells = <2>; 911 ranges; 912 }; 913 }; 914 915 pcie1: pcie@60000000 { 916 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 917 reg = <0x0 0x60000000 0x0 0xf1c>, 918 <0x0 0x60000f20 0x0 0xa8>, 919 <0x0 0x60001000 0x0 0x1000>, 920 <0x0 0x00088000 0x0 0x3000>, 921 <0x0 0x60100000 0x0 0x1000>, 922 <0x0 0x0008e000 0x0 0x1000>; 923 reg-names = "dbi", 924 "elbi", 925 "atu", 926 "parf", 927 "config", 928 "mhi"; 929 device_type = "pci"; 930 linux,pci-domain = <1>; 931 num-lanes = <1>; 932 #address-cells = <3>; 933 #size-cells = <2>; 934 935 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000>, 936 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000>; 937 938 msi-map = <0x0 &intc 0x0 0x1000>; 939 940 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "msi0", 950 "msi1", 951 "msi2", 952 "msi3", 953 "msi4", 954 "msi5", 955 "msi6", 956 "msi7", 957 "global"; 958 959 #interrupt-cells = <1>; 960 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 961 interrupt-map = <0 0 0 1 &intc 0 449 IRQ_TYPE_LEVEL_HIGH>, 962 <0 0 0 2 &intc 0 450 IRQ_TYPE_LEVEL_HIGH>, 963 <0 0 0 3 &intc 0 451 IRQ_TYPE_LEVEL_HIGH>, 964 <0 0 0 4 &intc 0 452 IRQ_TYPE_LEVEL_HIGH>; 965 966 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, 967 <&gcc GCC_PCIE1_AXI_S_CLK>, 968 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, 969 <&gcc GCC_PCIE1_RCHNG_CLK>, 970 <&gcc GCC_PCIE1_AHB_CLK>, 971 <&gcc GCC_PCIE1_AUX_CLK>; 972 clock-names = "axi_m", 973 "axi_s", 974 "axi_bridge", 975 "rchng", 976 "ahb", 977 "aux"; 978 979 assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>; 980 assigned-clock-rates = <100000000>; 981 982 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 983 <&gcc GCC_PCIE1_CORE_STICKY_RESET>, 984 <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, 985 <&gcc GCC_PCIE1_AXI_S_ARES>, 986 <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, 987 <&gcc GCC_PCIE1_AXI_M_ARES>, 988 <&gcc GCC_PCIE1_AUX_ARES>, 989 <&gcc GCC_PCIE1_AHB_ARES>; 990 reset-names = "pipe", 991 "sticky", 992 "axi_s_sticky", 993 "axi_s", 994 "axi_m_sticky", 995 "axi_m", 996 "aux", 997 "ahb"; 998 999 phys = <&pcie1_phy>; 1000 phy-names = "pciephy"; 1001 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, 1002 <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>; 1003 interconnect-names = "pcie-mem", "cpu-pcie"; 1004 1005 status = "disabled"; 1006 1007 pcie@0 { 1008 device_type = "pci"; 1009 reg = <0x0 0x0 0x0 0x0 0x0>; 1010 bus-range = <0x01 0xff>; 1011 1012 #address-cells = <3>; 1013 #size-cells = <2>; 1014 ranges; 1015 }; 1016 }; 1017 1018 pcie0: pcie@70000000 { 1019 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 1020 reg = <0x0 0x70000000 0x0 0xf1c>, 1021 <0x0 0x70000f20 0x0 0xa8>, 1022 <0x0 0x70001000 0x0 0x1000>, 1023 <0x0 0x00080000 0x0 0x3000>, 1024 <0x0 0x70100000 0x0 0x1000>, 1025 <0x0 0x00086000 0x0 0x1000>; 1026 reg-names = "dbi", 1027 "elbi", 1028 "atu", 1029 "parf", 1030 "config", 1031 "mhi"; 1032 device_type = "pci"; 1033 linux,pci-domain = <0>; 1034 num-lanes = <1>; 1035 #address-cells = <3>; 1036 #size-cells = <2>; 1037 1038 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000>, 1039 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>; 1040 1041 msi-map = <0x0 &intc 0x0 0x1000>; 1042 1043 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 1052 interrupt-names = "msi0", 1053 "msi1", 1054 "msi2", 1055 "msi3", 1056 "msi4", 1057 "msi5", 1058 "msi6", 1059 "msi7", 1060 "global"; 1061 1062 #interrupt-cells = <1>; 1063 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 1064 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, 1065 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, 1066 <0 0 0 3 &intc 0 436 IRQ_TYPE_LEVEL_HIGH>, 1067 <0 0 0 4 &intc 0 437 IRQ_TYPE_LEVEL_HIGH>; 1068 1069 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, 1070 <&gcc GCC_PCIE0_AXI_S_CLK>, 1071 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 1072 <&gcc GCC_PCIE0_RCHNG_CLK>, 1073 <&gcc GCC_PCIE0_AHB_CLK>, 1074 <&gcc GCC_PCIE0_AUX_CLK>; 1075 clock-names = "axi_m", 1076 "axi_s", 1077 "axi_bridge", 1078 "rchng", 1079 "ahb", 1080 "aux"; 1081 1082 assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>; 1083 assigned-clock-rates = <100000000>; 1084 1085 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 1086 <&gcc GCC_PCIE0_CORE_STICKY_RESET>, 1087 <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, 1088 <&gcc GCC_PCIE0_AXI_S_ARES>, 1089 <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, 1090 <&gcc GCC_PCIE0_AXI_M_ARES>, 1091 <&gcc GCC_PCIE0_AUX_ARES>, 1092 <&gcc GCC_PCIE0_AHB_ARES>; 1093 reset-names = "pipe", 1094 "sticky", 1095 "axi_s_sticky", 1096 "axi_s", 1097 "axi_m_sticky", 1098 "axi_m", 1099 "aux", 1100 "ahb"; 1101 1102 phys = <&pcie0_phy>; 1103 phy-names = "pciephy"; 1104 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, 1105 <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>; 1106 interconnect-names = "pcie-mem", "cpu-pcie"; 1107 1108 status = "disabled"; 1109 1110 pcie@0 { 1111 device_type = "pci"; 1112 reg = <0x0 0x0 0x0 0x0 0x0>; 1113 bus-range = <0x01 0xff>; 1114 1115 #address-cells = <3>; 1116 #size-cells = <2>; 1117 ranges; 1118 }; 1119 }; 1120 }; 1121 1122 thermal_zones: thermal-zones { 1123 cpu0-thermal { 1124 polling-delay-passive = <100>; 1125 thermal-sensors = <&tsens 14>; 1126 1127 trips { 1128 cpu-critical { 1129 temperature = <120000>; 1130 hysteresis = <9000>; 1131 type = "critical"; 1132 }; 1133 1134 cpu-passive { 1135 temperature = <110000>; 1136 hysteresis = <9000>; 1137 type = "passive"; 1138 }; 1139 }; 1140 }; 1141 1142 cpu1-thermal { 1143 polling-delay-passive = <100>; 1144 thermal-sensors = <&tsens 12>; 1145 1146 trips { 1147 cpu-critical { 1148 temperature = <120000>; 1149 hysteresis = <9000>; 1150 type = "critical"; 1151 }; 1152 1153 cpu-passive { 1154 temperature = <110000>; 1155 hysteresis = <9000>; 1156 type = "passive"; 1157 }; 1158 }; 1159 }; 1160 1161 cpu2-thermal { 1162 polling-delay-passive = <100>; 1163 thermal-sensors = <&tsens 11>; 1164 1165 trips { 1166 cpu-critical { 1167 temperature = <120000>; 1168 hysteresis = <9000>; 1169 type = "critical"; 1170 }; 1171 1172 cpu-passive { 1173 temperature = <110000>; 1174 hysteresis = <9000>; 1175 type = "passive"; 1176 }; 1177 }; 1178 }; 1179 1180 cpu3-thermal { 1181 polling-delay-passive = <100>; 1182 thermal-sensors = <&tsens 13>; 1183 1184 trips { 1185 cpu-critical { 1186 temperature = <120000>; 1187 hysteresis = <9000>; 1188 type = "critical"; 1189 }; 1190 1191 cpu-passive { 1192 temperature = <110000>; 1193 hysteresis = <9000>; 1194 type = "passive"; 1195 }; 1196 }; 1197 }; 1198 1199 wcss-tile2-thermal { 1200 thermal-sensors = <&tsens 9>; 1201 1202 trips { 1203 wcss-tile2-critical { 1204 temperature = <125000>; 1205 hysteresis = <9000>; 1206 type = "critical"; 1207 }; 1208 }; 1209 }; 1210 1211 wcss-tile3-thermal { 1212 thermal-sensors = <&tsens 10>; 1213 1214 trips { 1215 wcss-tile3-critical { 1216 temperature = <125000>; 1217 hysteresis = <9000>; 1218 type = "critical"; 1219 }; 1220 }; 1221 }; 1222 1223 top-glue-thermal { 1224 thermal-sensors = <&tsens 15>; 1225 1226 trips { 1227 top-glue-critical { 1228 temperature = <125000>; 1229 hysteresis = <9000>; 1230 type = "critical"; 1231 }; 1232 }; 1233 }; 1234 }; 1235 1236 timer { 1237 compatible = "arm,armv8-timer"; 1238 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1239 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1240 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1241 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1242 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1243 }; 1244}; 1245