1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * IPQ5018 SoC device tree source 4 * 5 * Copyright (c) 2023 The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/qcom,gcc-ipq5018.h> 11#include <dt-bindings/reset/qcom,gcc-ipq5018.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 }; 23 24 xo_board_clk: xo-board-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 enable-method = "psci"; 39 next-level-cache = <&l2_0>; 40 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 41 operating-points-v2 = <&cpu_opp_table>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x1>; 48 enable-method = "psci"; 49 next-level-cache = <&l2_0>; 50 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 51 operating-points-v2 = <&cpu_opp_table>; 52 }; 53 54 l2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-size = <0x80000>; 58 cache-unified; 59 }; 60 }; 61 62 cpu_opp_table: opp-table-cpu { 63 compatible = "operating-points-v2"; 64 opp-shared; 65 66 opp-800000000 { 67 opp-hz = /bits/ 64 <800000000>; 68 opp-microvolt = <1100000>; 69 clock-latency-ns = <200000>; 70 }; 71 72 opp-1008000000 { 73 opp-hz = /bits/ 64 <1008000000>; 74 opp-microvolt = <1100000>; 75 clock-latency-ns = <200000>; 76 }; 77 }; 78 79 firmware { 80 scm { 81 compatible = "qcom,scm-ipq5018", "qcom,scm"; 82 qcom,dload-mode = <&tcsr 0x6100>; 83 qcom,sdi-enabled; 84 }; 85 }; 86 87 memory@40000000 { 88 device_type = "memory"; 89 /* We expect the bootloader to fill in the size */ 90 reg = <0x0 0x40000000 0x0 0x0>; 91 }; 92 93 pmu { 94 compatible = "arm,cortex-a53-pmu"; 95 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 }; 97 98 psci { 99 compatible = "arm,psci-1.0"; 100 method = "smc"; 101 }; 102 103 reserved-memory { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 bootloader@4a800000 { 109 reg = <0x0 0x4a800000 0x0 0x200000>; 110 no-map; 111 }; 112 113 sbl@4aa00000 { 114 reg = <0x0 0x4aa00000 0x0 0x100000>; 115 no-map; 116 }; 117 118 smem@4ab00000 { 119 compatible = "qcom,smem"; 120 reg = <0x0 0x4ab00000 0x0 0x100000>; 121 no-map; 122 123 hwlocks = <&tcsr_mutex 3>; 124 }; 125 126 tz_region: tz@4ac00000 { 127 reg = <0x0 0x4ac00000 0x0 0x200000>; 128 no-map; 129 }; 130 }; 131 132 soc: soc@0 { 133 compatible = "simple-bus"; 134 #address-cells = <1>; 135 #size-cells = <1>; 136 ranges = <0 0 0 0xffffffff>; 137 138 usbphy0: phy@5b000 { 139 compatible = "qcom,ipq5018-usb-hsphy"; 140 reg = <0x0005b000 0x120>; 141 142 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; 143 144 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 145 146 #phy-cells = <0>; 147 148 status = "disabled"; 149 }; 150 151 pcie1_phy: phy@7e000 { 152 compatible = "qcom,ipq5018-uniphy-pcie-phy"; 153 reg = <0x0007e000 0x800>; 154 155 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 156 157 resets = <&gcc GCC_PCIE1_PHY_BCR>, 158 <&gcc GCC_PCIE1PHY_PHY_BCR>; 159 160 #clock-cells = <0>; 161 #phy-cells = <0>; 162 163 num-lanes = <1>; 164 165 status = "disabled"; 166 }; 167 168 pcie0_phy: phy@86000 { 169 compatible = "qcom,ipq5018-uniphy-pcie-phy"; 170 reg = <0x00086000 0x1000>; 171 172 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 173 174 resets = <&gcc GCC_PCIE0_PHY_BCR>, 175 <&gcc GCC_PCIE0PHY_PHY_BCR>; 176 177 #clock-cells = <0>; 178 #phy-cells = <0>; 179 180 num-lanes = <2>; 181 182 status = "disabled"; 183 }; 184 185 tlmm: pinctrl@1000000 { 186 compatible = "qcom,ipq5018-tlmm"; 187 reg = <0x01000000 0x300000>; 188 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 189 gpio-controller; 190 #gpio-cells = <2>; 191 gpio-ranges = <&tlmm 0 0 47>; 192 interrupt-controller; 193 #interrupt-cells = <2>; 194 195 uart1_pins: uart1-state { 196 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 197 function = "blsp1_uart1"; 198 drive-strength = <8>; 199 bias-pull-down; 200 }; 201 }; 202 203 gcc: clock-controller@1800000 { 204 compatible = "qcom,gcc-ipq5018"; 205 reg = <0x01800000 0x80000>; 206 clocks = <&xo_board_clk>, 207 <&sleep_clk>, 208 <&pcie0_phy>, 209 <&pcie1_phy>, 210 <0>, 211 <0>, 212 <0>, 213 <0>, 214 <0>; 215 #clock-cells = <1>; 216 #reset-cells = <1>; 217 }; 218 219 tcsr_mutex: hwlock@1905000 { 220 compatible = "qcom,tcsr-mutex"; 221 reg = <0x01905000 0x20000>; 222 #hwlock-cells = <1>; 223 }; 224 225 tcsr: syscon@1937000 { 226 compatible = "qcom,tcsr-ipq5018", "syscon"; 227 reg = <0x01937000 0x21000>; 228 }; 229 230 sdhc_1: mmc@7804000 { 231 compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; 232 reg = <0x7804000 0x1000>; 233 reg-names = "hc"; 234 235 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-names = "hc_irq", "pwr_irq"; 238 239 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 240 <&gcc GCC_SDCC1_APPS_CLK>, 241 <&xo_board_clk>; 242 clock-names = "iface", "core", "xo"; 243 non-removable; 244 status = "disabled"; 245 }; 246 247 blsp_dma: dma-controller@7884000 { 248 compatible = "qcom,bam-v1.7.0"; 249 reg = <0x07884000 0x1d000>; 250 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 252 clock-names = "bam_clk"; 253 #dma-cells = <1>; 254 qcom,ee = <0>; 255 }; 256 257 blsp1_uart1: serial@78af000 { 258 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 259 reg = <0x078af000 0x200>; 260 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 262 <&gcc GCC_BLSP1_AHB_CLK>; 263 clock-names = "core", "iface"; 264 status = "disabled"; 265 }; 266 267 blsp1_spi1: spi@78b5000 { 268 compatible = "qcom,spi-qup-v2.2.1"; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 reg = <0x078b5000 0x600>; 272 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 274 <&gcc GCC_BLSP1_AHB_CLK>; 275 clock-names = "core", "iface"; 276 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 277 dma-names = "tx", "rx"; 278 status = "disabled"; 279 }; 280 281 usb: usb@8af8800 { 282 compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; 283 reg = <0x08af8800 0x400>; 284 285 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-names = "hs_phy_irq"; 287 288 clocks = <&gcc GCC_USB0_MASTER_CLK>, 289 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 290 <&gcc GCC_USB0_SLEEP_CLK>, 291 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 292 clock-names = "core", 293 "iface", 294 "sleep", 295 "mock_utmi"; 296 297 resets = <&gcc GCC_USB0_BCR>; 298 299 qcom,select-utmi-as-pipe-clk; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 ranges; 303 304 status = "disabled"; 305 306 usb_dwc: usb@8a00000 { 307 compatible = "snps,dwc3"; 308 reg = <0x08a00000 0xe000>; 309 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 310 clock-names = "ref"; 311 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 312 phy-names = "usb2-phy"; 313 phys = <&usbphy0>; 314 tx-fifo-resize; 315 snps,is-utmi-l1-suspend; 316 snps,hird-threshold = /bits/ 8 <0x0>; 317 snps,dis_u2_susphy_quirk; 318 snps,dis_u3_susphy_quirk; 319 }; 320 }; 321 322 intc: interrupt-controller@b000000 { 323 compatible = "qcom,msm-qgic2"; 324 reg = <0x0b000000 0x1000>, /* GICD */ 325 <0x0b002000 0x2000>, /* GICC */ 326 <0x0b001000 0x1000>, /* GICH */ 327 <0x0b004000 0x2000>; /* GICV */ 328 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 329 interrupt-controller; 330 #interrupt-cells = <3>; 331 #address-cells = <1>; 332 #size-cells = <1>; 333 ranges = <0 0x0b00a000 0x1ffa>; 334 335 v2m0: v2m@0 { 336 compatible = "arm,gic-v2m-frame"; 337 reg = <0x00000000 0xff8>; 338 msi-controller; 339 }; 340 341 v2m1: v2m@1000 { 342 compatible = "arm,gic-v2m-frame"; 343 reg = <0x00001000 0xff8>; 344 msi-controller; 345 }; 346 }; 347 348 watchdog: watchdog@b017000 { 349 compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; 350 reg = <0x0b017000 0x40>; 351 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 352 clocks = <&sleep_clk>; 353 }; 354 355 apcs_glb: mailbox@b111000 { 356 compatible = "qcom,ipq5018-apcs-apps-global", 357 "qcom,ipq6018-apcs-apps-global"; 358 reg = <0x0b111000 0x1000>; 359 #clock-cells = <1>; 360 clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; 361 clock-names = "pll", "xo", "gpll0"; 362 #mbox-cells = <1>; 363 }; 364 365 a53pll: clock@b116000 { 366 compatible = "qcom,ipq5018-a53pll"; 367 reg = <0x0b116000 0x40>; 368 #clock-cells = <0>; 369 clocks = <&xo_board_clk>; 370 clock-names = "xo"; 371 }; 372 373 timer@b120000 { 374 compatible = "arm,armv7-timer-mem"; 375 reg = <0x0b120000 0x1000>; 376 #address-cells = <1>; 377 #size-cells = <1>; 378 ranges; 379 380 frame@b120000 { 381 reg = <0x0b121000 0x1000>, 382 <0x0b122000 0x1000>; 383 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 385 frame-number = <0>; 386 }; 387 388 frame@b123000 { 389 reg = <0xb123000 0x1000>; 390 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 391 frame-number = <1>; 392 status = "disabled"; 393 }; 394 395 frame@b124000 { 396 frame-number = <2>; 397 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 398 reg = <0x0b124000 0x1000>; 399 status = "disabled"; 400 }; 401 402 frame@b125000 { 403 reg = <0x0b125000 0x1000>; 404 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 405 frame-number = <3>; 406 status = "disabled"; 407 }; 408 409 frame@b126000 { 410 reg = <0x0b126000 0x1000>; 411 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 412 frame-number = <4>; 413 status = "disabled"; 414 }; 415 416 frame@b127000 { 417 reg = <0x0b127000 0x1000>; 418 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 419 frame-number = <5>; 420 status = "disabled"; 421 }; 422 423 frame@b128000 { 424 reg = <0x0b128000 0x1000>; 425 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 426 frame-number = <6>; 427 status = "disabled"; 428 }; 429 }; 430 431 pcie1: pcie@80000000 { 432 compatible = "qcom,pcie-ipq5018"; 433 reg = <0x80000000 0xf1d>, 434 <0x80000f20 0xa8>, 435 <0x80001000 0x1000>, 436 <0x00078000 0x3000>, 437 <0x80100000 0x1000>, 438 <0x0007b000 0x1000>; 439 reg-names = "dbi", 440 "elbi", 441 "atu", 442 "parf", 443 "config", 444 "mhi"; 445 device_type = "pci"; 446 linux,pci-domain = <1>; 447 bus-range = <0x00 0xff>; 448 num-lanes = <1>; 449 #address-cells = <3>; 450 #size-cells = <2>; 451 452 /* The controller supports Gen3, but the connected PHY is Gen2-capable */ 453 max-link-speed = <2>; 454 455 phys = <&pcie1_phy>; 456 phy-names ="pciephy"; 457 458 ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, 459 <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; 460 461 msi-map = <0x0 &v2m0 0x0 0xff8>; 462 463 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 472 interrupt-names = "msi0", 473 "msi1", 474 "msi2", 475 "msi3", 476 "msi4", 477 "msi5", 478 "msi6", 479 "msi7", 480 "global"; 481 482 #interrupt-cells = <1>; 483 interrupt-map-mask = <0 0 0 0x7>; 484 interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>, 485 <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>, 486 <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>, 487 <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>; 488 489 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 490 <&gcc GCC_PCIE1_AXI_M_CLK>, 491 <&gcc GCC_PCIE1_AXI_S_CLK>, 492 <&gcc GCC_PCIE1_AHB_CLK>, 493 <&gcc GCC_PCIE1_AUX_CLK>, 494 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; 495 clock-names = "iface", 496 "axi_m", 497 "axi_s", 498 "ahb", 499 "aux", 500 "axi_bridge"; 501 502 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 503 <&gcc GCC_PCIE1_SLEEP_ARES>, 504 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 505 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 506 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 507 <&gcc GCC_PCIE1_AHB_ARES>, 508 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, 509 <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; 510 reset-names = "pipe", 511 "sleep", 512 "sticky", 513 "axi_m", 514 "axi_s", 515 "ahb", 516 "axi_m_sticky", 517 "axi_s_sticky"; 518 519 status = "disabled"; 520 521 pcie@0 { 522 device_type = "pci"; 523 reg = <0x0 0x0 0x0 0x0 0x0>; 524 bus-range = <0x01 0xff>; 525 526 #address-cells = <3>; 527 #size-cells = <2>; 528 ranges; 529 }; 530 }; 531 532 pcie0: pcie@a0000000 { 533 compatible = "qcom,pcie-ipq5018"; 534 reg = <0xa0000000 0xf1d>, 535 <0xa0000f20 0xa8>, 536 <0xa0001000 0x1000>, 537 <0x00080000 0x3000>, 538 <0xa0100000 0x1000>, 539 <0x00083000 0x1000>; 540 reg-names = "dbi", 541 "elbi", 542 "atu", 543 "parf", 544 "config", 545 "mhi"; 546 device_type = "pci"; 547 linux,pci-domain = <0>; 548 bus-range = <0x00 0xff>; 549 num-lanes = <2>; 550 #address-cells = <3>; 551 #size-cells = <2>; 552 553 /* The controller supports Gen3, but the connected PHY is Gen2-capable */ 554 max-link-speed = <2>; 555 556 phys = <&pcie0_phy>; 557 phy-names ="pciephy"; 558 559 ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, 560 <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; 561 562 msi-map = <0x0 &v2m0 0x0 0xff8>; 563 564 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "msi0", 574 "msi1", 575 "msi2", 576 "msi3", 577 "msi4", 578 "msi5", 579 "msi6", 580 "msi7", 581 "global"; 582 583 #interrupt-cells = <1>; 584 interrupt-map-mask = <0 0 0 0x7>; 585 interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, 586 <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, 587 <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, 588 <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; 589 590 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 591 <&gcc GCC_PCIE0_AXI_M_CLK>, 592 <&gcc GCC_PCIE0_AXI_S_CLK>, 593 <&gcc GCC_PCIE0_AHB_CLK>, 594 <&gcc GCC_PCIE0_AUX_CLK>, 595 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; 596 clock-names = "iface", 597 "axi_m", 598 "axi_s", 599 "ahb", 600 "aux", 601 "axi_bridge"; 602 603 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 604 <&gcc GCC_PCIE0_SLEEP_ARES>, 605 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 606 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 607 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 608 <&gcc GCC_PCIE0_AHB_ARES>, 609 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 610 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 611 reset-names = "pipe", 612 "sleep", 613 "sticky", 614 "axi_m", 615 "axi_s", 616 "ahb", 617 "axi_m_sticky", 618 "axi_s_sticky"; 619 620 status = "disabled"; 621 622 pcie@0 { 623 device_type = "pci"; 624 reg = <0x0 0x0 0x0 0x0 0x0>; 625 bus-range = <0x01 0xff>; 626 627 #address-cells = <3>; 628 #size-cells = <2>; 629 ranges; 630 }; 631 }; 632 }; 633 634 timer { 635 compatible = "arm,armv8-timer"; 636 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 637 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 638 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 639 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 640 }; 641}; 642