1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef __DTS_GLYMUR_MAILBOX_IPCC_H 7 #define __DTS_GLYMUR_MAILBOX_IPCC_H 8 9 /* Glymur physical client IDs */ 10 #define IPCC_MPROC_AOP 0 11 #define IPCC_MPROC_TZ 1 12 #define IPCC_MPROC_MPSS 2 13 #define IPCC_MPROC_LPASS 3 14 #define IPCC_MPROC_SLPI 4 15 #define IPCC_MPROC_SDC 5 16 #define IPCC_MPROC_CDSP 6 17 #define IPCC_MPROC_NPU 7 18 #define IPCC_MPROC_APSS 8 19 #define IPCC_MPROC_GPU 9 20 #define IPCC_MPROC_ICP 11 21 #define IPCC_MPROC_VPU 12 22 #define IPCC_MPROC_PCIE0 13 23 #define IPCC_MPROC_PCIE1 14 24 #define IPCC_MPROC_PCIE2 15 25 #define IPCC_MPROC_SPSS 16 26 #define IPCC_MPROC_PCIE3 19 27 #define IPCC_MPROC_PCIE4 20 28 #define IPCC_MPROC_PCIE5 21 29 #define IPCC_MPROC_PCIE6 22 30 #define IPCC_MPROC_TME 23 31 #define IPCC_MPROC_WPSS 24 32 #define IPCC_MPROC_PCIE7 44 33 #define IPCC_MPROC_SOCCP 46 34 35 #define IPCC_COMPUTE_L0_LPASS 0 36 #define IPCC_COMPUTE_L0_CDSP 1 37 #define IPCC_COMPUTE_L0_APSS 2 38 #define IPCC_COMPUTE_L0_GPU 3 39 #define IPCC_COMPUTE_L0_CVP 6 40 #define IPCC_COMPUTE_L0_ICP 7 41 #define IPCC_COMPUTE_L0_VPU 8 42 #define IPCC_COMPUTE_L0_DPU 9 43 #define IPCC_COMPUTE_L0_SOCCP 11 44 45 #define IPCC_COMPUTE_L1_LPASS 0 46 #define IPCC_COMPUTE_L1_CDSP 1 47 #define IPCC_COMPUTE_L1_APSS 2 48 #define IPCC_COMPUTE_L1_GPU 3 49 #define IPCC_COMPUTE_L1_CVP 6 50 #define IPCC_COMPUTE_L1_ICP 7 51 #define IPCC_COMPUTE_L1_VPU 8 52 #define IPCC_COMPUTE_L1_DPU 9 53 #define IPCC_COMPUTE_L1_SOCCP 11 54 55 #define IPCC_PERIPH_LPASS 0 56 #define IPCC_PERIPH_APSS 1 57 #define IPCC_PERIPH_PCIE0 2 58 #define IPCC_PERIPH_PCIE1 3 59 #define IPCC_PERIPH_PCIE2 6 60 #define IPCC_PERIPH_PCIE3 7 61 #define IPCC_PERIPH_PCIE4 8 62 #define IPCC_PERIPH_PCIE5 9 63 #define IPCC_PERIPH_PCIE6 10 64 #define IPCC_PERIPH_PCIE7 11 65 #define IPCC_PERIPH_SOCCP 13 66 #define IPCC_PERIPH_WPSS 16 67 68 #endif 69