1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 3#include <dt-bindings/clock/nvidia,tegra264.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/nvidia,tegra264.h> 7#include <dt-bindings/reset/nvidia,tegra264.h> 8 9/ { 10 compatible = "nvidia,tegra264"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 reserved-memory { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 ranges; 19 20 shmem_bpmp: shmem@86070000 { 21 compatible = "nvidia,tegra264-bpmp-shmem"; 22 reg = <0x0 0x86070000 0x0 0x2000>; 23 no-map; 24 }; 25 }; 26 27 /* SYSTEM MMIO */ 28 bus@0 { 29 compatible = "simple-bus"; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>; 35 36 misc@100000 { 37 compatible = "nvidia,tegra234-misc"; 38 reg = <0x0 0x00100000 0x0 0x0f000>, 39 <0x0 0x0c140000 0x0 0x10000>; 40 }; 41 42 timer@8000000 { 43 compatible = "nvidia,tegra234-timer"; 44 reg = <0x0 0x08000000 0x0 0x140000>; 45 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>; 49 status = "disabled"; 50 }; 51 52 gpcdma: dma-controller@8400000 { 53 compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma"; 54 reg = <0x0 0x08400000 0x0 0x210000>; 55 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 87 #dma-cells = <1>; 88 iommus = <&smmu1 0x00000800>; 89 dma-coherent; 90 dma-channel-mask = <0xfffffffe>; 91 status = "disabled"; 92 }; 93 94 hsp_top: hsp@8800000 { 95 compatible = "nvidia,tegra264-hsp"; 96 reg = <0x0 0x08800000 0x0 0xd0000>; 97 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 106 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 107 "shared3", "shared4", "shared5", "shared6", 108 "shared7"; 109 #mbox-cells = <2>; 110 }; 111 112 rtc: rtc@c2c0000 { 113 compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc"; 114 reg = <0x0 0x0c2c0000 0x0 0x10000>; 115 interrupt-parent = <&pmc>; 116 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&bpmp TEGRA264_CLK_CLK_S>; 118 clock-names = "rtc"; 119 status = "disabled"; 120 }; 121 122 serial@c4e0000 { 123 compatible = "nvidia,tegra264-utc"; 124 reg = <0x0 0x0c4e0000 0x0 0x8000>, 125 <0x0 0x0c4e8000 0x0 0x8000>; 126 reg-names = "tx", "rx"; 127 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 128 rx-threshold = <4>; 129 tx-threshold = <4>; 130 status = "disabled"; 131 }; 132 133 serial@c5a0000 { 134 compatible = "nvidia,tegra264-utc"; 135 reg = <0x0 0x0c5a0000 0x0 0x8000>, 136 <0x0 0x0c5a8000 0x0 0x8000>; 137 reg-names = "tx", "rx"; 138 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 139 rx-threshold = <4>; 140 tx-threshold = <4>; 141 status = "disabled"; 142 }; 143 144 uart0: serial@c5f0000 { 145 compatible = "arm,sbsa-uart"; 146 reg = <0x0 0x0c5f0000 0x0 0x10000>; 147 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; 148 status = "disabled"; 149 }; 150 151 pmc: pmc@c800000 { 152 compatible = "nvidia,tegra264-pmc"; 153 reg = <0x0 0x0c800000 0x0 0x100000>, 154 <0x0 0x0c990000 0x0 0x10000>, 155 <0x0 0x0ca00000 0x0 0x10000>, 156 <0x0 0x0c980000 0x0 0x10000>, 157 <0x0 0x0c9c0000 0x0 0x40000>; 158 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 159 #interrupt-cells = <2>; 160 interrupt-controller; 161 }; 162 }; 163 164 /* TOP_MMIO */ 165 bus@8100000000 { 166 compatible = "simple-bus"; 167 168 #address-cells = <2>; 169 #size-cells = <2>; 170 171 ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */ 172 <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */ 173 <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */ 174 175 smmu1: iommu@5000000 { 176 compatible = "arm,smmu-v3"; 177 reg = <0x00 0x5000000 0x0 0x200000>; 178 interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 179 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>; 180 interrupt-names = "eventq", "gerror"; 181 status = "disabled"; 182 183 #iommu-cells = <1>; 184 dma-coherent; 185 }; 186 187 smmu2: iommu@6000000 { 188 compatible = "arm,smmu-v3"; 189 reg = <0x00 0x6000000 0x0 0x200000>; 190 interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, 191 <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 192 interrupt-names = "eventq", "gerror"; 193 status = "disabled"; 194 195 #iommu-cells = <1>; 196 dma-coherent; 197 }; 198 199 mc: memory-controller@8020000 { 200 compatible = "nvidia,tegra264-mc"; 201 reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */ 202 <0x00 0x8040000 0x0 0x20000>, /* MC 0 */ 203 <0x00 0x8060000 0x0 0x20000>, /* MC 1 */ 204 <0x00 0x8080000 0x0 0x20000>, /* MC 2 */ 205 <0x00 0x80a0000 0x0 0x20000>, /* MC 3 */ 206 <0x00 0x80c0000 0x0 0x20000>, /* MC 4 */ 207 <0x00 0x80e0000 0x0 0x20000>, /* MC 5 */ 208 <0x00 0x8100000 0x0 0x20000>, /* MC 6 */ 209 <0x00 0x8120000 0x0 0x20000>, /* MC 7 */ 210 <0x00 0x8140000 0x0 0x20000>, /* MC 8 */ 211 <0x00 0x8160000 0x0 0x20000>, /* MC 9 */ 212 <0x00 0x8180000 0x0 0x20000>, /* MC 10 */ 213 <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */ 214 <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */ 215 <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */ 216 <0x00 0x8200000 0x0 0x20000>, /* MC 14 */ 217 <0x00 0x8220000 0x0 0x20000>; /* MC 15 */ 218 reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3", 219 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", 220 "ch10", "ch11", "ch12", "ch13", "ch14", 221 "ch15"; 222 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 230 #interconnect-cells = <1>; 231 232 #address-cells = <2>; 233 #size-cells = <2>; 234 235 /* limit the DMA range for memory clients to [39:0] */ 236 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 237 238 emc: external-memory-controller@8800000 { 239 compatible = "nvidia,tegra264-emc"; 240 reg = <0x00 0x8800000 0x0 0x20000>, 241 <0x00 0x8890000 0x0 0x20000>; 242 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&bpmp TEGRA264_CLK_EMC>; 244 clock-names = "emc"; 245 246 #interconnect-cells = <0>; 247 nvidia,bpmp = <&bpmp>; 248 }; 249 }; 250 251 smmu0: iommu@a000000 { 252 compatible = "arm,smmu-v3"; 253 reg = <0x00 0xa000000 0x0 0x200000>; 254 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 255 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 256 interrupt-names = "eventq", "gerror"; 257 status = "disabled"; 258 259 #iommu-cells = <1>; 260 dma-coherent; 261 }; 262 263 smmu4: iommu@b000000 { 264 compatible = "arm,smmu-v3"; 265 reg = <0x00 0xb000000 0x0 0x200000>; 266 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 267 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 268 interrupt-names = "eventq", "gerror"; 269 status = "disabled"; 270 271 #iommu-cells = <1>; 272 dma-coherent; 273 }; 274 275 gic: interrupt-controller@46000000 { 276 compatible = "arm,gic-v3"; 277 reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */ 278 <0x00 0x46080000 0x0 0x400000>; /* GICR */ 279 interrupt-parent = <&gic>; 280 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 281 282 redistributor-stride = <0x0 0x40000>; 283 #redistributor-regions = <1>; 284 #interrupt-cells = <3>; 285 interrupt-controller; 286 287 #address-cells = <2>; 288 #size-cells = <2>; 289 290 ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>; 291 292 its: msi-controller@40000 { 293 compatible = "arm,gic-v3-its"; 294 reg = <0x0 0x40000 0x0 0x40000>; 295 #msi-cells = <1>; 296 msi-controller; 297 }; 298 }; 299 }; 300 301 /* DISP_USB MMIO */ 302 bus@8800000000 { 303 compatible = "simple-bus"; 304 #address-cells = <2>; 305 #size-cells = <2>; 306 307 ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; 308 309 smmu3: iommu@6000000 { 310 compatible = "arm,smmu-v3"; 311 reg = <0x00 0x6000000 0x0 0x200000>; 312 interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>; 314 interrupt-names = "eventq", "gerror"; 315 status = "disabled"; 316 317 #iommu-cells = <1>; 318 dma-coherent; 319 }; 320 }; 321 322 /* UPHY MMIO */ 323 bus@a800000000 { 324 compatible = "simple-bus"; 325 #address-cells = <2>; 326 #size-cells = <2>; 327 328 ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */ 329 <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */ 330 }; 331 332 cpus { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 336 cpu0: cpu@0 { 337 compatible = "arm,armv8"; 338 device_type = "cpu"; 339 reg = <0x00000>; 340 status = "okay"; 341 342 enable-method = "psci"; 343 344 i-cache-size = <65536>; 345 i-cache-line-size = <64>; 346 i-cache-sets = <256>; 347 d-cache-size = <65536>; 348 d-cache-line-size = <64>; 349 d-cache-sets = <256>; 350 }; 351 352 cpu1: cpu@1 { 353 compatible = "arm,armv8"; 354 device_type = "cpu"; 355 reg = <0x10000>; 356 status = "okay"; 357 358 enable-method = "psci"; 359 360 i-cache-size = <65536>; 361 i-cache-line-size = <64>; 362 i-cache-sets = <256>; 363 d-cache-size = <65536>; 364 d-cache-line-size = <64>; 365 d-cache-sets = <256>; 366 }; 367 }; 368 369 bpmp: bpmp { 370 compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp"; 371 mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB 372 TEGRA_HSP_DB_MASTER_BPMP>; 373 memory-region = <&shmem_bpmp>; 374 #clock-cells = <1>; 375 #reset-cells = <1>; 376 #power-domain-cells = <1>; 377 378 i2c { 379 compatible = "nvidia,tegra186-bpmp-i2c"; 380 nvidia,bpmp-bus-id = <5>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 }; 384 385 thermal { 386 compatible = "nvidia,tegra186-bpmp-thermal"; 387 #thermal-sensor-cells = <1>; 388 }; 389 }; 390 391 pmu { 392 compatible = "arm,armv8-pmuv3"; 393 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 394 status = "okay"; 395 }; 396 397 psci { 398 compatible = "arm,psci-1.0"; 399 status = "okay"; 400 method = "smc"; 401 }; 402 403 timer { 404 compatible = "arm,armv8-timer"; 405 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 406 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 407 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 408 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 409 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 410 status = "okay"; 411 }; 412}; 413