xref: /linux/scripts/dtc/include-prefixes/arm64/nvidia/tegra210-p2371-2180.dts (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1)
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include "tegra210-p2180.dtsi"
5#include "tegra210-p2597.dtsi"
6
7/ {
8	model = "NVIDIA Jetson TX1 Developer Kit";
9	compatible = "nvidia,p2371-2180", "nvidia,tegra210";
10
11	pcie@1003000 {
12		status = "okay";
13
14		hvddio-pex-supply = <&vdd_1v8>;
15		dvddio-pex-supply = <&vdd_pex_1v05>;
16		vddio-pex-ctl-supply = <&vdd_1v8>;
17
18		pci@1,0 {
19			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
20			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
21			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
22			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
23			phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
24			status = "okay";
25		};
26
27		pci@2,0 {
28			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
29			phy-names = "pcie-0";
30			status = "okay";
31		};
32	};
33
34	host1x@50000000 {
35		dsi@54300000 {
36			status = "okay";
37
38			avdd-dsi-csi-supply = <&vdd_dsi_csi>;
39
40			panel@0 {
41				compatible = "auo,b080uan01";
42				reg = <0>;
43
44				enable-gpios = <&gpio TEGRA_GPIO(V, 2)
45						GPIO_ACTIVE_HIGH>;
46				power-supply = <&vdd_5v0_io>;
47				backlight = <&backlight>;
48			};
49		};
50	};
51
52	i2c@7000c400 {
53		backlight: backlight@2c {
54			compatible = "ti,lp8557";
55			reg = <0x2c>;
56			power-supply = <&vdd_3v3_sys>;
57
58			dev-ctrl = /bits/ 8 <0x80>;
59			init-brt = /bits/ 8 <0xff>;
60
61			pwms = <&pwm 0 29334>;
62			pwm-names = "lp8557";
63
64			/* boost frequency 1 MHz */
65			rom-13h {
66				rom-addr = /bits/ 8 <0x13>;
67				rom-val = /bits/ 8 <0x01>;
68			};
69
70			/* 3 LED string */
71			rom-14h {
72				rom-addr = /bits/ 8 <0x14>;
73				rom-val = /bits/ 8 <0x87>;
74			};
75		};
76	};
77
78	i2c@7000c500 {
79		/* carrier board ID EEPROM */
80		eeprom@57 {
81			compatible = "atmel,24c02";
82			reg = <0x57>;
83
84			label = "system";
85			vcc-supply = <&vdd_1v8>;
86			address-width = <8>;
87			pagesize = <8>;
88			size = <256>;
89			read-only;
90		};
91	};
92
93	cec@70015000 {
94		status = "okay";
95
96		hdmi-phandle = <&sor1>;
97	};
98
99	clock@70110000 {
100		status = "okay";
101
102		nvidia,cf = <6>;
103		nvidia,ci = <0>;
104		nvidia,cg = <2>;
105		nvidia,droop-ctrl = <0x00000f00>;
106		nvidia,force-mode = <1>;
107		nvidia,sample-rate = <25000>;
108
109		nvidia,pwm-min-microvolts = <708000>;
110		nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
111		nvidia,pwm-to-pmic;
112		nvidia,pwm-tristate-microvolts = <1000000>;
113		nvidia,pwm-voltage-step-microvolts = <19200>;
114
115		pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
116		pinctrl-0 = <&dvfs_pwm_active_state>;
117		pinctrl-1 = <&dvfs_pwm_inactive_state>;
118	};
119
120	aconnect@702c0000 {
121		status = "okay";
122
123		ahub@702d0800 {
124			status = "okay";
125
126			admaif@702d0000 {
127				status = "okay";
128			};
129
130			i2s@702d1000 {
131				status = "okay";
132
133				ports {
134					#address-cells = <1>;
135					#size-cells = <0>;
136
137					port@0 {
138						reg = <0>;
139
140						i2s1_cif_ep: endpoint {
141							remote-endpoint = <&xbar_i2s1_ep>;
142						};
143					};
144
145					i2s1_port: port@1 {
146						reg = <1>;
147
148						i2s1_dap_ep: endpoint {
149							dai-format = "i2s";
150							/* Placeholder for external Codec */
151						};
152					};
153				};
154			};
155
156			i2s@702d1100 {
157				status = "okay";
158
159				ports {
160					#address-cells = <1>;
161					#size-cells = <0>;
162
163					port@0 {
164						reg = <0>;
165
166						i2s2_cif_ep: endpoint {
167							remote-endpoint = <&xbar_i2s2_ep>;
168						};
169					};
170
171					i2s2_port: port@1 {
172						reg = <1>;
173
174						i2s2_dap_ep: endpoint {
175							dai-format = "i2s";
176							/* Placeholder for external Codec */
177						};
178					};
179				};
180			};
181
182			i2s@702d1200 {
183				status = "okay";
184
185				ports {
186					#address-cells = <1>;
187					#size-cells = <0>;
188
189					port@0 {
190						reg = <0>;
191
192						i2s3_cif_ep: endpoint {
193							remote-endpoint = <&xbar_i2s3_ep>;
194						};
195					};
196
197					i2s3_port: port@1 {
198						reg = <1>;
199
200						i2s3_dap_ep: endpoint {
201							dai-format = "i2s";
202							/* Placeholder for external Codec */
203						};
204					};
205				};
206			};
207
208			i2s@702d1300 {
209				status = "okay";
210
211				ports {
212					#address-cells = <1>;
213					#size-cells = <0>;
214
215					port@0 {
216						reg = <0>;
217
218						i2s4_cif_ep: endpoint {
219							remote-endpoint = <&xbar_i2s4_ep>;
220						};
221					};
222
223					i2s4_port: port@1 {
224						reg = <1>;
225
226						i2s4_dap_ep: endpoint {
227							dai-format = "i2s";
228							/* Placeholder for external Codec */
229						};
230					};
231				};
232			};
233
234			i2s@702d1400 {
235				status = "okay";
236
237				ports {
238					#address-cells = <1>;
239					#size-cells = <0>;
240
241					port@0 {
242						reg = <0>;
243
244						i2s5_cif_ep: endpoint {
245							remote-endpoint = <&xbar_i2s5_ep>;
246						};
247					};
248
249					i2s5_port: port@1 {
250						reg = <1>;
251
252						i2s5_dap_ep: endpoint {
253							dai-format = "i2s";
254							/* Placeholder for external Codec */
255						};
256					};
257				};
258			};
259
260			sfc@702d2000 {
261				status = "okay";
262
263				ports {
264					#address-cells = <1>;
265					#size-cells = <0>;
266
267					port@0 {
268						reg = <0>;
269
270						sfc1_cif_in_ep: endpoint {
271							remote-endpoint = <&xbar_sfc1_in_ep>;
272						};
273					};
274
275					sfc1_out_port: port@1 {
276						reg = <1>;
277
278						sfc1_cif_out_ep: endpoint {
279							remote-endpoint = <&xbar_sfc1_out_ep>;
280						};
281					};
282				};
283			};
284
285			sfc@702d2200 {
286				status = "okay";
287
288				ports {
289					#address-cells = <1>;
290					#size-cells = <0>;
291
292					port@0 {
293						reg = <0>;
294
295						sfc2_cif_in_ep: endpoint {
296							remote-endpoint = <&xbar_sfc2_in_ep>;
297						};
298					};
299
300					sfc2_out_port: port@1 {
301						reg = <1>;
302
303						sfc2_cif_out_ep: endpoint {
304							remote-endpoint = <&xbar_sfc2_out_ep>;
305						};
306					};
307				};
308			};
309
310			sfc@702d2400 {
311				status = "okay";
312
313				ports {
314					#address-cells = <1>;
315					#size-cells = <0>;
316
317					port@0 {
318						reg = <0>;
319
320						sfc3_cif_in_ep: endpoint {
321							remote-endpoint = <&xbar_sfc3_in_ep>;
322						};
323					};
324
325					sfc3_out_port: port@1 {
326						reg = <1>;
327
328						sfc3_cif_out_ep: endpoint {
329							remote-endpoint = <&xbar_sfc3_out_ep>;
330						};
331					};
332				};
333			};
334
335			sfc@702d2600 {
336				status = "okay";
337
338				ports {
339					#address-cells = <1>;
340					#size-cells = <0>;
341
342					port@0 {
343						reg = <0>;
344
345						sfc4_cif_in_ep: endpoint {
346							remote-endpoint = <&xbar_sfc4_in_ep>;
347						};
348					};
349
350					sfc4_out_port: port@1 {
351						reg = <1>;
352
353						sfc4_cif_out_ep: endpoint {
354							remote-endpoint = <&xbar_sfc4_out_ep>;
355						};
356					};
357				};
358			};
359
360			amx@702d3000 {
361				status = "okay";
362
363				ports {
364					#address-cells = <1>;
365					#size-cells = <0>;
366
367					port@0 {
368						reg = <0>;
369
370						amx1_in1_ep: endpoint {
371							remote-endpoint = <&xbar_amx1_in1_ep>;
372						};
373					};
374
375					port@1 {
376						reg = <1>;
377
378						amx1_in2_ep: endpoint {
379							remote-endpoint = <&xbar_amx1_in2_ep>;
380						};
381					};
382
383					port@2 {
384						reg = <2>;
385
386						amx1_in3_ep: endpoint {
387							remote-endpoint = <&xbar_amx1_in3_ep>;
388						};
389					};
390
391					port@3 {
392						reg = <3>;
393
394						amx1_in4_ep: endpoint {
395							remote-endpoint = <&xbar_amx1_in4_ep>;
396						};
397					};
398
399					amx1_out_port: port@4 {
400						reg = <4>;
401
402						amx1_out_ep: endpoint {
403							remote-endpoint = <&xbar_amx1_out_ep>;
404						};
405					};
406				};
407			};
408
409			amx@702d3100 {
410				status = "okay";
411
412				ports {
413					#address-cells = <1>;
414					#size-cells = <0>;
415
416					port@0 {
417						reg = <0>;
418
419						amx2_in1_ep: endpoint {
420							remote-endpoint = <&xbar_amx2_in1_ep>;
421						};
422					};
423
424					port@1 {
425						reg = <1>;
426
427						amx2_in2_ep: endpoint {
428							remote-endpoint = <&xbar_amx2_in2_ep>;
429						};
430					};
431
432					amx2_in3_port: port@2 {
433						reg = <2>;
434
435						amx2_in3_ep: endpoint {
436							remote-endpoint = <&xbar_amx2_in3_ep>;
437						};
438					};
439
440					amx2_in4_port: port@3 {
441						reg = <3>;
442
443						amx2_in4_ep: endpoint {
444							remote-endpoint = <&xbar_amx2_in4_ep>;
445						};
446					};
447
448					amx2_out_port: port@4 {
449						reg = <4>;
450
451						amx2_out_ep: endpoint {
452							remote-endpoint = <&xbar_amx2_out_ep>;
453						};
454					};
455				};
456			};
457
458			adx@702d3800 {
459				status = "okay";
460
461				ports {
462					#address-cells = <1>;
463					#size-cells = <0>;
464
465					port@0 {
466						reg = <0>;
467
468						adx1_in_ep: endpoint {
469							remote-endpoint = <&xbar_adx1_in_ep>;
470						};
471					};
472
473					adx1_out1_port: port@1 {
474						reg = <1>;
475
476						adx1_out1_ep: endpoint {
477							remote-endpoint = <&xbar_adx1_out1_ep>;
478						};
479					};
480
481					adx1_out2_port: port@2 {
482						reg = <2>;
483
484						adx1_out2_ep: endpoint {
485							remote-endpoint = <&xbar_adx1_out2_ep>;
486						};
487					};
488
489					adx1_out3_port: port@3 {
490						reg = <3>;
491
492						adx1_out3_ep: endpoint {
493							remote-endpoint = <&xbar_adx1_out3_ep>;
494						};
495					};
496
497					adx1_out4_port: port@4 {
498						reg = <4>;
499
500						adx1_out4_ep: endpoint {
501							remote-endpoint = <&xbar_adx1_out4_ep>;
502						};
503					};
504				};
505			};
506
507			adx@702d3900 {
508				status = "okay";
509
510				ports {
511					#address-cells = <1>;
512					#size-cells = <0>;
513
514					port@0 {
515						reg = <0>;
516
517						adx2_in_ep: endpoint {
518							remote-endpoint = <&xbar_adx2_in_ep>;
519						};
520					};
521
522					adx2_out1_port: port@1 {
523						reg = <1>;
524
525						adx2_out1_ep: endpoint {
526							remote-endpoint = <&xbar_adx2_out1_ep>;
527						};
528					};
529
530					adx2_out2_port: port@2 {
531						reg = <2>;
532
533						adx2_out2_ep: endpoint {
534							remote-endpoint = <&xbar_adx2_out2_ep>;
535						};
536					};
537
538					adx2_out3_port: port@3 {
539						reg = <3>;
540
541						adx2_out3_ep: endpoint {
542							remote-endpoint = <&xbar_adx2_out3_ep>;
543						};
544					};
545
546					adx2_out4_port: port@4 {
547						reg = <4>;
548
549						adx2_out4_ep: endpoint {
550							remote-endpoint = <&xbar_adx2_out4_ep>;
551						};
552					};
553				};
554			};
555
556			dmic@702d4000 {
557				status = "okay";
558
559				ports {
560					#address-cells = <1>;
561					#size-cells = <0>;
562
563					port@0 {
564						reg = <0>;
565
566						dmic1_cif_ep: endpoint {
567							remote-endpoint = <&xbar_dmic1_ep>;
568						};
569					};
570
571					dmic1_port: port@1 {
572						reg = <1>;
573
574						dmic1_dap_ep: endpoint {
575							/* Placeholder for external Codec */
576						};
577					};
578				};
579			};
580
581			dmic@702d4100 {
582				status = "okay";
583
584				ports {
585					#address-cells = <1>;
586					#size-cells = <0>;
587
588					port@0 {
589						reg = <0>;
590
591						dmic2_cif_ep: endpoint {
592							remote-endpoint = <&xbar_dmic2_ep>;
593						};
594					};
595
596					dmic2_port: port@1 {
597						reg = <1>;
598
599						dmic2_dap_ep: endpoint {
600							/* Placeholder for external Codec */
601						};
602					};
603				};
604			};
605
606			dmic@702d4200 {
607				status = "okay";
608
609				ports {
610					#address-cells = <1>;
611					#size-cells = <0>;
612
613					port@0 {
614						reg = <0>;
615
616						dmic3_cif_ep: endpoint {
617							remote-endpoint = <&xbar_dmic3_ep>;
618						};
619					};
620
621					dmic3_port: port@1 {
622						reg = <1>;
623
624						dmic3_dap_ep: endpoint {
625							/* Placeholder for external Codec */
626						};
627					};
628				};
629			};
630
631			processing-engine@702d8000 {
632				status = "okay";
633
634				ports {
635					#address-cells = <1>;
636					#size-cells = <0>;
637
638					port@0 {
639						reg = <0x0>;
640
641						ope1_cif_in_ep: endpoint {
642							remote-endpoint = <&xbar_ope1_in_ep>;
643						};
644					};
645
646					ope1_out_port: port@1 {
647						reg = <0x1>;
648
649						ope1_cif_out_ep: endpoint {
650							remote-endpoint = <&xbar_ope1_out_ep>;
651						};
652					};
653				};
654			};
655
656			processing-engine@702d8400 {
657				status = "okay";
658
659				ports {
660					#address-cells = <1>;
661					#size-cells = <0>;
662
663					port@0 {
664						reg = <0x0>;
665
666						ope2_cif_in_ep: endpoint {
667							remote-endpoint = <&xbar_ope2_in_ep>;
668						};
669					};
670
671					ope2_out_port: port@1 {
672						reg = <0x1>;
673
674						ope2_cif_out_ep: endpoint {
675							remote-endpoint = <&xbar_ope2_out_ep>;
676						};
677					};
678				};
679			};
680
681			mvc@702da000 {
682				status = "okay";
683
684				ports {
685					#address-cells = <1>;
686					#size-cells = <0>;
687
688					port@0 {
689						reg = <0>;
690
691						mvc1_cif_in_ep: endpoint {
692							remote-endpoint = <&xbar_mvc1_in_ep>;
693						};
694					};
695
696					mvc1_out_port: port@1 {
697						reg = <1>;
698
699						mvc1_cif_out_ep: endpoint {
700							remote-endpoint = <&xbar_mvc1_out_ep>;
701						};
702					};
703				};
704			};
705
706			mvc@702da200 {
707				status = "okay";
708
709				ports {
710					#address-cells = <1>;
711					#size-cells = <0>;
712
713					port@0 {
714						reg = <0>;
715
716						mvc2_cif_in_ep: endpoint {
717							remote-endpoint = <&xbar_mvc2_in_ep>;
718						};
719					};
720
721					mvc2_out_port: port@1 {
722						reg = <1>;
723
724						mvc2_cif_out_ep: endpoint {
725							remote-endpoint = <&xbar_mvc2_out_ep>;
726						};
727					};
728				};
729			};
730
731			amixer@702dbb00 {
732				status = "okay";
733
734				ports {
735					#address-cells = <1>;
736					#size-cells = <0>;
737
738					port@0 {
739						reg = <0x0>;
740
741						mixer_in1_ep: endpoint {
742							remote-endpoint = <&xbar_mixer_in1_ep>;
743						};
744					};
745
746					port@1 {
747						reg = <0x1>;
748
749						mixer_in2_ep: endpoint {
750							remote-endpoint = <&xbar_mixer_in2_ep>;
751						};
752					};
753
754					port@2 {
755						reg = <0x2>;
756
757						mixer_in3_ep: endpoint {
758							remote-endpoint = <&xbar_mixer_in3_ep>;
759						};
760					};
761
762					port@3 {
763						reg = <0x3>;
764
765						mixer_in4_ep: endpoint {
766							remote-endpoint = <&xbar_mixer_in4_ep>;
767						};
768					};
769
770					port@4 {
771						reg = <0x4>;
772
773						mixer_in5_ep: endpoint {
774							remote-endpoint = <&xbar_mixer_in5_ep>;
775						};
776					};
777
778					port@5 {
779						reg = <0x5>;
780
781						mixer_in6_ep: endpoint {
782							remote-endpoint = <&xbar_mixer_in6_ep>;
783						};
784					};
785
786					port@6 {
787						reg = <0x6>;
788
789						mixer_in7_ep: endpoint {
790							remote-endpoint = <&xbar_mixer_in7_ep>;
791						};
792					};
793
794					port@7 {
795						reg = <0x7>;
796
797						mixer_in8_ep: endpoint {
798							remote-endpoint = <&xbar_mixer_in8_ep>;
799						};
800					};
801
802					port@8 {
803						reg = <0x8>;
804
805						mixer_in9_ep: endpoint {
806							remote-endpoint = <&xbar_mixer_in9_ep>;
807						};
808					};
809
810					port@9 {
811						reg = <0x9>;
812
813						mixer_in10_ep: endpoint {
814							remote-endpoint = <&xbar_mixer_in10_ep>;
815						};
816					};
817
818					mixer_out1_port: port@a {
819						reg = <0xa>;
820
821						mixer_out1_ep: endpoint {
822							remote-endpoint = <&xbar_mixer_out1_ep>;
823						};
824					};
825
826					mixer_out2_port: port@b {
827						reg = <0xb>;
828
829						mixer_out2_ep: endpoint {
830							remote-endpoint = <&xbar_mixer_out2_ep>;
831						};
832					};
833
834					mixer_out3_port: port@c {
835						reg = <0xc>;
836
837						mixer_out3_ep: endpoint {
838							remote-endpoint = <&xbar_mixer_out3_ep>;
839						};
840					};
841
842					mixer_out4_port: port@d {
843						reg = <0xd>;
844
845						mixer_out4_ep: endpoint {
846							remote-endpoint = <&xbar_mixer_out4_ep>;
847						};
848					};
849
850					mixer_out5_port: port@e {
851						reg = <0xe>;
852
853						mixer_out5_ep: endpoint {
854							remote-endpoint = <&xbar_mixer_out5_ep>;
855						};
856					};
857				};
858			};
859
860			ports {
861				xbar_i2s1_port: port@a {
862					reg = <0xa>;
863
864					xbar_i2s1_ep: endpoint {
865						remote-endpoint = <&i2s1_cif_ep>;
866					};
867				};
868
869				xbar_i2s2_port: port@b {
870					reg = <0xb>;
871
872					xbar_i2s2_ep: endpoint {
873						remote-endpoint = <&i2s2_cif_ep>;
874					};
875				};
876
877				xbar_i2s3_port: port@c {
878					reg = <0xc>;
879
880					xbar_i2s3_ep: endpoint {
881						remote-endpoint = <&i2s3_cif_ep>;
882					};
883				};
884
885				xbar_i2s4_port: port@d {
886					reg = <0xd>;
887
888					xbar_i2s4_ep: endpoint {
889						remote-endpoint = <&i2s4_cif_ep>;
890					};
891				};
892
893				xbar_i2s5_port: port@e {
894					reg = <0xe>;
895
896					xbar_i2s5_ep: endpoint {
897						remote-endpoint = <&i2s5_cif_ep>;
898					};
899				};
900
901				xbar_dmic1_port: port@f {
902					reg = <0xf>;
903
904					xbar_dmic1_ep: endpoint {
905						remote-endpoint = <&dmic1_cif_ep>;
906					};
907				};
908
909				xbar_dmic2_port: port@10 {
910					reg = <0x10>;
911
912					xbar_dmic2_ep: endpoint {
913						remote-endpoint = <&dmic2_cif_ep>;
914					};
915				};
916
917				xbar_dmic3_port: port@11 {
918					reg = <0x11>;
919
920					xbar_dmic3_ep: endpoint {
921						remote-endpoint = <&dmic3_cif_ep>;
922					};
923				};
924
925				xbar_sfc1_in_port: port@12 {
926					reg = <0x12>;
927
928					xbar_sfc1_in_ep: endpoint {
929						remote-endpoint = <&sfc1_cif_in_ep>;
930					};
931				};
932
933				port@13 {
934					reg = <0x13>;
935
936					xbar_sfc1_out_ep: endpoint {
937						remote-endpoint = <&sfc1_cif_out_ep>;
938					};
939				};
940
941				xbar_sfc2_in_port: port@14 {
942					reg = <0x14>;
943
944					xbar_sfc2_in_ep: endpoint {
945						remote-endpoint = <&sfc2_cif_in_ep>;
946					};
947				};
948
949				port@15 {
950					reg = <0x15>;
951
952					xbar_sfc2_out_ep: endpoint {
953						remote-endpoint = <&sfc2_cif_out_ep>;
954					};
955				};
956
957				xbar_sfc3_in_port: port@16 {
958					reg = <0x16>;
959
960					xbar_sfc3_in_ep: endpoint {
961						remote-endpoint = <&sfc3_cif_in_ep>;
962					};
963				};
964
965				port@17 {
966					reg = <0x17>;
967
968					xbar_sfc3_out_ep: endpoint {
969						remote-endpoint = <&sfc3_cif_out_ep>;
970					};
971				};
972
973				xbar_sfc4_in_port: port@18 {
974					reg = <0x18>;
975
976					xbar_sfc4_in_ep: endpoint {
977						remote-endpoint = <&sfc4_cif_in_ep>;
978					};
979				};
980
981				port@19 {
982					reg = <0x19>;
983
984					xbar_sfc4_out_ep: endpoint {
985						remote-endpoint = <&sfc4_cif_out_ep>;
986					};
987				};
988
989				xbar_mvc1_in_port: port@1a {
990					reg = <0x1a>;
991
992					xbar_mvc1_in_ep: endpoint {
993						remote-endpoint = <&mvc1_cif_in_ep>;
994					};
995				};
996
997				port@1b {
998					reg = <0x1b>;
999
1000					xbar_mvc1_out_ep: endpoint {
1001						remote-endpoint = <&mvc1_cif_out_ep>;
1002					};
1003				};
1004
1005				xbar_mvc2_in_port: port@1c {
1006					reg = <0x1c>;
1007
1008					xbar_mvc2_in_ep: endpoint {
1009						remote-endpoint = <&mvc2_cif_in_ep>;
1010					};
1011				};
1012
1013				port@1d {
1014					reg = <0x1d>;
1015
1016					xbar_mvc2_out_ep: endpoint {
1017						remote-endpoint = <&mvc2_cif_out_ep>;
1018					};
1019				};
1020
1021				xbar_amx1_in1_port: port@1e {
1022					reg = <0x1e>;
1023
1024					xbar_amx1_in1_ep: endpoint {
1025						remote-endpoint = <&amx1_in1_ep>;
1026					};
1027				};
1028
1029				xbar_amx1_in2_port: port@1f {
1030					reg = <0x1f>;
1031
1032					xbar_amx1_in2_ep: endpoint {
1033						remote-endpoint = <&amx1_in2_ep>;
1034					};
1035				};
1036
1037				xbar_amx1_in3_port: port@20 {
1038					reg = <0x20>;
1039
1040					xbar_amx1_in3_ep: endpoint {
1041						remote-endpoint = <&amx1_in3_ep>;
1042					};
1043				};
1044
1045				xbar_amx1_in4_port: port@21 {
1046					reg = <0x21>;
1047
1048					xbar_amx1_in4_ep: endpoint {
1049						remote-endpoint = <&amx1_in4_ep>;
1050					};
1051				};
1052
1053				port@22 {
1054					reg = <0x22>;
1055
1056					xbar_amx1_out_ep: endpoint {
1057						remote-endpoint = <&amx1_out_ep>;
1058					};
1059				};
1060
1061				xbar_amx2_in1_port: port@23 {
1062					reg = <0x23>;
1063
1064					xbar_amx2_in1_ep: endpoint {
1065						remote-endpoint = <&amx2_in1_ep>;
1066					};
1067				};
1068
1069				xbar_amx2_in2_port: port@24 {
1070					reg = <0x24>;
1071
1072					xbar_amx2_in2_ep: endpoint {
1073						remote-endpoint = <&amx2_in2_ep>;
1074					};
1075				};
1076
1077				xbar_amx2_in3_port: port@25 {
1078					reg = <0x25>;
1079
1080					xbar_amx2_in3_ep: endpoint {
1081						remote-endpoint = <&amx2_in3_ep>;
1082					};
1083				};
1084
1085				xbar_amx2_in4_port: port@26 {
1086					reg = <0x26>;
1087
1088					xbar_amx2_in4_ep: endpoint {
1089						remote-endpoint = <&amx2_in4_ep>;
1090					};
1091				};
1092
1093				port@27 {
1094					reg = <0x27>;
1095
1096					xbar_amx2_out_ep: endpoint {
1097						remote-endpoint = <&amx2_out_ep>;
1098					};
1099				};
1100
1101				xbar_adx1_in_port: port@28 {
1102					reg = <0x28>;
1103
1104					xbar_adx1_in_ep: endpoint {
1105						remote-endpoint = <&adx1_in_ep>;
1106					};
1107				};
1108
1109				port@29 {
1110					reg = <0x29>;
1111
1112					xbar_adx1_out1_ep: endpoint {
1113						remote-endpoint = <&adx1_out1_ep>;
1114					};
1115				};
1116
1117				port@2a {
1118					reg = <0x2a>;
1119
1120					xbar_adx1_out2_ep: endpoint {
1121						remote-endpoint = <&adx1_out2_ep>;
1122					};
1123				};
1124
1125				port@2b {
1126					reg = <0x2b>;
1127
1128					xbar_adx1_out3_ep: endpoint {
1129						remote-endpoint = <&adx1_out3_ep>;
1130					};
1131				};
1132
1133				port@2c {
1134					reg = <0x2c>;
1135
1136					xbar_adx1_out4_ep: endpoint {
1137						remote-endpoint = <&adx1_out4_ep>;
1138					};
1139				};
1140
1141				xbar_adx2_in_port: port@2d {
1142					reg = <0x2d>;
1143
1144					xbar_adx2_in_ep: endpoint {
1145						remote-endpoint = <&adx2_in_ep>;
1146					};
1147				};
1148
1149				port@2e {
1150					reg = <0x2e>;
1151
1152					xbar_adx2_out1_ep: endpoint {
1153						remote-endpoint = <&adx2_out1_ep>;
1154					};
1155				};
1156
1157				port@2f {
1158					reg = <0x2f>;
1159
1160					xbar_adx2_out2_ep: endpoint {
1161						remote-endpoint = <&adx2_out2_ep>;
1162					};
1163				};
1164
1165				port@30 {
1166					reg = <0x30>;
1167
1168					xbar_adx2_out3_ep: endpoint {
1169						remote-endpoint = <&adx2_out3_ep>;
1170					};
1171				};
1172
1173				port@31 {
1174					reg = <0x31>;
1175
1176					xbar_adx2_out4_ep: endpoint {
1177						remote-endpoint = <&adx2_out4_ep>;
1178					};
1179				};
1180
1181				xbar_mixer_in1_port: port@32 {
1182					reg = <0x32>;
1183
1184					xbar_mixer_in1_ep: endpoint {
1185						remote-endpoint = <&mixer_in1_ep>;
1186					};
1187				};
1188
1189				xbar_mixer_in2_port: port@33 {
1190					reg = <0x33>;
1191
1192					xbar_mixer_in2_ep: endpoint {
1193						remote-endpoint = <&mixer_in2_ep>;
1194					};
1195				};
1196
1197				xbar_mixer_in3_port: port@34 {
1198					reg = <0x34>;
1199
1200					xbar_mixer_in3_ep: endpoint {
1201						remote-endpoint = <&mixer_in3_ep>;
1202					};
1203				};
1204
1205				xbar_mixer_in4_port: port@35 {
1206					reg = <0x35>;
1207
1208					xbar_mixer_in4_ep: endpoint {
1209						remote-endpoint = <&mixer_in4_ep>;
1210					};
1211				};
1212
1213				xbar_mixer_in5_port: port@36 {
1214					reg = <0x36>;
1215
1216					xbar_mixer_in5_ep: endpoint {
1217						remote-endpoint = <&mixer_in5_ep>;
1218					};
1219				};
1220
1221				xbar_mixer_in6_port: port@37 {
1222					reg = <0x37>;
1223
1224					xbar_mixer_in6_ep: endpoint {
1225						remote-endpoint = <&mixer_in6_ep>;
1226					};
1227				};
1228
1229				xbar_mixer_in7_port: port@38 {
1230					reg = <0x38>;
1231
1232					xbar_mixer_in7_ep: endpoint {
1233						remote-endpoint = <&mixer_in7_ep>;
1234					};
1235				};
1236
1237				xbar_mixer_in8_port: port@39 {
1238					reg = <0x39>;
1239
1240					xbar_mixer_in8_ep: endpoint {
1241						remote-endpoint = <&mixer_in8_ep>;
1242					};
1243				};
1244
1245				xbar_mixer_in9_port: port@3a {
1246					reg = <0x3a>;
1247
1248					xbar_mixer_in9_ep: endpoint {
1249						remote-endpoint = <&mixer_in9_ep>;
1250					};
1251				};
1252
1253				xbar_mixer_in10_port: port@3b {
1254					reg = <0x3b>;
1255
1256					xbar_mixer_in10_ep: endpoint {
1257						remote-endpoint = <&mixer_in10_ep>;
1258					};
1259				};
1260
1261				port@3c {
1262					reg = <0x3c>;
1263
1264					xbar_mixer_out1_ep: endpoint {
1265						remote-endpoint = <&mixer_out1_ep>;
1266					};
1267				};
1268
1269				port@3d {
1270					reg = <0x3d>;
1271
1272					xbar_mixer_out2_ep: endpoint {
1273						remote-endpoint = <&mixer_out2_ep>;
1274					};
1275				};
1276
1277				port@3e {
1278					reg = <0x3e>;
1279
1280					xbar_mixer_out3_ep: endpoint {
1281						remote-endpoint = <&mixer_out3_ep>;
1282					};
1283				};
1284
1285				port@3f {
1286					reg = <0x3f>;
1287
1288					xbar_mixer_out4_ep: endpoint {
1289						remote-endpoint = <&mixer_out4_ep>;
1290					};
1291				};
1292
1293				port@40 {
1294					reg = <0x40>;
1295
1296					xbar_mixer_out5_ep: endpoint {
1297						remote-endpoint = <&mixer_out5_ep>;
1298					};
1299				};
1300
1301				xbar_ope1_in_port: port@41 {
1302					reg = <0x41>;
1303
1304					xbar_ope1_in_ep: endpoint {
1305						remote-endpoint = <&ope1_cif_in_ep>;
1306					};
1307				};
1308
1309				port@42 {
1310					reg = <0x42>;
1311
1312					xbar_ope1_out_ep: endpoint {
1313						remote-endpoint = <&ope1_cif_out_ep>;
1314					};
1315				};
1316
1317				xbar_ope2_in_port: port@43 {
1318					reg = <0x43>;
1319
1320					xbar_ope2_in_ep: endpoint {
1321						remote-endpoint = <&ope2_cif_in_ep>;
1322					};
1323				};
1324
1325				port@44 {
1326					reg = <0x44>;
1327
1328					xbar_ope2_out_ep: endpoint {
1329						remote-endpoint = <&ope2_cif_out_ep>;
1330					};
1331				};
1332			};
1333		};
1334
1335		dma-controller@702e2000 {
1336			status = "okay";
1337		};
1338
1339		interrupt-controller@702f9000 {
1340			status = "okay";
1341		};
1342	};
1343
1344	sound {
1345		compatible = "nvidia,tegra210-audio-graph-card";
1346		status = "okay";
1347
1348		dais = /* FE */
1349		       <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1350		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
1351		       <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
1352		       <&admaif10_port>,
1353		       /* Router */
1354		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
1355		       <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>,
1356		       <&xbar_dmic2_port>, <&xbar_dmic3_port>,
1357		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
1358		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
1359		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
1360		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
1361		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
1362		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
1363		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
1364		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
1365		       <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
1366		       <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
1367		       <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
1368		       <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
1369		       <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
1370		       <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
1371		       /* HW accelerators */
1372		       <&sfc1_out_port>, <&sfc2_out_port>,
1373		       <&sfc3_out_port>, <&sfc4_out_port>,
1374		       <&mvc1_out_port>, <&mvc2_out_port>,
1375		       <&amx1_out_port>, <&amx2_out_port>,
1376		       <&adx1_out1_port>, <&adx1_out2_port>,
1377		       <&adx1_out3_port>, <&adx1_out4_port>,
1378		       <&adx2_out1_port>, <&adx2_out2_port>,
1379		       <&adx2_out3_port>, <&adx2_out4_port>,
1380		       <&mixer_out1_port>, <&mixer_out2_port>,
1381		       <&mixer_out3_port>, <&mixer_out4_port>,
1382		       <&mixer_out5_port>,
1383		       <&ope1_out_port>, <&ope2_out_port>,
1384		       /* I/O DAP Ports */
1385		       <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
1386		       <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
1387
1388		label = "NVIDIA Jetson TX1 APE";
1389	};
1390};
1391