1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/leds/common.h> 10#include "lan9691.dtsi" 11 12/ { 13 model = "Microchip EV23X71A"; 14 compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691"; 15 16 aliases { 17 serial0 = &usart0; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 gpio-restart { 25 compatible = "gpio-restart"; 26 gpios = <&gpio 60 GPIO_ACTIVE_LOW>; 27 open-source; 28 priority = <200>; 29 }; 30 31 i2c-mux { 32 compatible = "i2c-mux-gpio"; 33 #address-cells = <1>; 34 #size-cells = <0>; 35 i2c-parent = <&i2c3>; 36 idle-state = <0x8>; 37 mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>, 38 <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>, 39 <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>; 40 settle-time-us = <100>; 41 42 i2c_sfp0: i2c@0 { 43 reg = <0x0>; 44 }; 45 46 i2c_sfp1: i2c@1 { 47 reg = <0x1>; 48 }; 49 50 i2c_sfp2: i2c@2 { 51 reg = <0x2>; 52 }; 53 54 i2c_sfp3: i2c@3 { 55 reg = <0x3>; 56 }; 57 58 i2c_poe: i2c@7 { 59 reg = <0x7>; 60 }; 61 }; 62 63 leds { 64 compatible = "gpio-leds"; 65 66 led-status { 67 color = <LED_COLOR_ID_GREEN>; 68 function = LED_FUNCTION_STATUS; 69 gpios = <&gpio 61 GPIO_ACTIVE_LOW>; 70 }; 71 72 led-sfp1-green { 73 color = <LED_COLOR_ID_GREEN>; 74 function = LED_FUNCTION_LAN; 75 function-enumerator = <0>; 76 gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>; 77 default-state = "off"; 78 }; 79 80 led-sfp1-yellow { 81 color = <LED_COLOR_ID_YELLOW>; 82 function = LED_FUNCTION_LAN; 83 function-enumerator = <0>; 84 gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>; 85 default-state = "off"; 86 }; 87 88 led-sfp2-green { 89 color = <LED_COLOR_ID_GREEN>; 90 function = LED_FUNCTION_LAN; 91 function-enumerator = <1>; 92 gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>; 93 default-state = "off"; 94 }; 95 96 led-sfp2-yellow { 97 color = <LED_COLOR_ID_YELLOW>; 98 function = LED_FUNCTION_LAN; 99 function-enumerator = <1>; 100 gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>; 101 default-state = "off"; 102 }; 103 104 led-sfp3-green { 105 color = <LED_COLOR_ID_GREEN>; 106 function = LED_FUNCTION_LAN; 107 function-enumerator = <2>; 108 gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>; 109 default-state = "off"; 110 }; 111 112 led-sfp3-yellow { 113 color = <LED_COLOR_ID_YELLOW>; 114 function = LED_FUNCTION_LAN; 115 function-enumerator = <2>; 116 gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>; 117 default-state = "off"; 118 }; 119 120 led-sfp4-green { 121 color = <LED_COLOR_ID_GREEN>; 122 function = LED_FUNCTION_LAN; 123 function-enumerator = <3>; 124 gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>; 125 default-state = "off"; 126 }; 127 128 led-sfp4-yellow { 129 color = <LED_COLOR_ID_YELLOW>; 130 function = LED_FUNCTION_LAN; 131 function-enumerator = <3>; 132 gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>; 133 default-state = "off"; 134 }; 135 }; 136 137 mux-controller { 138 compatible = "gpio-mux"; 139 #mux-control-cells = <0>; 140 mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>, 141 <&sgpio_out 1 3 GPIO_ACTIVE_LOW>; 142 }; 143 144 sfp0: sfp0 { 145 compatible = "sff,sfp"; 146 i2c-bus = <&i2c_sfp0>; 147 tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>; 148 los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>; 149 mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>; 150 tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>; 151 }; 152 153 sfp1: sfp1 { 154 compatible = "sff,sfp"; 155 i2c-bus = <&i2c_sfp1>; 156 tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>; 157 los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>; 158 mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>; 159 tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>; 160 }; 161 162 sfp2: sfp2 { 163 compatible = "sff,sfp"; 164 i2c-bus = <&i2c_sfp2>; 165 tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>; 166 los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>; 167 mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>; 168 tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>; 169 }; 170 171 sfp3: sfp3 { 172 compatible = "sff,sfp"; 173 i2c-bus = <&i2c_sfp3>; 174 tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>; 175 los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>; 176 mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>; 177 tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>; 178 }; 179}; 180 181&gpio { 182 emmc_sd_pins: emmc-sd-pins { 183 /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ 184 pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", 185 "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", 186 "GPIO_22", "GPIO_23", "GPIO_24"; 187 function = "emmc_sd"; 188 }; 189 190 fan_pins: fan-pins { 191 pins = "GPIO_25", "GPIO_26"; 192 function = "fan"; 193 }; 194 195 fc0_pins: fc0-pins { 196 pins = "GPIO_3", "GPIO_4"; 197 function = "fc"; 198 }; 199 200 fc2_pins: fc2-pins { 201 pins = "GPIO_64", "GPIO_65", "GPIO_66"; 202 function = "fc"; 203 }; 204 205 fc3_pins: fc3-pins { 206 pins = "GPIO_55", "GPIO_56"; 207 function = "fc"; 208 }; 209 210 mdio_irq_pins: mdio-irq-pins { 211 pins = "GPIO_11"; 212 function = "miim_irq"; 213 }; 214 215 mdio_pins: mdio-pins { 216 pins = "GPIO_9", "GPIO_10"; 217 function = "miim"; 218 }; 219 220 ptp_ext_pins: ptp-ext-pins { 221 pins = "GPIO_59"; 222 function = "ptpsync_5"; 223 }; 224 225 ptp_out_pins: ptp-out-pins { 226 pins = "GPIO_58"; 227 function = "ptpsync_4"; 228 }; 229 230 sgpio_pins: sgpio-pins { 231 /* SCK, D0, D1, LD */ 232 pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; 233 function = "sgpio_a"; 234 }; 235 236 usb_over_pins: usb-over-pins { 237 pins = "GPIO_13"; 238 function = "usb_over_detect"; 239 }; 240 241 usb_power_pins: usb-power-pins { 242 pins = "GPIO_1"; 243 function = "usb_power"; 244 }; 245 246 usb_rst_pins: usb-rst-pins { 247 pins = "GPIO_12"; 248 function = "usb2phy_rst"; 249 }; 250 251 usb_ulpi_pins: usb-ulpi-pins { 252 pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", 253 "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", 254 "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; 255 function = "usb_ulpi"; 256 }; 257}; 258 259&flx0 { 260 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; 261 status = "okay"; 262}; 263 264&flx2 { 265 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>; 266 status = "okay"; 267}; 268 269&flx3 { 270 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; 271 status = "okay"; 272}; 273 274&i2c3 { 275 pinctrl-0 = <&fc3_pins>; 276 pinctrl-names = "default"; 277 i2c-analog-filter; 278 i2c-digital-filter; 279 i2c-digital-filter-width-ns = <35>; 280 i2c-sda-hold-time-ns = <1500>; 281 status = "okay"; 282}; 283 284&mdio0 { 285 pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>; 286 pinctrl-names = "default"; 287 reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>; 288 status = "okay"; 289 290 phy3: phy@3 { 291 compatible = "ethernet-phy-ieee802.3-c22"; 292 reg = <3>; 293 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 294 interrupt-parent = <&gpio>; 295 }; 296 297 phy4: phy@4 { 298 compatible = "ethernet-phy-ieee802.3-c22"; 299 reg = <4>; 300 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 301 interrupt-parent = <&gpio>; 302 }; 303 304 phy5: phy@5 { 305 compatible = "ethernet-phy-ieee802.3-c22"; 306 reg = <5>; 307 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 308 interrupt-parent = <&gpio>; 309 }; 310 311 phy6: phy@6 { 312 compatible = "ethernet-phy-ieee802.3-c22"; 313 reg = <6>; 314 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 315 interrupt-parent = <&gpio>; 316 }; 317 318 phy7: phy@7 { 319 compatible = "ethernet-phy-ieee802.3-c22"; 320 reg = <7>; 321 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 322 interrupt-parent = <&gpio>; 323 }; 324 325 phy8: phy@8 { 326 compatible = "ethernet-phy-ieee802.3-c22"; 327 reg = <8>; 328 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 329 interrupt-parent = <&gpio>; 330 }; 331 332 phy9: phy@9 { 333 compatible = "ethernet-phy-ieee802.3-c22"; 334 reg = <9>; 335 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 336 interrupt-parent = <&gpio>; 337 }; 338 339 phy10: phy@10 { 340 compatible = "ethernet-phy-ieee802.3-c22"; 341 reg = <10>; 342 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 343 interrupt-parent = <&gpio>; 344 }; 345 346 phy11: phy@11 { 347 compatible = "ethernet-phy-ieee802.3-c22"; 348 reg = <11>; 349 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 350 interrupt-parent = <&gpio>; 351 }; 352 353 phy12: phy@12 { 354 compatible = "ethernet-phy-ieee802.3-c22"; 355 reg = <12>; 356 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 357 interrupt-parent = <&gpio>; 358 }; 359 360 phy13: phy@13 { 361 compatible = "ethernet-phy-ieee802.3-c22"; 362 reg = <13>; 363 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 364 interrupt-parent = <&gpio>; 365 }; 366 367 phy14: phy@14 { 368 compatible = "ethernet-phy-ieee802.3-c22"; 369 reg = <14>; 370 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 371 interrupt-parent = <&gpio>; 372 }; 373 374 phy15: phy@15 { 375 compatible = "ethernet-phy-ieee802.3-c22"; 376 reg = <15>; 377 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 378 interrupt-parent = <&gpio>; 379 }; 380 381 phy16: phy@16 { 382 compatible = "ethernet-phy-ieee802.3-c22"; 383 reg = <16>; 384 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 385 interrupt-parent = <&gpio>; 386 }; 387 388 phy17: phy@17 { 389 compatible = "ethernet-phy-ieee802.3-c22"; 390 reg = <17>; 391 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 392 interrupt-parent = <&gpio>; 393 }; 394 395 phy18: phy@18 { 396 compatible = "ethernet-phy-ieee802.3-c22"; 397 reg = <18>; 398 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 399 interrupt-parent = <&gpio>; 400 }; 401 402 phy19: phy@19 { 403 compatible = "ethernet-phy-ieee802.3-c22"; 404 reg = <19>; 405 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 406 interrupt-parent = <&gpio>; 407 }; 408 409 phy20: phy@20 { 410 compatible = "ethernet-phy-ieee802.3-c22"; 411 reg = <20>; 412 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 413 interrupt-parent = <&gpio>; 414 }; 415 416 phy21: phy@21 { 417 compatible = "ethernet-phy-ieee802.3-c22"; 418 reg = <21>; 419 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 420 interrupt-parent = <&gpio>; 421 }; 422 423 phy22: phy@22 { 424 compatible = "ethernet-phy-ieee802.3-c22"; 425 reg = <22>; 426 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 427 interrupt-parent = <&gpio>; 428 }; 429 430 phy23: phy@23 { 431 compatible = "ethernet-phy-ieee802.3-c22"; 432 reg = <23>; 433 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 434 interrupt-parent = <&gpio>; 435 }; 436 437 phy24: phy@24 { 438 compatible = "ethernet-phy-ieee802.3-c22"; 439 reg = <24>; 440 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 441 interrupt-parent = <&gpio>; 442 }; 443 444 phy25: phy@25 { 445 compatible = "ethernet-phy-ieee802.3-c22"; 446 reg = <25>; 447 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 448 interrupt-parent = <&gpio>; 449 }; 450 451 phy26: phy@26 { 452 compatible = "ethernet-phy-ieee802.3-c22"; 453 reg = <26>; 454 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 455 interrupt-parent = <&gpio>; 456 }; 457 458 phy27: phy@27 { 459 compatible = "ethernet-phy-ieee802.3-c22"; 460 reg = <27>; 461 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 462 interrupt-parent = <&gpio>; 463 }; 464}; 465 466&serdes { 467 status = "okay"; 468}; 469 470&sgpio { 471 pinctrl-0 = <&sgpio_pins>; 472 pinctrl-names = "default"; 473 microchip,sgpio-port-ranges = <0 1>, <6 9>; 474 status = "okay"; 475 476 gpio@0 { 477 ngpios = <128>; 478 }; 479 gpio@1 { 480 ngpios = <128>; 481 }; 482}; 483 484&spi2 { 485 pinctrl-0 = <&fc2_pins>; 486 pinctrl-names = "default"; 487 cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; 488 status = "okay"; 489}; 490 491&switch { 492 pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>; 493 pinctrl-names = "default"; 494 status = "okay"; 495 496 ethernet-ports { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 500 port0: port@0 { 501 reg = <0>; 502 phy-handle = <&phy4>; 503 phy-mode = "qsgmii"; 504 phys = <&serdes 0>; 505 microchip,bandwidth = <1000>; 506 }; 507 508 port1: port@1 { 509 reg = <1>; 510 phy-handle = <&phy5>; 511 phy-mode = "qsgmii"; 512 phys = <&serdes 0>; 513 microchip,bandwidth = <1000>; 514 }; 515 516 port2: port@2 { 517 reg = <2>; 518 phy-handle = <&phy6>; 519 phy-mode = "qsgmii"; 520 phys = <&serdes 0>; 521 microchip,bandwidth = <1000>; 522 }; 523 524 port3: port@3 { 525 reg = <3>; 526 phy-handle = <&phy7>; 527 phy-mode = "qsgmii"; 528 phys = <&serdes 0>; 529 microchip,bandwidth = <1000>; 530 }; 531 532 port4: port@4 { 533 reg = <4>; 534 phy-handle = <&phy8>; 535 phy-mode = "qsgmii"; 536 phys = <&serdes 1>; 537 microchip,bandwidth = <1000>; 538 }; 539 540 port5: port@5 { 541 reg = <5>; 542 phy-handle = <&phy9>; 543 phy-mode = "qsgmii"; 544 phys = <&serdes 1>; 545 microchip,bandwidth = <1000>; 546 }; 547 548 port6: port@6 { 549 reg = <6>; 550 phy-handle = <&phy10>; 551 phy-mode = "qsgmii"; 552 phys = <&serdes 1>; 553 microchip,bandwidth = <1000>; 554 }; 555 556 port7: port@7 { 557 reg = <7>; 558 phy-handle = <&phy11>; 559 phy-mode = "qsgmii"; 560 phys = <&serdes 1>; 561 microchip,bandwidth = <1000>; 562 }; 563 564 port8: port@8 { 565 reg = <8>; 566 phy-handle = <&phy12>; 567 phy-mode = "qsgmii"; 568 phys = <&serdes 2>; 569 microchip,bandwidth = <1000>; 570 }; 571 572 port9: port@9 { 573 reg = <9>; 574 phy-handle = <&phy13>; 575 phy-mode = "qsgmii"; 576 phys = <&serdes 2>; 577 microchip,bandwidth = <1000>; 578 }; 579 580 port10: port@10 { 581 reg = <10>; 582 phy-handle = <&phy14>; 583 phy-mode = "qsgmii"; 584 phys = <&serdes 2>; 585 microchip,bandwidth = <1000>; 586 }; 587 588 port11: port@11 { 589 reg = <11>; 590 phy-handle = <&phy15>; 591 phy-mode = "qsgmii"; 592 phys = <&serdes 2>; 593 microchip,bandwidth = <1000>; 594 }; 595 596 port12: port@12 { 597 reg = <12>; 598 phy-handle = <&phy16>; 599 phy-mode = "qsgmii"; 600 phys = <&serdes 3>; 601 microchip,bandwidth = <1000>; 602 }; 603 604 port13: port@13 { 605 reg = <13>; 606 phy-handle = <&phy17>; 607 phy-mode = "qsgmii"; 608 phys = <&serdes 3>; 609 microchip,bandwidth = <1000>; 610 }; 611 612 port14: port@14 { 613 reg = <14>; 614 phy-handle = <&phy18>; 615 phy-mode = "qsgmii"; 616 phys = <&serdes 3>; 617 microchip,bandwidth = <1000>; 618 }; 619 620 port15: port@15 { 621 reg = <15>; 622 phy-handle = <&phy19>; 623 phy-mode = "qsgmii"; 624 phys = <&serdes 3>; 625 microchip,bandwidth = <1000>; 626 }; 627 628 port16: port@16 { 629 reg = <16>; 630 phy-handle = <&phy20>; 631 phy-mode = "qsgmii"; 632 phys = <&serdes 4>; 633 microchip,bandwidth = <1000>; 634 }; 635 636 port17: port@17 { 637 reg = <17>; 638 phy-handle = <&phy21>; 639 phy-mode = "qsgmii"; 640 phys = <&serdes 4>; 641 microchip,bandwidth = <1000>; 642 }; 643 644 port18: port@18 { 645 reg = <18>; 646 phy-handle = <&phy22>; 647 phy-mode = "qsgmii"; 648 phys = <&serdes 4>; 649 microchip,bandwidth = <1000>; 650 }; 651 652 port19: port@19 { 653 reg = <19>; 654 phy-handle = <&phy23>; 655 phy-mode = "qsgmii"; 656 phys = <&serdes 4>; 657 microchip,bandwidth = <1000>; 658 }; 659 660 port20: port@20 { 661 reg = <20>; 662 phy-handle = <&phy24>; 663 phy-mode = "qsgmii"; 664 phys = <&serdes 5>; 665 microchip,bandwidth = <1000>; 666 }; 667 668 port21: port@21 { 669 reg = <21>; 670 phy-handle = <&phy25>; 671 phy-mode = "qsgmii"; 672 phys = <&serdes 5>; 673 microchip,bandwidth = <1000>; 674 }; 675 676 port22: port@22 { 677 reg = <22>; 678 phy-handle = <&phy26>; 679 phy-mode = "qsgmii"; 680 phys = <&serdes 5>; 681 microchip,bandwidth = <1000>; 682 }; 683 684 port23: port@23 { 685 reg = <23>; 686 phy-handle = <&phy27>; 687 phy-mode = "qsgmii"; 688 phys = <&serdes 5>; 689 microchip,bandwidth = <1000>; 690 }; 691 692 port24: port@24 { 693 reg = <24>; 694 phys = <&serdes 6>; 695 phy-mode = "10gbase-r"; 696 sfp = <&sfp0>; 697 managed = "in-band-status"; 698 microchip,bandwidth = <10000>; 699 microchip,sd-sgpio = <24>; 700 }; 701 702 port25: port@25 { 703 reg = <25>; 704 phys = <&serdes 7>; 705 phy-mode = "10gbase-r"; 706 sfp = <&sfp1>; 707 managed = "in-band-status"; 708 microchip,bandwidth = <10000>; 709 microchip,sd-sgpio = <28>; 710 }; 711 712 port26: port@26 { 713 reg = <26>; 714 phys = <&serdes 8>; 715 phy-mode = "10gbase-r"; 716 sfp = <&sfp2>; 717 managed = "in-band-status"; 718 microchip,bandwidth = <10000>; 719 microchip,sd-sgpio = <32>; 720 }; 721 722 port27: port@27 { 723 reg = <27>; 724 phys = <&serdes 9>; 725 phy-mode = "10gbase-r"; 726 sfp = <&sfp3>; 727 managed = "in-band-status"; 728 microchip,bandwidth = <10000>; 729 microchip,sd-sgpio = <36>; 730 }; 731 732 port29: port@29 { 733 reg = <29>; 734 phy-handle = <&phy3>; 735 phy-mode = "rgmii-id"; 736 microchip,bandwidth = <1000>; 737 }; 738 }; 739}; 740 741&tmon { 742 pinctrl-0 = <&fan_pins>; 743 pinctrl-names = "default"; 744}; 745 746&usart0 { 747 pinctrl-0 = <&fc0_pins>; 748 pinctrl-names = "default"; 749 status = "okay"; 750}; 751 752&usb { 753 pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>; 754 pinctrl-names = "default"; 755 status = "okay"; 756}; 757