1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. 4 */ 5 6#include <dt-bindings/dma/at91.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/mfd/at91-usart.h> 9#include <dt-bindings/mfd/atmel-flexcom.h> 10 11#include "clk-lan9691.h" 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 model = "Microchip LAN969x"; 18 compatible = "microchip,lan9691"; 19 interrupt-parent = <&gic>; 20 21 clocks { 22 fx100_clk: fx100-clk { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <320000000>; 26 }; 27 28 cpu_clk: cpu-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <1000000000>; 32 }; 33 34 ddr_clk: ddr-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <600000000>; 38 }; 39 40 fabric_clk: fabric-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <250000000>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 compatible = "arm,cortex-a53"; 53 device_type = "cpu"; 54 reg = <0x0 0x0>; 55 next-level-cache = <&l2_0>; 56 }; 57 58 l2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0"; 67 method = "smc"; 68 }; 69 70 pmu { 71 compatible = "arm,cortex-a53-pmu"; 72 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 73 }; 74 75 timer { 76 compatible = "arm,armv8-timer"; 77 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Secure Phys IRQ */ 78 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Non-secure Phys IRQ */ 79 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virt IRQ */ 80 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hyp IRQ */ 81 }; 82 83 axi: axi { 84 compatible = "simple-bus"; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges; 88 89 usb: usb@300000 { 90 compatible = "microchip,lan9691-dwc3", "snps,dwc3"; 91 reg = <0x300000 0x80000>; 92 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 93 clocks = <&clks GCK_GATE_USB_DRD>, 94 <&clks GCK_ID_USB_REFCLK>; 95 clock-names = "bus_early", "ref"; 96 assigned-clocks = <&clks GCK_ID_USB_REFCLK>; 97 assigned-clock-rates = <60000000>; 98 maximum-speed = "high-speed"; 99 dr_mode = "host"; 100 status = "disabled"; 101 }; 102 103 flx0: flexcom@e0040000 { 104 compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; 105 reg = <0xe0040000 0x100>; 106 ranges = <0x0 0xe0040000 0x800>; 107 clocks = <&clks GCK_ID_FLEXCOM0>; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 status = "disabled"; 111 112 usart0: serial@200 { 113 compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; 114 reg = <0x200 0x200>; 115 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 116 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 117 <&dma AT91_XDMAC_DT_PERID(2)>; 118 dma-names = "tx", "rx"; 119 clocks = <&fabric_clk>; 120 clock-names = "usart"; 121 atmel,fifo-size = <32>; 122 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 123 status = "disabled"; 124 }; 125 126 spi0: spi@400 { 127 compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; 128 reg = <0x400 0x200>; 129 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 130 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 131 <&dma AT91_XDMAC_DT_PERID(2)>; 132 dma-names = "tx", "rx"; 133 clocks = <&fabric_clk>; 134 clock-names = "spi_clk"; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 atmel,fifo-size = <32>; 138 status = "disabled"; 139 }; 140 141 i2c0: i2c@600 { 142 compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; 143 reg = <0x600 0x200>; 144 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 145 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 146 <&dma AT91_XDMAC_DT_PERID(2)>; 147 dma-names = "tx", "rx"; 148 clocks = <&fabric_clk>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 status = "disabled"; 152 }; 153 }; 154 155 flx1: flexcom@e0044000 { 156 compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; 157 reg = <0xe0044000 0x100>; 158 ranges = <0x0 0xe0044000 0x800>; 159 clocks = <&clks GCK_ID_FLEXCOM1>; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 status = "disabled"; 163 164 usart1: serial@200 { 165 compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; 166 reg = <0x200 0x200>; 167 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 168 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 169 <&dma AT91_XDMAC_DT_PERID(2)>; 170 dma-names = "tx", "rx"; 171 clocks = <&fabric_clk>; 172 clock-names = "usart"; 173 atmel,fifo-size = <32>; 174 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 175 status = "disabled"; 176 }; 177 178 spi1: spi@400 { 179 compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; 180 reg = <0x400 0x200>; 181 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 182 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 183 <&dma AT91_XDMAC_DT_PERID(2)>; 184 dma-names = "tx", "rx"; 185 clocks = <&fabric_clk>; 186 clock-names = "spi_clk"; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 atmel,fifo-size = <32>; 190 status = "disabled"; 191 }; 192 193 i2c1: i2c@600 { 194 compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; 195 reg = <0x600 0x200>; 196 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 197 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 198 <&dma AT91_XDMAC_DT_PERID(2)>; 199 dma-names = "tx", "rx"; 200 clocks = <&fabric_clk>; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 status = "disabled"; 204 }; 205 }; 206 207 trng: rng@e0048000 { 208 compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng"; 209 reg = <0xe0048000 0x100>; 210 clocks = <&fabric_clk>; 211 status = "disabled"; 212 }; 213 214 aes: crypto@e004c000 { 215 compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes"; 216 reg = <0xe004c000 0x100>; 217 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 218 dmas = <&dma AT91_XDMAC_DT_PERID(12)>, 219 <&dma AT91_XDMAC_DT_PERID(13)>; 220 dma-names = "tx", "rx"; 221 clocks = <&fabric_clk>; 222 clock-names = "aes_clk"; 223 status = "disabled"; 224 }; 225 226 flx2: flexcom@e0060000 { 227 compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; 228 reg = <0xe0060000 0x100>; 229 ranges = <0x0 0xe0060000 0x800>; 230 clocks = <&clks GCK_ID_FLEXCOM2>; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 status = "disabled"; 234 235 usart2: serial@200 { 236 compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; 237 reg = <0x200 0x200>; 238 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 239 dmas = <&dma AT91_XDMAC_DT_PERID(7)>, 240 <&dma AT91_XDMAC_DT_PERID(6)>; 241 dma-names = "tx", "rx"; 242 clocks = <&fabric_clk>; 243 clock-names = "usart"; 244 atmel,fifo-size = <32>; 245 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 246 status = "disabled"; 247 }; 248 249 spi2: spi@400 { 250 compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; 251 reg = <0x400 0x200>; 252 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 253 dmas = <&dma AT91_XDMAC_DT_PERID(7)>, 254 <&dma AT91_XDMAC_DT_PERID(6)>; 255 dma-names = "tx", "rx"; 256 clocks = <&fabric_clk>; 257 clock-names = "spi_clk"; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 atmel,fifo-size = <32>; 261 status = "disabled"; 262 }; 263 264 i2c2: i2c@600 { 265 compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; 266 reg = <0x600 0x200>; 267 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 268 dmas = <&dma AT91_XDMAC_DT_PERID(7)>, 269 <&dma AT91_XDMAC_DT_PERID(6)>; 270 dma-names = "tx", "rx"; 271 clocks = <&fabric_clk>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 status = "disabled"; 275 }; 276 }; 277 278 flx3: flexcom@e0064000 { 279 compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; 280 reg = <0xe0064000 0x100>; 281 ranges = <0x0 0xe0064000 0x800>; 282 clocks = <&clks GCK_ID_FLEXCOM3>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 status = "disabled"; 286 287 usart3: serial@200 { 288 compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; 289 reg = <0x200 0x200>; 290 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 291 dmas = <&dma AT91_XDMAC_DT_PERID(9)>, 292 <&dma AT91_XDMAC_DT_PERID(8)>; 293 dma-names = "tx", "rx"; 294 clocks = <&fabric_clk>; 295 clock-names = "usart"; 296 atmel,fifo-size = <32>; 297 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 298 status = "disabled"; 299 }; 300 301 spi3: spi@400 { 302 compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; 303 reg = <0x400 0x200>; 304 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 305 dmas = <&dma AT91_XDMAC_DT_PERID(9)>, 306 <&dma AT91_XDMAC_DT_PERID(8)>; 307 dma-names = "tx", "rx"; 308 clocks = <&fabric_clk>; 309 clock-names = "spi_clk"; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 atmel,fifo-size = <32>; 313 status = "disabled"; 314 }; 315 316 i2c3: i2c@600 { 317 compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; 318 reg = <0x600 0x200>; 319 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 320 dmas = <&dma AT91_XDMAC_DT_PERID(9)>, 321 <&dma AT91_XDMAC_DT_PERID(8)>; 322 dma-names = "tx", "rx"; 323 clocks = <&fabric_clk>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 status = "disabled"; 327 }; 328 }; 329 330 dma: dma-controller@e0068000 { 331 compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma"; 332 reg = <0xe0068000 0x1000>; 333 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 334 dma-channels = <16>; 335 #dma-cells = <1>; 336 clocks = <&fabric_clk>; 337 clock-names = "dma_clk"; 338 }; 339 340 sha: crypto@e006c000 { 341 compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha"; 342 reg = <0xe006c000 0xec>; 343 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 344 dmas = <&dma AT91_XDMAC_DT_PERID(14)>; 345 dma-names = "tx"; 346 clocks = <&fabric_clk>; 347 clock-names = "sha_clk"; 348 status = "disabled"; 349 }; 350 351 timer: timer@e008c000 { 352 compatible = "snps,dw-apb-timer"; 353 reg = <0xe008c000 0x400>; 354 clocks = <&fabric_clk>; 355 clock-names = "timer"; 356 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 357 status = "disabled"; 358 }; 359 360 watchdog: watchdog@e0090000 { 361 compatible = "snps,dw-wdt"; 362 reg = <0xe0090000 0x1000>; 363 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&fabric_clk>; 365 }; 366 367 cpu_ctrl: syscon@e00c0000 { 368 compatible = "microchip,lan966x-cpu-syscon", "syscon"; 369 reg = <0xe00c0000 0x350>; 370 }; 371 372 switch: switch@e00c0000 { 373 compatible = "microchip,lan9691-switch"; 374 reg = <0xe00c0000 0x0010000>, 375 <0xe2010000 0x1410000>; 376 reg-names = "cpu", "devices"; 377 interrupt-names = "xtr", "fdma", "ptp"; 378 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 381 resets = <&reset 0>; 382 reset-names = "switch"; 383 status = "disabled"; 384 }; 385 386 clks: clock-controller@e00c00b4 { 387 compatible = "microchip,lan9691-gck"; 388 reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>; 389 #clock-cells = <1>; 390 clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>; 391 clock-names = "cpu", "ddr", "sys"; 392 }; 393 394 reset: reset-controller@e201000c { 395 compatible = "microchip,lan9691-switch-reset", 396 "microchip,lan966x-switch-reset"; 397 reg = <0xe201000c 0x4>; 398 reg-names = "gcb"; 399 #reset-cells = <1>; 400 cpu-syscon = <&cpu_ctrl>; 401 }; 402 403 gpio: pinctrl@e20100d4 { 404 compatible = "microchip,lan9691-pinctrl"; 405 reg = <0xe20100d4 0xd4>, 406 <0xe2010370 0xa8>; 407 gpio-controller; 408 #gpio-cells = <2>; 409 gpio-ranges = <&gpio 0 0 66>; 410 interrupt-controller; 411 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 412 #interrupt-cells = <2>; 413 }; 414 415 mdio0: mdio@e20101a8 { 416 compatible = "microchip,lan9691-miim", "mscc,ocelot-miim"; 417 reg = <0xe20101a8 0x24>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 clocks = <&fx100_clk>; 421 status = "disabled"; 422 }; 423 424 mdio1: mdio@e20101cc { 425 compatible = "microchip,lan9691-miim", "mscc,ocelot-miim"; 426 reg = <0xe20101cc 0x24>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 clocks = <&fx100_clk>; 430 status = "disabled"; 431 }; 432 433 sgpio: gpio@e2010230 { 434 compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio"; 435 reg = <0xe2010230 0x118>; 436 clocks = <&fx100_clk>; 437 resets = <&reset 0>; 438 reset-names = "switch"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 443 sgpio_in: gpio@0 { 444 compatible = "microchip,lan9691-sgpio-bank", 445 "microchip,sparx5-sgpio-bank"; 446 reg = <0>; 447 gpio-controller; 448 #gpio-cells = <3>; 449 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 450 interrupt-controller; 451 #interrupt-cells = <3>; 452 }; 453 454 sgpio_out: gpio@1 { 455 compatible = "microchip,lan9691-sgpio-bank", 456 "microchip,sparx5-sgpio-bank"; 457 reg = <1>; 458 gpio-controller; 459 #gpio-cells = <3>; 460 }; 461 }; 462 463 tmon: hwmon@e2020100 { 464 compatible = "microchip,lan9691-temp", "microchip,sparx5-temp"; 465 reg = <0xe2020100 0xc>; 466 clocks = <&fx100_clk>; 467 #thermal-sensor-cells = <0>; 468 }; 469 470 serdes: serdes@e3410000 { 471 compatible = "microchip,lan9691-serdes"; 472 reg = <0xe3410000 0x150000>; 473 #phy-cells = <1>; 474 clocks = <&fabric_clk>; 475 }; 476 477 gic: interrupt-controller@e8c11000 { 478 compatible = "arm,gic-400"; 479 reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */ 480 <0xe8c12000 0x2000>, /* CPU interface GICC_ */ 481 <0xe8c14000 0x2000>, /* Virt interface control */ 482 <0xe8c16000 0x2000>; /* Virt CPU interface */ 483 #interrupt-cells = <3>; 484 interrupt-controller; 485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 486 }; 487 }; 488}; 489