1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Device tree for the CN9132-DB board. 6 */ 7 8#include "cn9131-db.dtsi" 9 10/ { 11 compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130", 12 "marvell,armada-ap807-quad", "marvell,armada-ap807"; 13 14 aliases { 15 gpio5 = &cp2_gpio1; 16 gpio6 = &cp2_gpio2; 17 ethernet5 = &cp2_eth0; 18 }; 19 20 cp2_reg_usb3_vbus0: regulator-7 { 21 compatible = "regulator-fixed"; 22 regulator-name = "cp2-xhci0-vbus"; 23 regulator-min-microvolt = <5000000>; 24 regulator-max-microvolt = <5000000>; 25 enable-active-high; 26 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; 27 }; 28 29 cp2_usb3_0_phy0: usb-phy-4 { 30 compatible = "usb-nop-xceiv"; 31 #phy-cells = <0>; 32 vcc-supply = <&cp2_reg_usb3_vbus0>; 33 }; 34 35 cp2_reg_usb3_vbus1: regulator-8 { 36 compatible = "regulator-fixed"; 37 regulator-name = "cp2-xhci1-vbus"; 38 regulator-min-microvolt = <5000000>; 39 regulator-max-microvolt = <5000000>; 40 enable-active-high; 41 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; 42 }; 43 44 cp2_usb3_0_phy1: usb-phy-5 { 45 compatible = "usb-nop-xceiv"; 46 #phy-cells = <0>; 47 vcc-supply = <&cp2_reg_usb3_vbus1>; 48 }; 49 50 cp2_reg_sd_vccq: regulator-9 { 51 compatible = "regulator-gpio"; 52 regulator-name = "cp2_sd_vcc"; 53 regulator-min-microvolt = <1800000>; 54 regulator-max-microvolt = <3300000>; 55 gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>; 56 states = <1800000 0x1 3300000 0x0>; 57 }; 58 59 cp2_sfp_eth0: sfp-eth-3 { 60 compatible = "sff,sfp"; 61 i2c-bus = <&cp2_sfpp0_i2c>; 62 los-gpios = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; 63 mod-def0-gpios = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>; 64 tx-disable-gpios = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>; 65 tx-fault-gpios = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>; 66 /* 67 * SFP cages are unconnected on early PCBs because of an the I2C 68 * lanes not being connected. Prevent the port for being 69 * unusable by disabling the SFP node. 70 */ 71 status = "disabled"; 72 }; 73}; 74 75/* 76 * Instantiate the second slave CP115 77 */ 78 79#define CP11X_NAME cp2 80#define CP11X_BASE f6000000 81#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) 82#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 83#define CP11X_PCIE0_BASE f6600000 84#define CP11X_PCIE1_BASE f6620000 85#define CP11X_PCIE2_BASE f6640000 86 87#include "armada-cp115.dtsi" 88 89#undef CP11X_NAME 90#undef CP11X_BASE 91#undef CP11X_PCIEx_MEM_BASE 92#undef CP11X_PCIEx_MEM_SIZE 93#undef CP11X_PCIE0_BASE 94#undef CP11X_PCIE1_BASE 95#undef CP11X_PCIE2_BASE 96 97&cp2_crypto { 98 status = "disabled"; 99}; 100 101&cp2_ethernet { 102 status = "okay"; 103}; 104 105/* SLM-1521-V2, CON9 */ 106&cp2_eth0 { 107 status = "disabled"; 108 phy-mode = "10gbase-r"; 109 /* Generic PHY, providing serdes lanes */ 110 phys = <&cp2_comphy4 0>; 111 managed = "in-band-status"; 112 sfp = <&cp2_sfp_eth0>; 113}; 114 115&cp2_gpio1 { 116 status = "okay"; 117}; 118 119&cp2_gpio2 { 120 status = "okay"; 121}; 122 123&cp2_i2c0 { 124 clock-frequency = <100000>; 125 126 /* SLM-1521-V2 - U3 */ 127 i2c-mux@72 { 128 compatible = "nxp,pca9544"; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 reg = <0x72>; 132 cp2_sfpp0_i2c: i2c@0 { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 reg = <0>; 136 }; 137 138 i2c@1 { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 reg = <1>; 142 /* U12 */ 143 cp2_module_expander1: pca9555@21 { 144 compatible = "nxp,pca9555"; 145 gpio-controller; 146 #gpio-cells = <2>; 147 reg = <0x21>; 148 }; 149 }; 150 }; 151}; 152 153/* SLM-1521-V2, CON6 */ 154&cp2_pcie0 { 155 status = "okay"; 156 num-lanes = <2>; 157 num-viewport = <8>; 158 /* Generic PHY, providing serdes lanes */ 159 phys = <&cp2_comphy0 0 160 &cp2_comphy1 0>; 161}; 162 163/* SLM-1521-V2, CON8 */ 164&cp2_pcie2 { 165 status = "okay"; 166 num-lanes = <1>; 167 num-viewport = <8>; 168 /* Generic PHY, providing serdes lanes */ 169 phys = <&cp2_comphy5 2>; 170}; 171 172&cp2_sata0 { 173 status = "okay"; 174 175 /* SLM-1521-V2, CON4 */ 176 sata-port@0 { 177 /* Generic PHY, providing serdes lanes */ 178 phys = <&cp2_comphy2 0>; 179 status = "okay"; 180 }; 181}; 182 183/* CON 2 on SLM-1683 - microSD */ 184&cp2_sdhci0 { 185 status = "okay"; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&cp2_sdhci_pins>; 188 bus-width = <4>; 189 cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>; 190 vqmmc-supply = <&cp2_reg_sd_vccq>; 191}; 192 193&cp2_syscon0 { 194 cp2_pinctrl: pinctrl { 195 compatible = "marvell,cp115-standalone-pinctrl"; 196 197 cp2_i2c0_pins: cp2-i2c-pins-0 { 198 marvell,pins = "mpp37", "mpp38"; 199 marvell,function = "i2c0"; 200 }; 201 cp2_sdhci_pins: cp2-sdhi-pins-0 { 202 marvell,pins = "mpp56", "mpp57", "mpp58", 203 "mpp59", "mpp60", "mpp61"; 204 marvell,function = "sdio"; 205 }; 206 }; 207}; 208 209&cp2_utmi { 210 status = "okay"; 211}; 212 213&cp2_usb3_0 { 214 status = "okay"; 215 usb-phy = <&cp2_usb3_0_phy0>; 216 phys = <&cp2_utmi0>; 217 phy-names = "usb"; 218 dr_mode = "host"; 219}; 220 221/* SLM-1521-V2, CON11 */ 222&cp2_usb3_1 { 223 status = "okay"; 224 usb-phy = <&cp2_usb3_0_phy1>; 225 /* Generic PHY, providing serdes lanes */ 226 phys = <&cp2_comphy3 1>, <&cp2_utmi1>; 227 phy-names = "usb", "utmi"; 228 dr_mode = "host"; 229}; 230